RTS;
ENDPROC(_blackfin_dcache_flush_range)
-ENTRY(_blackfin_dcache_invalidate_range)
+ENTRY(_blackfin_dcache_flush_invalidate_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
FLUSHINV[P0];
SSYNC;
RTS;
-ENDPROC(_blackfin_dcache_invalidate_range)
+ENDPROC(_blackfin_dcache_flush_invalidate_range)
extern void blackfin_icache_flush_range(const void *, const void *);
extern void blackfin_dcache_flush_range(const void *, const void *);
-extern void blackfin_dcache_invalidate_range(const void *, const void *);
+extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
/* Use DMA to move data from on chip to external memory. While this is
* required for only L1 instruction (it is not directly readable by the
bfin_write_MDMA_D0_CONFIG(0);
bfin_write_MDMA_S0_CONFIG(0);
}
+/* We should do a dcache invalidate on the destination after the dma, but since
+ * we lack such hardware capability, we'll flush/invalidate the destination
+ * before the dma and bank on the idea that u-boot is single threaded.
+ */
void *dma_memcpy(void *dst, const void *src, size_t count)
{
- if (dcache_status())
+ if (dcache_status()) {
blackfin_dcache_flush_range(src, src + count);
+ blackfin_dcache_flush_invalidate_range(dst, dst + count);
+ }
dma_memcpy_nocache(dst, src, count);
if (icache_status())
blackfin_icache_flush_range(dst, dst + count);
- if (dcache_status())
- blackfin_dcache_invalidate_range(dst, dst + count);
-
return dst;
}