#define CACHE_LINE_MASK (~(l1_line_sz - 1))
-#ifdef CONFIG_ISA_ARCV2
int slc_line_sz __section(".data");
bool slc_exists __section(".data") = false;
bool ioc_exists __section(".data") = false;
static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
{
+#ifdef CONFIG_ISA_ARCV2
+
unsigned int ctrl;
unsigned long end;
read_aux_reg(ARC_AUX_SLC_CTRL);
while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
+
+#endif /* CONFIG_ISA_ARCV2 */
}
static void arc_ioc_setup(void)
write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
}
-#endif /* CONFIG_ISA_ARCV2 */
-#ifdef CONFIG_ISA_ARCV2
static void read_decode_cache_bcr_arcv2(void)
{
+#ifdef CONFIG_ISA_ARCV2
+
union bcr_slc_cfg slc_cfg;
union bcr_clust_cfg cbcr;
union bcr_generic sbcr;
cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
if (cbcr.fields.c && ioc_enable)
ioc_exists = true;
+
+#endif /* CONFIG_ISA_ARCV2 */
}
-#endif
void read_decode_cache_bcr(void)
{
{
read_decode_cache_bcr();
-#ifdef CONFIG_ISA_ARCV2
- read_decode_cache_bcr_arcv2();
+ if (is_isa_arcv2())
+ read_decode_cache_bcr_arcv2();
- if (ioc_exists)
+ if (is_isa_arcv2() && ioc_exists)
arc_ioc_setup();
read_decode_mmu_bcr();
* only if PAE exists in current HW. So we had to check pae_exist
* before using them.
*/
- if (slc_exists && pae_exists)
+ if (is_isa_arcv2() && slc_exists && pae_exists)
slc_upper_region_init();
-#endif /* CONFIG_ISA_ARCV2 */
}
int icache_status(void)
{
__ic_entire_invalidate();
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists)
+ if (is_isa_arcv2() && slc_exists)
__slc_entire_op(OP_INV);
-#endif
}
int dcache_status(void)
if (start >= end)
return;
-#ifdef CONFIG_ISA_ARCV2
- if (!ioc_exists)
-#endif
+ /*
+ * ARCv1 -> call __dc_line_op
+ * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op
+ * ARCv2 && IOC enabled -> nothing
+ */
+ if (!is_isa_arcv2() || !ioc_exists)
__dc_line_op(start, end - start, OP_INV);
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists && !ioc_exists)
+ if (is_isa_arcv2() && slc_exists && !ioc_exists)
__slc_rgn_op(start, end - start, OP_INV);
-#endif
}
void flush_dcache_range(unsigned long start, unsigned long end)
if (start >= end)
return;
-#ifdef CONFIG_ISA_ARCV2
- if (!ioc_exists)
-#endif
+ /*
+ * ARCv1 -> call __dc_line_op
+ * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op
+ * ARCv2 && IOC enabled -> nothing
+ */
+ if (!is_isa_arcv2() || !ioc_exists)
__dc_line_op(start, end - start, OP_FLUSH);
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists && !ioc_exists)
+ if (is_isa_arcv2() && slc_exists && !ioc_exists)
__slc_rgn_op(start, end - start, OP_FLUSH);
-#endif
}
void flush_cache(unsigned long start, unsigned long size)
{
__dc_entire_op(OP_FLUSH_N_INV);
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists)
+ if (is_isa_arcv2() && slc_exists)
__slc_entire_op(OP_FLUSH_N_INV);
-#endif
}
void flush_dcache_all(void)
{
__dc_entire_op(OP_FLUSH);
-#ifdef CONFIG_ISA_ARCV2
- if (slc_exists)
+ if (is_isa_arcv2() && slc_exists)
__slc_entire_op(OP_FLUSH);
-#endif
}