rm9200 lowevel_init: don't touch reserved/readonly registers

For some reason the AT91rm9200 lowlevel init writes to a bunch of
reserved or read-only addresses.  All the boards seem to define the
value-to-be-written values as zero ... but they shouldn't actually
be writing *anything* there.

No documented erratum justifies these accesses.  It looks like maybe
some pre-release BDI-2000 setup code has been carried along by cargo
cult programming since at least late 2004 (per GIT history).

Here's a patch disabling what seems to be bogosity.  Tested on a
csb337; there were no behavioral changes.

Signed-off-by: David Brownell <david-b@pacbell.net>
on RM9200ek
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 0913284e793ab8a00c03900fa962a54941303d40..d8bb96004b9797caf5d43e74bfe84668fe1e74a5 100644 (file)
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -81,6 +81,7 @@ LoopOsc:
        bne     0b
        /* delay - this is all done by guess */
        ldr     r0, =0x00010000
+       /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
 1:
        subs    r0, r0, #1
        bhi     1b
@@ -108,16 +109,6 @@ LoopOsc:
        .ltorg
 
 SMRDATA:
-       .word AT91C_MC_PUIA
-       .word CONFIG_SYS_MC_PUIA_VAL
-       .word AT91C_MC_PUP
-       .word CONFIG_SYS_MC_PUP_VAL
-       .word AT91C_MC_PUER
-       .word CONFIG_SYS_MC_PUER_VAL
-       .word AT91C_MC_ASR
-       .word CONFIG_SYS_MC_ASR_VAL
-       .word AT91C_MC_AASR
-       .word CONFIG_SYS_MC_AASR_VAL
        .word AT91C_EBI_CFGR
        .word CONFIG_SYS_EBI_CFGR_VAL
        .word AT91C_SMC_CSR0
@@ -128,8 +119,7 @@ SMRDATA:
        .word CONFIG_SYS_PLLBR_VAL
        .word AT91C_MCKR
        .word CONFIG_SYS_MCKR_VAL
-       /* SMRDATA is 80 bytes long */
-       /* here there's a delay of 100 */
+       /* here there's a delay */
 SMRDATA1:
        .word AT91C_PIOC_ASR
        .word CONFIG_SYS_PIOC_ASR_VAL

diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 2017b666a73556192c4508e9f545115b092f437e..590c69a19cc6422a968ba59b2ae68779674bbfb2 100644 (file)
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -45,11 +45,6 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
 /* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL  0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL  0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
 #define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
 #define CONFIG_SYS_SMC_CSR0_VAL        0x00003284 /* 16bit, 2 TDF, 4 WS */
 

diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 58ec94a848d2ed9043dd33c98d32e8b0890008ed..b4f075ebc585279e172846a07b66572304410168 100644 (file)
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -56,11 +56,6 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
 /* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL  0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL  0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
 #define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
 #define CONFIG_SYS_SMC_CSR0_VAL        0x00003284 /* 16bit, 2 TDF, 4 WS */
 

diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index 80559bf1919a987e0befa198a6aac8eac098602c..be478b24e41dea28a1a3166f0b9ffb2b1cc19f0a 100644 (file)
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -44,11 +44,6 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
 /* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL  0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL  0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
 #define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
 #define CONFIG_SYS_SMC_CSR0_VAL        0x100032ad /* 16bit, 2 TDF, 4 WS */
 

diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index 7a5769696a83e71ee2bfad23273e4fdef09e4e18..f4fd808e46e9d1d363beb68f637326a359165912 100644 (file)
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -45,11 +45,6 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
 /* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL  0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL  0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
 #define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
 #define CONFIG_SYS_SMC_CSR0_VAL        0x00003284 /* 16bit, 2 TDF, 4 WS */
 

diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index 32a8194a2bd92e75339102f1d06b741c05fa5863..5c066426cf7f05e36c39c5b7419dc9d17fc62401 100644 (file)
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -46,11 +46,6 @@
  */
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
 /* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL  0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL  0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
 #define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
 #define CONFIG_SYS_SMC_CSR0_VAL        0x00003284 /* 16bit, 2 TDF, 4 WS */
 

diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index ac678d0b608ea2fd56c1a956d651bad3b88909e5..0c2ee6057ee5f07d3bedce4569ba6e3defa1d55d 100644 (file)
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -49,11 +49,6 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
 /* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL  0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL  0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
 #define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
 #define CONFIG_SYS_SMC_CSR0_VAL        0x00003084 /* 16bit, 2 TDF, 4 WS */