# Option processing based on util-linux-2.13/getopt-parse.bash
-# Note that we use `"$@"' to let each command-line parameter expand to a
+# Note that we use `"$@"' to let each command-line parameter expand to a
# separate word. The quotes around `$@' are essential!
# We need TEMP as the `eval set --' would nuke the return value of
# getopt.
- CONFIG_ENV_MAX_ENTRIES
- Maximum number of entries in the hash table that is used
- internally to store the environment settings. The default
- setting is supposed to be generous and should work in most
- cases. This setting can be used to tune behaviour; see
- lib/hashtable.c for details.
+ Maximum number of entries in the hash table that is used
+ internally to store the environment settings. The default
+ setting is supposed to be generous and should work in most
+ cases. This setting can be used to tune behaviour; see
+ lib/hashtable.c for details.
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
dram_init();
}
#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
-
int arch_cpu_init(void)
{
pxa_gpio_setup();
-// pxa_wait_ticks(0x8000);
+/* pxa_wait_ticks(0x8000); */
pxa_wakeup();
pxa_interrupt_setup();
pxa_clock_setup();
* 0xC: 0xB808XXXX
*
* then it is necessary to count address for storing the most significant
- * 16bits from _exception_handler address and copy it to
+ * 16bits from _exception_handler address and copy it to
* 0xa address. Big endian use offset in r10=0 that's why is it just
* 0xa address. The same is done for the least significant 16 bits
* for 0xe address.
ramdisk_flags |= RD_PROMPT;
else
ramdisk_flags &= ~RD_PROMPT;
-
+
val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
if (val == 1)
ramdisk_flags |= RD_DOLOAD;
int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr = 0x20000000 + 0x200000; // AMS2
+ ulong addr = 0x20000000 + 0x200000; /* AMS2 */
uchar data;
if (argc < 2)
# For use with external or internal boots.
TEXT_BASE = 0x80008000
-
#endif
/*
- * The top 4 lines of the local bus address are pulled low/high and
- * can be read to determine the least significant digit of a board's
- * model number.
- */
+ * The top 4 lines of the local bus address are pulled low/high and
+ * can be read to determine the least significant digit of a board's
+ * model number.
+ */
return gur->gpporcr >> 28;
}
-
-
* There are traditionally three board-specific SDRAM timing parameters
* which must be calculated based on the particular PCB artwork. These are:
* 1.) CPO (Read Capture Delay)
- * - TIMING_CFG_2 register
- * Source: Calculation based on board trace lengths and
- * chip-specific internal delays.
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths and
+ * chip-specific internal delays.
* 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- * - DDR_SDRAM_CLK_CNTL register
- * Source: Signal Integrity Simulations
+ * - DDR_SDRAM_CLK_CNTL register
+ * Source: Signal Integrity Simulations
* 3.) 2T Timing on Addr/Ctl
- * - TIMING_CFG_2 register
- * Source: Signal Integrity Simulations
- * Usually only needed with heavy load/very high speed (>DDR2-800)
+ * - TIMING_CFG_2 register
+ * Source: Signal Integrity Simulations
+ * Usually only needed with heavy load/very high speed (>DDR2-800)
*
* ====== XPedite550x DDR3-800 read delay calculations ======
*
const board_specific_parameters_t board_specific_parameters[][20] = {
{
/* Controller 0 */
- {
+ {
/* DDR3-600/667 */
.datarate_mhz_low = 500,
.datarate_mhz_high = 750,
.clk_adjust = 5,
.cpo = 31,
},
- {
+ {
/* DDR3-800 */
.datarate_mhz_low = 750,
.datarate_mhz_high = 850,
popts->rtt_override = 1;
popts->rtt_override_value = 3;
}
-
and start with code execution on this address.
- The First page contains u-boot code from u-boot:nand_spl/nand_boot_fsl_nfc.c
- which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE and loads
+ which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE and loads
the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
@CONFIG_SYS_NAND_U_BOOT_START
(gdb) add-symbol-file u-boot 0x8ff08000
add symbol table from file "u-boot" at
- .text_addr = 0x8ff08000
+ .text_addr = 0x8ff08000
(y or n) y
Reading symbols from /home/hs/celf/u-boot/u-boot...done.
(gdb) c
^C
Program received signal SIGSTOP, Stopped (signal).
0x8ff17f18 in serial_getc () at serial_mxc.c:192
-192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
(gdb)
add-symbol-file u-boot 0x8ff08000
- ^^^^^^^^^^
- get this address from u-boot debug printfs
+ ^^^^^^^^^^
+ get this address from u-boot debug printfs
U-Boot 2010.06-rc2-00009-gf77b8b8-dirty (Jun 22 2010 - 09:43:46)
LCD panel info: 640 x 480, 16 bit/pix
Reserving 600k for LCD Framebuffer at: 8ff6a000
Reserving 391k for U-Boot at: 8ff08000
- ^^^^^^^^
+ ^^^^^^^^
Reserving 1280k for malloc() at: 8fdc8000
Reserving 24 Bytes for Board Info at: 8fdc7fe8
Reserving 52 Bytes for Global Data at: 8fdc7fb4
relocation Offset is: eff08000
mon: 00058BAC gd->monLen: 00061F10
Now running in RAM - U-Boot at: 8ff08000
- ^^^^^^^^
+ ^^^^^^^^
Now you can use gdb as usual :-)
u32 reserved1;
u32 ifr;
u32 man;
- u32 reserved2[54]; // version and PDC not needed
+ u32 reserved2[54]; /* version and PDC not needed */
} atmel_usart3_t;
/* Bitfields in CR */
cp->bmAttributes |= USB_CONFIG_ATT_ONE;
return len;
}
-
error("%s failed. error = %d", __func__, status);
return status;
}
-
buf[1] = USB_DT_STRING;
return buf[0];
}
-
#define CONFIG_SYS_XLB_PIPELINING 1
#undef CONFIG_NET_MULTI
-#undef CONFIG_EEPRO100
+#undef CONFIG_EEPRO100
/* Partitions */
#define CONFIG_MAC_PARTITION
/*
* Processor Settings
*/
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 16384000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
+/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 3
-#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
+#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
/*
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
+ common/dlmalloc.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
+ . = DEFINED(env_offset) ? env_offset : .; \
+ common/env_embedded.o (.text .text.*);
#endif
* AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz
* One extra clock needed because AX88180 is asynchronous to CPU.
*/
- /* bank 1 0 */
+ /* bank 1 0 */
#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
- /* bank 3 2 */
+ /* bank 3 2 */
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
/* memory layout */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-
/*
* CS8900 Ethernet drivers
*/
#define CONFIG_BAUDRATE 115200
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ELF
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
#define CONFIG_BOOTFILE "mx1ads"
#undef _CONFIG_UART4 /* internal uart 4 */
#undef CONFIG_SILENT_CONSOLE /* use this to disable output */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#undef CONFIG_CMD_PING
#undef CONFIG_CMD_SOURCE
-
/*
* Boot options. Setting delay to -1 stops autostart count down.
*/
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
-
-
#define CONFIG_STACKSIZE (120<<10) /* stack size */
#ifdef CONFIG_USE_IRQ
* Select serial console configuration
*/
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_SOURCE
-
/*
* Boot options. Setting delay to -1 stops autostart count down.
* NOTE: Sending parameters to kernel depends on kernel version and
#define CONFIG_INITRD_TAG 1 /* send initrd params */
#undef CONFIG_VFD /* do not send framebuffer setup */
-
/*
* Malloc pool need to host env + 128 Kb reserve for other allocations.
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
-
-
#define CONFIG_STACKSIZE (120<<10) /* stack size */
#ifdef CONFIG_USE_IRQ
#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
-/*
- * Flash Controller settings
- */
-
-/*
- * Hardware drivers
- */
-
-
/*
* Configuration for FLASH memory for the Synertronixx board
*/
unsigned char readPort(void);
void sclock(void);
#endif
-
__u32 type; /* see FB_TYPE_* */
__u32 type_aux; /* Interleave for interleaved Planes */
__u32 visual; /* see FB_VISUAL_* */
- __u16 xpanstep; /* zero if no hardware panning */
- __u16 ypanstep; /* zero if no hardware panning */
- __u16 ywrapstep; /* zero if no hardware ywrap */
- __u32 line_length; /* length of a line in bytes */
- unsigned long mmio_start; /* Start of Memory Mapped I/O */
+ __u16 xpanstep; /* zero if no hardware panning */
+ __u16 ypanstep; /* zero if no hardware panning */
+ __u16 ywrapstep; /* zero if no hardware ywrap */
+ __u32 line_length; /* length of a line in bytes */
+ unsigned long mmio_start; /* Start of Memory Mapped I/O */
/* (physical address) */
- __u32 mmio_len; /* Length of Memory Mapped I/O */
+ __u32 mmio_len; /* Length of Memory Mapped I/O */
__u32 accel; /* Indicate to driver which */
/* specific chip/card we have */
__u16 reserved[3]; /* Reserved for future compatibility */
};
-#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
+#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
#define FB_NONSTD_REV_PIX_IN_B 2 /* order of pixels in each byte is reversed */
#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/
#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */
#define FB_ACTIVATE_MASK 15
/* values */
-#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */
+#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */
#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */
#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */
#define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/
-#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */
+#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */
#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
#define FB_SYNC_EXT 4 /* external sync */
-#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
-#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
+#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
+#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
/* vtotal = 144d/288n/576i => PAL */
/* vtotal = 121d/242n/484i => NTSC */
#define FB_SYNC_ON_GREEN 32 /* sync on green */
-#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
+#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
#define FB_VMODE_INTERLACED 1 /* interlaced */
#define FB_VMODE_DOUBLE 2 /* double scan */
#define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */
#define FB_VMODE_MASK 255
-#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
+#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
/*
* Display rotation support
*/
-#define FB_ROTATE_UR 0
-#define FB_ROTATE_CW 1
-#define FB_ROTATE_UD 2
-#define FB_ROTATE_CCW 3
+#define FB_ROTATE_UR 0
+#define FB_ROTATE_CW 1
+#define FB_ROTATE_UD 2
+#define FB_ROTATE_CCW 3
#define PICOS2KHZ(a) (1000000000UL/(a))
#define KHZ2PICOS(a) (1000000000UL/(a))
};
/* VESA Blanking Levels */
-#define VESA_NO_BLANKING 0
-#define VESA_VSYNC_SUSPEND 1
-#define VESA_HSYNC_SUSPEND 2
-#define VESA_POWERDOWN 3
+#define VESA_NO_BLANKING 0
+#define VESA_VSYNC_SUSPEND 1
+#define VESA_HSYNC_SUSPEND 2
+#define VESA_POWERDOWN 3
enum {
*/
#define FB_CUR_SETIMAGE 0x01
-#define FB_CUR_SETPOS 0x02
-#define FB_CUR_SETHOT 0x04
-#define FB_CUR_SETCMAP 0x08
+#define FB_CUR_SETPOS 0x02
+#define FB_CUR_SETHOT 0x04
+#define FB_CUR_SETCMAP 0x08
#define FB_CUR_SETSHAPE 0x10
#define FB_CUR_SETSIZE 0x20
-#define FB_CUR_SETALL 0xFF
+#define FB_CUR_SETALL 0xFF
struct fbcurpos {
__u16 x, y;
* if you own it
*/
#define FB_EVENT_RESUME 0x03
-/* An entry from the modelist was removed */
-#define FB_EVENT_MODE_DELETE 0x04
-/* A driver registered itself */
-#define FB_EVENT_FB_REGISTERED 0x05
-/* A driver unregistered itself */
-#define FB_EVENT_FB_UNREGISTERED 0x06
-/* CONSOLE-SPECIFIC: get console to framebuffer mapping */
-#define FB_EVENT_GET_CONSOLE_MAP 0x07
-/* CONSOLE-SPECIFIC: set console to framebuffer mapping */
-#define FB_EVENT_SET_CONSOLE_MAP 0x08
-/* A hardware display blank change occured */
-#define FB_EVENT_BLANK 0x09
-/* Private modelist is to be replaced */
-#define FB_EVENT_NEW_MODELIST 0x0A
+/* An entry from the modelist was removed */
+#define FB_EVENT_MODE_DELETE 0x04
+/* A driver registered itself */
+#define FB_EVENT_FB_REGISTERED 0x05
+/* A driver unregistered itself */
+#define FB_EVENT_FB_UNREGISTERED 0x06
+/* CONSOLE-SPECIFIC: get console to framebuffer mapping */
+#define FB_EVENT_GET_CONSOLE_MAP 0x07
+/* CONSOLE-SPECIFIC: set console to framebuffer mapping */
+#define FB_EVENT_SET_CONSOLE_MAP 0x08
+/* A hardware display blank change occured */
+#define FB_EVENT_BLANK 0x09
+/* Private modelist is to be replaced */
+#define FB_EVENT_NEW_MODELIST 0x0A
/* The resolution of the passed in fb_info about to change and
- all vc's should be changed */
+ all vc's should be changed */
#define FB_EVENT_MODE_CHANGE_ALL 0x0B
/* A software display blank change occured */
-#define FB_EVENT_CONBLANK 0x0C
-/* Get drawing requirements */
-#define FB_EVENT_GET_REQ 0x0D
-/* Unbind from the console if possible */
-#define FB_EVENT_FB_UNBIND 0x0E
+#define FB_EVENT_CONBLANK 0x0C
+/* Get drawing requirements */
+#define FB_EVENT_GET_REQ 0x0D
+/* Unbind from the console if possible */
+#define FB_EVENT_FB_UNBIND 0x0E
struct fb_event {
struct fb_info *info;
* format the hardware needs.
*/
-#define FB_PIXMAP_DEFAULT 1 /* used internally by fbcon */
-#define FB_PIXMAP_SYSTEM 2 /* memory is in system RAM */
-#define FB_PIXMAP_IO 4 /* memory is iomapped */
-#define FB_PIXMAP_SYNC 256 /* set if GPU can DMA */
+#define FB_PIXMAP_DEFAULT 1 /* used internally by fbcon */
+#define FB_PIXMAP_SYSTEM 2 /* memory is in system RAM */
+#define FB_PIXMAP_IO 4 /* memory is iomapped */
+#define FB_PIXMAP_SYNC 256 /* set if GPU can DMA */
struct fb_pixmap {
u8 *addr; /* pointer to memory */
u32 scan_align; /* alignment per scanline */
u32 access_align; /* alignment per read/write (bits) */
u32 flags; /* see FB_PIXMAP_* */
- u32 blit_x; /* supported bit block dimensions (1-32)*/
- u32 blit_y; /* Format: blit_x = 1 << (width - 1) */
- /* blit_y = 1 << (height - 1) */
- /* if 0, will be set to 0xffffffff (all)*/
+ u32 blit_x; /* supported bit block dimensions (1-32)*/
+ u32 blit_y; /* Format: blit_x = 1 << (width - 1) */
+ /* blit_y = 1 << (height - 1) */
+ /* if 0, will be set to 0xffffffff (all)*/
/* access methods */
void (*writeio)(struct fb_info *info, void *dst, void *src, unsigned int size);
void (*readio) (struct fb_info *info, void *dst, void *src, unsigned int size);
* meaning, it is set by the fb subsystem depending FOREIGN_ENDIAN flag
* and host endianness. Drivers should not use this flag.
*/
-#define FBINFO_BE_MATH 0x100000
+#define FBINFO_BE_MATH 0x100000
struct fb_info {
int node;
struct fb_pixmap pixmap; /* Image hardware mapper */
struct fb_pixmap sprite; /* Cursor hardware mapper */
struct fb_cmap cmap; /* Current cmap */
- struct list_head modelist; /* mode list */
+ struct list_head modelist; /* mode list */
struct fb_videomode *mode; /* current mode */
char *screen_base; /* Virtual address */
#define FBINFO_STATE_RUNNING 0
#define FBINFO_STATE_SUSPENDED 1
u32 state; /* Hardware state i.e suspend */
- void *fbcon_par; /* fbcon use-only private area */
+ void *fbcon_par; /* fbcon use-only private area */
/* From here on everything is device dependent */
void *par;
};
#define FBINFO_FLAG_MODULE FBINFO_MODULE
#define FBINFO_FLAG_DEFAULT FBINFO_DEFAULT
-// This will go away
+/* This will go away */
#if defined(__sparc__)
/* We map all of our framebuffers such that big-endian accesses
* are what we want, so the following is sufficient.
*/
-// This will go away
+/* This will go away */
#define fb_readb sbus_readb
#define fb_readw sbus_readw
#define fb_readl sbus_readl
#endif
-#define FB_LEFT_POS(p, bpp) (fb_be_math(p) ? (32 - (bpp)) : 0)
+#define FB_LEFT_POS(p, bpp) (fb_be_math(p) ? (32 - (bpp)) : 0)
#define FB_SHIFT_HIGH(p, val, bits) (fb_be_math(p) ? (val) >> (bits) : \
(val) << (bits))
#define FB_SHIFT_LOW(p, val, bits) (fb_be_math(p) ? (val) << (bits) : \
#define FB_MODE_IS_VESA 4
#define FB_MODE_IS_CALCULATED 8
#define FB_MODE_IS_FIRST 16
-#define FB_MODE_IS_FROM_VAR 32
+#define FB_MODE_IS_FROM_VAR 32
/* drivers/video/fbcmap.c */
#define __LINUX_KBUILD_H
#define DEFINE(sym, val) \
- asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+ asm volatile("\n->" #sym " %0 " #val : : "i" (val))
#define BLANK() asm volatile("\n->" : : )
* Remy Bohmer <linux@bohmer.net>
*/
-
-
#define USB_CDC_SUBCLASS_ACM 0x02
#define USB_CDC_SUBCLASS_ETHERNET 0x06
#define USB_CDC_SUBCLASS_WHCM 0x08
#define USB_CDC_PACKET_TYPE_BROADCAST (1 << 3)
#define USB_CDC_PACKET_TYPE_MULTICAST (1 << 4) /* filtered */
-
/*-------------------------------------------------------------------------*/
/*
__le16 wIndex;
__le16 wLength;
} __attribute__ ((packed));
-
/*
* [Aho,Sethi,Ullman] Compilers: Principles, Techniques and Tools, 1986
- * [Knuth] The Art of Computer Programming, part 3 (6.4)
+ * [Knuth] The Art of Computer Programming, part 3 (6.4)
*/
/*
if (htab->table[idx].used) {
/*
- * Further action might be required according to the
+ * Further action might be required according to the
* action value.
*/
unsigned hval2;
do {
/*
- * Because SIZE is prime this guarantees to
- * step through all available indices.
+ * Because SIZE is prime this guarantees to
+ * step through all available indices.
*/
if (idx <= hval2)
idx = htab->size + idx - hval2;
/* An empty bucket has been found. */
if (action == ENTER) {
/*
- * If table is full and another entry should be
- * entered return with error.
+ * If table is full and another entry should be
+ * entered return with error.
*/
if (htab->filled == htab->size) {
__set_errno(ENOMEM);
#endif
void qsort(void *base,
- size_t nel,
- size_t width,
- int (*comp)(const void *, const void *))
+ size_t nel,
+ size_t width,
+ int (*comp)(const void *, const void *))
{
size_t wgap, i, j, k;
char tmp;
return ret;
}
-
-
/* Verify FPGA addresslines */
static int fpga_post_addrline(ulong *address, ulong *base, ulong size)
{
projects / u-boot / commitdiff