arm: socfpga: Actually enable L2 cache

The L2 cache was never enabled in the v7_outer_cache_enable(), fix
this and enable the L2 cache.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index b110f5bb42ba317d9da64c00429e2433ca3a9224..a54d2b9faaa60a5201060c40f3d187b7b4eef656 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -54,14 +54,23 @@ void enable_caches(void)
 
 void v7_outer_cache_enable(void)
 {
-       /* disable the L2 cache */
-       writel(0, &pl310->pl310_ctrl);
+       /* Disable the L2 cache */
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
        /* enable BRESP, instruction and data prefetch, full line of zeroes */
        setbits_le32(&pl310->pl310_aux_ctrl,
                     L310_AUX_CTRL_DATA_PREFETCH_MASK |
                     L310_AUX_CTRL_INST_PREFETCH_MASK |
                     L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+       /* Enable the L2 cache */
+       setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+       /* Disable the L2 cache */
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
 
 /*