ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,

	PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
  processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
  across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
  processors
- Add register bit definitions for Memory Queue Configuration registers

Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 1c3632428cada5c58f552fd28362940512b9ea91..c7ed161fde3501c3c4708bfda52639bab3587d34 100644 (file)
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -2172,6 +2172,11 @@ static void program_memory_queue(unsigned long *dimm_populated,
        unsigned long i;
        unsigned long bank_0_populated = 0;
        phys_size_t total_size = 0;
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
+       unsigned long val;
+#endif
 
        /*------------------------------------------------------------------
         * Reset the rank_base_address.
@@ -2249,17 +2254,31 @@ static void program_memory_queue(unsigned long *dimm_populated,
                }
        }
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
+
        /*
-        * Enable high bandwidth access on 460EX/GT.
-        * This should/could probably be done on other
-        * PPC's too, like 440SPe.
+        * Enable high bandwidth access
         * This is currently not used, but with this setup
         * it is possible to use it later on in e.g. the Linux
         * EMAC driver for performance gain.
         */
        mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
        mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
+
+       /*
+        * Set optimal value for Memory Queue HB/LL Configuration registers
+        */
+
+       val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
+       mtdcr(SDRAM_CONF1HB, val);
+
+       val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+       mtdcr(SDRAM_CONF1LL, val);
+
+       val = (mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
+       mtdcr(SDRAM_CONFPATHB, val);
 #endif
 }
 

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index e2d04027815a8e44b430ce2f17764ad78bb8ddd7..281819af602db1df0fd816b18dc193f55cee4079 100644 (file)
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -138,7 +138,9 @@ void reconfigure_pll(u32 new_cpu_freq)
 void
 cpu_init_f (void)
 {
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || defined(CONFIG_405EX)   || \
+    defined(CONFIG_460GT) || defined(CONFIG_460SX)
        u32 val;
 #endif
 
@@ -301,6 +303,18 @@ cpu_init_f (void)
        val |= 0x400;
        mtsdr(SDR0_USB2HOST_CFG, val);
 #endif /* CONFIG_460EX */
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
+    defined(CONFIG_405EX) || defined(CONFIG_460SX)
+       /*
+        * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
+        */
+       val = (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+       mtdcr(plb0_acr, val);
+       val = (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+       mtdcr(plb1_acr, val);
+#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 }
 
 /*

diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index df787b3d4c7d961a2031263916956a3135f9a1da..0174d6235155473fc9b47247cb20a4825380dfc3 100644 (file)
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -259,23 +259,39 @@
 /*
  * Memory queue defines
  */
-#define SDRAMQ_DCR_BASE        0x040
-
-#define SDRAM_R0BAS    (SDRAMQ_DCR_BASE+0x0)   /* rank 0 base address & size  */
-#define SDRAM_R1BAS    (SDRAMQ_DCR_BASE+0x1)   /* rank 1 base address & size  */
-#define SDRAM_R2BAS    (SDRAMQ_DCR_BASE+0x2)   /* rank 2 base address & size  */
-#define SDRAM_R3BAS    (SDRAMQ_DCR_BASE+0x3)   /* rank 3 base address & size  */
-#define SDRAM_CONF1HB  (SDRAMQ_DCR_BASE+0x5)   /* configuration 1 HB          */
-#define SDRAM_ERRSTATHB        (SDRAMQ_DCR_BASE+0x7)   /* error status HB             */
-#define SDRAM_ERRADDUHB        (SDRAMQ_DCR_BASE+0x8)   /* error address upper 32 HB   */
-#define SDRAM_ERRADDLHB        (SDRAMQ_DCR_BASE+0x9)   /* error address lower 32 HB   */
-#define SDRAM_PLBADDULL        (SDRAMQ_DCR_BASE+0xA)   /* PLB base address upper 32 LL */
-#define SDRAM_CONF1LL  (SDRAMQ_DCR_BASE+0xB)   /* configuration 1 LL          */
-#define SDRAM_ERRSTATLL        (SDRAMQ_DCR_BASE+0xC)   /* error status LL             */
-#define SDRAM_ERRADDULL        (SDRAMQ_DCR_BASE+0xD)   /* error address upper 32 LL   */
-#define SDRAM_ERRADDLLL        (SDRAMQ_DCR_BASE+0xE)   /* error address lower 32 LL   */
-#define SDRAM_CONFPATHB        (SDRAMQ_DCR_BASE+0xF)   /* configuration between paths */
-#define SDRAM_PLBADDUHB        (SDRAMQ_DCR_BASE+0x10)  /* PLB base address upper 32 LL */
+#define SDRAMQ_DCR_BASE 0x040
+
+#define SDRAM_R0BAS            (SDRAMQ_DCR_BASE+0x0)   /* rank 0 base address & size  */
+#define SDRAM_R1BAS            (SDRAMQ_DCR_BASE+0x1)   /* rank 1 base address & size  */
+#define SDRAM_R2BAS            (SDRAMQ_DCR_BASE+0x2)   /* rank 2 base address & size  */
+#define SDRAM_R3BAS            (SDRAMQ_DCR_BASE+0x3)   /* rank 3 base address & size  */
+#define SDRAM_CONF1HB          (SDRAMQ_DCR_BASE+0x5)   /* configuration 1 HB          */
+#define SDRAM_CONF1HB_AAFR     0x80000000      /* Address Ack on First Request - Bit 0 */
+#define SDRAM_CONF1HB_PRPD     0x00080000      /* PLB Read pipeline Disable - Bit 12 */
+#define SDRAM_CONF1HB_PWPD     0x00040000      /* PLB Write pipeline Disable - Bit 13 */
+#define SDRAM_CONF1HB_PRW      0x00020000      /* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1HB_RPEN     0x00000800      /* Read Passing Enable - Bit 20 */
+#define SDRAM_CONF1HB_RFTE     0x00000400      /* Read Flow Through Enable - Bit 21 */
+
+#define SDRAM_ERRSTATHB                (SDRAMQ_DCR_BASE+0x7)   /* error status HB             */
+#define SDRAM_ERRADDUHB                (SDRAMQ_DCR_BASE+0x8)   /* error address upper 32 HB   */
+#define SDRAM_ERRADDLHB                (SDRAMQ_DCR_BASE+0x9)   /* error address lower 32 HB   */
+#define SDRAM_PLBADDULL                (SDRAMQ_DCR_BASE+0xA)   /* PLB base address upper 32 LL */
+#define SDRAM_CONF1LL          (SDRAMQ_DCR_BASE+0xB)   /* configuration 1 LL          */
+#define SDRAM_CONF1LL_AAFR     0x80000000              /* Address Ack on First Request - Bit 0 */
+#define SDRAM_CONF1LL_PRPD     0x00080000              /* PLB Read pipeline Disable - Bit 12 */
+#define SDRAM_CONF1LL_PWPD     0x00040000              /* PLB Write pipeline Disable - Bit 13 */
+#define SDRAM_CONF1LL_PRW      0x00020000              /* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1LL_RPEN     0x00000800              /* Read Passing Enable - Bit 20 */
+#define SDRAM_CONF1LL_RFTE     0x00000400              /* Read Flow Through Enable - Bit 21 */
+
+#define SDRAM_ERRSTATLL                (SDRAMQ_DCR_BASE+0xC)   /* error status LL             */
+#define SDRAM_ERRADDULL                (SDRAMQ_DCR_BASE+0xD)   /* error address upper 32 LL   */
+#define SDRAM_ERRADDLLL                (SDRAMQ_DCR_BASE+0xE)   /* error address lower 32 LL   */
+#define SDRAM_CONFPATHB                (SDRAMQ_DCR_BASE+0xF)   /* configuration between paths */
+#define SDRAM_CONFPATHB_TPEN   0x08000000              /* Transaction Passing Enable - Bit 4 */
+
+#define SDRAM_PLBADDUHB                (SDRAMQ_DCR_BASE+0x10)  /* PLB base address upper 32 LL */
 
 #if !defined(CONFIG_405EX)
 /*

diff --git a/include/ppc440.h b/include/ppc440.h
index 92db15f312af27f66045b36e68b4c7fe3b2c07e2..3584fd24e82ad2b008996eff0fc4b02587ba4776 100644 (file)
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -341,53 +341,6 @@
 
 #define PLB4_ACR_WRP           (0x80000000 >> 7)
 
-/* Nebula PLB4 Arbiter - PowerPC440EP */
-#define PLB_ARBITER_BASE   0x80
-
-#define plb0_revid                (PLB_ARBITER_BASE+ 0x00)
-#define plb0_acr                  (PLB_ARBITER_BASE+ 0x01)
-#define   plb0_acr_ppm_mask             0xF0000000
-#define   plb0_acr_ppm_fixed            0x00000000
-#define   plb0_acr_ppm_fair             0xD0000000
-#define   plb0_acr_hbu_mask             0x08000000
-#define   plb0_acr_hbu_disabled         0x00000000
-#define   plb0_acr_hbu_enabled          0x08000000
-#define   plb0_acr_rdp_mask             0x06000000
-#define   plb0_acr_rdp_disabled         0x00000000
-#define   plb0_acr_rdp_2deep            0x02000000
-#define   plb0_acr_rdp_3deep            0x04000000
-#define   plb0_acr_rdp_4deep            0x06000000
-#define   plb0_acr_wrp_mask             0x01000000
-#define   plb0_acr_wrp_disabled         0x00000000
-#define   plb0_acr_wrp_2deep            0x01000000
-
-#define plb0_besrl                (PLB_ARBITER_BASE+ 0x02)
-#define plb0_besrh                (PLB_ARBITER_BASE+ 0x03)
-#define plb0_bearl                (PLB_ARBITER_BASE+ 0x04)
-#define plb0_bearh                (PLB_ARBITER_BASE+ 0x05)
-#define plb0_ccr                  (PLB_ARBITER_BASE+ 0x08)
-
-#define plb1_acr                  (PLB_ARBITER_BASE+ 0x09)
-#define   plb1_acr_ppm_mask             0xF0000000
-#define   plb1_acr_ppm_fixed            0x00000000
-#define   plb1_acr_ppm_fair             0xD0000000
-#define   plb1_acr_hbu_mask             0x08000000
-#define   plb1_acr_hbu_disabled         0x00000000
-#define   plb1_acr_hbu_enabled          0x08000000
-#define   plb1_acr_rdp_mask             0x06000000
-#define   plb1_acr_rdp_disabled         0x00000000
-#define   plb1_acr_rdp_2deep            0x02000000
-#define   plb1_acr_rdp_3deep            0x04000000
-#define   plb1_acr_rdp_4deep            0x06000000
-#define   plb1_acr_wrp_mask             0x01000000
-#define   plb1_acr_wrp_disabled         0x00000000
-#define   plb1_acr_wrp_2deep            0x01000000
-
-#define plb1_besrl                (PLB_ARBITER_BASE+ 0x0A)
-#define plb1_besrh                (PLB_ARBITER_BASE+ 0x0B)
-#define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
-#define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
-
 /* Pin Function Control Register 1 */
 #define SDR0_PFC1                    0x4101
 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */

diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index c71da6084405cedde696408679eedab84e134faf..e1613ddcc848eb5ed9ee7179073e24a100bd4988 100644 (file)
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -46,6 +46,62 @@
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2   /* IBM DDR(2) controller */
 #endif
 
+/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
+#if defined(CONFIG_405EX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
+    defined(CONFIG_460SX)
+
+#define PLB_ARBITER_BASE               0x80
+
+#define plb0_revid                     (PLB_ARBITER_BASE+ 0x00)
+#define plb0_acr                       (PLB_ARBITER_BASE+ 0x01)
+#define plb0_acr_ppm_mask              0xF0000000
+#define plb0_acr_ppm_fixed             0x00000000
+#define plb0_acr_ppm_fair              0xD0000000
+#define plb0_acr_hbu_mask              0x08000000
+#define plb0_acr_hbu_disabled          0x00000000
+#define plb0_acr_hbu_enabled           0x08000000
+#define plb0_acr_rdp_mask              0x06000000
+#define plb0_acr_rdp_disabled          0x00000000
+#define plb0_acr_rdp_2deep             0x02000000
+#define plb0_acr_rdp_3deep             0x04000000
+#define plb0_acr_rdp_4deep             0x06000000
+#define plb0_acr_wrp_mask              0x01000000
+#define plb0_acr_wrp_disabled          0x00000000
+#define plb0_acr_wrp_2deep             0x01000000
+
+#define plb0_besrl                     (PLB_ARBITER_BASE+ 0x02)
+#define plb0_besrh                     (PLB_ARBITER_BASE+ 0x03)
+#define plb0_bearl                     (PLB_ARBITER_BASE+ 0x04)
+#define plb0_bearh                     (PLB_ARBITER_BASE+ 0x05)
+#define plb0_ccr                       (PLB_ARBITER_BASE+ 0x08)
+
+#define plb1_acr                       (PLB_ARBITER_BASE+ 0x09)
+#define plb1_acr_ppm_mask              0xF0000000
+#define plb1_acr_ppm_fixed             0x00000000
+#define plb1_acr_ppm_fair              0xD0000000
+#define plb1_acr_hbu_mask              0x08000000
+#define plb1_acr_hbu_disabled          0x00000000
+#define plb1_acr_hbu_enabled           0x08000000
+#define plb1_acr_rdp_mask              0x06000000
+#define plb1_acr_rdp_disabled          0x00000000
+#define plb1_acr_rdp_2deep             0x02000000
+#define plb1_acr_rdp_3deep             0x04000000
+#define plb1_acr_rdp_4deep             0x06000000
+#define plb1_acr_wrp_mask              0x01000000
+#define plb1_acr_wrp_disabled          0x00000000
+#define plb1_acr_wrp_2deep             0x01000000
+
+#define plb1_besrl                     (PLB_ARBITER_BASE+ 0x0A)
+#define plb1_besrh                     (PLB_ARBITER_BASE+ 0x0B)
+#define plb1_bearl                     (PLB_ARBITER_BASE+ 0x0C)
+#define plb1_bearh                     (PLB_ARBITER_BASE+ 0x0D)
+
+#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
+
 #if defined(CONFIG_440)
 /*
  * Enable long long (%ll ...) printf format on 440 PPC's since most of