MPC85xx: TQM8548: use cache for AG and BE variants

This patch makes accesses to the system memory cachable by removing the
caching-inhibited and guarded flags from the relevant TLB entries for
the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards
are configured similarly.

This results in a big averall performace improvement. TFTP downloads,
NAND Flash accesses, kernel boots, etc. are much faster.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>

diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index ad96dd11cf16f830a040b68522fa6dfe030f33c9..71fe3ab49608ad270ea59b988d68d98ad407d262 100644 (file)
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -128,12 +128,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * Without SPD EEPROM configured DDR, this must be setup manually.
         */
        SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+                      MAS3_SX | MAS3_SW | MAS3_SR, 0,
                       0, 7, BOOKE_PAGESZ_1G, 1),
 
        SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
                       CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-                      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+                      MAS3_SX | MAS3_SW | MAS3_SR, 0,
                       0, 8, BOOKE_PAGESZ_1G, 1),
 #else
        /*