__weak int dram_init(void)
{
- gd->ram_size = initdram();
+ initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#include <asm/addrspace.h>
#include <mach/ddr.h>
-phys_size_t initdram(void)
+DECLARE_GLOBAL_DATA_PTR;
+
+int initdram(void)
{
ddr_tap_tuning();
- return get_ram_size((void *)KSEG1, SZ_256M);
+ gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
+
+ return 0;
}
}
/* initialize the DDR2 Controller and DDR2 PHY */
-phys_size_t initdram(void)
+int initdram(void)
{
ddr2_pmd_ungate();
ddr2_phy_init();
ddr2_ctrl_init();
- return ddr2_calculate_size();
+ gd->ram_size = ddr2_calculate_size();
+
+ return 0;
}
int misc_init_r(void)
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
!defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(void)
+int initdram(void)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
defined(CONFIG_ARCH_QEMU_E500)
- return fsl_ddr_sdram_size();
+ gd->ram_size = fsl_ddr_sdram_size();
#else
- return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
+
+ return 0;
}
#else /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size = 0;
#endif
debug("DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
#endif
#include "ecc.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
do { \
u32 data; \
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
* Reduce RAM size to avoid overwriting memory used by
* current stack? Not sure what is happening.
*/
- return sdram_memsize() / 2;
+ gd->ram_size = sdram_memsize() / 2;
+
+ return 0;
}
num_dimm_banks = sizeof(iic0_dimm_addr);
*/
set_mcsr(get_mcsr());
- return sdram_memsize();
+ gd->ram_size = sdram_memsize();
+
+ return 0;
}
static void get_spd_info(unsigned long *dimm_populated,
* time parameters.
* Configures the PPC405EX(r) and PPC460EX/GT
*---------------------------------------------------------------------------*/
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned long val;
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
- return (CONFIG_SYS_MBYTES_SDRAM << 20);
+ gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+ return 0;
}
#endif /* CONFIG_SPD_EEPROM */
#include <asm/mmu.h>
#include <asm/cache.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_ranks[MAXDIMMS];
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
void board_add_ram_info(int use_default)
#include "sdram.h"
#include "ecc.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_SDRAM_BANK0
#ifndef CONFIG_440
/*
* Autodetect onboard SDRAM on 405 platforms
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong speed;
ulong sdtr1;
/*
* OK, size detected -> all done
*/
- return size;
+ gd->ram_size = size;
+
+ return 0;
}
}
- return 0;
+ return -ENXIO;
}
#else /* CONFIG_440 */
* so this should be extended for other future boards
* using this routine!
*/
-phys_size_t initdram(void)
+int initdram(void)
{
int i;
int tr1_bank1;
/*
* OK, size detected -> all done
*/
- return size;
+ gd->ram_size = size;
+
+ return 0;
}
}
- return 0; /* nothing found ! */
+ return -ENXIO; /* nothing found ! */
}
#endif /* CONFIG_440 */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
int size, i;
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
#endif
- return size;
+ gd->ram_size = size;
+
+ return 0;
}
#if defined(CONFIG_SYS_DRAM_TEST)
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
static void get_revisions(int *failsavelevel, int *digiboardversion,
#include "mt46v32m16.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
* is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
uint svr, pvr;
__asm__ volatile ("sync");
}
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
}
int checkboard (void)
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
+DECLARE_GLOBAL_DATA_PTR;
+
extern void board_pll_init_f(void);
static void cram_bcr_write(u32 wr_val)
return;
}
-phys_size_t initdram(void)
+int initdram(void)
{
int i;
u32 val;
for (i=0; i<200000; i++)
;
- return (CONFIG_SYS_MBYTES_RAM << 20);
+ gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20;
+
+ return 0;
}
#include <asm/ppc440.h>
#include "bamboo.h"
+DECLARE_GLOBAL_DATA_PTR;
+
void ext_bus_cntlr_init(void);
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
}
-phys_size_t initdram(void)
+int initdram(void)
{
- return spd_sdram();
+ gd->ram_size = spd_sdram();
+
+ return 0;
}
/*----------------------------------------------------------------------------+
#include <asm/processor.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
long int spd_sdram(void);
int board_early_init_f(void)
initdram() reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
-phys_size_t initdram(void)
+int initdram(void)
{
- return spd_sdram();
+ gd->ram_size = spd_sdram();
+
+ return 0;
}
#include <asm/io.h>
#include <asm/ppc440.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*-----------------------------------------------------------------------------+
* Prototypes
*-----------------------------------------------------------------------------*/
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-phys_size_t initdram(void)
+int initdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
ulong speed = get_bus_freq(0);
*/
set_mcsr(get_mcsr());
- return (CONFIG_SYS_MBYTES_SDRAM << 20);
+ gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+ return 0;
}
#include <asm/processor.h>
#include <spd_sdram.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int board_early_init_f(void)
{
/*-------------------------------------------------------------------------+
* initdram() reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
*/
-phys_size_t initdram(void)
+int initdram(void)
{
- return spd_sdram();
+ gd->ram_size = spd_sdram();
+
+ return 0;
}
*tr1_value = (first_good + last_bad) / 2;
}
-phys_size_t initdram(void)
+int initdram(void)
{
register uint reg;
int tr1_bank1, tr1_bank2;
sdram_tr1_set(0x08000000, &tr1_bank2);
mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
- return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
+ gd->ram_size = CONFIG_SYS_SDRAM_BANKS *
+ (CONFIG_SYS_KBYTES_SDRAM * 1024); /* set bytes */
+
+ return 0;
}
/*************************************************************************
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
* (Do not rely on the SDCS register(s) being set to 0x00000000
* during reset as stated in the data sheet.)
*/
- return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
0x80000000 - CONFIG_SYS_SDRAM_BASE);
+
+ return 0;
}
#define UART_BASE MMAP_UART0
#include "mt48lc16m32s2-75.h"
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
* is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#endif /* CONFIG_SYS_RAMBOOT */
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
int checkboard (void)
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
__asm__ volatile ("sync");
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
}
#include <common.h>
#include <asm/immap.h>
+DECLARE_GLOBAL_DATA_PTR;
int checkboard (void)
{
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
/* Dummy write to start SDRAM */
*((volatile unsigned long *) 0) = 0;
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+ return 0;
};
int testdram (void)
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t initdram(void)
+int initdram(void)
{
- return fixed_sdram(NULL, NULL, 0);
+ gd->ram_size = fixed_sdram(NULL, NULL, 0);
+
+ return 0;
}
int misc_init_r(void)
#include <asm/mipsregs.h>
#include <asm/io.h>
-phys_size_t initdram(void)
+DECLARE_GLOBAL_DATA_PTR;
+
+int initdram(void)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
- return MEM_SIZE*1024*1024;
+ gd->ram_size = MEM_SIZE * 1024 * 1024;
+
+ return 0;
}
#define BCSR_PCMCIA_PC0DRVEN 0x0010
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
- return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+ gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+
+ return 0;
}
int misc_init_r(void)
#include <asm/mmu.h>
#include <asm/ppc440.h>
+DECLARE_GLOBAL_DATA_PTR;
+
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t size;
int n;
sdram_conf[n].banks);
/* check for suitable configuration */
- if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
- return size;
+ if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) {
+ gd->ram_size = size;
+ return 0;
+ }
/* delete TLB entries */
remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
}
- return 0;
+ return -ENXIO;
}
#include <i2c.h>
#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void ddr_enable_ecc(unsigned int dram_size);
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM - Main memory */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = get_ram_size(0, msize);
/* return total bus SDRAM size(bytes) -- DDR */
- return msize * 1024 * 1024;
+ gd->ram_size = msize * 1024 * 1024;
+
+ return 0;
}
int checkboard(void)
popts->cpo_sample = 0x3e;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
puts("\n\n");
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_NAND_BOOT
nand_boot();
i2c_init_all();
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("TPL\n");
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
dram_size *= 0x100000;
debug(" DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
}
#endif
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
fsl_dp_resume();
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
void dram_init_banksize(void)
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- gd->ram_size = initdram();
-
- return 0;
+ return initdram();
}
#ifdef CONFIG_FSL_ESDHC
#endif
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
fsl_dp_ddr_restore();
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- gd->ram_size = initdram();
+ initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
}
#endif
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
fsl_dp_ddr_restore();
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
popts->cpo_sample = 0x70;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
erratum_a008850_post();
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- gd->ram_size = initdram();
+ initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
popts->cpo_sample = 0x70;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
erratum_a008850_post();
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
return 0;
}
#endif
-phys_size_t initdram(void)
+int initdram(void)
{
- phys_size_t dram_size;
-
puts("Initializing DDR....");
puts("using SPD\n");
- dram_size = fsl_ddr_sdram();
+ gd->ram_size = fsl_ddr_sdram();
- return dram_size;
+ return 0;
}
}
}
-phys_size_t initdram(void)
+int initdram(void)
{
- phys_size_t dram_size;
-
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- return fsl_ddr_sdram_size();
+ gd->ram_size = fsl_ddr_sdram_size();
#else
puts("Initializing DDR....using SPD\n");
- dram_size = fsl_ddr_sdram();
+ gd->ram_size = fsl_ddr_sdram();
#endif
- return dram_size;
+ return 0;
}
}
}
-phys_size_t initdram(void)
+int initdram(void)
{
- phys_size_t dram_size;
-
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- return fsl_ddr_sdram_size();
+ gd->ram_size = fsl_ddr_sdram_size();
#else
puts("Initializing DDR....using SPD\n");
- dram_size = fsl_ddr_sdram();
+ gd->ram_size = fsl_ddr_sdram();
#endif
- return dram_size;
+ return 0;
}
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
udelay(100);
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
u32 dramsize;
udelay(100);
#endif
- return (dramsize);
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
#include <malloc.h>
#include <asm/immap.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard (void) {
ulong val;
uchar val8;
};
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned long junk = 0xa5a59696;
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+ return 0;
};
#include <netdev.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("Board: ");
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
u32 dramsize = 0;
mb();
}
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
}
int testdram(void)
#include <asm/immap.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("Board: ");
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
/*
* Check to see if the SDRAM has already been initialized
*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
}
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+ return 0;
}
int testdram(void)
#include <asm/immap.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
int checkboard (void) {
puts ("Board: ");
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+ return 0;
};
int testdram (void) {
#include <asm/immap.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define PERIOD 13 /* system bus period in ns */
#define SDRAM_TREFI 7800 /* in ns */
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
| MCF_SDRAMC_SDCR_DQS_OE(0x3));
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+ return 0;
};
int testdram(void)
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
u32 dramsize, i, dramclk;
/* Write to the SDRAM Mode Register */
*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
}
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
udelay(100);
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
udelay(100);
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
udelay(100);
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
u32 dramsize;
udelay(100);
#endif
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
udelay(100);
#endif
- return (dramsize);
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
udelay(100);
#endif
- return (dramsize << 1);
+ gd->ram_size = dramsize << 1;
+
+ return 0;
};
int testdram(void)
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
siu_t *siu = (siu_t *) (MMAP_SIU);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
udelay(100);
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
return 0;
};
-phys_size_t initdram(void)
+int initdram(void)
{
siu_t *siu = (siu_t *) (MMAP_SIU);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
udelay(100);
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
};
int testdram(void)
return(ismicron);
}
-phys_size_t initdram(void)
+int initdram(void)
{
u32 msize = 0;
/*
sizeof(elpida_init_sequence)/sizeof(u32));
}
- return msize;
+ gd->ram_size = msize;
+
+ return 0;
}
int misc_init_r(void)
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
}
-phys_size_t initdram(void)
+int initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize;
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM */
msize = fixed_sdram();
/* return total bus SDRAM size(bytes) -- DDR */
- return msize;
+ gd->ram_size = msize;
+
+ return 0;
}
return msize;
}
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM - Main SODIMM */
msize = fixed_sdram();
#endif
/* return total bus SDRAM size(bytes) -- DDR */
- return msize;
+ gd->ram_size = msize;
+
+ return 0;
}
}
#endif /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM */
msize = fixed_sdram();
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
resume_from_sleep();
- /* return total bus SDRAM size(bytes) -- DDR */
- return msize;
+ /* set total bus SDRAM size(bytes) -- DDR */
+ gd->ram_size = msize;
+
+ return 0;
}
#endif
#include <asm/mmu.h>
+DECLARE_GLOBAL_DATA_PTR;
+
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* UCC3 */
{1, 0, 1, 0, 1}, /* TxD0 */
int fixed_sdram(void);
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
+ /* set total bus SDRAM size(bytes) -- DDR */
+ gd->ram_size = msize * 1024 * 1024;
+
+ return 0;
}
/*************************************************************************
#include "../common/pq-mds-pib.h"
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* ETH3 */
{1, 0, 1, 0, 1}, /* TxD0 */
int fixed_sdram(void);
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
+ /* set total bus SDRAM size(bytes) -- DDR */
+ gd->ram_size = msize * 1024 * 1024;
+
+ return 0;
}
/*************************************************************************
#include <libfdt.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
int fixed_sdram(void);
void sdram_init(void);
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
phys_size_t msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
*/
sdram_init();
- /* return total bus SDRAM size(bytes) -- DDR */
- return msize;
+ /* set total bus SDRAM size(bytes) -- DDR */
+ gd->ram_size = msize;
+
+ return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
#include <libfdt.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SPD_EEPROM
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
};
#endif /* CONFIG_PCI */
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
#endif
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#endif
/* return total bus RAM size(bytes) */
- return msize * 1024 * 1024;
+ gd->ram_size = msize * 1024 * 1024;
+
+ return 0;
}
int checkboard(void)
#include "pci.h"
#include "../common/pq-mds-pib.h"
+DECLARE_GLOBAL_DATA_PTR;
+
int board_early_init_f(void)
{
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
#endif
int fixed_sdram(void);
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
+ return -ENXIO;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#endif
/* return total bus DDR size(bytes) */
- return (msize * 1024 * 1024);
+ gd->ram_size = msize * 1024 * 1024;
+
+ return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
#include <vsc7385.h>
#include <fsl_esdhc.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
#endif
int fixed_sdram(void);
-phys_size_t initdram(void)
+int initdram(void)
{
immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
+ return -ENXIO;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
ddr_enable_ecc(msize * 1024 * 1024);
#endif
/* return total bus DDR size(bytes) */
- return (msize * 1024 * 1024);
+ gd->ram_size = msize * 1024 * 1024;
+
+ return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void sdram_init(void);
phys_size_t fixed_sdram(void);
int mpc8610hpcd_diu_init(void);
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size = 0;
setup_ddr_bat(dram_size);
debug(" DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
#include <fdt_support.h>
#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+
phys_size_t fixed_sdram(void);
int checkboard(void)
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size = 0;
setup_ddr_bat(dram_size);
debug(" DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
i2c_init_all();
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("\nTertiary program loader running in sram...");
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+DECLARE_GLOBAL_DATA_PTR;
+
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size = 0;
dram_size = fsl_ddr_sdram();
} else {
puts("no SPD and fixed parameters\n");
- return dram_size;
+ return -ENXIO;
}
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
debug(" DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
}
#endif
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
fsl_dp_resume();
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
i2c_init_all();
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
}
#endif
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
fsl_dp_resume();
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
i2c_init_all();
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
}
#endif
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
fsl_dp_resume();
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
}
#endif
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
fsl_dp_resume();
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
puts("\n\n");
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x64;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
i2c_init_all();
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x54;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
i2c_init_all();
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x63;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
i2c_init_all();
- gd->ram_size = initdram();
+ initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x64;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
i2c_init_all();
- gd->ram_size = initdram();
+ initdram();
mmc_boot();
}
#include <config.h>
#include <asm/leon.h>
-phys_size_t initdram(void)
+int initdram(void)
{
- return 1;
+ /* Does not set gd->ram_size here */
+
+ return 0;
}
int checkboard(void)
#include <config.h>
#include <asm/leon.h>
-phys_size_t initdram(void)
+int initdram(void)
{
- return 1;
+ /* Does not set gd->ram_size here */
+
+ return 0;
}
int checkboard(void)
#include <config.h>
#include <asm/leon.h>
-phys_size_t initdram(void)
+int initdram(void)
{
- return 1;
+ /* Does not set gd->ram_size here */
+
+ return 0;
}
int checkboard(void)
#include <common.h>
#include <asm/leon.h>
-phys_size_t initdram(void)
+int initdram(void)
{
- return 1;
+ /* Does not set gd->ram_size here */
+
+ return 0;
}
int checkboard(void)
#include <common.h>
#include <asm/leon.h>
-phys_size_t initdram(void)
+int initdram(void)
{
- return 1;
+ /* Does not set gd->ram_size here */
+
+ return 0;
}
int checkboard(void)
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
}
-phys_size_t initdram(void)
+int initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize;
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
+ return -ENXIO;
/* DDR SDRAM */
msize = fixed_sdram();
/* return total bus SDRAM size(bytes) -- DDR */
- return msize;
+ gd->ram_size = msize;
+
+ return 0;
}
return msize;
}
-phys_size_t initdram(void)
+int initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
fsl_lbc_t *lbc = &im->im_lbc;
u32 msize = 0;
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
+ return -ENXIO;
msize = setup_sdram();
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
sync();
- return msize;
+ gd->ram_size = msize;
+
+ return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
/* EMPTY, optional, we don't do it */
};
-phys_size_t initdram(void)
+int initdram(void)
{
- return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
+ gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
+ ARRAY_SIZE(sdram_init_seq));
+
+ return 0;
}
int misc_init_r(void)
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
struct mpc5xxx_mmap_ctl *mmap_ctl =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
out_be32(&sdram->sdelay, 0x04);
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
#include "boston-regs.h"
-phys_size_t initdram(void)
+DECLARE_GLOBAL_DATA_PTR;
+
+int initdram(void)
{
u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
- return (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) << 30;
+ gd->ram_size = (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) <<
+ 30;
+
+ return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
#include "superio.h"
+DECLARE_GLOBAL_DATA_PTR;
+
enum core_card {
CORE_UNKNOWN,
CORE_LV,
}
}
-phys_size_t initdram(void)
+int initdram(void)
{
- return CONFIG_SYS_MEM_SIZE;
+ gd->ram_size = CONFIG_SYS_MEM_SIZE;
+
+ return 0;
}
int checkboard(void)
#include <common.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* initialize the DDR Controller and PHY */
-phys_size_t initdram(void)
+int initdram(void)
{
/* MIG IP block is smart and doesn't need SW
* to do any init */
- return CONFIG_SYS_SDRAM_SIZE; /* in bytes */
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */
+
+ return 0;
}
#error "INKA4x0 SDRAM: invalid chip type specified!"
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
* is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
}
#endif /* CONFIG_SYS_RAMBOOT */
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
}
int checkboard (void)
* CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
int checkboard(void)
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
struct mpc5xxx_mmap_ctl *mmap_ctl =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
*/
out_be32 (&sdram->sdelay, 0x04);
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
int checkboard (void)
#define SDRAM_CONFIG2 0x88b70004
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
* is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
__asm__ volatile ("sync");
}
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
int checkboard (void)
#include <i2c.h>
#include "../common/common.h"
+DECLARE_GLOBAL_DATA_PTR;
+
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
/*
#endif /* CONFIG_SYS_SDRAM_LIST */
-phys_size_t initdram(void)
+int initdram(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
memctl8260_t *memctl = &immap->im_memctl;
icache_enable();
- return psize;
+ gd->ram_size = psize;
+
+ return 0;
}
int checkboard(void)
#include "../common/common.h"
+DECLARE_GLOBAL_DATA_PTR;
+
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
const qe_iop_conf_t qe_iop_conf_tab[] = {
return msize;
}
-phys_size_t initdram(void)
+int initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
+ return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar,
CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
#endif
/* return total bus SDRAM size(bytes) -- DDR */
- return msize * 1024 * 1024;
+ gd->ram_size = msize * 1024 * 1024;
+
+ return 0;
}
int checkboard(void)
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size = 0;
dram_size *= 0x100000;
debug(" DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
#include <asm/ppc440.h>
#include <watchdog.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
* region. Right now the cache should still be disabled in U-Boot because of the
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-phys_size_t initdram(void)
+int initdram(void)
{
/* CL=4 */
mtsdram(DDR0_02, 0x00000000);
*/
set_mcsr(get_mcsr());
- return (CONFIG_SYS_MBYTES_SDRAM << 20);
+ gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+ return 0;
}
#define BOARD_NAME_ADD " NOR"
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
int board_early_init_f(void)
{
/*
* SDRAM is already configured by the bootstrap code, only return the
* auto-detected size here
*/
-phys_size_t initdram(void)
+int initdram(void)
{
- return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_MBYTES_SDRAM << 20);
+
+ return 0;
}
int checkboard(void)
#include <status_led.h>
#endif /* CONFIG_LED_STATUS */
+DECLARE_GLOBAL_DATA_PTR;
+
/* Kollmorgen DPR initialization data */
struct init_elem {
unsigned long addr;
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
#endif /* CONFIG_SYS_RAMBOOT */
/* return total ram size */
- return dramsize;
+ gd->ram_size = dramsize;
+
+ return 0;
}
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
}
-phys_size_t initdram(void)
+int initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize;
/* DDR SDRAM */
msize = fixed_sdram();
- /* return total bus SDRAM size(bytes) -- DDR */
- return msize;
+ /* set total bus SDRAM size(bytes) -- DDR */
+ gd->ram_size = msize;
+
+ return 0;
}
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned long bank_reg[4], tmp, bank_size;
printf ("ECC ");
test_dram (TotalSize * MEGA_BYTE);
- return (TotalSize * MEGA_BYTE);
+ gd->ram_size = TotalSize * MEGA_BYTE;
+
+ return 0;
}
/* ------------------------------------------------------------------------- */
asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+DECLARE_GLOBAL_DATA_PTR;
+
/************************************************************************
* Early debug routines
*/
/*
* Get RAM size.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned char board_rev;
unsigned long reg;
/* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
lmr<<=2;
in32(CONFIG_SYS_SDRAM_BASE + lmr);
- /* ok, we're done, return SDRAM size */
- return ((0x400000 << sdram_table[i].sz)); /* log2 value of 4MByte */
+ /* ok, we're done, set SDRAM size to log2 value of 4MByte*/
+ gd->ram_size = 0x400000 << sdram_table[i].sz;
+
+ return 0;
}
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned long bank_reg[4], tmp, bank_size;
int i, ds;
(void) get_clocks();
if (gd->cpu_clk > 220000000)
TotalSize /= 2;
- return (TotalSize * 1024 * 1024);
+ gd->ram_size = TotalSize * 1024 * 1024;
+
+ return 0;
}
/* ------------------------------------------------------------------------- */
#include "mt48lc16m16a2-75.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
* is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#endif /* CONFIG_SYS_RAMBOOT */
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
int checkboard (void)
#include <asm/mipsregs.h>
#include <asm/io.h>
-phys_size_t initdram(void)
+DECLARE_GLOBAL_DATA_PTR;
+
+int initdram(void)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
- return 64*1024*1024;
+ gd->ram_size = 64 * 1024 * 1024;
+
+ return 0;
}
#define BCSR_PCMCIA_PC0DRVEN 0x0010
},
};
-phys_size_t initdram(void)
+int initdram(void)
{
int i;
u32 msize = 0;
break;
}
- return msize;
+ gd->ram_size = msize;
+
+ return 0;
}
static int set_lcd_brightness(char *);
#include "mt46v32m16-75.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
{
* is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
#endif /* CONFIG_SYS_RAMBOOT */
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
int checkboard(void)
#include <asm/io.h>
#include <netdev.h>
-phys_size_t initdram(void)
+DECLARE_GLOBAL_DATA_PTR;
+
+int initdram(void)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
- return MEM_SIZE*1024*1024;
+ gd->ram_size = MEM_SIZE * 1024 * 1024;
+
+ return 0;
}
int checkboard(void)
#include <libfdt.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
int fixed_sdram(void);
void sdram_init(void);
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
+ /* set total bus SDRAM size(bytes) -- DDR */
+ gd->ram_size = msize * 1024 * 1024;
+
+ return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
#include <libfdt.h>
#include <fdt_support.h>
+DECLARE_GLOBAL_DATA_PTR;
+
long int fixed_sdram (void);
int board_early_init_f (void)
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
long dram_size = 0;
#endif
debug (" DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
#if defined(CONFIG_SYS_DRAM_TEST)
#include <dm.h>
#include <dm/platform_data/serial_coldfire.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void init_lcd(void)
{
/* setup for possible K0108 lcd connected on the parallel port */
asm volatile ("nop");
}
-phys_size_t initdram(void)
+int initdram(void)
{
u32 dramsize, RC;
out_be32(&dc->dacr0, 0x0000b344);
out_be32((u32 *)0x00000c00, 0xbeaddeed);
- return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
}
static struct coldfire_serial_platdata mcf5307_serial_plat = {
* is something else than 0x00000000.
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
}
#if defined(CONFIG_TQM5200_B)
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
#else
- return dramsize;
+ gd->ram_size = dramsize;
#endif /* CONFIG_TQM5200_B */
+
+ return 0;
}
int checkboard (void)
/**************************************************************************
* DRAM initalization and size detection
*/
-phys_size_t initdram(void)
+int initdram(void)
{
long bank_size;
long size;
if(size < DDR_MAX_SIZE_PER_CS) break;
}
- return size;
+ gd->ram_size = size;
+
+ return 0;
}
/**************************************************************************
/* ------------------------------------------------------------------------- */
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
#endif /* CONFIG_ISP1362_USB */
- return (size_b0 + size_b1);
+ gd->ram_size = size_b0 + size_b1;
+
+ return 0;
}
/* ------------------------------------------------------------------------- */
#include <net.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
#endif /* !CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(void)
+int initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
__asm__ volatile ("sync");
}
- return dramsize + dramsize2;
+ gd->ram_size = dramsize + dramsize2;
+
+ return 0;
}
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size;
dram_size *= 0x100000;
debug(" DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
return msize;
}
-phys_size_t initdram(void)
+int initdram(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &im->im_lbc;
sync();
/* return total bus SDRAM size(bytes) -- DDR */
- return msize;
+ gd->ram_size = msize;
+
+ return 0;
}
#define VE8313_WDT_EN 0x00020000
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
- return spd_sdram();
+ gd->ram_size = spd_sdram();
+
+ return 0;
}
/*
#include <pca953x.h>
#include "../common/fsl_8xxx_misc.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
extern void ft_board_pci_setup(void *blob, bd_t *bd);
#endif
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size = fsl_ddr_sdram();
ddr_enable_ecc(dram_size);
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
#include <common.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
ulong get_PCI_freq(void)
{
return 0;
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
- return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+ gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+
+ return 0;
}
void get_sys_info(sys_info_t *sys_info)
#include <netdev.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("Xilinx PPC440 Generic Board\n");
return 0;
}
-phys_size_t initdram(void)
+int initdram(void)
{
- return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+ gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+
+ return 0;
}
void get_sys_info(sys_info_t *sys_info)
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int init_func_ram(void)
{
- gd->ram_size = initdram();
-
- if (gd->ram_size > 0)
- return 0;
-
- puts("*** failed ***\n");
- return 1;
+ return initdram();
}
#endif
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
* of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
int cpu_init(void);
/* */
-phys_size_t initdram(void);
+int initdram(void);
#include <display_options.h>
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