E: ThomasF@hyperion-entertainment.com
D: Support for AmigaOne
-N: Niklaus Giger
-E: niklaus.giger@netstal.com
-D: Support for HCU(x) boards
-W: www.netstal.com
-
N: Paul Gortmaker
E: paul.gortmaker@windriver.com
D: Support for WRS SBC8347/8349 boards
WUH405 PPC405EP
CMS700 PPC405EP
-Niklaus Giger <niklaus.giger@netstal.com>
-
- HCU4 PPC405GPr
- MCU25 PPC405GPr
- HCU5 PPC440EPx
-
Siddarth Gore <gores@marvell.com>
guruplug ARM926EJS (Kirkwood SoC)
$(obj)board/voiceblue/eeprom \
$(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
$(obj)u-boot.lds \
- $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]
+ $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
+ $(obj)arch/blackfin/cpu/init.{lds,elf}
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
/lib Architecture specific library files
/mips Files generic to MIPS architecture
/cpu CPU specific files
+ /mips32 Files specific to MIPS32 CPUs
/lib Architecture specific library files
/nios2 Files generic to Altera NIOS2 architecture
/cpu CPU specific files
2. The core frequency as calculated above is multiplied
by this value.
+- MIPS CPU options:
+ CONFIG_SYS_INIT_SP_OFFSET
+
+ Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
+ pointer. This is needed for the temporary stack before
+ relocation.
+
+ CONFIG_SYS_MIPS_CACHE_MODE
+
+ Cache operation mode for the MIPS CPU.
+ See also arch/mips/include/asm/mipsregs.h.
+ Possible values are:
+ CONF_CM_CACHABLE_NO_WA
+ CONF_CM_CACHABLE_WA
+ CONF_CM_UNCACHED
+ CONF_CM_CACHABLE_NONCOHERENT
+ CONF_CM_CACHABLE_CE
+ CONF_CM_CACHABLE_COW
+ CONF_CM_CACHABLE_CUW
+ CONF_CM_CACHABLE_ACCELERATED
+
+ CONFIG_SYS_XWAY_EBU_BOOTCFG
+
+ Special option for Lantiq XWAY SoCs for booting from NOR flash.
+ See also arch/mips/cpu/mips32/start.S.
+
+ CONFIG_XWAY_SWAP_BYTES
+
+ Enable compilation of tools/xway-swap-bytes needed for Lantiq
+ XWAY SoCs for booting from NOR flash. The U-Boot image needs to
+ be swapped if a flash programmer is used.
+
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
globally (CONFIG_CMD_MEM).
- CONFIG_SKIP_LOWLEVEL_INIT
- [ARM only] If this variable is defined, then certain
+ [ARM, MIPS only] If this variable is defined, then certain
low level initializations (like setting up the memory
controller) are omitted and/or U-Boot does not
relocate itself into RAM.
All contributions to U-Boot should conform to the Linux kernel
coding style; see the file "Documentation/CodingStyle" and the script
-"scripts/Lindent" in your Linux kernel source directory. In sources
-originating from U-Boot a style corresponding to "Lindent -pcs" (adding
-spaces before parameters to function calls) is actually used.
+"scripts/Lindent" in your Linux kernel source directory.
Source files originating from a different project (for example the
MTD subsystem) are generally exempt from these guidelines and are not
Please also stick to the following formatting rules:
- remove any trailing white space
-- use TAB characters for indentation, not spaces
+- use TAB characters for indentation and vertical alignment, not spaces
- make sure NOT to use DOS '\r\n' line feeds
-- do not add more than 2 empty lines to source files
+- do not add more than 2 consecutive empty lines to source files
- do not add trailing empty lines to source files
Submissions which do not conform to the standards may be returned
* For major contributions, your entry to the CREDITS file
* When you add support for a new board, don't forget to add this
- board to the MAKEALL script, too.
+ board to the MAINTAINERS file, too.
* If your patch adds new configuration options, don't forget to
document these in the README file.
* The patch itself. If you are using git (which is *strongly*
recommended) you can easily generate the patch using the
- "git-format-patch". If you then use "git-send-email" to send it to
+ "git format-patch". If you then use "git send-email" to send it to
the U-Boot mailing list, you will avoid most of the common problems
with some other mail clients.
/* Command 16 to read aBlocks from the MMC/SD - caed */
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
- /* The addres on the MMC/SD-card is in bytes,
+ /* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
/* Command 24 to write a block to the MMC/SD - card */
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
- /* The addres on the MMC/SD-card is in bytes,
+ /* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-/* Interupt-Controller base addresses */
+/* Interrupt-Controller base addresses */
INTMR1: .word 0x80000280 @ 32 bit size
INTMR2: .word 0x80001280 @ 16 bit size
INTMR3: .word 0x80002280 @ 8 bit size
when the value in TC_RC is reached */
writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
- writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
+ writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
# if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
&dispatchQInfo[qId].statusMask);
- /* Set the interupt source is this queue is in the range 0-31 */
+ /* Set the interrupt source is this queue is in the range 0-31 */
if (qId < IX_QMGR_MIN_QUEUPP_QID)
{
ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
BOOL portInitialized;
UINT32 npeId; /**< NpeId for this port */
IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
- IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
+ IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
} IxEthAccPortDataInfo;
extern IxEthAccPortDataInfo ixEthAccPortData[];
*/
typedef struct
{
- UINT32 rxBitField; /**< Recieved bit field */
+ UINT32 rxBitField; /**< Received bit field */
UINT32 atmCellHeader; /**< ATM Cell Header */
UINT32 rsvdWord0; /**< Reserved field */
UINT16 currMbufLen; /**< Mbuf Length */
* @brief Queue interrupt source select.
*
* This enum defines the different source conditions on a queue that result in
- * an interupt being fired by the AQM. Interrupt source is configurable for
+ * an interrupt being fired by the AQM. Interrupt source is configurable for
* queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
* NE(Nearly Empty) status flag.
*
*
* @def IX_ETH_ACC_RX_FRAME_ETH_Q
*
-* @brief Eth0/Eth1 NPE Frame Recieve Q.
+* @brief Eth0/Eth1 NPE Frame Receive Q.
*
* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
*
msr cpsr,r0
#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
-#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
+#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */
#define pCLKSET 0x80000420 /* clock divisor register */
/* disable watchdog, set watchdog control register to
*/
-/* Interupt-Controller base address */
+/* Interrupt-Controller base address */
IC_BASE: .word 0x90050000
#define ICMR 0x04
void setup_serial_tag (struct tag **params);
void setup_revision_tag (struct tag **params);
-/* ------------------------------------------------------------ */
-/* Here is a list of some prototypes which are incompatible to */
-/* the U-Boot implementation */
-/* To be fixed! */
-/* ------------------------------------------------------------ */
-/* common/cmd_nvedit.c */
-int setenv (char *, char *);
-
/* cpu/.../interrupt.c */
int arch_interrupt_init (void);
void reset_timer_masked (void);
ulong get_timer_masked (void);
void udelay_masked (unsigned long usec);
-/* cpu/.../timer.c */
-int timer_init (void);
-
#endif /* _U_BOOT_ARM_H_ */
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <net.h>
#include <serial.h>
extern void dataflash_print_info(void);
#endif
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
-const char version_string[] =
- U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;
-
#ifdef CONFIG_DRIVER_RTL8019
extern void rtl8019_get_enetaddr (uchar * addr);
#endif
+++ /dev/null
-/*
- * Copyright (C) 2005, 2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_AVR32_INITCALLS_H__
-#define __ASM_AVR32_INITCALLS_H__
-
-#include <config.h>
-
-extern int cpu_init(void);
-extern int timer_init(void);
-
-#endif /* __ASM_AVR32_INITCALLS_H__ */
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <net.h>
#include <miiphy.h>
#endif
-#include <asm/initcalls.h>
#include <asm/sections.h>
#include <asm/arch/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
-const char version_string[] =
- U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME") " CONFIG_IDENT_STRING;
-
unsigned long monitor_flash_len;
/* Weak aliases for optional board functions */
bootrom-asm-offsets.[chs]
+
+init.lds
+init.elf
LIB = $(obj)lib$(CPU).o
-EXTRA :=
+EXTRA := init.elf
CEXTRA := initcode.o
SEXTRA := start.o
SOBJS := interrupt.o cache.o
fi
endif
+$(obj)init.lds: init.lds.S
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@
+$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o
+ $(LD) $(LDFLAGS) -T $^ -o $@
+
#########################################################################
# defines $(obj).depend target
#include "cpu.h"
#include "serial.h"
+#include "initcode.h"
ulong bfin_poweron_retx;
extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
}
-#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
- /* The BF537 bootrom will reset the EBIU_AMGCTL register on us
- * after it has finished loading the LDR. So configure it again.
+
+ /*
+ * Make sure our async settings are committed. Some bootroms
+ * (like the BF537) will reset some registers on us after it
+ * has finished loading the LDR. Or if we're booting over
+ * JTAG, the initcode never got a chance to run. Or if we
+ * aren't booting from parallel flash, the initcode skipped
+ * this step completely.
*/
- else
- bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
-#endif
+ program_async_controller(NULL);
/* Save RETX so we can pass it while booting Linux */
bfin_poweron_retx = bootflag;
return 0;
}
+#ifdef CONFIG_BFIN_GPIO_TRACK
void bfin_gpio_free(unsigned gpio)
{
if (check_gpio(gpio) < 0)
set_label(gpio, "free");
}
+#endif
#ifdef BFIN_SPECIAL_GPIO_BANKS
DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
--- /dev/null
+#include <asm/blackfin.h>
+ENTRY(_start)
+ sp.l = LO(L1_SRAM_SCRATCH_END - 20);
+ sp.h = HI(L1_SRAM_SCRATCH_END - 20);
+ call _initcode;
+1:
+ emuexcpt;
+ jump 1b;
+END(_start)
--- /dev/null
+/*
+ * linker script for simple init.elf
+ *
+ * Copyright (c) 2005-2011 Analog Device Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text.l1 : { *(.text .text.*) } >l1_code
+}
* cannot make any function calls as it may be executed all by itself by
* the Blackfin's bootrom in LDR format.
*
- * Copyright (c) 2004-2008 Analog Devices Inc.
+ * Copyright (c) 2004-2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
+#define BUG() while (1) { asm volatile("emuexcpt;"); }
+
#include "serial.h"
__attribute__((always_inline))
static inline void serial_init(void)
{
+ uint32_t uart_base = UART_DLL;
+
#ifdef __ADSPBF54x__
# ifdef BFIN_BOOT_UART_USE_RTS
# define BFIN_UART_USE_RTS 1
if (BFIN_DEBUG_EARLY_SERIAL) {
int ucen = bfin_read16(&pUART->gctl) & UCEN;
- serial_early_init();
+ serial_early_init(uart_base);
/* If the UART is off, that means we need to program
* the baud rate ourselves initially.
*/
if (ucen != UCEN)
- serial_early_set_baud(CONFIG_BAUDRATE);
+ serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
}
}
static inline void serial_deinit(void)
{
#ifdef __ADSPBF54x__
+ uint32_t uart_base = UART_DLL;
+
if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
/* clear forced RTS rather than relying on auto RTS */
bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
__attribute__((always_inline))
static inline void serial_putc(char c)
{
+ uint32_t uart_base = UART_DLL;
+
if (!BFIN_DEBUG_EARLY_SERIAL)
return;
continue;
}
+#include "initcode.h"
+
__attribute__((always_inline)) static inline void
program_nmi_handler(void)
{
# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
#endif
-#ifndef CONFIG_EBIU_RSTCTL_VAL
-# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
-#endif
-#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
-# error invalid EBIU_RSTCTL value: must not set reserved bits
-#endif
-
-#ifndef CONFIG_EBIU_MBSCTL_VAL
-# define CONFIG_EBIU_MBSCTL_VAL 0
-#endif
-
-#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
-# error invalid EBIU_DDRQUE value: must not set reserved bits
-#endif
-
/* Make sure our voltage value is sane so we don't blow up! */
#ifndef CONFIG_VR_CTL_VAL
# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
unsigned int quotient;
for (quotient = 0; dividend > 0; ++quotient)
dividend -= divisor;
- serial_early_put_div(quotient - ANOMALY_05000230);
+ serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230);
serial_putc('c');
}
serial_putc('e');
}
-__attribute__((always_inline)) static inline void
-program_async_controller(ADI_BOOT_DATA *bs)
-{
- serial_putc('a');
-
- /* Program the async banks controller. */
- bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
- bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
- bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
-
- serial_putc('b');
-
- /* Not all parts have these additional MMRs. */
-#ifdef EBIU_MBSCTL
- bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
-#endif
-#ifdef EBIU_MODE
-# ifdef CONFIG_EBIU_MODE_VAL
- bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
-# endif
-# ifdef CONFIG_EBIU_FCTL_VAL
- bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
-# endif
-#endif
-
- serial_putc('c');
-}
-
BOOTROM_CALLED_FUNC_ATTR
void initcode(ADI_BOOT_DATA *bs)
{
--- /dev/null
+/*
+ * Code for early processor initialization
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_INITCODE_H__
+#define __BFIN_INITCODE_H__
+
+#include <asm/mach-common/bits/bootrom.h>
+
+#ifndef BFIN_IN_INITCODE
+# define serial_putc(c)
+#endif
+
+#ifndef CONFIG_EBIU_RSTCTL_VAL
+# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
+#endif
+#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
+# error invalid EBIU_RSTCTL value: must not set reserved bits
+#endif
+
+#ifndef CONFIG_EBIU_MBSCTL_VAL
+# define CONFIG_EBIU_MBSCTL_VAL 0
+#endif
+
+#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
+# error invalid EBIU_DDRQUE value: must not set reserved bits
+#endif
+
+__attribute__((always_inline)) static inline void
+program_async_controller(ADI_BOOT_DATA *bs)
+{
+#ifdef BFIN_IN_INITCODE
+ /*
+ * We really only need to setup the async banks early if we're
+ * booting out of it. Otherwise, do it later on in cpu_init.
+ */
+ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS &&
+ CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA)
+ return;
+#endif
+
+ serial_putc('a');
+
+ /* Program the async banks controller. */
+ bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
+ bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
+ bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+
+ serial_putc('b');
+
+ /* Not all parts have these additional MMRs. */
+#ifdef EBIU_MBSCTL
+ bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
+#endif
+#ifdef EBIU_MODE
+# ifdef CONFIG_EBIU_MODE_VAL
+ bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
+# endif
+# ifdef CONFIG_EBIU_FCTL_VAL
+ bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
+# endif
+#endif
+
+ serial_putc('c');
+}
+
+#endif
static bool jtag_write_emudat(uint32_t emudat)
{
static bool overflowed = false;
- ulong timeout = get_timer(0) + CONFIG_JTAG_CONSOLE_TIMEOUT;
+ ulong timeout = get_timer(0);
while (bfin_read_DBGSTAT() & 0x1) {
if (overflowed)
return overflowed;
- if (timeout < get_timer(0))
+ if (get_timer(timeout) > CONFIG_JTAG_CONSOLE_TIMEOUT)
overflowed = true;
}
overflowed = false;
/* The BF526 ROM will crash during reset */
#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
- bfin_read_SWRST();
+ /* Seems to be fixed with newer parts though ... */
+ if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
+ bfin_read_SWRST();
#endif
/* Wait for the SWRST write to complete. Cannot rely on SSYNC
#include <common.h>
#include <watchdog.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/uart.h>
#include "serial.h"
#ifdef CONFIG_DEBUG_SERIAL
-uint16_t cached_lsr[256];
-uint16_t cached_rbr[256];
-size_t cache_count;
+static uint16_t cached_lsr[256];
+static uint16_t cached_rbr[256];
+static size_t cache_count;
/* The LSR is read-to-clear on some parts, so we have to make sure status
* bits aren't inadvertently lost when doing various tests. This also
* tally of all the status bits.
*/
static uint16_t uart_lsr_save;
-static uint16_t uart_lsr_read(void)
+static uint16_t uart_lsr_read(uint32_t uart_base)
{
- uint16_t lsr = bfin_read16(&pUART->lsr);
+ uint16_t lsr = bfin_read(&pUART->lsr);
uart_lsr_save |= (lsr & (OE|PE|FE|BI));
return lsr | uart_lsr_save;
}
/* Just do the clear for everyone since it can't hurt. */
-static void uart_lsr_clear(void)
+static void uart_lsr_clear(uint32_t uart_base)
{
uart_lsr_save = 0;
- bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
+ bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
}
#else
/* When debugging is disabled, we only care about the DR bit, so if other
* bits get set/cleared, we don't really care since we don't read them
* anyways (and thus anomaly 05000099 is irrelevant).
*/
-static uint16_t uart_lsr_read(void)
+static inline uint16_t uart_lsr_read(uint32_t uart_base)
{
- return bfin_read16(&pUART->lsr);
+ return bfin_read(&pUART->lsr);
}
-static void uart_lsr_clear(void)
+static void uart_lsr_clear(uint32_t uart_base)
{
- bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
+ bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
}
#endif
-/* Symbol for our assembly to call. */
-void serial_set_baud(uint32_t baud)
-{
- serial_early_set_baud(baud);
-}
-
-/* Symbol for common u-boot code to call.
- * Setup the baudrate (brg: baudrate generator).
- */
-void serial_setbrg(void)
-{
- serial_set_baud(gd->baudrate);
-}
-
-/* Symbol for our assembly to call. */
-void serial_initialize(void)
-{
- serial_early_init();
-}
-
-/* Symbol for common u-boot code to call. */
-int serial_init(void)
-{
- serial_initialize();
- serial_setbrg();
- uart_lsr_clear();
-#ifdef CONFIG_DEBUG_SERIAL
- cache_count = 0;
- memset(cached_lsr, 0x00, sizeof(cached_lsr));
- memset(cached_rbr, 0x00, sizeof(cached_rbr));
-#endif
- return 0;
-}
-
-void serial_putc(const char c)
+static void uart_putc(uint32_t uart_base, const char c)
{
/* send a \r for compatibility */
if (c == '\n')
WATCHDOG_RESET();
/* wait for the hardware fifo to clear up */
- while (!(uart_lsr_read() & THRE))
+ while (!(uart_lsr_read(uart_base) & THRE))
continue;
/* queue the character for transmission */
- bfin_write16(&pUART->thr, c);
+ bfin_write(&pUART->thr, c);
SSYNC();
WATCHDOG_RESET();
}
-int serial_tstc(void)
+static int uart_tstc(uint32_t uart_base)
{
WATCHDOG_RESET();
- return (uart_lsr_read() & DR) ? 1 : 0;
+ return (uart_lsr_read(uart_base) & DR) ? 1 : 0;
}
-int serial_getc(void)
+static int uart_getc(uint32_t uart_base)
{
uint16_t uart_rbr_val;
/* wait for data ! */
- while (!serial_tstc())
+ while (!uart_tstc(uart_base))
continue;
/* grab the new byte */
- uart_rbr_val = bfin_read16(&pUART->rbr);
+ uart_rbr_val = bfin_read(&pUART->rbr);
#ifdef CONFIG_DEBUG_SERIAL
/* grab & clear the LSR */
- uint16_t uart_lsr_val = uart_lsr_read();
+ uint16_t uart_lsr_val = uart_lsr_read(uart_base);
cached_lsr[cache_count] = uart_lsr_val;
cached_rbr[cache_count] = uart_rbr_val;
uint16_t dll, dlh;
printf("\n[SERIAL ERROR]\n");
ACCESS_LATCH();
- dll = bfin_read16(&pUART->dll);
- dlh = bfin_read16(&pUART->dlh);
+ dll = bfin_read(&pUART->dll);
+ dlh = bfin_read(&pUART->dlh);
ACCESS_PORT_IER();
printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
do {
--cache_count;
- printf("\t%3i: RBR=0x%02x LSR=0x%02x\n", cache_count,
+ printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
cached_rbr[cache_count], cached_lsr[cache_count]);
} while (cache_count > 0);
return -1;
}
#endif
- uart_lsr_clear();
+ uart_lsr_clear(uart_base);
return uart_rbr_val;
}
+#ifdef CONFIG_SYS_BFIN_UART
+
+static void uart_puts(uint32_t uart_base, const char *s)
+{
+ while (*s)
+ uart_putc(uart_base, *s++);
+}
+
+#define DECL_BFIN_UART(n) \
+static int uart##n##_init(void) \
+{ \
+ const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
+ peripheral_request_list(pins, "bfin-uart"); \
+ uart_init(MMR_UART(n)); \
+ serial_early_set_baud(MMR_UART(n), gd->baudrate); \
+ uart_lsr_clear(MMR_UART(n)); \
+ return 0; \
+} \
+\
+static int uart##n##_uninit(void) \
+{ \
+ return serial_early_uninit(MMR_UART(n)); \
+} \
+\
+static void uart##n##_setbrg(void) \
+{ \
+ serial_early_set_baud(MMR_UART(n), gd->baudrate); \
+} \
+\
+static int uart##n##_getc(void) \
+{ \
+ return uart_getc(MMR_UART(n)); \
+} \
+\
+static int uart##n##_tstc(void) \
+{ \
+ return uart_tstc(MMR_UART(n)); \
+} \
+\
+static void uart##n##_putc(const char c) \
+{ \
+ uart_putc(MMR_UART(n), c); \
+} \
+\
+static void uart##n##_puts(const char *s) \
+{ \
+ uart_puts(MMR_UART(n), s); \
+} \
+\
+struct serial_device bfin_serial##n##_device = { \
+ .name = "bfin_uart"#n, \
+ .init = uart##n##_init, \
+ .uninit = uart##n##_uninit, \
+ .setbrg = uart##n##_setbrg, \
+ .getc = uart##n##_getc, \
+ .tstc = uart##n##_tstc, \
+ .putc = uart##n##_putc, \
+ .puts = uart##n##_puts, \
+};
+
+#ifdef UART0_DLL
+DECL_BFIN_UART(0)
+#endif
+#ifdef UART1_DLL
+DECL_BFIN_UART(1)
+#endif
+#ifdef UART2_DLL
+DECL_BFIN_UART(2)
+#endif
+#ifdef UART3_DLL
+DECL_BFIN_UART(3)
+#endif
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if CONFIG_UART_CONSOLE == 0
+ return &bfin_serial0_device;
+#elif CONFIG_UART_CONSOLE == 1
+ return &bfin_serial1_device;
+#elif CONFIG_UART_CONSOLE == 2
+ return &bfin_serial2_device;
+#elif CONFIG_UART_CONSOLE == 3
+ return &bfin_serial3_device;
+#endif
+}
+
+void serial_register_bfin_uart(void)
+{
+#ifdef UART0_DLL
+ serial_register(&bfin_serial0_device);
+#endif
+#ifdef UART1_DLL
+ serial_register(&bfin_serial1_device);
+#endif
+#ifdef UART2_DLL
+ serial_register(&bfin_serial2_device);
+#endif
+#ifdef UART3_DLL
+ serial_register(&bfin_serial3_device);
+#endif
+}
+
+#else
+
+/* Symbol for our assembly to call. */
+void serial_set_baud(uint32_t baud)
+{
+ serial_early_set_baud(UART_DLL, baud);
+}
+
+/* Symbol for common u-boot code to call.
+ * Setup the baudrate (brg: baudrate generator).
+ */
+void serial_setbrg(void)
+{
+ serial_set_baud(gd->baudrate);
+}
+
+/* Symbol for our assembly to call. */
+void serial_initialize(void)
+{
+ serial_early_init(UART_DLL);
+}
+
+/* Symbol for common u-boot code to call. */
+int serial_init(void)
+{
+ serial_initialize();
+ serial_setbrg();
+ uart_lsr_clear(UART_DLL);
+ return 0;
+}
+
+int serial_tstc(void)
+{
+ return uart_tstc(UART_DLL);
+}
+
+int serial_getc(void)
+{
+ return uart_getc(UART_DLL);
+}
+
+void serial_putc(const char c)
+{
+ uart_putc(UART_DLL, c);
+}
+
void serial_puts(const char *s)
{
while (*s)
}
#endif
+
+#endif
#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
-#define MMR_UART(mmr) _PASTE_UART(CONFIG_UART_CONSOLE, UART, DLL)
-#define P_UART(pin) _PASTE_UART(CONFIG_UART_CONSOLE, P_UART, pin)
+#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
+#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
+#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
#ifndef UART_DLL
-# define UART_DLL MMR_UART(DLL)
+# define UART_DLL MMR_UART(CONFIG_UART_CONSOLE)
#else
+# define UART0_DLL UART_DLL
# if CONFIG_UART_CONSOLE != 0
# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
# endif
#endif
-#define pUART ((volatile struct bfin_mmr_serial *)UART_DLL)
+#define pUART ((volatile struct bfin_mmr_serial *)uart_base)
#if BFIN_UART_HW_VER == 2
# define ACCESS_LATCH()
# define ACCESS_PORT_IER()
#else
# define ACCESS_LATCH() \
- bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB)
+ bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) | DLAB)
# define ACCESS_PORT_IER() \
- bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB)
+ bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) & ~DLAB)
#endif
__attribute__((always_inline))
}
__attribute__((always_inline))
-static inline void serial_early_init(void)
+static inline int uart_init(uint32_t uart_base)
{
- /* handle portmux crap on different Blackfins */
- serial_do_portmux();
-
/* always enable UART -- avoids anomalies 05000309 and 05000350 */
- bfin_write16(&pUART->gctl, UCEN);
+ bfin_write(&pUART->gctl, UCEN);
/* Set LCR to Word Lengh 8-bit word select */
- bfin_write16(&pUART->lcr, WLS_8);
+ bfin_write(&pUART->lcr, WLS_8);
SSYNC();
+
+ return 0;
}
__attribute__((always_inline))
-static inline void serial_early_put_div(uint16_t divisor)
+static inline int serial_early_init(uint32_t uart_base)
+{
+ /* handle portmux crap on different Blackfins */
+ serial_do_portmux();
+
+ return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+ /* disable the UART by clearing UCEN */
+ bfin_write(&pUART->gctl, 0);
+
+ return 0;
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint32_t uart_base, uint16_t divisor)
{
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH();
SSYNC();
/* Program the divisor to get the baud rate we want */
- bfin_write16(&pUART->dll, LOB(divisor));
- bfin_write16(&pUART->dlh, HIB(divisor));
+ bfin_write(&pUART->dll, LOB(divisor));
+ bfin_write(&pUART->dlh, HIB(divisor));
SSYNC();
/* Clear DLAB in LCR to Access THR RBR IER */
__attribute__((always_inline))
static inline uint16_t serial_early_get_div(void)
{
+ uint32_t uart_base = UART_DLL;
+
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH();
SSYNC();
- uint8_t dll = bfin_read16(&pUART->dll);
- uint8_t dlh = bfin_read16(&pUART->dlh);
+ uint8_t dll = bfin_read(&pUART->dll);
+ uint8_t dlh = bfin_read(&pUART->dlh);
uint16_t divisor = (dlh << 8) | dll;
/* Clear DLAB in LCR to Access THR RBR IER */
#endif
__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t baud)
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
{
/* Translate from baud into divisor in terms of SCLK. The
* weird multiplication is to make sure we over sample just
* a little rather than under sample the incoming signals.
*/
- serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
+ serial_early_put_div(uart_base,
+ (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
}
#ifndef BFIN_IN_INITCODE
*/
#ifdef CONFIG_DEBUG_EARLY_SERIAL
# define serial_early_puts(str) \
- call _get_pc; \
- jump 1f; \
+ .section .rodata; \
+ 7: \
.ascii "Early:"; \
.ascii __FILE__; \
.ascii ": "; \
.ascii str; \
.asciz "\n"; \
- .align 4; \
-1: \
- R0 += 2; \
+ .previous; \
+ R0.L = 7b; \
+ R0.H = 7b; \
call _serial_puts;
#else
# define serial_early_puts(str)
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/pll.h>
#include "serial.h"
# define NOP_PAD_ANOMALY_05000198
#endif
-#define bfin_read8(addr) ({ \
- uint8_t __v; \
+#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
+ u32 __v; \
__asm__ __volatile__( \
NOP_PAD_ANOMALY_05000198 \
- "%0 = b[%1] (z);" \
+ "%0 = " #asm_size "[%1]" #asm_ext ";" \
: "=d" (__v) \
: "a" (addr) \
); \
__v; })
-
-#define bfin_read16(addr) ({ \
- uint16_t __v; \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- "%0 = w[%1] (z);" \
- : "=d" (__v) \
- : "a" (addr) \
- ); \
- __v; })
-
-#define bfin_read32(addr) ({ \
- uint32_t __v; \
+#define _bfin_writeX(addr, val, size, asm_size) \
__asm__ __volatile__( \
NOP_PAD_ANOMALY_05000198 \
- "%0 = [%1];" \
- : "=d" (__v) \
- : "a" (addr) \
- ); \
- __v; })
-
-#define bfin_readPTR(addr) bfin_read32(addr)
-
-#define bfin_write8(addr, val) \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- "b[%0] = %1;" \
- : \
- : "a" (addr), "d" (val) \
- : "memory" \
- )
-
-#define bfin_write16(addr, val) \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- "w[%0] = %1;" \
+ #asm_size "[%0] = %1;" \
: \
- : "a" (addr), "d" (val) \
+ : "a" (addr), "d" ((u##size)(val)) \
: "memory" \
)
-#define bfin_write32(addr, val) \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- "[%0] = %1;" \
- : \
- : "a" (addr), "d" (val) \
- : "memory" \
- )
+#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
+#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
+#define bfin_read32(addr) _bfin_readX(addr, 32, , )
+#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
+#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
+#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
+
+#define bfin_read(addr) \
+({ \
+ sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
+ sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
+ sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
+ ({ BUG(); 0; }); \
+})
+#define bfin_write(addr, val) \
+do { \
+ switch (sizeof(*(addr))) { \
+ case 1: bfin_write8(addr, val); break; \
+ case 2: bfin_write16(addr, val); break; \
+ case 4: bfin_write32(addr, val); break; \
+ default: BUG(); \
+ } \
+} while (0)
+
+#define bfin_write_or(addr, bits) \
+do { \
+ typeof(addr) __addr = (addr); \
+ bfin_write(__addr, bfin_read(__addr) | (bits)); \
+} while (0)
+
+#define bfin_write_and(addr, bits) \
+do { \
+ typeof(addr) __addr = (addr); \
+ bfin_write(__addr, bfin_read(__addr) & (bits)); \
+} while (0)
+#define bfin_readPTR(addr) bfin_read32(addr)
#define bfin_writePTR(addr, val) bfin_write32(addr, val)
/* SSYNC implementation for C file */
#ifndef CONFIG_SYS_MEMTEST_END
# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
#endif
+#ifndef CONFIG_SYS_POST_WORD_ADDR
+# define CONFIG_SYS_POST_WORD_ADDR (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE - 4)
+#endif
/* Check to make sure everything fits in external RAM */
#if CONFIG_SYS_MAX_RAM_SIZE && \
#ifdef CONFIG_BFIN_GPIO_TRACK
void bfin_gpio_labels(void);
+void bfin_gpio_free(unsigned gpio);
#else
#define bfin_gpio_labels()
+#define bfin_gpio_free(gpio)
#define bfin_gpio_request(gpio, label) bfin_gpio_request(gpio)
#define bfin_special_gpio_request(gpio, label) bfin_special_gpio_request(gpio)
#endif
#endif
int bfin_gpio_request(unsigned gpio, const char *label);
-void bfin_gpio_free(unsigned gpio);
int bfin_gpio_direction_input(unsigned gpio);
int bfin_gpio_direction_output(unsigned gpio, int value);
int bfin_gpio_get_value(unsigned gpio);
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
+ * - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List
*/
#if __SILICON_REVISION__ < 0
#define ANOMALY_05000310 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000472 (1)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
+/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */
+#define ANOMALY_05000476 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
+/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */
+#define ANOMALY_05000478 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */
+#define ANOMALY_05000486 (1)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */
+#define ANOMALY_05000495 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
+ * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
*/
-/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
#if __SILICON_REVISION__ < 0
# error will not work on BF518 silicon version
#endif
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
+#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
+#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
+/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
+#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
-#define ANOMALY_05000485 (0)
+#define ANOMALY_05000480 (0)
#endif
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
+ * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
+ * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
/* Incorrect Default Internal Voltage Regulator Setting */
#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))
+#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
/* DEB2_URGENT Bit Not Functional */
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (1)
-/* USB DMA Mode 1 Short Packet Data Corruption */
+#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
+/* USB DMA Short Packet Data Corruption */
#define ANOMALY_05000450 (1)
/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (1)
+#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
-/* USB Rx DMA hang */
+/* USB Rx DMA Hang */
#define ANOMALY_05000465 (1)
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
#define ANOMALY_05000466 (1)
-/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
+/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
#define ANOMALY_05000467 (1)
/* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000469 (1)
/* Incorrect Default MSEL Value in PLL_CTL */
#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
#define ANOMALY_05000483 (1)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
/* The CODEC Zero-Cross Detect Feature is not Functional */
#define ANOMALY_05000487 (1)
-/* IFLUSH sucks at life */
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#endif
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
#define ANOMALY_05000462 (1)
/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
#define ANOMALY_05000471 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
-/* These anomalies have been "phased" out of analog.com anomaly sheets and are
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
*/
#define ANOMALY_05000362 (1)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (1)
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
/* EMAC TX DMA Error After an Early Frame Abort */
#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
#define ANOMALY_05000280 (1)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
+/* Instruction Cache Is Not Functional */
+#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
+/* Buffered CLKIN Output Is Disabled by Default */
+#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
+ * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
+ * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000229 (1)
/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
#define ANOMALY_05000233 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (1)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
+#define ANOMALY_05000272 (ANOMALY_BF538)
/* Writes to Synchronous SDRAM Memory May Be Lost */
#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
+/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
+#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
+#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (1)
+#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
/* FIFO Boot Mode Not Functional */
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
+/*
+ * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
+ * shows that the fix itself does not cover all cases.
+ */
+#define ANOMALY_05000353 (1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* External Memory Read Access Hangs Core With PLL Bypass */
#define ANOMALY_05000360 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000365 (1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
#define ANOMALY_05000369 (1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
#define ANOMALY_05000379 (1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
/* Lockbox SESR Disallows Certain User Interrupts */
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
+#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Mode 1 Short Packet Data Corruption */
+/* USB DMA Short Packet Data Corruption */
#define ANOMALY_05000450 (1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
#define ANOMALY_05000456 (1)
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
#define ANOMALY_05000457 (1)
/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
+#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
+#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
/* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (1)
+#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
/* USB TX DMA Hang */
-#define ANOMALY_05000464 (1)
-/* USB Rx DMA hang */
+#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
+/* USB Rx DMA Hang */
#define ANOMALY_05000465 (1)
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
-#define ANOMALY_05000467 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
+/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
+#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
-/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
-#define ANOMALY_05000474 (1)
+/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
+#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
-/* IFLUSH sucks at life */
+#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
+#define ANOMALY_05000500 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
+#define ANOMALY_05000502 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* False Hardware Error when ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
+/* TWI Slave Boot Mode Is Not Functional */
+#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
+/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
+#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
+/* Incorrect Access of OTP_STATUS During otp_write() Function */
+#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
+/* Synchronous Burst Flash Boot Mode Is Not Functional */
+#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
+/* Host DMA Boot Modes Are Not Functional */
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
+/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
+#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
+/* Inadequate Rotary Debounce Logic Duration */
+#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
+/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
+#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
+/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
+/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
+#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
+/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
+#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
+/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
+#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value Is Not Initialized */
+#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0x5411
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
+/* Data Lost when Core Reads SDH Data FIFO */
+#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
+/* PLL Status Register Is Inaccurate */
+#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
+/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
+#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
+/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
+#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
+/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
+#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
+/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
+#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
+/* Changed Meaning of BCODE Field in SYSCR Register */
+#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
+/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
+#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
+/* OTP Write Accesses Not Supported */
+#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
+/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
+#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000440 (0)
#define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
#endif
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
+ * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000074 (1)
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
#define ANOMALY_05000120 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
/* SIGNBITS Instruction Not Functional under Certain Conditions */
#define ANOMALY_05000127 (1)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
/* IMDMA S1/D1 Channel May Stall */
#define ANOMALY_05000149 (1)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1)
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
/* Cache Fill Buffer Data lost */
#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
/* Overlapping Sequencer and Memory Stalls */
#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
/* PPI Not Functional at Core Voltage < 1Volt */
#define ANOMALY_05000190 (1)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
/* Restarting SPORT in Specific Modes May Cause Data Corruption */
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
/* Temporarily walk around for bug 5423 till this issue is confirmed by
* official anomaly document. It looks 05000281 still exists on bf561
* v0.5.
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
#define ANOMALY_05000462 (1)
/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
#define ANOMALY_05000471 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
+#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
+/* Erroneous Exception when Enabling Cache */
+#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
+/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
+#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
+/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
+#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
+/* Stall in multi-unit DMA operations */
+#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
+/* Allowing the SPORT RX FIFO to fill will cause an overflow */
+#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
+/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
+#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
+/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
+#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
+/* DMA and TESTSET conflict when both are accessing external memory */
+#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
+/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
+#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
+/* MDMA may lose the first few words of a descriptor chain */
+#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
+/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
+#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
+/* DMA engine may lose data due to incorrect handshaking */
+#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
+/* DMA stalls when all three controllers read data from the same source */
+#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
+/* Execution stall when executing in L2 and doing external accesses */
+#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
+/* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
+/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
+#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
+/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
+#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
+/* A read from external memory may return a wrong value with data cache enabled */
+#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
+/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
+/* DMEM_CONTROL<12> is not set on Reset */
+#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
+/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
+#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
+/* DSPID register values incorrect */
+#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
+/* DMA vs Core accesses to external memory */
+#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
+/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
+#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000119 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
#define peripheral_request_list(per, label) peripheral_request_list(per)
#endif
+#ifndef __ASSEMBLY__
+
int peripheral_request(unsigned short per, const char *label);
void peripheral_free(unsigned short per);
int peripheral_request_list(const unsigned short per[], const char *label);
void peripheral_free_list(const unsigned short per[]);
+#endif
+
#include <asm/blackfin.h>
#ifndef P_SPORT2_TFS
#include <common.h>
#include <command.h>
#include <stdio_dev.h>
+#include <serial.h>
#include <environment.h>
#include <malloc.h>
#include <mmc.h>
#include <net.h>
-#include <timestamp.h>
#include <status_led.h>
#include <version.h>
DECLARE_GLOBAL_DATA_PTR;
-const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")";
-
__attribute__((always_inline))
static inline void serial_early_puts(const char *s)
{
static int display_banner(void)
{
- printf("\n\n%s\n\n", version_string);
+ display_options();
printf("CPU: ADSP %s "
"(Detected Rev: 0.%d) "
"(%s boot)\n",
init_baudrate();
serial_early_puts("Serial init\n");
serial_init();
+#ifdef CONFIG_SERIAL_MULTI
+ serial_initialize();
+#endif
serial_early_puts("Console init flash\n");
console_init_f();
serial_early_puts("End of early debugging\n");
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
/*------------------------------------------------------------------------------*/
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#include <common.h>
#include <command.h>
#include <malloc.h>
-#include <timestamp.h>
#include <version.h>
#include <watchdog.h>
#include <stdio_dev.h>
DECLARE_GLOBAL_DATA_PTR;
-const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")";
-
#ifdef CONFIG_SYS_GPIO_0
extern int gpio_init (void);
#endif
#include <asm/regdef.h>
#include <asm/mipsregs.h>
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
_start:
RVECENT(reset,0) # U-boot entry point
RVECENT(reset,1) # software reboot
-#ifdef CONFIG_INCA_IP
- .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during
- .word 0x00000000 # booting phase of the flash
+#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+ /*
+ * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
+ * access external NOR flashes. If the board boots from NOR flash the
+ * internal BootROM does a blind read at address 0xB0000010 to read the
+ * initial configuration for that EBU in order to access the flash
+ * device with correct parameters. This config option is board-specific.
+ */
+ .word CONFIG_SYS_XWAY_EBU_BOOTCFG
+ .word 0x00000000
#else
RVECENT(romReserved,2)
#endif
nop
/* ... and enable them */
- li t0, CONF_CM_CACHABLE_NONCOHERENT
+ li t0, CONFIG_SYS_MIPS_CACHE_MODE
mtc0 t0, CP0_CONFIG
#endif
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <net.h>
#include <environment.h>
ulong monitor_flash_len;
-const char version_string[] =
- U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")";
-
static char *failed = "*** failed ***\n";
/*
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
#include <version.h>
/*************************************************************************
bge r4, r0, dly_clks
ret
-
-#if !defined(CONFIG_IDENT_STRING)
-#define CONFIG_IDENT_STRING ""
-#endif
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
#include <asm-offsets.h>
#include <config.h>
#include <74xx_7xx.h>
-#include <timestamp.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <galileo/gt64260R.h>
#endif
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING "MPC512X"
+#endif
#include <version.h>
#define CONFIG_521X 1 /* needed for Linux kernel header files*/
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING "MPC512X"
-#endif
-
/*
* Floating Point enable, Machine Check and Recoverable Interr.
*/
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii " ", CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
/*
* Vector Table
#include <asm-offsets.h>
#include <config.h>
#include <mpc5xx.h>
-#include <timestamp.h>
#include <version.h>
#define CONFIG_5xx 1 /* needed for Linux kernel header files */
#include <asm/processor.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't have a MMU.
*/
#undef MSR_KERNEL
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
#include <asm-offsets.h>
#include <config.h>
#include <mpc5xxx.h>
-#include <timestamp.h>
#include <version.h>
#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
/*
* Exception vectors
#include <asm-offsets.h>
#include <config.h>
#include <mpc8220.h>
-#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
/*
* Exception vectors
#include <asm-offsets.h>
#include <config.h>
#include <mpc824x.h>
-#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
#include <asm-offsets.h>
#include <config.h>
#include <mpc8260.h>
-#include <timestamp.h>
#include <version.h>
#define CONFIG_8260 1 /* needed for Linux kernel header files */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
/*
* Hard Reset Configuration Word (HRCW) table
#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
-#include <timestamp.h>
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING "MPC83XX"
+#endif
#include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING "MPC83XX"
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii " ", CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 2
COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
-COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o
-COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
+COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
COBJS-$(CONFIG_P1025) += p1021_serdes.o
COBJS-$(CONFIG_P2010) += p2020_serdes.o
COBJS-$(CONFIG_P2020) += p2020_serdes.o
-COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
{
sys_info_t sysinfo;
uint pvr, svr;
- uint fam;
uint ver;
uint major, minor;
struct cpu_type *cpu;
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
- fam = PVR_FAM(pvr);
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
printf("Core: ");
- if (PVR_FAM(PVR_85xx)) {
- switch(PVR_MEM(pvr)) {
- case 0x1:
- case 0x2:
- puts("E500");
- break;
- case 0x3:
- puts("E500MC");
- break;
- case 0x4:
- puts("E5500");
- break;
- default:
- puts("Unknown");
- break;
- }
- } else {
+ switch(ver) {
+ case PVR_VER_E500_V1:
+ case PVR_VER_E500_V2:
+ puts("E500");
+ break;
+ case PVR_VER_E500MC:
+ puts("E500MC");
+ break;
+ case PVR_VER_E5500:
+ puts("E5500");
+ break;
+ default:
puts("Unknown");
+ break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
lbc_sdram_init();
#endif
- puts("DDR: ");
+ debug("DDR: ");
return dram_size;
}
#endif /* CONFIG_SYS_RAMBOOT */
void cpu_init_f (void)
{
extern void m8560_cpm_reset (void);
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
/* Invalidate the CPC before DDR gets enabled */
invalidate_cpc();
+
+ #ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* set DCSRCR so that DCSR space is 1G */
+ setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
+ in_be32(&gur->dcsrcr);
+#endif
+
}
/* Implement a dummy function for those platforms w/o SERDES */
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+ if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+ (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
+ puts("N/A\n");
+ goto skip_l2;
+ }
+
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
/* invalidate the L2 cache */
;
printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
}
+
+skip_l2:
#else
puts("disabled\n");
#endif
u32 *ph;
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
u32 size, line_size, num_ways, num_sets;
+ int has_l2 = 1;
+
+ /* P2040/P2040E has no L2, so dont set any L2 props */
+ if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+ (SVR_SOC_VER(get_svr()) == SVR_P2040_E))
+ has_l2 = 0;
size = (l2cfg0 & 0x3fff) * 64 * 1024;
num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
goto next;
}
+ if (has_l2) {
#ifdef CONFIG_SYS_CACHE_STASHING
- {
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
if (reg)
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
(*reg * 2) + 32 + 1);
- }
#endif
- fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
- fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
- fdt_setprop_cell(blob, l2_off, "cache-size", size);
- fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
- fdt_setprop_cell(blob, l2_off, "cache-level", 2);
- fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
+ fdt_setprop_cell(blob, l2_off, "cache-block-size",
+ line_size);
+ fdt_setprop_cell(blob, l2_off, "cache-size", size);
+ fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
+ fdt_setprop_cell(blob, l2_off, "cache-level", 2);
+ fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ }
if (l3_off < 0) {
ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
*/
do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
"timer-frequency", gd->bus_clk/2, 1);
+
+ do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
+ "clock_freq", gd->bus_clk, 1);
+}
+
+/*
+ * For some CCSR devices, we only have the virtual address, not the physical
+ * address. This is because we map CCSR as a whole, so we typically don't need
+ * a macro for the physical address of any device within CCSR. In this case,
+ * we calculate the physical address of that device using it's the difference
+ * between the virtual address of the device and the virtual address of the
+ * beginning of CCSR.
+ */
+#define CCSR_VIRT_TO_PHYS(x) \
+ (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
+
+/*
+ * Verify the device tree
+ *
+ * This function compares several CONFIG_xxx macros that contain physical
+ * addresses with the corresponding nodes in the device tree, to see if
+ * the physical addresses are all correct. For example, if
+ * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
+ * of the first UART. We convert this to a physical address and compare
+ * that with the physical address of the first ns16550-compatible node
+ * in the device tree. If they don't match, then we display a warning.
+ *
+ * Returns 1 on success, 0 on failure
+ */
+int ft_verify_fdt(void *fdt)
+{
+ uint64_t ccsr = 0;
+ int aliases;
+ int off;
+
+ /* First check the CCSR base address */
+ off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
+ if (off > 0)
+ ccsr = fdt_get_base_address(fdt, off);
+
+ if (!ccsr) {
+ printf("Warning: could not determine base CCSR address in "
+ "device tree\n");
+ /* No point in checking anything else */
+ return 0;
+ }
+
+ if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) {
+ printf("Warning: U-Boot configured CCSR at address %llx,\n"
+ "but the device tree has it at %llx\n",
+ (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr);
+ /* No point in checking anything else */
+ return 0;
+ }
+
+ /*
+ * Get the 'aliases' node. If there isn't one, then there's nothing
+ * left to do.
+ */
+ aliases = fdt_path_offset(fdt, "/aliases");
+ if (aliases > 0) {
+#ifdef CONFIG_SYS_NS16550_COM1
+ if (!fdt_verify_alias_address(fdt, aliases, "serial0",
+ CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
+ return 0;
+#endif
+
+#ifdef CONFIG_SYS_NS16550_COM2
+ if (!fdt_verify_alias_address(fdt, aliases, "serial1",
+ CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
+ return 0;
+#endif
+ }
+
+ return 1;
}
+++ /dev/null
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
- /* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO( 1, 2, 1, 0),
- SET_QP_INFO( 3, 4, 2, 1),
- SET_QP_INFO( 5, 6, 3, 2),
- SET_QP_INFO( 7, 8, 4, 3),
- SET_QP_INFO( 9, 10, 5, 4),
- SET_QP_INFO( 0, 0, 0, 5),
- SET_QP_INFO( 0, 0, 0, 6),
- SET_QP_INFO( 0, 0, 0, 7),
- SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
- SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
-};
-#endif
-
-struct liodn_id_table liodn_tbl[] = {
-#ifdef CONFIG_SYS_DPAA_QBMAN
- SET_QMAN_LIODN(31),
- SET_BMAN_LIODN(32),
-#endif
-
- SET_SDHC_LIODN(1, 64),
-
- SET_PME_LIODN(117),
-
- SET_USB_LIODN(1, "fsl-usb2-mph", 125),
- SET_USB_LIODN(2, "fsl-usb2-dr", 126),
-
- SET_SATA_LIODN(1, 127),
- SET_SATA_LIODN(2, 128),
-
- SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
- SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
- SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
-
- SET_DMA_LIODN(1, 197),
- SET_DMA_LIODN(2, 198),
-
- SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
- SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
- SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
- SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
-};
-int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-struct liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 10),
- SET_FMAN_RX_1G_LIODN(1, 1, 11),
- SET_FMAN_RX_1G_LIODN(1, 2, 12),
- SET_FMAN_RX_1G_LIODN(1, 3, 13),
- SET_FMAN_RX_1G_LIODN(1, 4, 14),
-#if (CONFIG_SYS_NUM_FM1_10GEC == 1)
- SET_FMAN_RX_10G_LIODN(1, 0, 15),
-#endif
-};
-int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-#endif
-
-struct liodn_id_table sec_liodn_tbl[] = {
- SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
- SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
- SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
- SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
- SET_SEC_RTIC_LIODN_ENTRY(a, 154),
- SET_SEC_RTIC_LIODN_ENTRY(b, 155),
- SET_SEC_RTIC_LIODN_ENTRY(c, 156),
- SET_SEC_RTIC_LIODN_ENTRY(d, 157),
- SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
- SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
-};
-int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
-
-struct liodn_id_table liodn_bases[] = {
- [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
-#ifdef CONFIG_SYS_DPAA_FMAN
- [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
-#endif
-#ifdef CONFIG_SYS_DPAA_PME
- [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
-#endif
-};
+++ /dev/null
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_serdes.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "fsl_corenet_serdes.h"
-
-static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
- [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
- NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
- [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
- [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
- PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
- SATA2, NONE, NONE, NONE, NONE, },
- [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
- PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE,
- NONE, NONE, NONE, NONE, NONE, NONE, },
- [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
- PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
- PCIE3, NONE, NONE, NONE, NONE, },
- [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
- SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
- [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
- PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
- SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
- NONE, NONE, NONE, },
- [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
- NONE, NONE, NONE, },
- [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE,
- NONE, NONE, NONE, NONE, NONE, },
- [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
- PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
- NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
- [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
- SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
- NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
- [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
- SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
-};
-
-enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
-{
- if (!serdes_lane_enabled(lane))
- return NONE;
-
- return serdes_cfg_tbl[cfg][lane];
-}
-
-int is_serdes_prtcl_valid(u32 prtcl)
-{
- int i;
-
- if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
- return 0;
-
- for (i = 0; i < SRDS_MAX_LANES; i++) {
- if (serdes_cfg_tbl[prtcl][i] != NONE)
- return 1;
- }
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO( 1, 2, 1, 0),
+ SET_QP_INFO( 3, 4, 2, 1),
+ SET_QP_INFO( 5, 6, 3, 2),
+ SET_QP_INFO( 7, 8, 4, 3),
+ SET_QP_INFO( 9, 10, 5, 4),
+ SET_QP_INFO( 0, 0, 0, 5),
+ SET_QP_INFO( 0, 0, 0, 6),
+ SET_QP_INFO( 0, 0, 0, 7),
+ SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
+ SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(31),
+ SET_BMAN_LIODN(32),
+#endif
+
+ SET_SDHC_LIODN(1, 64),
+
+ SET_PME_LIODN(117),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 125),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 126),
+
+ SET_SATA_LIODN(1, 127),
+ SET_SATA_LIODN(2, 128),
+
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
+
+ SET_DMA_LIODN(1, 197),
+ SET_DMA_LIODN(2, 198),
+
+ SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+ SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+ SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+ SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 10),
+ SET_FMAN_RX_1G_LIODN(1, 1, 11),
+ SET_FMAN_RX_1G_LIODN(1, 2, 12),
+ SET_FMAN_RX_1G_LIODN(1, 3, 13),
+ SET_FMAN_RX_1G_LIODN(1, 4, 14),
+#if (CONFIG_SYS_NUM_FM1_10GEC == 1)
+ SET_FMAN_RX_10G_LIODN(1, 0, 15),
+#endif
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+ SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+ SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+ SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 154),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 155),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 156),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 157),
+ SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
+ SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+struct liodn_id_table liodn_bases[] = {
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
+#endif
+};
--- /dev/null
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+ [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+ NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+ [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+ [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+ PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
+ SATA2, NONE, NONE, NONE, NONE, },
+ [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+ PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, },
+ [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+ PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
+ PCIE3, NONE, NONE, NONE, NONE, },
+ [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+ SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+ [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+ PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
+ NONE, NONE, NONE, },
+ [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
+ NONE, NONE, NONE, },
+ [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, NONE, NONE, NONE, NONE, },
+ [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+ PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
+ NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
+ [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+ SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
+ NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
+ [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
+ SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+ enum srds_prtcl prtcl;
+ u32 svr = get_svr();
+ u32 ver = SVR_SOC_VER(svr);
+
+ if (!serdes_lane_enabled(lane))
+ return NONE;
+
+ prtcl = serdes_cfg_tbl[cfg][lane];
+
+ /* P2040[e] does not support XAUI */
+ if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+ prtcl = NONE;
+
+ return prtcl;
+}
+
+int is_serdes_prtcl_valid(u32 prtcl)
+{
+ int i;
+ u32 svr = get_svr();
+ u32 ver = SVR_SOC_VER(svr);
+
+ if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ /* P2040[e] does not support XAUI */
+ if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_cfg_tbl[prtcl][i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com>
*
* See file CREDITS for list of people who contributed to this
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE
+ /* skip L2 setup on P2040/P2040E as they have no L2 */
+ mfspr r2,SPRN_SVR
+ lis r3,SVR_P2040@h
+ ori r3,r3,SVR_P2040@l
+ cmpw r2,r3
+ beq 3f
+
+ lis r3,SVR_P2040_E@h
+ ori r3,r3,SVR_P2040_E@l
+ cmpw r2,r3
+ beq 3f
+
/* Enable/invalidate the L2 cache */
msync
lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
andis. r1,r3,L2CSR0_L2E@h
beq 2b
#endif
+3:
#define EPAPR_MAGIC (0x45504150)
#define ENTRY_ADDR_UPPER 0
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
-#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <asm/cache.h>
#include <asm/mmu.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
.long 0x27051956 /* U-BOOT Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.align 4
.globl _start_cont
/* Cache functions.
*/
+.globl flush_icache
+flush_icache:
.globl invalidate_icache
invalidate_icache:
mfspr r0,L1CSR1
#include <asm-offsets.h>
#include <config.h>
#include <mpc86xx.h>
-#include <timestamp.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/*
* Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
*/
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
#include <asm-offsets.h>
#include <config.h>
#include <mpc8xx.h>
-#include <timestamp.h>
#include <version.h>
#define CONFIG_8xx 1 /* needed for Linux kernel header files */
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
#include <common.h>
#include <config.h>
#include <version.h>
-#include <timestamp.h>
#include <i2c.h>
#include <linux/types.h>
#include <stdio_dev.h>
#include <asm/fsl_serdes.h>
#include <phy.h>
#include <hwconfig.h>
-#ifdef CONFIG_HAS_FSL_DR_USB
-#include <usb.h>
-#endif
+
+#define FSL_MAX_NUM_USB_CTRLS 2
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
char str[5];
int i, j;
- for (i = 1; i <= USB_MAX_DEVICE; i++) {
+ for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) {
int mode_idx = -1, phy_idx = -1;
sprintf(str, "%s%d", "usb", i);
if (hwconfig(str)) {
usb1_defined = 1;
if (mode_idx < 0 && phy_idx < 0)
printf("WARNING: invalid phy or mode\n");
- } else {
- break;
}
}
if (!usb1_defined) {
#include <asm-offsets.h>
#include <config.h>
#include <asm/ppc4xx.h>
-#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <asm/mmu.h>
#include <asm/ppc4xx-isram.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#ifdef CONFIG_SYS_INIT_DCACHE_CS
# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
# define PBxAP PB1AP
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
u32 cgencrl; /* Core general control */
u8 res31[184];
u32 sriopstecr; /* SRIO prescaler timer enable control */
- u8 res32[1788];
+ u32 dcsrcr; /* DCSR Control register */
+ u8 res32[1784];
u32 pmuxcr; /* Pin multiplexing control */
u8 res33[60];
u32 iovselsr; /* I/O voltage selection status */
u8 res37[380];
} ccsr_gur_t;
+#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
+#define FSL_CORENET_DCSR_SZ_4M 0x0
+#define FSL_CORENET_DCSR_SZ_1G 0x3
+
/*
* On p4080 we have an LIODN for msg unit (rmu) but not maintenance
* everything after has RMan thus msg unit LIODN is used for maintenance
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
#define PVR_85xx 0x80200000
#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
+#define PVR_VER_E500_V1 0x8020
+#define PVR_VER_E500_V2 0x8021
+#define PVR_VER_E500MC 0x8023
+#define PVR_VER_E5500 0x8024
#define PVR_86xx 0x80040000
* r8: 0
* r9: 0
*/
-#if defined(CONFIG_85xx) || defined(CONFIG_440)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
#define EPAPR_MAGIC (0x45504150)
#else
#define EPAPR_MAGIC (0x65504150)
return ret;
}
+/*
+ * Verify the device tree.
+ *
+ * This function is called after all device tree fix-ups have been enacted,
+ * so that the final device tree can be verified. The definition of "verified"
+ * is up to the specific implementation. However, it generally means that the
+ * addresses of some of the devices in the device tree are compared with the
+ * actual addresses at which U-Boot has placed them.
+ *
+ * Returns 1 on success, 0 on failure. If 0 is returned, U-boot will halt the
+ * boot process.
+ */
+static int __ft_verify_fdt(void *fdt)
+{
+ return 1;
+}
+__attribute__((weak, alias("__ft_verify_fdt"))) int ft_verify_fdt(void *fdt);
+
static int boot_body_linux(bootm_headers_t *images)
{
ulong rd_len;
/* fixup the initrd now that we know where it should be */
if (*initrd_start && *initrd_end)
fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+
+ if (!ft_verify_fdt(*of_flat_tree))
+ return -1;
}
#endif /* CONFIG_OF_LIBFDT */
return 0;
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <watchdog.h>
#include <net.h>
extern int dram_init(void);
extern int timer_init(void);
-const char version_string[] = U_BOOT_VERSION" ("U_BOOT_DATE" - "U_BOOT_TIME")";
-
unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
#ifndef CONFIG_SYS_NO_FLASH
#include <asm/psr.h>
#include <asm/stack.h>
#include <asm/leon.h>
-#include <timestamp.h>
#include <version.h>
/* Entry for traps which jump to a programmer-specified trap handler. */
.data
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.section ".text"
.align 4
#include <asm/psr.h>
#include <asm/stack.h>
#include <asm/leon.h>
-#include <timestamp.h>
#include <version.h>
/* Entry for traps which jump to a programmer-specified trap handler. */
.extern leon3_snooping_avail
.globl version_string
version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
+ .ascii U_BOOT_VERSION_STRING, "\0"
.section ".text"
.align 4
*
* Interrupt Transfers.
* --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
* will be inserted after the appropriate (depending the interval setting) skeleton TD.
* If an interrupt has been detected the dev->irqhandler is called. The status and number
* of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
movw %ax, %es
movw %ax, %ss
- /* Clear the interupt vectors */
+ /* Clear the interrupt vectors */
lidt blank_idt_ptr
/* Early platform init (setup gpio, etc ) */
/* arch/x86/cpu/interrupts.c */
void set_vector(u8 intnum, void *routine);
-/* arch/x86/lib/interupts.c */
+/* arch/x86/lib/interrupts.c */
void disable_irq(int irq);
void enable_irq(int irq);
int register_timer_isr (timer_fnc_t *isr_func);
/* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */
-int timer_init(void);
int dram_init_f(void);
/* cpu/.../interrupts.c */
#include <watchdog.h>
#include <command.h>
#include <stdio_dev.h>
-#include <timestamp.h>
#include <version.h>
#include <malloc.h>
#include <net.h>
extern ulong __bss_start;
extern ulong __bss_end;
-const char version_string[] =
- U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")";
-
/************************************************************************
* Init Utilities *
************************************************************************
remap gt regs?
map PCI mem/io
map device space
- clear out interupts
+ clear out interrupts
init_timebase
env_init
serial_init
status = i2c_get_data (data, len);
if (status) {
#ifdef DEBUG_I2C
- printf ("Data not recieved: 0x%02x\n", status);
+ printf ("Data not received: 0x%02x\n", status);
#endif
return status;
}
#define dlm ier
#define FCR_FIFO_EN 0x01 /*fifo enable*/
-#define FCR_RXSR 0x02 /*reciever soft reset*/
+#define FCR_RXSR 0x02 /*receiver soft reset*/
#define FCR_TXSR 0x04 /*transmitter soft reset*/
#define CHANNEL2_REGISTER10 0x9070
#define CHANNEL2_REGISTER11 0x9074
-/* MPSCs Interupts */
+/* MPSCs Interrupts */
#define MPSC0_CAUSE 0xb824
#define MPSC0_MASK 0xb8a4
#define afr iirfcrafr
#define FCR_FIFO_EN 0x01 /*fifo enable */
-#define FCR_RXSR 0x02 /*reciever soft reset */
+#define FCR_RXSR 0x02 /*receiver soft reset */
#define FCR_TXSR 0x04 /*transmitter soft reset */
#define FCR_DMS 0x08 /* DMA Mode Select */
return 0;
}
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
+static void board_init_enetaddr(char *var)
{
- puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
- eth_setenv_enetaddr("ethaddr", mac_addr);
+#ifdef CONFIG_NET_MULTI
+ uchar enetaddr[6];
+
+ if (eth_getenv_enetaddr(var, enetaddr))
+ return;
+
+ printf("Warning: %s: generating 'random' MAC address\n", var);
+ bfin_gen_rand_mac(enetaddr);
+ eth_setenv_enetaddr(var, enetaddr);
+#endif
}
+#ifndef CONFIG_BFIN_MAC
+# define bfin_EMAC_initialize(x) 1
+#endif
+#ifndef CONFIG_SMC911X
+# define smc911x_initialize(n, x) 1
+#endif
int board_eth_init(bd_t *bis)
{
- return bfin_EMAC_initialize(bis);
+ /* return ok if at least 1 eth device works */
+ return bfin_EMAC_initialize(bis) &
+ smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
-#endif
int misc_init_r(void)
{
-#ifdef CONFIG_BFIN_MAC
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- board_init_enetaddr(enetaddr);
-#endif
+ board_init_enetaddr("ethaddr");
+ board_init_enetaddr("eth1addr");
gpio_cfi_flash_init();
return 0;
}
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
+static void board_init_enetaddr(char *var)
{
- puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
- eth_setenv_enetaddr("ethaddr", mac_addr);
-}
+#ifdef CONFIG_NET_MULTI
+ uchar enetaddr[6];
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
+ if (eth_getenv_enetaddr(var, enetaddr))
+ return;
+
+ printf("Warning: %s: generating 'random' MAC address\n", var);
+ bfin_gen_rand_mac(enetaddr);
+ eth_setenv_enetaddr(var, enetaddr);
#endif
+}
-#ifdef CONFIG_SMC911X
+#ifndef CONFIG_BFIN_MAC
+# define bfin_EMAC_initialize(x) 1
+#endif
+#ifndef CONFIG_SMC911X
+# define smc911x_initialize(n, x) 1
+#endif
int board_eth_init(bd_t *bis)
{
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ /* return ok if at least 1 eth device works */
+ return bfin_EMAC_initialize(bis) &
+ smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
-#endif
int misc_init_r(void)
{
-#ifdef CONFIG_BFIN_MAC
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- board_init_enetaddr(enetaddr);
-#endif
+ board_init_enetaddr("ethaddr");
+ board_init_enetaddr("eth1addr");
gpio_cfi_flash_init();
remap gt regs?
map PCI mem/io
map device space
- clear out interupts
+ clear out interrupts
init_timebase
env_init
serial_init
status = i2c_get_data(data, len);
if (status) {
#ifdef DEBUG_I2C
- printf("Data not recieved: 0x%02x\n", status);
+ printf("Data not received: 0x%02x\n", status);
#endif
return status;
}
#endif
fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
}
int board_eth_init(bd_t *bis)
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
#endif
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
The 11th column addre will still be mucxed correctly onto the bus.
Also be aware that the MPC8266ADS board Rev B has not connected
- Row addres 13 to anything.
+ Row address 13 to anything.
The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
*/
setup_ddr_bat(dram_size);
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
setup_ddr_bat(dram_size);
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
*/
int
-fpga_load (int mezz, uchar *addr, ulong size)
+fpga_load(int mezz, const uchar *addr, ulong size)
{
hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
xlx_info_t *fp;
xlx_iopins_t *fpgaio;
volatile uchar *fpgabase;
volatile uint cnt;
- uchar *eaddr = addr + size;
+ const uchar *eaddr = addr + size;
int result;
if (mezz)
#define EEPROM_ADDR_IDENT 0 /* identification word offset */
#define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */
#define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */
-#define EEPROM_ADDR_ETHADDR 23 /* ethernet addres offset */
+#define EEPROM_ADDR_ETHADDR 23 /* ethernet address offset */
#endif
return 0;
}
-int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
{
unsigned char *data = (unsigned char *) buf;
int i;
extern int fpga_config_fn(int assert, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
extern int fpga_null_fn(int cookie);
return 0;
}
-int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
{
unsigned char *data = (unsigned char *) buf;
int i;
extern int fpga_config_fn(int assert, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
extern int fpga_null_fn(int cookie);
return 0;
}
-int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
{
unsigned char *data = (unsigned char *) buf;
int i;
extern int fpga_config_fn(int assert, int flush, int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
extern int fpga_null_fn(int cookie);
*
* Interrupt Transfers.
* --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
* will be inserted after the appropriate (depending the interval setting) skeleton TD.
* If an interrupt has been detected the dev->irqhandler is called. The status and number
* of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include "nm.h"
-
-#if defined(DEBUG)
-void show_sdram_registers(void)
-{
- u32 value;
-
- printf("SDRAM Controller Registers --\n");
- mfsdram(SDRAM0_CFG, value);
- printf(" SDRAM0_CFG : 0x%08x\n", value);
- mfsdram(SDRAM0_STATUS, value);
- printf(" SDRAM0_STATUS: 0x%08x\n", value);
- mfsdram(SDRAM0_B0CR, value);
- printf(" SDRAM0_B0CR : 0x%08x\n", value);
- mfsdram(SDRAM0_B1CR, value);
- printf(" SDRAM0_B1CR : 0x%08x\n", value);
- mfsdram(SDRAM0_TR, value);
- printf(" SDRAM0_TR : 0x%08x\n", value);
- mfsdram(SDRAM0_RTR, value);
- printf(" SDRAM0_RTR : 0x%08x\n", value);
-}
-#endif
-
-long int init_ppc405_sdram(unsigned int dram_size)
-{
-#ifdef DEBUG
- printf(__FUNCTION__);
-#endif
- /* disable memory controller */
- mtsdram(SDRAM0_CFG, 0x00000000);
-
- udelay (500);
-
- /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
- mtsdram(SDRAM0_BESR0, 0xffffffff);
-
- /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
- mtsdram(SDRAM0_BESR1, 0xffffffff);
-
- /* Clear SDRAM0_ECCCFG (disable ECC) */
- mtsdram(SDRAM0_ECCCFG, 0x00000000);
-
- /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
- mtsdram(SDRAM0_ECCESR, 0xffffffff);
-
- /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
- */
- mtsdram(SDRAM0_TR, 0x008a4015);
-
- /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
- * and refresh timer
- */
- switch (dram_size >> 20) {
- case 32:
- mtsdram(SDRAM0_B0CR, 0x00062001);
- mtsdram(SDRAM0_RTR, 0x07F00000);
- break;
- case 64:
- mtsdram(SDRAM0_B0CR, 0x00084001);
- mtsdram(SDRAM0_RTR, 0x04100000);
- break;
- case 128:
- mtsdram(SDRAM0_B0CR, 0x000A4001);
- mtsdram(SDRAM0_RTR, 0x04100000);
- break;
- default:
- printf("Invalid memory size of %d MB given\n", dram_size >> 20);
- }
-
- /* Power management idle timer set to the default. */
- mtsdram(SDRAM0_PMIT, 0x07c00000);
-
- udelay (500);
-
- /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
- mtsdram(SDRAM0_CFG, 0x90800000);
-
-#ifdef DEBUG
- printf("%s: done\n", __FUNCTION__);
-#endif
- return dram_size;
-}
+++ /dev/null
-/*
- *(C) Copyright 2005-2007 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-extern void hcu_led_set(u32 value);
-extern u32 get_serial_number(void);
-extern u32 hcu_get_slot(void);
-extern int board_with_pci(void);
-extern void nm_show_print(int generation, int index, int hw_capabilities);
-extern void set_params_for_sw_install(int install_requested, char *board_name );
-extern void common_misc_init_r(void);
-
-enum {
- /* HW_GENERATION_HCU1/2 is no longer supported */
- HW_GENERATION_HCU3 = 0x10,
- HW_GENERATION_HCU4 = 0x20,
- HW_GENERATION_HCU5 = 0x30,
- HW_GENERATION_MCU = 0x08,
- HW_GENERATION_MCU20 = 0x0a,
- HW_GENERATION_MCU25 = 0x09,
-};
-
-#ifdef CONFIG_405GP
-#if defined(DEBUG)
-void show_sdram_registers(void);
-#endif
-long int init_ppc405_sdram(unsigned int dram_size);
-#endif
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include "nm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DEFAULT_ETH_ADDR "ethaddr"
-
-typedef struct {u8 id; char *name;} generation_info;
-
-generation_info generations[6] = {
- {HW_GENERATION_HCU3, "HCU3"},
- {HW_GENERATION_HCU4, "HCU4"},
- {HW_GENERATION_HCU5, "HCU5"},
- {HW_GENERATION_MCU, "MCU"},
- {HW_GENERATION_MCU20, "MCU20"},
- {HW_GENERATION_MCU25, "MCU25"},
-};
-
-void nm_show_print(int generation, int index, int hw_capabilities)
-{
- int j;
- char *generationName=0;
-
- /* reset ANSI terminal color mode */
- printf("\x1B""[0m""Netstal Maschinen AG: ");
- for (j=0; j < (sizeof(generations)/sizeof(generations[0])); j++) {
- if (generations[j].id == generation) {
- generationName = generations[j].name;
- break;
- }
- }
- printf("%s: index %d HW 0x%x\n", generationName, index, hw_capabilities);
- for (j = 0;j < 6; j++) {
- hcu_led_set(1 << j);
- udelay(200 * 1000);
- }
-}
-
-void set_params_for_sw_install(int install_requested, char *board_name )
-{
- if (install_requested) {
- char string[128];
-
- printf("\n\n%s SW-Installation: %d patching boot parameters\n",
- board_name, install_requested);
- setenv("bootdelay", "0");
- setenv("loadaddr", "0x01000000");
- setenv("serverip", "172.25.1.1");
- setenv("bootcmd", "run install");
- sprintf(string, "tftp ${loadaddr} admin/sw_on_hd; "
- "tftp ${loadaddr} installer/%s_sw_inst; "
- "run boot_sw_inst", board_name);
- setenv("install", string);
- sprintf(string, "setenv bootargs emac(0,0)c:%s/%s_sw_inst "
- "e=${ipaddr} h=${serverip} f=0x1000; "
- "bootvx ${loadaddr}%c",
- board_name, board_name, 0);
- setenv("boot_sw_inst", string);
- }
-}
-
-void common_misc_init_r(void)
-{
- IPaddr_t ipaddr;
- char *ipstring;
- uchar ethaddr[6];
-
- if (!eth_getenv_enetaddr(DEFAULT_ETH_ADDR, ethaddr)) {
- /* Must be in sync with CONFIG_ETHADDR */
- u32 serial = get_serial_number();
- ethaddr[0] = 0x00;
- ethaddr[1] = 0x60;
- ethaddr[2] = 0x13;
- ethaddr[3] = (serial >> 16) & 0xff;
- ethaddr[4] = (serial >> 8) & 0xff;
- ethaddr[5] = hcu_get_slot();
- eth_setenv_enetaddr(DEFAULT_ETH_ADDR, ethaddr);
- }
-
- /* IP-Adress update */
- ipstring = getenv("ipaddr");
- if (ipstring == 0)
- ipaddr = string_to_ip("172.25.1.99");
- else
- ipaddr = string_to_ip(ipstring);
- if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
- char tmp[22];
-
- ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
- ip_to_string (ipaddr, tmp);
- printf("%s: enforce %s\n", __FUNCTION__, tmp);
- setenv("ipaddr", tmp);
- saveenv();
- }
-}
+++ /dev/null
-#
-# (C) Copyright 2007-2008 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o \
- ../common/fixed_sdram.o \
- ../common/nm_bsp.o
-
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $^)
-
-clean:
- rm -f $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-HCU4 Configuration Details
-
-Memory Bank 0 -- Flash chip
----------------------------
-
-0xfff00000 - 0xffffffff
-
-The flash chip is really only 512Kbytes, but the high address bit of
-the 1Meg region is ignored, so the flash is replicated through the
-region. Thus, this is consistent with a flash base address 0xfff80000.
-
-The placement at the end is to be consistent with reset behavior,
-where the processor itself initially uses this bus to load the branch
-vector and start running.
-
-On-Chip Memory
---------------
-
-0xf4000000 - 0xf4000fff
-
-The 405GPr includes a 4K on-chip memory that can be placed however
-software chooses. I choose to place the memory at this address, to
-keep it out of the cachable areas.
-
-
-Internal Peripherals
---------------------
-
-0xef600300 - 0xef6008ff
-
-These are scattered various peripherals internal to the PPC405GPr
-chip.
-
-Chip-Select 2: Flash Memory
----------------------------
-
-0x70000000
-
-Chip-Select 3: CAN Interface
-----------------------------
-0x7800000
-
-
-Chip-Select 4: IMC-bus standard
--------------------------------
-
-Our IO-Bus (slow version)
-
-
-Chip-Select 5: IMC-bus fast (inactive)
---------------------------------------
-
-Our IO-Bus (fast, but not yet use)
-
-
-Memory Bank 1 -- SDRAM
--------------------------------------
-
-0x00000000 - 0x1ffffff # Default 32 MB
+++ /dev/null
-#
-# (C) Copyright 2005 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Netstal Maschinen AG: HCU4 boards
-#
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG -g
-endif
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/u-boot.h>
-#include "../common/nm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000)
-#define HCU_SLOT_ADDRESS (0x7C000000 + 0x400000)
-#define HCU_DIGITAL_IO_REGISTER (0x7C000000 + 0x500000)
-#define HCU_SW_INSTALL_REQUESTED 0x10
-
-/*
- * This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
- * of being in the init_sequence array.
- *
- * The SDRAM has been initialized already -- start.S:start called
- * init.S:init_sdram early on -- but it is not yet being used for
- * anything, not even stack. So be careful.
- */
-
-/* Attention: If you want 1 microsecs times from the external oscillator
- * 0x00004051 is okay for u-boot/linux, but different from old vxworks values
- * 0x00804051 causes problems with u-boot and linux!
- */
-#define CPC0_CR0_VALUE 0x0030103c
-#define CPC0_CR1_VALUE 0x00004051
-
-int board_early_init_f (void)
-{
- /*
- * Interrupt controller setup for the HCU4 board.
- * Note: IRQ 0-15 405GP internally generated; high; level sensitive
- * IRQ 16 405GP internally generated; low; level sensitive
- * IRQ 17-24 RESERVED/UNUSED
- * IRQ 31 (EXT IRQ 6) (unused)
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
- mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
- mtdcr(CPC0_ECR, 0x60606000);
- mtdcr(CPC0_EIRR, 0x7C000000);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_PRE_INIT
-int board_pre_init (void)
-{
- return board_early_init_f ();
-}
-#endif
-
-int sys_install_requested(void)
-{
- u16 ioValue = in_be16((u16 *)HCU_DIGITAL_IO_REGISTER);
- return (ioValue & HCU_SW_INSTALL_REQUESTED) != 0;
-}
-
-int checkboard (void)
-{
- u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
- u16 generation = boardVersReg & 0xf0;
- u16 index = boardVersReg & 0x0f;
-
- /* Cannot be done in board_early_init */
- mtdcr(CPC0_CR0, CPC0_CR0_VALUE);
-
- /* Force /RTS to active. The board it not wired quite
- * correctly to use cts/rtc flow control, so just force the
- * /RST active and forget about it.
- */
- writeb (readb (0xef600404) | 0x03, 0xef600404);
- nm_show_print(generation, index, 0);
-
- return 0;
-}
-
-u32 hcu_led_get(void)
-{
- return (~(in_be32((u32 *)GPIO0_OR)) >> 23) & 0xff;
-}
-
-/*
- * hcu_led_set value to be placed into the LEDs (max 6 bit)
- */
-void hcu_led_set(u32 value)
-{
- u32 tmp = ~value;
-
- tmp = (tmp << 23) | 0x7FFFFF;
- out_be32((u32 *)GPIO0_OR, tmp);
-}
-
-/*
- * hcu_get_slot
- */
-u32 hcu_get_slot(void)
-{
- u16 slot = in_be16((u16 *)HCU_SLOT_ADDRESS);
- return slot & 0x7f;
-}
-
-/*
- * get_serial_number
- */
-u32 get_serial_number(void)
-{
- u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
-
- if (serial == 0xffffffff)
- return 0;
-
- return serial;
-}
-
-
-/*
- * misc_init_r.
- */
-
-int misc_init_r(void)
-{
- common_misc_init_r();
- set_params_for_sw_install( sys_install_requested(), "hcu4" );
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- long dram_size = 0;
- u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
- u16 generation = boardVersReg & 0xf0;
- u16 index = boardVersReg & 0x0f;
-
- if (generation == HW_GENERATION_HCU3 && index < 0xf)
- dram_size = 32 << 20; /* 32 MB - RAM */
- else
- dram_size = 64 << 20; /* 64 MB - RAM */
- init_ppc405_sdram(dram_size);
-
-#ifdef DEBUG
- show_sdram_registers();
-#endif
-
- return dram_size;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = 1;
- info->chipwidth = 1;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
+++ /dev/null
-#
-# (C) Copyright 2007-2008 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o \
- sdram.o \
- ../common/nm_bsp.o
-SOBJS = init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-all: $(LIB) $(SOBJS)
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $^)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-HCU5 configuration details and startup sequence
-
-(C) Copyright 2007 Netstal Maschinen AG
- Niklaus Giger (Niklaus.Giger@netstal.com)
-
-TODO:
------
-- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT !
- - Does not occur if both EMAC are connected
-- Fix RTS/CTS problem (HW?)
- CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
- Switching to interrupt driven serial input mode
-
-Caveats:
---------
-Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c)
-see hcu5.c.
-
-
-Memory Bank 0 -- Flash chip
----------------------------
-
-0xfff00000 - 0xffffffff
-
-The flash chip is really only 512Kbytes, but the high address bit of
-the 1Meg region is ignored, so the flash is replicated through the
-region. Thus, this is consistent with a flash base address 0xfff80000.
-
-The placement at the end is to be consistent with reset behavior,
-where the processor itself initially uses this bus to load the branch
-vector and start running.
-
-On-Chip Memory
---------------
-
-0xe0010000- 0xe0013fff CONFIG_SYS_OCM_BASE
-The 440EPx includes a 16K on-chip memory that can be placed however
-software chooses.
-
-Internal Peripherals
---------------------
-
-0xef600300 - 0xef6008ff
-
-These are scattered various peripherals internal to the PPC440EPX
-chip.
-
-Chip-Select 2: Flash Memory
----------------------------
-
-Not used
-
-Chip-Select 3: CAN Interface
-----------------------------
-0xc800000: 2 Intel 82527 CAN-Controller
-
-
-Chip-Select 4: IMC-bus standard
--------------------------------
-
-0xcc00000: Netstal specific IO-Bus
-
-
-Chip-Select 5: IMC-bus fast (inactive)
---------------------------------------
-
-0xce00000: Netstal specific IO-Bus (fast, but not yet used)
-
-
-Memory Bank 1 -- DDR2
--------------------------------------
-
-0x00000000 - 0xfffffff # Default 256 MB
-
-PCI ??
-
-USB ??
-Only USB_STORAGE is enabled to load vxWorks
-from a memory stick.
-
-System-LEDs ??? (Analog zu HCU4 ???)
-
-Startup sequence
-----------------
-
-(arch/powerpc/cpu/ppc4xx/resetvec.S)
-depending on configs option
-call _start_440 _start_pci oder _start
-
-(arch/powerpc/cpu/ppc4xx/start.S)
-
-_start_440:
- initialize register like
- CCR0
- debug
- setup interrupt vectors
- configure cache regions
- clear and setup TLB
- enable internal RAM
- jump start_ram
- which in turn will jump to start
-_start:
- Clear and set up some registers.
- Debug setup
- Setup the internal SRAM
- Setup the stack in internal SRAM
- setup stack pointer (r1)
- setup GOT
- call cpu_init_f /* run low-level CPU init code (from Flash) */
-
- call cpu_init_f
- board_init_f: (arch/powerpc/lib\board.c)
- init_sequence defines a list of function to be called
- board_early_init_f: (board/netstal/hcu5/hcu5.c)
- We are using Bootstrap-Option A
- if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot
- Setup the GPIO pins
- Setup the interrupt controller polarities, triggers, etc.
- Ethernet, PCI, USB enable
- setup BOOT FLASH (Chip timing)
- init_baudrate,
- serial_init
- checkcpu
- misc_init_f #ifdef
- init_func_i2c #ifdef
- post_init_f #ifdef
- init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c
- (EYE function removed!!)
- test_dram call
-
- * Reserve memory at end of RAM for (top down in that order):
- * - kernel log buffer
- * - protected RAM
- * - LCD framebuffer
- * - monitor code
- * - board info struct
- Save local variables to board info struct
- call relocate_code() does not return
- relocate_code: (arch/powerpc/cpu/ppc4xx/start.S)
--------------------------------------------------------
-From now on our copy is in RAM and we will run from there,
- starting with board_init_r
--------------------------------------------------------
- board_init_r: (arch/powerpc/lib\board.c)
- setup bd function pointers
- trap_init
- flash_init: (board/netstal/hcu5/flash.c)
- /* setup for u-boot erase, update */
- setup bd flash info
- cpu_init_r: (arch/powerpc/cpu/ppc4xx/cpu_init.c)
- peripheral chip select in using defines like
- CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h
- mem_malloc_init
- malloc_bin_reloc
- spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
- env_relocated
- misc_init_r(bd): (board/netstal/hcu5.c)
- ethaddr mit serial number ergänzen
- Then we will somehow go into the command loop
-
-Most of the HW specific code for the HCU5 may be found in
-include/configs/hcu5.h
-board/netstal/hcu5/*
-arch/powerpc/cpu/ppc4xx/*
-arch/powerpc/lib/*
-include/ppc440.h
-
-Drivers for serial etc are found under drivers/
-
-Don't ask question if you did not look at the README !!
-Most CONFIG_SYS_* and CONFIG_* switches are mentioned/explained there.
+++ /dev/null
-#
-# (C) Copyright 2005 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Netstal Maschinen AG: HCU5 boards
-#
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG -g
-endif
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc440.h>
-#include <asm/io.h>
-#include <asm/4xx_pci.h>
-
-#include "../common/nm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#undef BOOTSTRAP_OPTION_A_ACTIVE
-
-#define SDR0_CP440 0x0180
-
-#define SYSTEM_RESET 0x30000000
-#define CHIP_RESET 0x20000000
-
-#define SDR0_ECID0 0x0080
-#define SDR0_ECID1 0x0081
-#define SDR0_ECID2 0x0082
-#define SDR0_ECID3 0x0083
-
-#define SYS_IO_ADDRESS (CONFIG_SYS_CS_2 + 0x00e00000)
-#define SYS_SLOT_ADDRESS (CONFIG_SYS_CPLD + 0x00400000)
-#define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000)
-#define HCU_SW_INSTALL_REQUESTED 0x10
-
-/*
- * This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
- * of being in the init_sequence array.
- *
- * The SDRAM has been initialized already -- start.S:start called
- * init.S:init_sdram early on -- but it is not yet being used for
- * anything, not even stack. So be careful.
- */
-
-int board_early_init_f(void)
-{
-
-#ifdef BOOTSTRAP_OPTION_A_ACTIVE
- /* Booting with Bootstrap Option A
- * First boot, with CPR0_ICFG_RLI_MASK == 0
- * no we setup varios boot strapping register,
- * then we do reset the PPC440 using a chip reset
- * Unfortunately, we cannot use this option, as Nto1 is not set
- * with Bootstrap Option A and cannot be changed later on by SW
- * There are no other possible boostrap options with a 8 bit ROM
- * See Errata (Version 1.04) CHIP_9
- */
-
- u32 cpr0icfg;
- u32 dbcr;
-
- mfcpr(CPR0_ICFG, cpr0icfg);
- if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
- mtcpr(CPR0_MALD, 0x02000000);
- mtcpr(CPR0_OPBD, 0x02000000);
- mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
- mtcpr(CPR0_PLLC, 0x40000238);
- mtcpr(CPR0_PLLD, 0x01010414);
- mtcpr(CPR0_PRIMAD, 0x01000000);
- mtcpr(CPR0_PRIMBD, 0x01000000);
- mtcpr(CPR0_SPCID, 0x03000000);
- mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
- mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
- mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
-
- /*
- * Initiate system reset in debug control register DBCR
- */
- dbcr = mfspr(SPRN_DBCR0);
- mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
- }
- mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
-#endif
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, 0xb8400000);
-
- /*
- * Setup the GPIO pins
- */
- out32(GPIO0_OR, 0x00000000);
- out32(GPIO0_TCR, 0x7C2FF1CF);
- out32(GPIO0_OSRL, 0x40055000);
- out32(GPIO0_OSRH, 0x00000000);
- out32(GPIO0_TSRL, 0x40055000);
- out32(GPIO0_TSRH, 0x00000400);
- out32(GPIO0_ISR1L, 0x40000000);
- out32(GPIO0_ISR1H, 0x00000000);
- out32(GPIO0_ISR2L, 0x00000000);
- out32(GPIO0_ISR2H, 0x00000000);
- out32(GPIO0_ISR3L, 0x00000000);
- out32(GPIO0_ISR3H, 0x00000000);
-
- out32(GPIO1_OR, 0x00000000);
- out32(GPIO1_TCR, 0xC6007FFF);
- out32(GPIO1_OSRL, 0x00140000);
- out32(GPIO1_OSRH, 0x00000000);
- out32(GPIO1_TSRL, 0x00000000);
- out32(GPIO1_TSRH, 0x00000000);
- out32(GPIO1_ISR1L, 0x05415555);
- out32(GPIO1_ISR1H, 0x40000000);
- out32(GPIO1_ISR2L, 0x00000000);
- out32(GPIO1_ISR2H, 0x00000000);
- out32(GPIO1_ISR3L, 0x00000000);
- out32(GPIO1_ISR3H, 0x00000000);
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */
- mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */
-
- /* setup BOOT FLASH */
- mtsdr(SDR0_CUST0, 0xC0082350);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_PRE_INIT
-int board_pre_init(void)
-{
- return board_early_init_f();
-}
-
-#endif
-
-int sys_install_requested(void)
-{
- u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
- return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
-}
-
-int checkboard(void)
-{
- u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
- u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
- u16 generation = in_be16(boardVersReg) & 0xf0;
- u16 index = in_be16(boardVersReg) & 0x0f;
- u32 ecid0, ecid1, ecid2, ecid3;
-
- nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
- mfsdr(SDR0_ECID0, ecid0);
- mfsdr(SDR0_ECID1, ecid1);
- mfsdr(SDR0_ECID2, ecid2);
- mfsdr(SDR0_ECID3, ecid3);
-
- printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
-
- return 0;
-}
-
-u32 hcu_led_get(void)
-{
- return in16(SYS_IO_ADDRESS) & 0x3f;
-}
-
-/*
- * hcu_led_set value to be placed into the LEDs (max 6 bit)
- */
-void hcu_led_set(u32 value)
-{
- out16(SYS_IO_ADDRESS, value);
-}
-
-/*
- * get_serial_number
- */
-u32 get_serial_number(void)
-{
- u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
-
- if (in_be32(serial) == 0xffffffff)
- return 0;
-
- return in_be32(serial);
-}
-
-
-/*
- * hcu_get_slot
- */
-u32 hcu_get_slot(void)
-{
- u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
- return in_be16(slot) & 0x7f;
-}
-
-
-/*
- * misc_init_r.
- */
-int misc_init_r(void)
-{
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-#endif
-
- /*
- * USB stuff...
- */
-
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
-
- /* An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
-
- /* To enable the USB 2.0 Device function through the UTMI interface */
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /*clear resets*/
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
- printf("USB: Host(int phy) Device(ext phy)\n");
-
- common_misc_init_r();
- set_params_for_sw_install( sys_install_requested(), "hcu5" );
- /* We cannot easily enable trace before, as there are other
- * routines messing around with sdr0_pfc1. And I do not need it.
- */
- if (mfspr(SPRN_DBCR0) & 0x80000000) {
- /* External debugger alive
- * enable trace facilty for Lauterbach
- * CCR0[DTB]=0 Enable broadcast of trace information
- * SDR0_PFC0[TRE] Trace signals are enabled instead of
- * GPIO49-63
- */
- mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));
- mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
- }
- return 0;
-}
-#ifdef CONFIG_PCI
-int board_with_pci(void)
-{
- u32 reg;
-
- mfsdr(SDR0_PCI0, reg);
- return (reg & SDR0_PCI0_PAE_MASK);
-}
-
-/*
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- */
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- if (!board_with_pci()) { return 0; }
-
- /*
- * Set priority for all PLB3 devices to 0.
- * Set PLB3 arbiter to fair mode.
- */
- mfsdr(SDR0_AMP1, addr);
- mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3A0_ACR);
- mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */
-
- /*
- * Set priority for all PLB4 devices to 0.
- */
- mfsdr(SDR0_AMP0, addr);
- mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4A0_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4A0_ACR, addr); /* Sequoia */
-
- /*
- * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
- * Workaround: Disable write pipelining to DDR SDRAM by setting
- * PLB4A0_ACR[WRP] = 0.
- */
- mtdcr(PLB4A0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
-
- /* Segment1 */
- mtdcr(PLB4A1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
-
- return board_with_pci();
-}
-
-/*
- * Override weak default pci_master_init()
- */
-void pci_master_init(struct pci_controller *hose)
-{
- if (!board_with_pci())
- return;
-
- __pci_master_init(hose);
-}
-#endif /* defined(CONFIG_PCI) */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = 1;
- info->chipwidth = 1;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
+++ /dev/null
-/*
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
- tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
- /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
- AC_RWX | SA_IG )
-
- /* TLB#2: TLB-entry for EBC */
- tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG)
-
- /*
- * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
- * off to use the speed up boot process. It is patched after relocation
- * to enable SA_I
- */
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
- AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
- /* TLB#4: */
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
- AC_RW | SA_IG )
- /* TLB#5: */
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
- AC_RW | SA_IG )
- /* TLB#6: */
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
- AC_RW | SA_IG )
-
- /* TLB-entry for Internal Registers & OCM */
- /* TLB#7: */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
- AC_RWX | SA_IG )
-
- /*TLB-entry PCI registers*/
- /* TLB#8: */
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for peripherals */
- /* TLB#9: */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
- /* CAN */
- /* TLB#10: */
- tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG )
-
- /* TLB#11: CPLD and IMC-Standard 32 MB */
- tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG )
-
- /* TLB#12: */
- tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
- AC_RWX | SA_IG )
-
- /* IMC-Fast 32 MB */
- /* TLB#13: */
- tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG )
- /* TLB#14: */
- tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
- AC_RWX | SA_IG )
-
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* define DEBUG for debug output */
-#undef DEBUG
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/ppc440.h>
-
-void hcu_led_set(u32 value);
-void dcbz_area(u32 start_address, u32 num_bytes);
-
-#define ECC_RAM 0x03267F0B
-#define NO_ECC_RAM 0x00267F0B
-
-#define HCU_HW_SDRAM_CONFIG_MASK 0x7
-
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
- /* disable caching on DDR2 */
-
-void board_add_ram_info(int use_default)
-{
- PPC4xx_SYS_INFO board_cfg;
- u32 val;
-
- mfsdram(DDR0_22, val);
- val &= DDR0_22_CTRL_RAW_MASK;
- switch (val) {
- case DDR0_22_CTRL_RAW_ECC_DISABLE:
- puts(" (ECC disabled");
- break;
- case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
- puts(" (ECC check only");
- break;
- case DDR0_22_CTRL_RAW_NO_ECC_RAM:
- puts(" (no ECC ram");
- break;
- case DDR0_22_CTRL_RAW_ECC_ENABLE:
- puts(" (ECC enabled");
- break;
- }
-
- get_sys_info(&board_cfg);
- printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
-
- mfsdram(DDR0_03, val);
- val = DDR0_03_CASLAT_DECODE(val);
- printf(", CL%d)", val);
-}
-
-/*--------------------------------------------------------------------
- * wait_for_dlllock.
- *--------------------------------------------------------------------*/
-static int wait_for_dlllock(void)
-{
- unsigned long val;
- int wait = 0;
-
- /* -----------------------------------------------------------+
- * Wait for the DCC master delay line to finish calibration
- * ----------------------------------------------------------*/
- mtdcr(SDRAM0_CFGADDR, DDR0_17);
- val = DDR0_17_DLLLOCKREG_UNLOCKED;
-
- while (wait != 0xffff) {
- val = mfdcr(SDRAM0_CFGDATA);
- if ((val & DDR0_17_DLLLOCKREG_MASK) ==
- DDR0_17_DLLLOCKREG_LOCKED)
- /* dlllockreg bit on */
- return 0;
- else
- wait++;
- }
- debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
- debug("Waiting for dlllockreg bit to raise\n");
-
- return -1;
-}
-
-/***********************************************************************
- *
- * sdram_panic -- Panic if we cannot configure the sdram correctly
- *
- ************************************************************************/
-void sdram_panic(const char *reason)
-{
- printf("\n%s: reason %s", __FUNCTION__, reason);
- hcu_led_set(0xff);
- while (1) {
- }
- /* Never return */
-}
-
-#ifdef CONFIG_DDR_ECC
-void blank_string(int size)
-{
- int i;
-
- for (i=0; i<size; i++)
- putc('\b');
- for (i=0; i<size; i++)
- putc(' ');
- for (i=0; i<size; i++)
- putc('\b');
-}
-/*---------------------------------------------------------------------------+
- * program_ecc.
- *---------------------------------------------------------------------------*/
-static void program_ecc(unsigned long start_address, unsigned long num_bytes)
-{
- u32 val;
- char str[] = "ECC generation -";
-#if defined(CONFIG_PRAM)
- u32 *magicPtr;
- u32 magic;
-
- if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) {
- /* only if no external debugger is alive!
- * Check whether vxWorks is using EDR logging, if yes zero
- * also PostMortem and user reserved memory
- */
- magicPtr = (u32 *)(start_address + num_bytes -
- (CONFIG_PRAM*1024) + sizeof(u32));
- magic = in_be32(magicPtr);
- debug("%s: CONFIG_PRAM %d kB magic 0x%x 0x%p\n",
- __FUNCTION__, CONFIG_PRAM,
- magicPtr, magic);
- if (magic == 0xbeefbabe) {
- printf("%s: preserving at %p\n", __FUNCTION__, magicPtr);
- num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
- }
- }
-#endif
-
- sync();
-
- puts(str);
-
- /* ECC bit set method for cached memory */
- /* Fast method, no noticeable delay */
- dcbz_area(start_address, num_bytes);
- /* Write modified dcache lines back to memory */
- clean_dcache_range(start_address, start_address + num_bytes);
- blank_string(strlen(str));
-
- /* Clear error status */
- mfsdram(DDR0_00, val);
- mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
-
- /*
- * Clear possible ECC errors
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
-
- /* Set 'int_mask' parameter to functionnal value */
- mfsdram(DDR0_01, val);
- mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
- DDR0_01_INT_MASK_ALL_OFF));
-
- return;
-}
-#endif
-
-
-/***********************************************************************
- *
- * initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
-{
- unsigned int dram_size = 0;
-
- mtsdram(DDR0_02, 0x00000000);
-
- /* Values must be kept in sync with Excel-table <<A0001492.>> ! */
- mtsdram(DDR0_00, 0x0000190A);
- mtsdram(DDR0_01, 0x01000000);
- mtsdram(DDR0_03, 0x02030602);
- mtsdram(DDR0_04, 0x0A020200);
- mtsdram(DDR0_05, 0x02020307);
- switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) {
- case 1:
- dram_size = 256 * 1024 * 1024 ;
- mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
- mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
- mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
- break;
- case 0:
- default:
- dram_size = 128 * 1024 * 1024 ;
- mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
- mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
- mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
- break;
- }
- mtsdram(DDR0_07, 0x00090100);
-
- /*
- * TCPD=200 cycles of clock input is required to lock the DLL.
- * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
- */
- mtsdram(DDR0_08, 0x02C80001);
- mtsdram(DDR0_09, 0x00011D5F);
- mtsdram(DDR0_10, 0x00000100);
- mtsdram(DDR0_12, 0x00000003);
- mtsdram(DDR0_14, 0x00000000);
- mtsdram(DDR0_17, 0x1D000000);
- mtsdram(DDR0_18, 0x1D1D1D1D);
- mtsdram(DDR0_19, 0x1D1D1D1D);
- mtsdram(DDR0_20, 0x0B0B0B0B);
- mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
- mtsdram(DDR0_22, ECC_RAM);
-#else
- mtsdram(DDR0_22, NO_ECC_RAM);
-#endif
-
- mtsdram(DDR0_23, 0x00000000);
- mtsdram(DDR0_24, 0x01020001);
- mtsdram(DDR0_26, 0x2D930517);
- mtsdram(DDR0_27, 0x00008236);
- mtsdram(DDR0_28, 0x00000000);
- mtsdram(DDR0_31, 0x00000000);
- mtsdram(DDR0_42, 0x01000006);
- mtsdram(DDR0_44, 0x00000003);
- mtsdram(DDR0_02, 0x00000001);
- wait_for_dlllock();
- mtsdram(DDR0_00, 0x40000000); /* Zero init bit */
-
- /*
- * Program tlb entries for this size (dynamic)
- */
- remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
- program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
-
- /*
- * Setup 2nd TLB with same physical address but different virtual
- * address with cache enabled. This is done for fast ECC generation.
- */
- program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
-
-#ifdef CONFIG_DDR_ECC
- /*
- * If ECC is enabled, initialize the parity bits.
- */
- program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
-#endif
-
- return (dram_size);
-}
+++ /dev/null
-#
-# (C) Copyright 2007-2008 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o \
- ../common/fixed_sdram.o \
- ../common/nm_bsp.o
-
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $^)
-
-clean:
- rm -f $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-MCU25 Configuration Details
-
-Memory Bank 0 -- Flash chip
----------------------------
-
-0xfff00000 - 0xffffffff
-
-The flash chip is really only 512Kbytes, but the high address bit of
-the 1Meg region is ignored, so the flash is replicated through the
-region. Thus, this is consistent with a flash base address 0xfff80000.
-
-The placement at the end is to be consistent with reset behavior,
-where the processor itself initially uses this bus to load the branch
-vector and start running.
-
-On-Chip Memory
---------------
-
-0xf4000000 - 0xf4000fff
-
-The 405GPr includes a 4K on-chip memory that can be placed however
-software chooses. I choose to place the memory at this address, to
-keep it out of the cachable areas.
-
-
-Internal Peripherals
---------------------
-
-0xef600300 - 0xef6008ff
-
-These are scattered various peripherals internal to the PPC405GPr
-chip.
-
-Chip-Select 2: Flash Memory
----------------------------
-
-0x70000000
-
-Chip-Select 3: CAN Interface
-----------------------------
-0x7800000
-
-
-Chip-Select 4: IMC-bus standard
--------------------------------
-
-Our IO-Bus (slow version)
-
-
-Chip-Select 5: IMC-bus fast (inactive)
---------------------------------------
-
-Our IO-Bus (fast, but not yet use)
-
-
-Memory Bank 1 -- SDRAM
--------------------------------------
-
-0x00000000 - 0x2ffffff # Default 64 MB
+++ /dev/null
-#
-# (C) Copyright 2005 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Netstal Maschinen AG: MCU25 board
-#
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG -g
-endif
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/u-boot.h>
-#include "../common/nm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define MCU25_SLOT_ADDRESS (0x7A000000 + 0x0A)
-#define MCU25_DIGITAL_IO_REGISTER (0x7A000000 + 0xc0)
-
-#define MCU25_LED_REGISTER_ADDRESS (0x7C000000 + 0x10)
-#define MCU25_VERSIONS_REGISTER (0x7C000000 + 0x0C)
-#define MCU25_IO_CONFIGURATION (0x7C000000 + 0x0e)
-#define MCU_SW_INSTALL_REQUESTED 0x08
-
-#define SDRAM_LEN (32 << 20) /* 32 MB - RAM */
-
-/*
- * This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
- * of being in the init_sequence array.
- *
- * The SDRAM has been initialized already -- start.S:start called
- * init.S:init_sdram early on -- but it is not yet being used for
- * anything, not even stack. So be careful.
- */
-
-/* Attention: If you want 1 microsecs times from the external oscillator
- * 0x00004051 is okay for u-boot/linux, but different from old vxworks values
- * 0x00804051 causes problems with u-boot and linux!
- */
-#define CPC0_CR0_VALUE 0x0007F03C
-#define CPC0_CR1_VALUE 0x00004051
-
-int board_early_init_f (void)
-{
- /* Documented in A-1171
- *
- * Interrupt controller setup for the MCU25 board.
- * Note: IRQ 0-15 405GP internally generated; high; level sensitive
- * IRQ 16 405GP internally generated; low; level sensitive
- * IRQ 17-24 RESERVED/UNUSED
- * IRQ 31 (EXT IRQ 6) (unused)
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
- mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
- mtdcr(CPC0_ECR, 0x60606000);
- mtdcr(CPC0_EIRR, 0x7C000000);
- out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR );
- out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);
- out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);
- mtspr(SPRN_CCR0, 0x00700000);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_PRE_INIT
-int board_pre_init (void)
-{
- return board_early_init_f ();
-}
-#endif
-
-int sys_install_requested(void)
-{
- u16 ioValue = in_be16((u16 *)MCU25_DIGITAL_IO_REGISTER);
- return (ioValue & MCU_SW_INSTALL_REQUESTED) != 0;
-}
-
-int checkboard (void)
-{
- u16 boardVersReg = in_be16((u16 *)MCU25_VERSIONS_REGISTER);
- u16 hwConfig = in_be16((u16 *)MCU25_IO_CONFIGURATION);
- u16 generation = boardVersReg & 0x0f;
- u16 index = boardVersReg & 0xf0;
-
- /* Cannot be done in board_early_init */
- mtdcr(CPC0_CR0, CPC0_CR0_VALUE);
-
- /* Force /RTS to active. The board it not wired quite
- * correctly to use cts/rtc flow control, so just force the
- * /RST active and forget about it.
- */
- writeb (readb (0xef600404) | 0x03, 0xef600404);
- nm_show_print(generation, index, hwConfig);
- return 0;
-}
-
-u32 hcu_led_get(void)
-{
- return in_be16((u16 *)MCU25_LED_REGISTER_ADDRESS) & 0x3ff;
-}
-
-/*
- * hcu_led_set value to be placed into the LEDs (max 6 bit)
- */
-void hcu_led_set(u32 value)
-{
- out_be16((u16 *)MCU25_LED_REGISTER_ADDRESS, value);
-}
-
-/*
- * hcu_get_slot
- */
-u32 hcu_get_slot(void)
-{
- u16 slot = in_be16((u16 *)MCU25_SLOT_ADDRESS);
- return slot & 0x7f;
-}
-
-/*
- * get_serial_number
- */
-u32 get_serial_number(void)
-{
- u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
-
- if (serial == 0xffffffff)
- return 0;
-
- return serial;
-}
-
-
-/*
- * misc_init_r.
- */
-
-int misc_init_r(void)
-{
- common_misc_init_r();
- set_params_for_sw_install( sys_install_requested(), "mcu25" );
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- unsigned int dram_size = 64*1024*1024;
- init_ppc405_sdram(dram_size);
-
-#ifdef DEBUG
- show_sdram_registers();
-#endif
-
- return dram_size;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = 1;
- info->chipwidth = 1;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
dram_size = fixed_sdram ();
#endif
- puts (" DDR: ");
+ debug (" DDR: ");
return dram_size;
}
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#endif
}
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup (blob, bd);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
int
board_early_init_f(void)
{
return 0;
}
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
+static void board_init_enetaddr(char *var)
{
- puts("Warning: Generating 'random' MAC address\n");
- bfin_gen_rand_mac(mac_addr);
- eth_setenv_enetaddr("ethaddr", mac_addr);
+#ifdef CONFIG_NET_MULTI
+ uchar enetaddr[6];
+
+ if (eth_getenv_enetaddr(var, enetaddr))
+ return;
+
+ printf("Warning: %s: generating 'random' MAC address\n", var);
+ bfin_gen_rand_mac(enetaddr);
+ eth_setenv_enetaddr(var, enetaddr);
+#endif
}
+#ifndef CONFIG_BFIN_MAC
+# define bfin_EMAC_initialize(x) 1
+#endif
+#ifndef CONFIG_SMC911X
+# define smc911x_initialize(n, x) 1
+#endif
int board_eth_init(bd_t *bis)
{
- return bfin_EMAC_initialize(bis);
+ /* return ok if at least 1 eth device works */
+ return bfin_EMAC_initialize(bis) &
+ smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
-#endif
int misc_init_r(void)
{
-#ifdef CONFIG_BFIN_MAC
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- board_init_enetaddr(enetaddr);
-#endif
+ board_init_enetaddr("ethaddr");
+ board_init_enetaddr("eth1addr");
gpio_cfi_flash_init();
/* Local functions */
static int detect_num_flash_banks(void);
-static long int get_ddr_bank_size(short cs, volatile long *base);
+static long int get_ddr_bank_size(short cs, long *base);
static void set_cs_bounds(short cs, long base, long size);
static void set_cs_config(short cs, long config);
static void set_ddr_config(void);
debug("\nDetecting Bank%d\n", cs);
bank_size = get_ddr_bank_size(cs,
- (volatile long*)(CONFIG_SYS_DDR_BASE + size));
+ (long *)(CONFIG_SYS_DDR_BASE + size));
size += bank_size;
debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
/*************************************************************************
* Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
*/
-static long int get_ddr_bank_size(short cs, volatile long *base)
+static long int get_ddr_bank_size(short cs, long *base)
{
/* This array lists all valid DDR SDRAM configurations, with
* Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
MIP405 powerpc ppc4xx mip405 mpl
MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T
PIP405 powerpc ppc4xx pip405 mpl
-hcu4 powerpc ppc4xx hcu4 netstal
-hcu5 powerpc ppc4xx hcu5 netstal
-mcu25 powerpc ppc4xx mcu25 netstal
alpr powerpc ppc4xx - prodrive
p3p440 powerpc ppc4xx - prodrive
KAREF powerpc ppc4xx karef sandburst
} /* bank */
}
if (!found) {
- /* error, addres not in flash */
+ /* error, address not in flash */
printf("Error: end address (0x%08lx) not in flash!\n", *addr);
return 1;
}
{
const void *fit_hdr = (const void *)fpga_data;
int noffset;
- void *fit_data;
+ const void *fit_data;
if (fit_uname == NULL) {
puts ("No FIT subimage unit name\n");
return 0;
}
-int setenv(char *varname, char *varvalue)
+int setenv(const char *varname, const char *varvalue)
{
- char * const argv[4] = { "setenv", varname, varvalue, NULL };
+ const char * const argv[4] = { "setenv", varname, varvalue, NULL };
+
if ((varvalue == NULL) || (varvalue[0] == '\0'))
- return _do_env_set(0, 2, argv);
+ return _do_env_set(0, 2, (char * const *)argv);
else
- return _do_env_set(0, 3, argv);
+ return _do_env_set(0, 3, (char * const *)argv);
}
int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
* return address of storage for that variable,
* or NULL if not found
*/
-char *getenv(char *name)
+char *getenv(const char *name)
{
if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
ENTRY e, *ep;
/*
* Look up variable from environment for restricted C runtime env.
*/
-int getenv_f(char *name, char *buf, unsigned len)
+int getenv_f(const char *name, char *buf, unsigned len)
{
int i, nxt;
#include <common.h>
#include <command.h>
#include <version.h>
+#include <linux/compiler.h>
-extern char version_string[];
+const char __weak version_string[] = U_BOOT_VERSION_STRING;
int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <version.h>
#ifdef CONFIG_MODEM_SUPPORT
#include <malloc.h> /* for free() prototype */
#endif
#ifdef CONFIG_VERSION_VARIABLE
{
- extern char version_string[];
-
setenv ("ver", version_string); /* set version variable */
}
#endif /* CONFIG_VERSION_VARIABLE */
#if defined(CONFIG_SYS_PSC6)
serial_register(&serial6_device);
#endif
+#endif
+#if defined(CONFIG_SYS_BFIN_UART)
+ serial_register_bfin_uart();
#endif
serial_assign (default_serial_console ()->name);
}
ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n"));
/*
* Consume any trailing crap left in the inbuffer from
- * previous recieved blocks. Since very few files are an exact multiple
+ * previous received blocks. Since very few files are an exact multiple
* of the transfer block size, there will almost always be some gunk here.
* If we don't eat it now, RedBoot will think the user typed it.
*/
CONFIG_SYS_INIT_RAM_ADDR
-- defines the base address of the MCF5272 internal SRAM
CONFIG_SYS_ENET_BD_BASE
- -- defines the base addres of the FEC buffer descriptors
+ -- defines the base address of the FEC buffer descriptors
CONFIG_SYS_SCR -- defines the contents of the System Configuration Register
CONFIG_SYS_SPR -- defines the contents of the System Protection Register
CONFIG_SYS_INT_FLASH_BASE
-- defines the base address of the MCF5282 internal Flash memory
CONFIG_SYS_ENET_BD_BASE
- -- defines the base addres of the FEC buffer descriptors
+ -- defines the base address of the FEC buffer descriptors
CONFIG_SYS_MFD
-- defines the PLL Multiplication Factor Devider
#config to build the kernel
qemu_mips_defconfig
-#patch to fix mips interupt init on 2.6.24.y kernel
+#patch to fix mips interrupt init on 2.6.24.y kernel
qemu_mips_kernel.patch
initrd.gz
vmlinux
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
#endif
-static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
-static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
-/* static int ACEX1K_ps_info( Altera_desc *desc ); */
+static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
+static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
+/* static int ACEX1K_ps_info(Altera_desc *desc); */
/* ------------------------------------------------------------------------- */
/* ACEX1K Generic Implementation */
-int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
+int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
return ret_val;
}
-int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize)
+int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
/* ACEX1K Passive Serial Generic Implementation */
-static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
+static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
return ret_val;
}
-static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
+static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
static int altera_validate (Altera_desc * desc, const char *fn);
/* ------------------------------------------------------------------------- */
-int altera_load( Altera_desc *desc, void *buf, size_t bsize )
+int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
return ret_val;
}
-int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
+int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
#endif
-static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize );
-static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
+static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
+static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
/* static int CYC2_ps_info( Altera_desc *desc ); */
/* ------------------------------------------------------------------------- */
/* CYCLON2 Generic Implementation */
-int CYC2_load (Altera_desc * desc, void *buf, size_t bsize)
+int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
return ret_val;
}
-int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize)
+int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
/* CYCLON2 Passive Serial Generic Implementation */
-static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize)
+static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
return ret_val;
}
-static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
+static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
/* Local static functions */
static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum );
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf,
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn );
static int fpga_dev_info( int devnum );
/* fpga_validate
* generic parameter checking code
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf,
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn )
{
fpga_desc * desc = fpga_get_desc( devnum );
/*
* Generic multiplexing code
*/
-int fpga_load( int devnum, void *buf, size_t bsize )
+int fpga_load(int devnum, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume failure */
fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
/* fpga_dump
* generic multiplexing code
*/
-int fpga_dump( int devnum, void *buf, size_t bsize )
+int fpga_dump(int devnum, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume failure */
fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan2_sp_info( Xilinx_desc *desc ); */
+static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan2_sp_info(Xilinx_desc *desc ); */
-static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan2_ss_info( Xilinx_desc *desc ); */
+static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan2_ss_info(Xilinx_desc *desc ); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
return ret_val;
}
-int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
/* ------------------------------------------------------------------------- */
-static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan3_sp_info( Xilinx_desc *desc ); */
+static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan3_sp_info(Xilinx_desc *desc ); */
-static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan3_ss_info( Xilinx_desc *desc ); */
+static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan3_ss_info(Xilinx_desc *desc); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
return ret_val;
}
-int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
/* ------------------------------------------------------------------------- */
-static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
#endif
-static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize);
+static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize);
-static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize);
+static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize)
+int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
return ret_val;
}
-int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
* INIT_B and DONE lines. If both are high, configuration has
* succeeded. Congratulations!
*/
-static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
/*
* Read the FPGA configuration data
*/
-static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
return ret_val;
}
-static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
}
-static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
/* ------------------------------------------------------------------------- */
-int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
+int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
return ret_val;
}
-int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
rc = 0;
}
- /* handle MAL RX EOB interupt from a receive */
+ /* handle MAL RX EOB interrupt from a receive */
/* check for EOB on valid channels */
if (uic_mal & UIC_MAL_RXEOB) {
mal_eob = mfdcr(MAL0_RXEOBISR);
GRETH_REGORIN(®s->control, GRETH_RXEN);
}
done:
- /* return positive length of packet or 0 if non recieved */
+ /* return positive length of packet or 0 if non received */
return len;
}
* ready to send and receive packets.
*
* Side effects:
- * leaves the natsemi initialized, and ready to recieve packets.
+ * leaves the natsemi initialized, and ready to receive packets.
*
* Returns: struct eth_device *: pointer to NIC data structure
*/
* Description: Retrieves the MAC address of the card, and sets up some
* globals required by other routines, and initializes the NIC, making it
* ready to send and receive packets.
- * Side effects: initializes ns8382xs, ready to recieve packets.
+ * Side effects: initializes ns8382xs, ready to receive packets.
* Returns: int: number of cards found
*/
hose->current_busno = hose->first_busno;
out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
- out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
+ out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
* - Master abort (pci)
* - Master PERR (pci)
* - ICCA (PCIe)
volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */
volatile ulong ctr; /* MBAR+0x810: current time register */
volatile ulong cdr; /* MBAR+0x814: current data register */
- volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interupt register */
+ volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interrupt register */
volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */
volatile ulong trdr; /* MBAR+0x820: test register/divides register */
} RTC5200;
* At the moment only the 8x16 font is tested and the font fore- and
* background color is limited to black/white/gray colors. The Linux
* logo can be placed in the upper left corner and additional board
- * information strings (that normaly goes to serial port) can be drawed.
+ * information strings (that normally goes to serial port) can be drawn.
*
* The console driver can use the standard PC keyboard interface (i8042)
* for character input. Character output goes to a memory mapped video
* framebuffer with little or big-endian organisation.
* With environment setting 'console=serial' the console i/o can be
* forced to serial port.
-
- The driver uses graphic specific defines/parameters/functions:
-
- (for SMI LynxE graphic chip)
-
- CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810
- VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian
- VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill
- VIDEO_HW_BITBLT - graphic driver supports hardware bit blt
-
- Console Parameters are set by graphic drivers global struct:
-
- VIDEO_VISIBLE_COLS - x resolution
- VIDEO_VISIBLE_ROWS - y resolution
- VIDEO_PIXEL_SIZE - storage size in byte per pixel
- VIDEO_DATA_FORMAT - graphical data format GDF
- VIDEO_FB_ADRS - start of video memory
-
- CONFIG_I8042_KBD - AT Keyboard driver for i8042
- VIDEO_KBD_INIT_FCT - init function for keyboard
- VIDEO_TSTC_FCT - keyboard_tstc function
- VIDEO_GETC_FCT - keyboard_getc function
-
- CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with delay
- loop in VIDEO_TSTC_FCT (i8042)
- CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate
- CONFIG_CONSOLE_TIME - display time/date in upper right corner,
- needs CONFIG_CMD_DATE and CONFIG_CONSOLE_CURSOR
- CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner
- CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo
- CONFIG_CONSOLE_EXTRA_INFO - display additional board information strings
- that normaly goes to serial port. This define
- requires a board specific function:
- video_drawstring (VIDEO_INFO_X,
- VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT,
- info);
- that fills a info buffer at i=row.
- s.a: board/eltec/bab7xx.
-CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be initialised
- as an output only device. The Keyboard driver
- will not be set-up. This may be used, if you
- have none or more than one Keyboard devices
- (USB Keyboard, AT Keyboard).
-
-CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last character. No
- blinking is provided. Uses the macros CURSOR_SET
- and CURSOR_OFF.
-CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the
- graphic chip. Uses the macro CURSOR_SET.
- ATTENTION: If booting an OS, the display driver
- must disable the hardware register of the graphic
- chip. Otherwise a blinking field is displayed
-*/
+ *
+ * The driver uses graphic specific defines/parameters/functions:
+ *
+ * (for SMI LynxE graphic chip)
+ *
+ * CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810
+ * VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian
+ * VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill
+ * VIDEO_HW_BITBLT - graphic driver supports hardware bit blt
+ *
+ * Console Parameters are set by graphic drivers global struct:
+ *
+ * VIDEO_VISIBLE_COLS - x resolution
+ * VIDEO_VISIBLE_ROWS - y resolution
+ * VIDEO_PIXEL_SIZE - storage size in byte per pixel
+ * VIDEO_DATA_FORMAT - graphical data format GDF
+ * VIDEO_FB_ADRS - start of video memory
+ *
+ * CONFIG_I8042_KBD - AT Keyboard driver for i8042
+ * VIDEO_KBD_INIT_FCT - init function for keyboard
+ * VIDEO_TSTC_FCT - keyboard_tstc function
+ * VIDEO_GETC_FCT - keyboard_getc function
+ *
+ * CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with
+ * delay loop in VIDEO_TSTC_FCT (i8042)
+ *
+ * CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate
+ * CONFIG_CONSOLE_TIME - display time/date in upper right
+ * corner, needs CONFIG_CMD_DATE and
+ * CONFIG_CONSOLE_CURSOR
+ * CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner
+ * CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo
+ * CONFIG_CONSOLE_EXTRA_INFO - display additional board information
+ * strings that normaly goes to serial
+ * port. This define requires a board
+ * specific function:
+ * video_drawstring (VIDEO_INFO_X,
+ * VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT,
+ * info);
+ * that fills a info buffer at i=row.
+ * s.a: board/eltec/bab7xx.
+ * CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be
+ * initialized as an output only device.
+ * The Keyboard driver will not be
+ * set-up. This may be used, if you have
+ * no or more than one Keyboard devices
+ * (USB Keyboard, AT Keyboard).
+ *
+ * CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last
+ * character. No blinking is provided.
+ * Uses the macros CURSOR_SET and
+ * CURSOR_OFF.
+ *
+ * CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability
+ * of the graphic chip. Uses the macro
+ * CURSOR_SET. ATTENTION: If booting an
+ * OS, the display driver must disable
+ * the hardware register of the graphic
+ * chip. Otherwise a blinking field is
+ * displayed.
+ */
#include <common.h>
-
+#include <version.h>
#include <malloc.h>
-/*****************************************************************************/
-/* Console device defines with SMI graphic */
-/* Any other graphic must change this section */
-/*****************************************************************************/
+/*
+ * Console device defines with SMI graphic
+ * Any other graphic must change this section
+ */
#ifdef CONFIG_VIDEO_SMI_LYNXEM
#define VIDEO_HW_BITBLT
#endif
-/*****************************************************************************/
-/* Defines for the CT69000 driver */
-/*****************************************************************************/
+/*
+ * Defines for the CT69000 driver
+ */
#ifdef CONFIG_VIDEO_CT69000
#define VIDEO_FB_LITTLE_ENDIAN
#define VIDEO_HW_BITBLT
#endif
-/*****************************************************************************/
-/* Defines for the SED13806 driver */
-/*****************************************************************************/
+/*
+ * Defines for the SED13806 driver
+ */
#ifdef CONFIG_VIDEO_SED13806
#ifndef CONFIG_TOTAL5200
#define VIDEO_HW_BITBLT
#endif
-/*****************************************************************************/
-/* Defines for the SED13806 driver */
-/*****************************************************************************/
+/*
+ * Defines for the SED13806 driver
+ */
#ifdef CONFIG_VIDEO_SM501
#ifdef CONFIG_HH405
#endif
#endif
-/*****************************************************************************/
-/* Defines for the MB862xx driver */
-/*****************************************************************************/
+/*
+ * Defines for the MB862xx driver
+ */
#ifdef CONFIG_VIDEO_MB862xx
#ifdef CONFIG_VIDEO_CORALP
#endif
#endif
-/*****************************************************************************/
-/* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */
-/*****************************************************************************/
+/*
+ * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc.
+ */
#include <video_fb.h>
-/*****************************************************************************/
-/* some Macros */
-/*****************************************************************************/
+/*
+ * some Macros
+ */
#define VIDEO_VISIBLE_COLS (pGD->winSizeX)
#define VIDEO_VISIBLE_ROWS (pGD->winSizeY)
#define VIDEO_PIXEL_SIZE (pGD->gdfBytesPP)
#define VIDEO_DATA_FORMAT (pGD->gdfIndex)
#define VIDEO_FB_ADRS (pGD->frameAdrs)
-/*****************************************************************************/
-/* Console device defines with i8042 keyboard controller */
-/* Any other keyboard controller must change this section */
-/*****************************************************************************/
+/*
+ * Console device defines with i8042 keyboard controller
+ * Any other keyboard controller must change this section
+ */
#ifdef CONFIG_I8042_KBD
#include <i8042.h>
#define VIDEO_GETC_FCT i8042_getc
#endif
-/*****************************************************************************/
-/* Console device */
-/*****************************************************************************/
+/*
+ * Console device
+ */
#include <version.h>
#include <linux/types.h>
#endif
-/*****************************************************************************/
-/* Cursor definition: */
-/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c) */
-/* to let the cursor blink. Uses the macros */
-/* CURSOR_OFF and CURSOR_ON. */
-/* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No */
-/* blinking is provided. Uses the macros CURSOR_SET */
-/* and CURSOR_OFF. */
-/* CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the */
-/* graphic chip. Uses the macro CURSOR_SET. */
-/* ATTENTION: If booting an OS, the display driver */
-/* must disable the hardware register of the graphic */
-/* chip. Otherwise a blinking field is displayed */
-/*****************************************************************************/
+/*
+ * Cursor definition:
+ * CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c)
+ * to let the cursor blink. Uses the macros
+ * CURSOR_OFF and CURSOR_ON.
+ * CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No
+ * blinking is provided. Uses the macros CURSOR_SET
+ * and CURSOR_OFF.
+ * CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the
+ * graphic chip. Uses the macro CURSOR_SET.
+ * ATTENTION: If booting an OS, the display driver
+ * must disable the hardware register of the graphic
+ * chip. Otherwise a blinking field is displayed
+ */
#if !defined(CONFIG_CONSOLE_CURSOR) && \
!defined(CONFIG_VIDEO_SW_CURSOR) && \
!defined(CONFIG_VIDEO_HW_CURSOR)
#ifdef CONFIG_CONSOLE_CURSOR
#ifdef CURSOR_ON
-#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined
+#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
+ or CONFIG_VIDEO_HW_CURSOR can be defined
#endif
-void console_cursor (int state);
+void console_cursor(int state);
+
#define CURSOR_ON console_cursor(1)
#define CURSOR_OFF console_cursor(0)
#define CURSOR_SET
#ifdef CONFIG_VIDEO_SW_CURSOR
#ifdef CURSOR_ON
-#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined
+#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
+ or CONFIG_VIDEO_HW_CURSOR can be defined
#endif
#define CURSOR_ON
#define CURSOR_OFF video_putchar(console_col * VIDEO_FONT_WIDTH,\
#ifdef CONFIG_VIDEO_HW_CURSOR
#ifdef CURSOR_ON
-#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined
+#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
+ or CONFIG_VIDEO_HW_CURSOR can be defined
#endif
#define CURSOR_ON
#define CURSOR_OFF
#define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \
(console_row * VIDEO_FONT_HEIGHT) + video_logo_height)
-#endif /* CONFIG_VIDEO_HW_CURSOR */
+#endif /* CONFIG_VIDEO_HW_CURSOR */
#ifdef CONFIG_VIDEO_LOGO
#ifdef CONFIG_VIDEO_BMP_LOGO
#define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET
#define VIDEO_LOGO_COLORS BMP_LOGO_COLORS
-#else /* CONFIG_VIDEO_BMP_LOGO */
+#else /* CONFIG_VIDEO_BMP_LOGO */
#define LINUX_LOGO_WIDTH 80
#define LINUX_LOGO_HEIGHT 80
#define LINUX_LOGO_COLORS 214
#define VIDEO_LOGO_HEIGHT LINUX_LOGO_HEIGHT
#define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET
#define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS
-#endif /* CONFIG_VIDEO_BMP_LOGO */
+#endif /* CONFIG_VIDEO_BMP_LOGO */
#define VIDEO_INFO_X (VIDEO_LOGO_WIDTH)
#define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2)
-#else /* CONFIG_VIDEO_LOGO */
+#else /* CONFIG_VIDEO_LOGO */
#define VIDEO_LOGO_WIDTH 0
#define VIDEO_LOGO_HEIGHT 0
-#endif /* CONFIG_VIDEO_LOGO */
+#endif /* CONFIG_VIDEO_LOGO */
#define VIDEO_COLS VIDEO_VISIBLE_COLS
#define VIDEO_ROWS VIDEO_VISIBLE_ROWS
/* Macros */
#ifdef VIDEO_FB_LITTLE_ENDIAN
-#define SWAP16(x) ((((x) & 0x00ff) << 8) | ( (x) >> 8))
-#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
- (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
-#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | (((x) & 0x0000ff00) >> 8)|\
- (((x) & 0x00ff0000) << 8) | (((x) & 0xff000000) >> 8) )
+#define SWAP16(x) ((((x) & 0x00ff) << 8) | \
+ ((x) >> 8) \
+ )
+#define SWAP32(x) ((((x) & 0x000000ff) << 24) | \
+ (((x) & 0x0000ff00) << 8) | \
+ (((x) & 0x00ff0000) >> 8) | \
+ (((x) & 0xff000000) >> 24) \
+ )
+#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | \
+ (((x) & 0x0000ff00) >> 8) | \
+ (((x) & 0x00ff0000) << 8) | \
+ (((x) & 0xff000000) >> 8) \
+ )
#else
-#define SWAP16(x) (x)
-#define SWAP32(x) (x)
+#define SWAP16(x) (x)
+#define SWAP32(x) (x)
#if defined(VIDEO_FB_16BPP_WORD_SWAP)
-#define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) )
+#define SHORTSWAP32(x) (((x) >> 16) | ((x) << 16))
#else
-#define SHORTSWAP32(x) (x)
-#endif
+#define SHORTSWAP32(x) (x)
#endif
-
-#if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE)
-#define PRINTD(x) printf(x)
-#else
-#define PRINTD(x)
#endif
-
#ifdef CONFIG_CONSOLE_EXTRA_INFO
-extern void video_get_info_str ( /* setup a board string: type, speed, etc. */
- int line_number, /* location to place info string beside logo */
- char *info /* buffer for info string */
- );
-
+/*
+ * setup a board string: type, speed, etc.
+ *
+ * line_number: location to place info string beside logo
+ * info: buffer for info string
+ */
+extern void video_get_info_str(int line_number, char *info);
#endif
/* Locals */
static GraphicDevice *pGD; /* Pointer to Graphic array */
-static void *video_fb_address; /* frame buffer address */
+static void *video_fb_address; /* frame buffer address */
static void *video_console_address; /* console buffer start address */
static int video_logo_height = VIDEO_LOGO_HEIGHT;
-static int console_col = 0; /* cursor col */
-static int console_row = 0; /* cursor row */
+static int console_col; /* cursor col */
+static int console_row; /* cursor row */
-static u32 eorx, fgx, bgx; /* color pats */
+static u32 eorx, fgx, bgx; /* color pats */
static const int video_font_draw_table8[] = {
- 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
- 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
- 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
- 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff };
+ 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
+ 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
+ 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
+ 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
+};
static const int video_font_draw_table15[] = {
- 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff };
+ 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff
+};
static const int video_font_draw_table16[] = {
- 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff };
+ 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff
+};
static const int video_font_draw_table24[16][3] = {
- { 0x00000000, 0x00000000, 0x00000000 },
- { 0x00000000, 0x00000000, 0x00ffffff },
- { 0x00000000, 0x0000ffff, 0xff000000 },
- { 0x00000000, 0x0000ffff, 0xffffffff },
- { 0x000000ff, 0xffff0000, 0x00000000 },
- { 0x000000ff, 0xffff0000, 0x00ffffff },
- { 0x000000ff, 0xffffffff, 0xff000000 },
- { 0x000000ff, 0xffffffff, 0xffffffff },
- { 0xffffff00, 0x00000000, 0x00000000 },
- { 0xffffff00, 0x00000000, 0x00ffffff },
- { 0xffffff00, 0x0000ffff, 0xff000000 },
- { 0xffffff00, 0x0000ffff, 0xffffffff },
- { 0xffffffff, 0xffff0000, 0x00000000 },
- { 0xffffffff, 0xffff0000, 0x00ffffff },
- { 0xffffffff, 0xffffffff, 0xff000000 },
- { 0xffffffff, 0xffffffff, 0xffffffff } };
+ {0x00000000, 0x00000000, 0x00000000},
+ {0x00000000, 0x00000000, 0x00ffffff},
+ {0x00000000, 0x0000ffff, 0xff000000},
+ {0x00000000, 0x0000ffff, 0xffffffff},
+ {0x000000ff, 0xffff0000, 0x00000000},
+ {0x000000ff, 0xffff0000, 0x00ffffff},
+ {0x000000ff, 0xffffffff, 0xff000000},
+ {0x000000ff, 0xffffffff, 0xffffffff},
+ {0xffffff00, 0x00000000, 0x00000000},
+ {0xffffff00, 0x00000000, 0x00ffffff},
+ {0xffffff00, 0x0000ffff, 0xff000000},
+ {0xffffff00, 0x0000ffff, 0xffffffff},
+ {0xffffffff, 0xffff0000, 0x00000000},
+ {0xffffffff, 0xffff0000, 0x00ffffff},
+ {0xffffffff, 0xffffffff, 0xff000000},
+ {0xffffffff, 0xffffffff, 0xffffffff}
+};
static const int video_font_draw_table32[16][4] = {
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
- { 0x00000000, 0x00000000, 0x00000000, 0x00ffffff },
- { 0x00000000, 0x00000000, 0x00ffffff, 0x00000000 },
- { 0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff },
- { 0x00000000, 0x00ffffff, 0x00000000, 0x00000000 },
- { 0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff },
- { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000 },
- { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff },
- { 0x00ffffff, 0x00000000, 0x00000000, 0x00000000 },
- { 0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff },
- { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000 },
- { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff },
- { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000 },
- { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff },
- { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000 },
- { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } };
-
-
-/******************************************************************************/
-
-static void video_drawchars (int xx, int yy, unsigned char *s, int count)
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x00000000, 0x00000000, 0x00000000, 0x00ffffff},
+ {0x00000000, 0x00000000, 0x00ffffff, 0x00000000},
+ {0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff},
+ {0x00000000, 0x00ffffff, 0x00000000, 0x00000000},
+ {0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff},
+ {0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000},
+ {0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff},
+ {0x00ffffff, 0x00000000, 0x00000000, 0x00000000},
+ {0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff},
+ {0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000},
+ {0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff},
+ {0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000},
+ {0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff},
+ {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000},
+ {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff}
+};
+
+
+static void video_drawchars(int xx, int yy, unsigned char *s, int count)
{
u8 *cdat, *dest, *dest0;
int rows, offset, c;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = (video_font_draw_table8[bits >> 4] & eorx) ^ bgx;
- ((u32 *) dest)[1] = (video_font_draw_table8[bits & 15] & eorx) ^ bgx;
+ ((u32 *) dest)[0] =
+ (video_font_draw_table8[bits >> 4] &
+ eorx) ^ bgx;
+ ((u32 *) dest)[1] =
+ (video_font_draw_table8[bits & 15] &
+ eorx) ^ bgx;
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 6] & eorx) ^ bgx);
- ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 4 & 3] & eorx) ^ bgx);
- ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 2 & 3] & eorx) ^ bgx);
- ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table15 [bits & 3] & eorx) ^ bgx);
+ ((u32 *) dest)[0] =
+ SHORTSWAP32((video_font_draw_table15
+ [bits >> 6] & eorx) ^
+ bgx);
+ ((u32 *) dest)[1] =
+ SHORTSWAP32((video_font_draw_table15
+ [bits >> 4 & 3] & eorx) ^
+ bgx);
+ ((u32 *) dest)[2] =
+ SHORTSWAP32((video_font_draw_table15
+ [bits >> 2 & 3] & eorx) ^
+ bgx);
+ ((u32 *) dest)[3] =
+ SHORTSWAP32((video_font_draw_table15
+ [bits & 3] & eorx) ^
+ bgx);
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 6] & eorx) ^ bgx);
- ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 4 & 3] & eorx) ^ bgx);
- ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 2 & 3] & eorx) ^ bgx);
- ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table16 [bits & 3] & eorx) ^ bgx);
+ ((u32 *) dest)[0] =
+ SHORTSWAP32((video_font_draw_table16
+ [bits >> 6] & eorx) ^
+ bgx);
+ ((u32 *) dest)[1] =
+ SHORTSWAP32((video_font_draw_table16
+ [bits >> 4 & 3] & eorx) ^
+ bgx);
+ ((u32 *) dest)[2] =
+ SHORTSWAP32((video_font_draw_table16
+ [bits >> 2 & 3] & eorx) ^
+ bgx);
+ ((u32 *) dest)[3] =
+ SHORTSWAP32((video_font_draw_table16
+ [bits & 3] & eorx) ^
+ bgx);
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = SWAP32 ((video_font_draw_table32 [bits >> 4][0] & eorx) ^ bgx);
- ((u32 *) dest)[1] = SWAP32 ((video_font_draw_table32 [bits >> 4][1] & eorx) ^ bgx);
- ((u32 *) dest)[2] = SWAP32 ((video_font_draw_table32 [bits >> 4][2] & eorx) ^ bgx);
- ((u32 *) dest)[3] = SWAP32 ((video_font_draw_table32 [bits >> 4][3] & eorx) ^ bgx);
- ((u32 *) dest)[4] = SWAP32 ((video_font_draw_table32 [bits & 15][0] & eorx) ^ bgx);
- ((u32 *) dest)[5] = SWAP32 ((video_font_draw_table32 [bits & 15][1] & eorx) ^ bgx);
- ((u32 *) dest)[6] = SWAP32 ((video_font_draw_table32 [bits & 15][2] & eorx) ^ bgx);
- ((u32 *) dest)[7] = SWAP32 ((video_font_draw_table32 [bits & 15][3] & eorx) ^ bgx);
+ ((u32 *) dest)[0] =
+ SWAP32((video_font_draw_table32
+ [bits >> 4][0] & eorx) ^ bgx);
+ ((u32 *) dest)[1] =
+ SWAP32((video_font_draw_table32
+ [bits >> 4][1] & eorx) ^ bgx);
+ ((u32 *) dest)[2] =
+ SWAP32((video_font_draw_table32
+ [bits >> 4][2] & eorx) ^ bgx);
+ ((u32 *) dest)[3] =
+ SWAP32((video_font_draw_table32
+ [bits >> 4][3] & eorx) ^ bgx);
+ ((u32 *) dest)[4] =
+ SWAP32((video_font_draw_table32
+ [bits & 15][0] & eorx) ^ bgx);
+ ((u32 *) dest)[5] =
+ SWAP32((video_font_draw_table32
+ [bits & 15][1] & eorx) ^ bgx);
+ ((u32 *) dest)[6] =
+ SWAP32((video_font_draw_table32
+ [bits & 15][2] & eorx) ^ bgx);
+ ((u32 *) dest)[7] =
+ SWAP32((video_font_draw_table32
+ [bits & 15][3] & eorx) ^ bgx);
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
- rows--;
- dest += VIDEO_LINE_LEN) {
+ rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
- ((u32 *) dest)[0] = (video_font_draw_table24[bits >> 4][0] & eorx) ^ bgx;
- ((u32 *) dest)[1] = (video_font_draw_table24[bits >> 4][1] & eorx) ^ bgx;
- ((u32 *) dest)[2] = (video_font_draw_table24[bits >> 4][2] & eorx) ^ bgx;
- ((u32 *) dest)[3] = (video_font_draw_table24[bits & 15][0] & eorx) ^ bgx;
- ((u32 *) dest)[4] = (video_font_draw_table24[bits & 15][1] & eorx) ^ bgx;
- ((u32 *) dest)[5] = (video_font_draw_table24[bits & 15][2] & eorx) ^ bgx;
+ ((u32 *) dest)[0] =
+ (video_font_draw_table24[bits >> 4][0]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[1] =
+ (video_font_draw_table24[bits >> 4][1]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[2] =
+ (video_font_draw_table24[bits >> 4][2]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[3] =
+ (video_font_draw_table24[bits & 15][0]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[4] =
+ (video_font_draw_table24[bits & 15][1]
+ & eorx) ^ bgx;
+ ((u32 *) dest)[5] =
+ (video_font_draw_table24[bits & 15][2]
+ & eorx) ^ bgx;
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
}
}
-/*****************************************************************************/
-
-static inline void video_drawstring (int xx, int yy, unsigned char *s)
+static inline void video_drawstring(int xx, int yy, unsigned char *s)
{
- video_drawchars (xx, yy, s, strlen ((char *)s));
+ video_drawchars(xx, yy, s, strlen((char *) s));
}
-/*****************************************************************************/
-
-static void video_putchar (int xx, int yy, unsigned char c)
+static void video_putchar(int xx, int yy, unsigned char c)
{
- video_drawchars (xx, yy + video_logo_height, &c, 1);
+ video_drawchars(xx, yy + video_logo_height, &c, 1);
}
-/*****************************************************************************/
#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR)
-static void video_set_cursor (void)
+static void video_set_cursor(void)
{
/* swap drawing colors */
eorx = fgx;
bgx = eorx;
eorx = fgx ^ bgx;
/* draw cursor */
- video_putchar (console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT,
- ' ');
+ video_putchar(console_col * VIDEO_FONT_WIDTH,
+ console_row * VIDEO_FONT_HEIGHT, ' ');
/* restore drawing colors */
eorx = fgx;
fgx = bgx;
eorx = fgx ^ bgx;
}
#endif
-/*****************************************************************************/
+
#ifdef CONFIG_CONSOLE_CURSOR
-void console_cursor (int state)
+void console_cursor(int state)
{
static int last_state = 0;
/* time update only if cursor is on (faster scroll) */
if (state) {
- rtc_get (&tm);
-
- sprintf (info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min,
- tm.tm_sec);
- video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y, (uchar *)info);
-
- sprintf (info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon,
- tm.tm_year);
- video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, (uchar *)info);
+ rtc_get(&tm);
+
+ sprintf(info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min,
+ tm.tm_sec);
+ video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
+ VIDEO_INFO_Y, (uchar *) info);
+
+ sprintf(info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon,
+ tm.tm_year);
+ video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
+ VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT,
+ (uchar *) info);
}
#endif
if (state && (last_state != state)) {
- video_set_cursor ();
+ video_set_cursor();
}
if (!state && (last_state != state)) {
/* clear cursor */
- video_putchar (console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT,
- ' ');
+ video_putchar(console_col * VIDEO_FONT_WIDTH,
+ console_row * VIDEO_FONT_HEIGHT, ' ');
}
last_state = state;
}
#endif
-/*****************************************************************************/
-
#ifndef VIDEO_HW_RECTFILL
-static void memsetl (int *p, int c, int v)
+static void memsetl(int *p, int c, int v)
{
while (c--)
*(p++) = v;
}
#endif
-/*****************************************************************************/
-
#ifndef VIDEO_HW_BITBLT
-static void memcpyl (int *d, int *s, int c)
+static void memcpyl(int *d, int *s, int c)
{
while (c--)
*(d++) = *(s++);
}
#endif
-/*****************************************************************************/
-
-static void console_scrollup (void)
+static void console_scrollup(void)
{
/* copy up rows ignoring the first one */
#ifdef VIDEO_HW_BITBLT
- video_hw_bitblt (VIDEO_PIXEL_SIZE, /* bytes per pixel */
- 0, /* source pos x */
- video_logo_height + VIDEO_FONT_HEIGHT, /* source pos y */
- 0, /* dest pos x */
- video_logo_height, /* dest pos y */
- VIDEO_VISIBLE_COLS, /* frame width */
- VIDEO_VISIBLE_ROWS - video_logo_height - VIDEO_FONT_HEIGHT /* frame height */
+ video_hw_bitblt(VIDEO_PIXEL_SIZE, /* bytes per pixel */
+ 0, /* source pos x */
+ video_logo_height +
+ VIDEO_FONT_HEIGHT, /* source pos y */
+ 0, /* dest pos x */
+ video_logo_height, /* dest pos y */
+ VIDEO_VISIBLE_COLS, /* frame width */
+ VIDEO_VISIBLE_ROWS
+ - video_logo_height
+ - VIDEO_FONT_HEIGHT /* frame height */
);
#else
- memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND,
- CONSOLE_SCROLL_SIZE >> 2);
+ memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND,
+ CONSOLE_SCROLL_SIZE >> 2);
#endif
/* clear the last one */
#ifdef VIDEO_HW_RECTFILL
- video_hw_rectfill (VIDEO_PIXEL_SIZE, /* bytes per pixel */
- 0, /* dest pos x */
- VIDEO_VISIBLE_ROWS - VIDEO_FONT_HEIGHT, /* dest pos y */
- VIDEO_VISIBLE_COLS, /* frame width */
- VIDEO_FONT_HEIGHT, /* frame height */
- CONSOLE_BG_COL /* fill color */
+ video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */
+ 0, /* dest pos x */
+ VIDEO_VISIBLE_ROWS
+ - VIDEO_FONT_HEIGHT, /* dest pos y */
+ VIDEO_VISIBLE_COLS, /* frame width */
+ VIDEO_FONT_HEIGHT, /* frame height */
+ CONSOLE_BG_COL /* fill color */
);
#else
- memsetl (CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL);
+ memsetl(CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL);
#endif
}
-/*****************************************************************************/
-
-static void console_back (void)
+static void console_back(void)
{
CURSOR_OFF;
console_col--;
if (console_row < 0)
console_row = 0;
}
- video_putchar (console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT,
- ' ');
+ video_putchar(console_col * VIDEO_FONT_WIDTH,
+ console_row * VIDEO_FONT_HEIGHT, ' ');
}
-/*****************************************************************************/
-
-static void console_newline (void)
+static void console_newline(void)
{
/* Check if last character in the line was just drawn. If so, cursor was
overwriten and need not to be cleared. Cursor clearing without this
/* Check if we need to scroll the terminal */
if (console_row >= CONSOLE_ROWS) {
/* Scroll everything up */
- console_scrollup ();
+ console_scrollup();
/* Decrement row number */
console_row--;
}
}
-static void console_cr (void)
+static void console_cr(void)
{
CURSOR_OFF;
console_col = 0;
}
-/*****************************************************************************/
-
-void video_putc (const char c)
+void video_putc(const char c)
{
static int nl = 1;
switch (c) {
case 13: /* back to first column */
- console_cr ();
+ console_cr();
break;
case '\n': /* next line */
if (console_col || (!console_col && nl))
- console_newline ();
+ console_newline();
nl = 1;
break;
console_col &= ~0x0007;
if (console_col >= CONSOLE_COLS)
- console_newline ();
+ console_newline();
break;
case 8: /* backspace */
- console_back ();
+ console_back();
break;
default: /* draw the char */
- video_putchar (console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT,
- c);
+ video_putchar(console_col * VIDEO_FONT_WIDTH,
+ console_row * VIDEO_FONT_HEIGHT, c);
console_col++;
/* check for newline */
if (console_col >= CONSOLE_COLS) {
- console_newline ();
+ console_newline();
nl = 0;
}
}
CURSOR_SET;
}
-
-/*****************************************************************************/
-
-void video_puts (const char *s)
+void video_puts(const char *s)
{
- int count = strlen (s);
+ int count = strlen(s);
while (count--)
- video_putc (*s++);
+ video_putc(*s++);
}
-/*****************************************************************************/
-
/*
* Do not enforce drivers (or board code) to provide empty
* video_set_lut() if they do not support 8 bpp format.
* Implement weak default function instead.
*/
-void __video_set_lut (unsigned int index, unsigned char r,
- unsigned char g, unsigned char b)
+void __video_set_lut(unsigned int index, unsigned char r,
+ unsigned char g, unsigned char b)
{
}
-void video_set_lut (unsigned int, unsigned char, unsigned char, unsigned char)
- __attribute__((weak, alias("__video_set_lut")));
+
+void video_set_lut(unsigned int, unsigned char, unsigned char, unsigned char)
+ __attribute__ ((weak, alias("__video_set_lut")));
#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
}
#define FILL_15BIT_555RGB(r,g,b) { \
- *(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \
+ *(unsigned short *)fb = \
+ SWAP16((unsigned short)(((r>>3)<<10) | \
+ ((g>>3)<<5) | \
+ (b>>3))); \
fb += 2; \
}
#define FILL_16BIT_565RGB(r,g,b) { \
- *(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \
+ *(unsigned short *)fb = \
+ SWAP16((unsigned short)((((r)>>3)<<11)| \
+ (((g)>>2)<<5) | \
+ ((b)>>3))); \
fb += 2; \
}
#define FILL_32BIT_X888RGB(r,g,b) { \
- *(unsigned long *)fb = SWAP32((unsigned long)(((r<<16) | (g<<8) | b))); \
+ *(unsigned long *)fb = \
+ SWAP32((unsigned long)(((r<<16) | \
+ (g<<8) | \
+ b))); \
fb += 4; \
}
#endif
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
-static void inline fill_555rgb_pswap(uchar *fb, int x,
- u8 r, u8 g, u8 b)
+static inline void fill_555rgb_pswap(uchar *fb, int x, u8 r, u8 g, u8 b)
{
- ushort *dst = (ushort *)fb;
- ushort color = (ushort)(((r >> 3) << 10) |
- ((g >> 3) << 5) |
- (b >> 3));
+ ushort *dst = (ushort *) fb;
+ ushort color = (ushort) (((r >> 3) << 10) |
+ ((g >> 3) << 5) |
+ (b >> 3));
if (x & 1)
*(--dst) = color;
else
/* Pre-calculated color table entry */
struct palette {
union {
- unsigned short w; /* word */
- unsigned int dw; /* double word */
- } ce; /* color entry */
+ unsigned short w; /* word */
+ unsigned int dw; /* double word */
+ } ce; /* color entry */
};
/*
* Helper to draw encoded/unencoded run.
*/
-static void draw_bitmap (uchar **fb, uchar *bm, struct palette *p,
- int cnt, int enc)
+static void draw_bitmap(uchar **fb, uchar *bm, struct palette *p,
+ int cnt, int enc)
{
- ulong addr = (ulong)*fb;
+ ulong addr = (ulong) *fb;
int *off;
int enc_off = 1;
int i;
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
for (i = 0; i < cnt; i++)
- *(unsigned char *)addr++ = bm[*off];
+ *(unsigned char *) addr++ = bm[*off];
break;
case GDF_15BIT_555RGB:
case GDF_16BIT_565RGB:
/* differences handled while pre-calculating palette */
for (i = 0; i < cnt; i++) {
- *(unsigned short *)addr = p[bm[*off]].ce.w;
+ *(unsigned short *) addr = p[bm[*off]].ce.w;
addr += 2;
}
break;
case GDF_32BIT_X888RGB:
for (i = 0; i < cnt; i++) {
- *(unsigned long *)addr = p[bm[*off]].ce.dw;
+ *(unsigned long *) addr = p[bm[*off]].ce.dw;
addr += 4;
}
break;
}
- *fb = (uchar *)addr; /* return modified address */
+ *fb = (uchar *) addr; /* return modified address */
}
-static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff,
- int width, int height)
+static int display_rle8_bitmap(bmp_image_t *img, int xoff, int yoff,
+ int width, int height)
{
unsigned char *bm;
unsigned char *fbp;
y = __le32_to_cpu(img->header.height) - 1;
ncolors = __le32_to_cpu(img->header.colors_used);
bpp = VIDEO_PIXEL_SIZE;
- fbp = (unsigned char *)((unsigned int)video_fb_address +
- (((y + yoff) * VIDEO_COLS) + xoff) * bpp);
+ fbp = (unsigned char *) ((unsigned int) video_fb_address +
+ (((y + yoff) * VIDEO_COLS) + xoff) * bpp);
- bm = (uchar *)img + __le32_to_cpu(img->header.data_offset);
+ bm = (uchar *) img + __le32_to_cpu(img->header.data_offset);
/* pre-calculate and setup palette */
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
for (i = 0; i < ncolors; i++) {
cte = img->color_table[i];
- video_set_lut (i, cte.red, cte.green, cte.blue);
+ video_set_lut(i, cte.red, cte.green, cte.blue);
}
break;
case GDF_15BIT_555RGB:
case GDF_32BIT_X888RGB:
for (i = 0; i < ncolors; i++) {
cte = img->color_table[i];
- p[i].ce.dw = SWAP32((cte.red << 16) | (cte.green << 8) |
+ p[i].ce.dw = SWAP32((cte.red << 16) |
+ (cte.green << 8) |
cte.blue);
}
break;
default:
printf("RLE Bitmap unsupported in video mode 0x%x\n",
- VIDEO_DATA_FORMAT);
+ VIDEO_DATA_FORMAT);
return -1;
}
x = 0;
y--;
fbp = (unsigned char *)
- ((unsigned int)video_fb_address +
+ ((unsigned int) video_fb_address +
(((y + yoff) * VIDEO_COLS) +
xoff) * bpp);
continue;
x += bm[2];
y -= bm[3];
fbp = (unsigned char *)
- ((unsigned int)video_fb_address +
+ ((unsigned int) video_fb_address +
(((y + yoff) * VIDEO_COLS) +
x + xoff) * bpp);
bm += 4;
}
if (x + runlen > width)
cnt = width - x;
- draw_bitmap (&fbp, bm, p, cnt, 0);
+ draw_bitmap(&fbp, bm, p, cnt, 0);
x += runlen;
}
next_run:
bm += runlen;
if (runlen & 1)
- bm++; /* 0 padding if length is odd */
+ bm++; /* 0 padding if length is odd */
}
break;
default:
if (pixels > limit)
goto error;
- if (y < height) { /* only draw into visible area */
+ if (y < height) { /* only draw into visible area */
if (x >= width) {
x += runlen;
bm += 2;
}
if (x + runlen > width)
cnt = width - x;
- draw_bitmap (&fbp, bm, p, cnt, 1);
+ draw_bitmap(&fbp, bm, p, cnt, 1);
x += runlen;
}
bm += 2;
/*
* Display the BMP file located at address bmp_image.
*/
-int video_display_bitmap (ulong bmp_image, int x, int y)
+int video_display_bitmap(ulong bmp_image, int x, int y)
{
ushort xcount, ycount;
uchar *fb;
unsigned colors;
unsigned long compression;
bmp_color_table_entry_t cte;
+
#ifdef CONFIG_VIDEO_BMP_GZIP
unsigned char *dst = NULL;
ulong len;
#endif
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
if (dst == NULL) {
printf("Error: malloc in gunzip failed!\n");
- return(1);
+ return 1;
}
- if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, (uchar *)bmp_image, &len) != 0) {
- printf ("Error: no valid bmp or bmp.gz image at %lx\n", bmp_image);
+ if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
+ (uchar *) bmp_image,
+ &len) != 0) {
+ printf("Error: no valid bmp or bmp.gz image at %lx\n",
+ bmp_image);
free(dst);
return 1;
}
if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
- printf("Image could be truncated (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
+ printf("Image could be truncated "
+ "(increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
}
/*
* Set addr to decompressed image
*/
- bmp = (bmp_image_t *)dst;
+ bmp = (bmp_image_t *) dst;
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
- printf ("Error: no valid bmp.gz image at %lx\n", bmp_image);
+ printf("Error: no valid bmp.gz image at %lx\n",
+ bmp_image);
free(dst);
return 1;
}
#else
- printf ("Error: no valid bmp image at %lx\n", bmp_image);
+ printf("Error: no valid bmp image at %lx\n", bmp_image);
return 1;
#endif /* CONFIG_VIDEO_BMP_GZIP */
}
- width = le32_to_cpu (bmp->header.width);
- height = le32_to_cpu (bmp->header.height);
- bpp = le16_to_cpu (bmp->header.bit_count);
- colors = le32_to_cpu (bmp->header.colors_used);
- compression = le32_to_cpu (bmp->header.compression);
+ width = le32_to_cpu(bmp->header.width);
+ height = le32_to_cpu(bmp->header.height);
+ bpp = le16_to_cpu(bmp->header.bit_count);
+ colors = le32_to_cpu(bmp->header.colors_used);
+ compression = le32_to_cpu(bmp->header.compression);
- debug ("Display-bmp: %d x %d with %d colors\n",
- width, height, colors);
+ debug("Display-bmp: %d x %d with %d colors\n",
+ width, height, colors);
if (compression != BMP_BI_RGB
#ifdef CONFIG_VIDEO_BMP_RLE8
&& compression != BMP_BI_RLE8
#endif
- ) {
- printf ("Error: compression type %ld not supported\n",
- compression);
+ ) {
+ printf("Error: compression type %ld not supported\n",
+ compression);
#ifdef CONFIG_VIDEO_BMP_GZIP
if (dst)
free(dst);
if ((y + height) > VIDEO_VISIBLE_ROWS)
height = VIDEO_VISIBLE_ROWS - y;
- bmap = (uchar *) bmp + le32_to_cpu (bmp->header.data_offset);
+ bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset);
fb = (uchar *) (video_fb_address +
((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) +
x * VIDEO_PIXEL_SIZE);
#ifdef CONFIG_VIDEO_BMP_RLE8
if (compression == BMP_BI_RLE8) {
- return display_rle8_bitmap(bmp,
- x, y, width, height);
+ return display_rle8_bitmap(bmp, x, y, width, height);
}
#endif
/* We handle only 4, 8, or 24 bpp bitmaps */
- switch (le16_to_cpu (bmp->header.bit_count)) {
+ switch (le16_to_cpu(bmp->header.bit_count)) {
case 4:
padded_line -= width / 2;
ycount = height;
switch (VIDEO_DATA_FORMAT) {
case GDF_32BIT_X888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
/*
* Don't assume that 'width' is an
* even number
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ VIDEO_PIXEL_SIZE;
}
break;
default:
/* Copy colormap */
for (xcount = 0; xcount < colors; ++xcount) {
cte = bmp->color_table[xcount];
- video_set_lut (xcount, cte.red, cte.green, cte.blue);
+ video_set_lut(xcount, cte.red, cte.green,
+ cte.blue);
}
}
ycount = height;
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
*fb++ = *bmap++;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF__8BIT_332RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
- FILL_8BIT_332RGB (cte.red, cte.green, cte.blue);
+ FILL_8BIT_332RGB(cte.red, cte.green,
+ cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_15BIT_555RGB:
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
- fill_555rgb_pswap (fb, xpos++, cte.red,
- cte.green, cte.blue);
+ fill_555rgb_pswap(fb, xpos++, cte.red,
+ cte.green,
+ cte.blue);
fb += 2;
#else
- FILL_15BIT_555RGB (cte.red, cte.green, cte.blue);
+ FILL_15BIT_555RGB(cte.red, cte.green,
+ cte.blue);
#endif
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_16BIT_565RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
- FILL_16BIT_565RGB (cte.red, cte.green, cte.blue);
+ FILL_16BIT_565RGB(cte.red, cte.green,
+ cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_32BIT_X888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
- FILL_32BIT_X888RGB (cte.red, cte.green, cte.blue);
+ FILL_32BIT_X888RGB(cte.red, cte.green,
+ cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_24BIT_888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
- FILL_24BIT_888RGB (cte.red, cte.green, cte.blue);
+ FILL_24BIT_888RGB(cte.red, cte.green,
+ cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
}
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_332RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
- FILL_8BIT_332RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_8BIT_332RGB(bmap[2], bmap[1],
+ bmap[0]);
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_15BIT_555RGB:
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
- fill_555rgb_pswap (fb, xpos++, bmap[2],
- bmap[1], bmap[0]);
+ fill_555rgb_pswap(fb, xpos++, bmap[2],
+ bmap[1], bmap[0]);
fb += 2;
#else
- FILL_15BIT_555RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_15BIT_555RGB(bmap[2], bmap[1],
+ bmap[0]);
#endif
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_16BIT_565RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
- FILL_16BIT_565RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_16BIT_565RGB(bmap[2], bmap[1],
+ bmap[0]);
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_32BIT_X888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
- FILL_32BIT_X888RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_32BIT_X888RGB(bmap[2], bmap[1],
+ bmap[0]);
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_24BIT_888RGB:
while (ycount--) {
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
xcount = width;
while (xcount--) {
- FILL_24BIT_888RGB (bmap[2], bmap[1], bmap[0]);
+ FILL_24BIT_888RGB(bmap[2], bmap[1],
+ bmap[0]);
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
+ fb -= (VIDEO_VISIBLE_COLS + width) *
+ VIDEO_PIXEL_SIZE;
}
break;
default:
- printf ("Error: 24 bits/pixel bitmap incompatible with current video mode\n");
+ printf("Error: 24 bits/pixel bitmap incompatible "
+ "with current video mode\n");
break;
}
break;
default:
- printf ("Error: %d bit/pixel bitmaps not supported by U-Boot\n",
- le16_to_cpu (bmp->header.bit_count));
+ printf("Error: %d bit/pixel bitmaps not supported by U-Boot\n",
+ le16_to_cpu(bmp->header.bit_count));
break;
}
}
#endif
-/*****************************************************************************/
#ifdef CONFIG_VIDEO_LOGO
-void logo_plot (void *screen, int width, int x, int y)
+void logo_plot(void *screen, int width, int x, int y)
{
int xcount, i;
- int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE;
+ int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE;
int ycount = video_logo_height;
unsigned char r, g, b, *logo_red, *logo_blue, *logo_green;
unsigned char *source;
- unsigned char *dest = (unsigned char *)screen +
- ((y * width * VIDEO_PIXEL_SIZE) +
- x * VIDEO_PIXEL_SIZE);
+ unsigned char *dest = (unsigned char *) screen +
+ ((y * width * VIDEO_PIXEL_SIZE) + x * VIDEO_PIXEL_SIZE);
#ifdef CONFIG_VIDEO_BMP_LOGO
source = bmp_logo_bitmap;
/* Allocate temporary space for computing colormap */
- logo_red = malloc (BMP_LOGO_COLORS);
- logo_green = malloc (BMP_LOGO_COLORS);
- logo_blue = malloc (BMP_LOGO_COLORS);
+ logo_red = malloc(BMP_LOGO_COLORS);
+ logo_green = malloc(BMP_LOGO_COLORS);
+ logo_blue = malloc(BMP_LOGO_COLORS);
/* Compute color map */
for (i = 0; i < VIDEO_LOGO_COLORS; i++) {
logo_red[i] = (bmp_logo_palette[i] & 0x0f00) >> 4;
if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) {
for (i = 0; i < VIDEO_LOGO_COLORS; i++) {
- video_set_lut (i + VIDEO_LOGO_LUT_OFFSET,
- logo_red[i], logo_green[i], logo_blue[i]);
+ video_set_lut(i + VIDEO_LOGO_LUT_OFFSET,
+ logo_red[i], logo_green[i],
+ logo_blue[i]);
}
}
*dest = *source;
break;
case GDF__8BIT_332RGB:
- *dest = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
+ *dest = ((r >> 5) << 5) |
+ ((g >> 5) << 2) |
+ (b >> 6);
break;
case GDF_15BIT_555RGB:
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
- fill_555rgb_pswap (dest, xpos++, r, g, b);
+ fill_555rgb_pswap(dest, xpos++, r, g, b);
#else
*(unsigned short *) dest =
- SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)));
+ SWAP16((unsigned short) (
+ ((r >> 3) << 10) |
+ ((g >> 3) << 5) |
+ (b >> 3)));
#endif
break;
case GDF_16BIT_565RGB:
*(unsigned short *) dest =
- SWAP16 ((unsigned short) (((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3)));
+ SWAP16((unsigned short) (
+ ((r >> 3) << 11) |
+ ((g >> 2) << 5) |
+ (b >> 3)));
break;
case GDF_32BIT_X888RGB:
*(unsigned long *) dest =
- SWAP32 ((unsigned long) ((r << 16) | (g << 8) | b));
+ SWAP32((unsigned long) (
+ (r << 16) |
+ (g << 8) |
+ b));
break;
case GDF_24BIT_888RGB:
#ifdef VIDEO_FB_LITTLE_ENDIAN
dest += skip;
}
#ifdef CONFIG_VIDEO_BMP_LOGO
- free (logo_red);
- free (logo_green);
- free (logo_blue);
+ free(logo_red);
+ free(logo_green);
+ free(logo_blue);
#endif
}
-/*****************************************************************************/
-
-static void *video_logo (void)
+static void *video_logo(void)
{
char info[128];
- extern char version_string;
int space, len, y_off = 0;
#ifdef CONFIG_SPLASH_SCREEN
char *s;
ulong addr;
- if ((s = getenv ("splashimage")) != NULL) {
+ s = getenv("splashimage");
+ if (s != NULL) {
int x = 0, y = 0;
- addr = simple_strtoul (s, NULL, 16);
+ addr = simple_strtoul(s, NULL, 16);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
- if ((s = getenv ("splashpos")) != NULL) {
+ s = getenv("splashpos");
+ if (s != NULL) {
if (s[0] == 'm')
x = BMP_ALIGN_CENTER;
else
- x = simple_strtol (s, NULL, 0);
+ x = simple_strtol(s, NULL, 0);
- if ((s = strchr (s + 1, ',')) != NULL) {
+ s = strchr(s + 1, ',');
+ if (s != NULL) {
if (s[1] == 'm')
y = BMP_ALIGN_CENTER;
else
- y = simple_strtol (s + 1, NULL, 0);
+ y = simple_strtol(s + 1, NULL, 0);
}
}
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
- if (video_display_bitmap (addr, x, y) == 0) {
+ if (video_display_bitmap(addr, x, y) == 0) {
video_logo_height = 0;
return ((void *) (video_fb_address));
}
}
#endif /* CONFIG_SPLASH_SCREEN */
- logo_plot (video_fb_address, VIDEO_COLS, 0, 0);
+ logo_plot(video_fb_address, VIDEO_COLS, 0, 0);
- sprintf (info, " %s", &version_string);
+ sprintf(info, " %s", version_string);
space = (VIDEO_LINE_LEN / 2 - VIDEO_INFO_X) / VIDEO_FONT_WIDTH;
len = strlen(info);
if (len > space) {
- video_drawchars (VIDEO_INFO_X, VIDEO_INFO_Y,
- (uchar *)info, space);
- video_drawchars (VIDEO_INFO_X + VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
- (uchar *)info + space, len - space);
+ video_drawchars(VIDEO_INFO_X, VIDEO_INFO_Y,
+ (uchar *) info, space);
+ video_drawchars(VIDEO_INFO_X + VIDEO_FONT_WIDTH,
+ VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
+ (uchar *) info + space, len - space);
y_off = 1;
} else
- video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *)info);
+ video_drawstring(VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *) info);
#ifdef CONFIG_CONSOLE_EXTRA_INFO
{
- int i, n = ((video_logo_height - VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT);
+ int i, n =
+ ((video_logo_height -
+ VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT);
for (i = 1; i < n; i++) {
- video_get_info_str (i, info);
+ video_get_info_str(i, info);
if (!*info)
continue;
len = strlen(info);
if (len > space) {
- video_drawchars (VIDEO_INFO_X,
- VIDEO_INFO_Y +
- (i + y_off) * VIDEO_FONT_HEIGHT,
- (uchar *)info, space);
+ video_drawchars(VIDEO_INFO_X,
+ VIDEO_INFO_Y +
+ (i + y_off) *
+ VIDEO_FONT_HEIGHT,
+ (uchar *) info, space);
y_off++;
- video_drawchars (VIDEO_INFO_X + VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y +
- (i + y_off) * VIDEO_FONT_HEIGHT,
- (uchar *)info + space,
- len - space);
+ video_drawchars(VIDEO_INFO_X +
+ VIDEO_FONT_WIDTH,
+ VIDEO_INFO_Y +
+ (i + y_off) *
+ VIDEO_FONT_HEIGHT,
+ (uchar *) info + space,
+ len - space);
} else {
- video_drawstring (VIDEO_INFO_X,
- VIDEO_INFO_Y +
- (i + y_off) * VIDEO_FONT_HEIGHT,
- (uchar *)info);
+ video_drawstring(VIDEO_INFO_X,
+ VIDEO_INFO_Y +
+ (i + y_off) *
+ VIDEO_FONT_HEIGHT,
+ (uchar *) info);
}
}
}
}
#endif
-
-/*****************************************************************************/
-
-static int video_init (void)
+static int video_init(void)
{
unsigned char color8;
- if ((pGD = video_hw_init ()) == NULL)
+ pGD = video_hw_init();
+ if (pGD == NULL)
return -1;
video_fb_address = (void *) VIDEO_FB_ADRS;
#ifdef CONFIG_VIDEO_HW_CURSOR
- video_init_hw_cursor (VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT);
+ video_init_hw_cursor(VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT);
#endif
/* Init drawing pats */
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
- video_set_lut (0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL);
- video_set_lut (0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, CONSOLE_BG_COL);
+ video_set_lut(0x01, CONSOLE_FG_COL, CONSOLE_FG_COL,
+ CONSOLE_FG_COL);
+ video_set_lut(0x00, CONSOLE_BG_COL, CONSOLE_BG_COL,
+ CONSOLE_BG_COL);
fgx = 0x01010101;
bgx = 0x00000000;
break;
case GDF__8BIT_332RGB:
color8 = ((CONSOLE_FG_COL & 0xe0) |
- ((CONSOLE_FG_COL >> 3) & 0x1c) | CONSOLE_FG_COL >> 6);
- fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8;
+ ((CONSOLE_FG_COL >> 3) & 0x1c) |
+ CONSOLE_FG_COL >> 6);
+ fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) |
+ color8;
color8 = ((CONSOLE_BG_COL & 0xe0) |
- ((CONSOLE_BG_COL >> 3) & 0x1c) | CONSOLE_BG_COL >> 6);
- bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8;
+ ((CONSOLE_BG_COL >> 3) & 0x1c) |
+ CONSOLE_BG_COL >> 6);
+ bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) |
+ color8;
break;
case GDF_15BIT_555RGB:
fgx = (((CONSOLE_FG_COL >> 3) << 26) |
- ((CONSOLE_FG_COL >> 3) << 21) | ((CONSOLE_FG_COL >> 3) << 16) |
- ((CONSOLE_FG_COL >> 3) << 10) | ((CONSOLE_FG_COL >> 3) << 5) |
- (CONSOLE_FG_COL >> 3));
+ ((CONSOLE_FG_COL >> 3) << 21) |
+ ((CONSOLE_FG_COL >> 3) << 16) |
+ ((CONSOLE_FG_COL >> 3) << 10) |
+ ((CONSOLE_FG_COL >> 3) << 5) |
+ (CONSOLE_FG_COL >> 3));
bgx = (((CONSOLE_BG_COL >> 3) << 26) |
- ((CONSOLE_BG_COL >> 3) << 21) | ((CONSOLE_BG_COL >> 3) << 16) |
- ((CONSOLE_BG_COL >> 3) << 10) | ((CONSOLE_BG_COL >> 3) << 5) |
- (CONSOLE_BG_COL >> 3));
+ ((CONSOLE_BG_COL >> 3) << 21) |
+ ((CONSOLE_BG_COL >> 3) << 16) |
+ ((CONSOLE_BG_COL >> 3) << 10) |
+ ((CONSOLE_BG_COL >> 3) << 5) |
+ (CONSOLE_BG_COL >> 3));
break;
case GDF_16BIT_565RGB:
fgx = (((CONSOLE_FG_COL >> 3) << 27) |
- ((CONSOLE_FG_COL >> 2) << 21) | ((CONSOLE_FG_COL >> 3) << 16) |
- ((CONSOLE_FG_COL >> 3) << 11) | ((CONSOLE_FG_COL >> 2) << 5) |
- (CONSOLE_FG_COL >> 3));
+ ((CONSOLE_FG_COL >> 2) << 21) |
+ ((CONSOLE_FG_COL >> 3) << 16) |
+ ((CONSOLE_FG_COL >> 3) << 11) |
+ ((CONSOLE_FG_COL >> 2) << 5) |
+ (CONSOLE_FG_COL >> 3));
bgx = (((CONSOLE_BG_COL >> 3) << 27) |
- ((CONSOLE_BG_COL >> 2) << 21) | ((CONSOLE_BG_COL >> 3) << 16) |
- ((CONSOLE_BG_COL >> 3) << 11) | ((CONSOLE_BG_COL >> 2) << 5) |
- (CONSOLE_BG_COL >> 3));
+ ((CONSOLE_BG_COL >> 2) << 21) |
+ ((CONSOLE_BG_COL >> 3) << 16) |
+ ((CONSOLE_BG_COL >> 3) << 11) |
+ ((CONSOLE_BG_COL >> 2) << 5) |
+ (CONSOLE_BG_COL >> 3));
break;
case GDF_32BIT_X888RGB:
- fgx = (CONSOLE_FG_COL << 16) | (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL;
- bgx = (CONSOLE_BG_COL << 16) | (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL;
+ fgx = (CONSOLE_FG_COL << 16) |
+ (CONSOLE_FG_COL << 8) |
+ CONSOLE_FG_COL;
+ bgx = (CONSOLE_BG_COL << 16) |
+ (CONSOLE_BG_COL << 8) |
+ CONSOLE_BG_COL;
break;
case GDF_24BIT_888RGB:
- fgx = (CONSOLE_FG_COL << 24) | (CONSOLE_FG_COL << 16) |
- (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL;
- bgx = (CONSOLE_BG_COL << 24) | (CONSOLE_BG_COL << 16) |
- (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL;
+ fgx = (CONSOLE_FG_COL << 24) |
+ (CONSOLE_FG_COL << 16) |
+ (CONSOLE_FG_COL << 8) |
+ CONSOLE_FG_COL;
+ bgx = (CONSOLE_BG_COL << 24) |
+ (CONSOLE_BG_COL << 16) |
+ (CONSOLE_BG_COL << 8) |
+ CONSOLE_BG_COL;
break;
}
eorx = fgx ^ bgx;
#ifdef CONFIG_VIDEO_LOGO
/* Plot the logo and get start point of console */
- PRINTD ("Video: Drawing the logo ...\n");
- video_console_address = video_logo ();
+ debug("Video: Drawing the logo ...\n");
+ video_console_address = video_logo();
#else
video_console_address = video_fb_address;
#endif
return 0;
}
-
-/*****************************************************************************/
-
/*
* Implement a weak default function for boards that optionally
* need to skip the video initialization.
/* As default, don't skip test */
return 0;
}
-int board_video_skip(void) __attribute__((weak, alias("__board_video_skip")));
-int drv_video_init (void)
+int board_video_skip(void)
+ __attribute__ ((weak, alias("__board_video_skip")));
+
+int drv_video_init(void)
{
int skip_dev_init;
struct stdio_dev console_dev;
return 0;
/* Init video chip - returns with framebuffer cleared */
- skip_dev_init = (video_init () == -1);
+ skip_dev_init = (video_init() == -1);
#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
- PRINTD ("KBD: Keyboard init ...\n");
+ debug("KBD: Keyboard init ...\n");
skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1);
#endif
return 0;
/* Init vga device */
- memset (&console_dev, 0, sizeof (console_dev));
- strcpy (console_dev.name, "vga");
+ memset(&console_dev, 0, sizeof(console_dev));
+ strcpy(console_dev.name, "vga");
console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */
console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
console_dev.putc = video_putc; /* 'putc' function */
console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */
#endif /* CONFIG_VGA_AS_SINGLE_DEVICE */
- if (stdio_register (&console_dev) != 0)
+ if (stdio_register(&console_dev) != 0)
return 0;
/* Return success */
#include <altera.h>
-extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size );
-extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize );
-extern int ACEX1K_info( Altera_desc *desc );
+extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size);
+extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int ACEX1K_info(Altera_desc *desc);
-extern int CYC2_load( Altera_desc *desc, void *image, size_t size );
-extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize );
-extern int CYC2_info( Altera_desc *desc );
+extern int CYC2_load(Altera_desc *desc, const void *image, size_t size);
+extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int CYC2_info(Altera_desc *desc);
/* Slave Serial Implementation function table */
typedef struct {
/* Generic Altera Functions
*********************************************************************/
-extern int altera_load( Altera_desc *desc, void *image, size_t size );
-extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize );
-extern int altera_info( Altera_desc *desc );
+extern int altera_load(Altera_desc *desc, const void *image, size_t size);
+extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int altera_info(Altera_desc *desc);
/* Board specific implementation specific function types
*********************************************************************/
typedef int (*Altera_done_fn)( int cookie );
typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
-typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie);
+typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
typedef int (*Altera_abort_fn)( int cookie );
typedef int (*Altera_post_fn)( int cookie );
void hang (void) __attribute__ ((noreturn));
+int timer_init(void);
+int cpu_init(void);
+
/* */
phys_size_t initdram (int);
int display_options (void);
int env_init (void);
void env_relocate (void);
int envmatch (uchar *, int);
-char *getenv (char *);
-int getenv_f (char *name, char *buf, unsigned len);
+char *getenv (const char *);
+int getenv_f (const char *name, char *buf, unsigned len);
int saveenv (void);
#ifdef CONFIG_PPC /* ARM version to be fixed! */
-int inline setenv (char *, char *);
+int inline setenv (const char *, const char *);
#else
-int setenv (char *, char *);
+int setenv (const char *, const char *);
#endif /* CONFIG_PPC */
#ifdef CONFIG_ARM
# include <asm/mach-types.h>
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#ifdef __linux__
# include <endian.h>
# include <byteswap.h>
-#elif defined(__MACH__)
+#elif defined(__MACH__) || defined(__FreeBSD__)
# include <machine/endian.h>
typedef unsigned long ulong;
#endif
+------+----------------+------------------------------------------------------------
| # | Name | Comment
+------+----------------+------------------------------------------------------------
- | IRQ1 | UINTER_3V | S interupt chips interrupt (common)
+ | IRQ1 | UINTER_3V | S interrupt chips interrupt (common)
| IRQ3 | IRQ_DSP | DSP interrupt
| IRQ4 | IRQ_DSP1 | Extra DSP interrupt
+------+----------------+------------------------------------------------------------
#define CONFIG_FMAN_ENET
#endif
+#define CONFIG_SYS_FMAN_FW
#ifndef CONFIG_NAND
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
-#define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR
#else
#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000
-#define CONFIG_SYS_FMAN_FW_ADDR 0x10000000
-#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
#endif
+#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
#define CONFIG_SYS_TEXT_BASE 0x80000000
-/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
+/* IMMR Base Address Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR 0xff400000
/* System clock. Primary input clock when in PCI host mode */
#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
#endif
-#define CONFIG_SYS_POST_WORD_ADDR 0xFF903FFC
/* These are for board tests */
#if 0
#ifndef CONFIG_BAUDRATE
# define CONFIG_BAUDRATE 57600
#endif
+#ifndef CONFIG_DEBUG_EARLY_SERIAL
+# define CONFIG_SERIAL_MULTI
+# define CONFIG_SYS_BFIN_UART
+#endif
/*
* Debug Settings
"nc=" \
"set ncip ${serverip};" \
"set stdin nc;" \
- "set stdout nc" \
+ "set stdout nc;" \
+ "set stderr nc" \
"\0"
# else
# define NETCONSOLE_ENV
# define CONFIG_NET_RETRY_COUNT 20
#endif
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+
/*
* SPI Settings
*/
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0x20308000
+#define CONFIG_SMC911X_16_BIT
#define CONFIG_NETCONSOLE 1
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_SYS_MAX_FLASH_SECT 35
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+
+
/*
* Env Storage Settings
*/
#define CONFIG_HARD_I2C 1
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
+
/*
* Misc Settings
*/
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
*/
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
-#define CONFIG_NET_MULTI
-/* The next 3 lines are for use with SMSC on EXT-BF5xx-USB-ETH2 */
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_BASE 0x24000000
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0x20308000
#define CONFIG_SMC911X_16_BIT
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_HOSTNAME cm-bf537u
/* Uncomment next line to use fixed MAC address */
#define CONFIG_SYS_MAX_FLASH_SECT 35
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+
+
/*
* Env Storage Settings
*/
#define CONFIG_HARD_I2C 1
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
/*
* Misc Settings
*/
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_MMC
+++ /dev/null
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * hcu4.h - configuration for HCU4 board (similar to hcu5.h)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_HCU4 1 /* Board is HCU4 */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_405GP 1
-#define CONFIG_4xx 1
-#define CONFIG_HOSTNAME hcu4
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
-
-/*
- * Include common defines/options for all boards produced by Netstal Maschinen
- */
-#include "netstal-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
-*----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-/* ... with on-chip memory here (4KBytes) */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
-/* Do not set up locked dcache as init ram. */
-#undef CONFIG_SYS_INIT_DCACHE_CS
-
-/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* Set console baudrate to 9600 */
-#define CONFIG_BAUDRATE 9600
-
-/*-----------------------------------------------------------------------
- * Flash
- *----------------------------------------------------------------------*/
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* board provides its own flash_init code */
-#define CONFIG_FLASH_CFI_LEGACY 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-
-#undef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_NOWHERE
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-/* Put the environment after the SDRAM configuration */
-#define PROM_SIZE 2048
-#define CONFIG_ENV_OFFSET 512
-#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-/* Put the environment in Flash */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
- * the first internal I2C controller of the PPC440EPx
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SPD_BUS_NUM 0
-
-#define CONFIG_IPADDR 172.25.1.14
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_NETSTAL_DEF_ENV \
- CONFIG_NETSTAL_DEF_ENV_POWERPC \
- ""
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-
-/* SPD EEPROM (sdram speed config) disabled */
-#define CONFIG_SPD_EEPROM 1
-#define SPD_EEPROM_ADDRESS 0x50
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_SPR)
-
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
-#undef CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CONFIG_SYS_EBC_CFG 0x98400000
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x02005400
-#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
-
-#define CONFIG_SYS_EBC_PB1AP 0x03041200
-#define CONFIG_SYS_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_EBC_PB2AP 0x02054500
-#define CONFIG_SYS_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_EBC_PB3AP 0x01840300
-#define CONFIG_SYS_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_EBC_PB4AP 0x01800300
-#define CONFIG_SYS_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_GPIO0_OR 0xF27FFFFF /* GPIO value */
-#define CONFIG_SYS_GPIO0_TCR 0x7FFE0000 /* GPIO value */
-#define CONFIG_SYS_GPIO0_ODR 0x00E897FC /* GPIO value */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
-
-/* Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * hcu5.h - configuration for HCU5 board (derived from sequoia.h)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_HCU5 1 /* Board is HCU5 */
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_HOSTNAME hcu5
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
-
-/*
- * Include common defines/options for all boards produced by Netstal Maschinen
- */
-#include "netstal-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 3
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xfff00000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_BAUDRATE 115200
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-
-#undef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_NOWHERE
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-/* Put the environment after the SDRAM and bootstrap configuration */
-#define PROM_SIZE 2048
-#define CONFIG_SYS_BOOSTRAP_OPTION_OFFSET 512
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_BOOSTRAP_OPTION_OFFSET + 0x10)
-#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-/* Put the environment in Flash */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#endif
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
-#define CONFIG_SYS_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */
-#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
-#define CONFIG_DDR_ECC 1 /* enable ECC */
-
-/* Following two definitions must be kept in sync with config.h of vxWorks */
-#define USER_RESERVED_MEM ( 0) /* in kB */
-#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */
-#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM )
-
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
- /* 440EPx errata CHIP 11 */
-
-/*-----------------------------------------------------------------------
- * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
- * the second internal I2C controller of the PPC440EPx
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SPD_BUS_NUM 1
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_IPADDR 172.25.1.15
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_NETSTAL_DEF_ENV \
- CONFIG_NETSTAL_DEF_ENV_POWERPC \
- ""
-
-#define CONFIG_M88E1111_PHY 1
-#define CONFIG_IBM_EMAC4_V4 1
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 2
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_USB
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_SPR)
-
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
-#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI 1 /* include pci support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr map to CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash
- *----------------------------------------------------------------------*/
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* board provides its own flash_init code */
-#define CONFIG_FLASH_CFI_LEGACY 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS_1 0xC8000000 /* CAN */
-#define CONFIG_SYS_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
-#define CONFIG_SYS_CPLD CONFIG_SYS_CS_2
-#define CONFIG_SYS_CS_3 0xCE000000 /* CPLD and IMC-Bus Fast */
-
-#define CONFIG_SYS_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
-#define CONFIG_SYS_EBC_PB0AP 0x02005400
-#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* (CONFIG_SYS_FLASH | 0xda000) */
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-
-/* Memory Bank 1 CAN-Chips initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x02054500
-#define CONFIG_SYS_EBC_PB1CR 0xC8018000
-
-/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x01840300
-#define CONFIG_SYS_EBC_PB2CR 0xCC0BA000
-
-/* Memory Bank 3 IMC-Bus fast mode initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x01800300
-#define CONFIG_SYS_EBC_PB3CR 0xCE0BA000
-
-/* Memory Bank 4 (not used) initialization */
-#undef CONFIG_SYS_EBC_PB4AP
-#undef CONFIG_SYS_EBC_PB4CR
-
-/* Memory Bank 5 (not used) initialization */
-#undef CONFIG_SYS_EBC_PB5AP
-#undef CONFIG_SYS_EBC_PB5CR
-
-#define HCU_CPLD_VERSION_REGISTER ( CONFIG_SYS_CPLD + 0x0F00000 )
-#define HCU_HW_VERSION_REGISTER ( CONFIG_SYS_CPLD + 0x1400000 )
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#ifdef CONFIG_SYS_HUSH_PARSER
- #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#endif /* __CONFIG_H */
#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
+#define CONFIG_XWAY_SWAP_BYTES
+
/*
* Clock for the MIPS core (MHz)
* allowed values: 100000000, 133000000, and 150000000 (default)
#define CONFIG_CPU_CLOCK_RATE 150000000
#endif
-#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */
+#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+++ /dev/null
-/*
- *(C) Copyright 2005-2007 Netstal Maschinen AG
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * mcu25.h - configuration for MCU25 board (similar to hcu4.h)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_MCU25 1 /* Board is MCU25 */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_405GP 1
-#define CONFIG_4xx 1
-#define CONFIG_HOSTNAME mcu25
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
-
-/*
- * Include common defines/options for all boards produced by Netstal Maschinen
- */
-#include "netstal-common.h"
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
-*----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-/* ... with on-chip memory here (4KBytes) */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
-/* Do not set up locked dcache as init ram. */
-#undef CONFIG_SYS_INIT_DCACHE_CS
-
-/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* Set console baudrate to 9600 */
-#define CONFIG_BAUDRATE 9600
-
-/*-----------------------------------------------------------------------
- * Flash
- *----------------------------------------------------------------------*/
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* board provides its own flash_init code */
-#define CONFIG_FLASH_CFI_LEGACY 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-
-#undef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_NOWHERE
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-/* Put the environment after the SDRAM configuration */
-#define PROM_SIZE 2048
-#define CONFIG_ENV_OFFSET 512
-#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-/* Put the environment in Flash */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
- * the first internal I2C controller of the PPC440EPx
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SPD_BUS_NUM 0
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_IPADDR 172.25.1.25
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_NETSTAL_DEF_ENV \
- CONFIG_NETSTAL_DEF_ENV_POWERPC \
- ""
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-
-/* SPD EEPROM (sdram speed config) disabled */
-#define CONFIG_SPD_EEPROM 1
-#define SPD_EEPROM_ADDRESS 0x50
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_SPR)
-
-#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
-#undef CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CONFIG_SYS_EBC_CFG 0x98400000
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x02005400
-#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/
-
-#define CONFIG_SYS_EBC_PB1AP 0x03041200
-#define CONFIG_SYS_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-
-#define CONFIG_SYS_EBC_PB2AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CONFIG_SYS_EBC_PB2CR 0x7A09A000u
-
-#define CONFIG_SYS_EBC_PB3AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CONFIG_SYS_EBC_PB3CR 0x7B09A000u
-
-#define CONFIG_SYS_EBC_PB4AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CONFIG_SYS_EBC_PB4CR 0x7C09A000u
-
-#define CONFIG_SYS_EBC_PB5AP 0x00800200u
-#define CONFIG_SYS_EBC_PB5CR 0x7D81A000u
-
-#define CONFIG_SYS_EBC_PB6AP 0x01040200u
-#define CONFIG_SYS_EBC_PB6CR 0x7D91A000u
-
-#define CONFIG_SYS_GPIO0_OR 0x087FFFFF /* GPIO value */
-#define CONFIG_SYS_GPIO0_TCR 0x7FFF8000 /* GPIO value */
-#define CONFIG_SYS_GPIO0_ODR 0xFFFF0000 /* GPIO value */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Niklaus Giger, Netstal Maschinen AG, niklaus.giger@netstal.com
- * adapted from amcc-common.h by
- * (C) Copyright 2008
- * * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Common configuration options for all Netstal boards
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __NETSTAL_COMMON_H
-#define __NETSTAL_COMMON_H
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * UART
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SERIAL_MULTI
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*
- * I2C
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/* This is the 7bit address of the device, not including P. */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-
-/*
- * Ethernet/EMAC/PHY
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_NET_MULTI 1
-#if defined(CONFIG_440)
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* number of eth rx buffers */
-#else
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* number of eth rx buffers */
-#endif
-#define CONFIG_HAS_ETH0
-
-/*
- * Commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#if defined(CONFIG_440)
-#define CONFIG_CMD_CACHE
-#endif
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_BOOT_RETRY_TIME 30
-#define CONFIG_RESET_TO_RETRY
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_LOOPW /* enable loopw command */
-#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE /* include version env variable */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
-
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
-/*
- * Booting and default environment
- */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
- "echo"
-#define CONFIG_BOOTCOMMAND "run vx"
-
-/*
- * Only very few boards have default console not on ttyS0 (like Taishan)
- */
-#if !defined(CONFIG_USE_TTY)
-#define CONFIG_USE_TTY ttyS0
-#endif
-
-/*
- * Only some 4xx PPC's are equipped with an FPU
- */
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
-/*
- * Only some boards need to extend the bootargs by some additional
- * parameters (like Makalu)
- */
-#if !defined(CONFIG_ADDMISC)
-#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0"
-#endif
-
-#define xstr(s) str(s)
-#define str(s) #s
-
-/* Setup some values for the default environment variables */
-#define CONFIG_SERVERIP 172.25.1.1
-#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define CONFIG_SYS_TFTP_LOADADDR 0x01000000
-#define CONFIG_SYS_VXWORKS_ADD_PARAMS "u=dpu pw=netstal8752"
-#define CONFIG_SYS_VXWORKS_SERVERNAME "c"
-/*
- * General common environment variables shared by all boards produced by Netstal Maschinen
- */
-#define CONFIG_NETSTAL_DEF_ENV \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
- CONFIG_ADDMISC \
- "initrd_high=30000000\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=800000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "uload=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " " \
- xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
- "vx_rom=" xstr(CONFIG_HOSTNAME) "/" \
- xstr(CONFIG_HOSTNAME) "_vx_rom\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"\
- "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "cp.b ${fileaddr} "xstr(CONFIG_SYS_MONITOR_BASE) \
- " ${filesize}; setenv filesize\0" \
- "upd=run uload update\0" \
- "vx=setenv bootfile ${vx_rom}; tftp " \
- xstr(CONFIG_SYS_TFTP_LOADADDR) "; bootvx\0" \
- CONFIG_NETSTAL_DEF_ENV_ROOTPATH
-
-/*
- * Default environment for arch/powerpc booting
- * for boards that are ported to arch/powerpc
- */
-#define CONFIG_NETSTAL_DEF_ENV_POWERPC \
- "flash_self=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
-
-#endif /* __NETSTAL_COMMON_H */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
#define CONFIG_MPC8560 1
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_PCI /* PCI ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
/*
* I2C
*/
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
-/* TCM-BF537E has no PHY on it, but EXT-BF5xx-USB/Ethernet board has */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0x20308000
+#define CONFIG_SMC911X_16_BIT
#define CONFIG_NETCONSOLE 1
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_SYS_MAX_FLASH_SECT 67
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+
+
/*
* Env Storage Settings
*/
#define CONFIG_HARD_I2C 1
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
/*
* Misc Settings
*/
/* The build system likes to know if the env is embedded */
#ifdef DO_DEPS_ONLY
# ifdef ENV_IS_EMBEDDED
-# define CONFIG_ENV_IS_EMBEDDED
+# ifndef CONFIG_ENV_IS_EMBEDDED
+# define CONFIG_ENV_IS_EMBEDDED
+# endif
# endif
#endif
int vprintf(const char *, va_list);
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
-char *getenv (char *name);
-int setenv (char *varname, char *varvalue);
+char *getenv (const char *name);
+int setenv (const char *varname, const char *varvalue);
long simple_strtol(const char *cp,char **endp,unsigned int base);
int strcmp(const char * cs,const char * ct);
int ustrtoul(const char *cp, char **endp, unsigned int base);
/* root function definitions */
-extern void fpga_init( void );
-extern int fpga_add( fpga_type devtype, void *desc );
-extern int fpga_count( void );
-extern int fpga_load( int devnum, void *buf, size_t bsize );
-extern int fpga_dump( int devnum, void *buf, size_t bsize );
-extern int fpga_info( int devnum );
+extern void fpga_init(void);
+extern int fpga_add(fpga_type devtype, void *desc);
+extern int fpga_count(void);
+extern int fpga_load(int devnum, const void *buf, size_t bsize);
+extern int fpga_dump(int devnum, const void *buf, size_t bsize);
+extern int fpga_info(int devnum);
#endif /* _FPGA_H_ */
#define CHANNEL2_REGISTER10 0x9070
#define CHANNEL2_REGISTER11 0x9074
-/* MPSCs Interupts */
+/* MPSCs Interrupts */
#define MPSC0_CAUSE 0xb824
#define MPSC0_MASK 0xb8a4
sdma->IntPend = (1 << tasknum); \
}
-/* get interupt pending bit of a task */
+/* get interrupt pending bit of a task */
#define SDMA_GET_PENDINGBIT(tasknum) \
((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
-/* get interupt mask bit of a task */
+/* get interrupt mask bit of a task */
#define SDMA_GET_MASKBIT(tasknum) \
((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
#define PLTR 0x8000000d /* PCI Latancy Timer Register */
#define PHTR 0x8000000e /* PCI Header Type Register */
#define BISTCTRL 0x8000000f /* BIST Control */
-#define LMBAR 0x80000010 /* Local Base Addres Register */
+#define LMBAR 0x80000010 /* Local Base Address Register */
#define PCSRBAR 0x80000014 /* PCSR Base Address Register */
#define ILR 0x8000003c /* PCI Interrupt Line Register */
#define IPR 0x8000003d /* Interrupt Pin Register */
extern struct post_test post_list[];
extern unsigned int post_list_size;
extern int post_hotkeys_pressed(void);
+extern int memory_post_test(int flags);
/*
* If GCC is configured to use a version of GAS that supports
} ACTION;
typedef struct entry {
- char *key;
+ const char *key;
char *data;
} ENTRY;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
+#if defined(CONFIG_SYS_BFIN_UART)
+extern void serial_register_bfin_uart(void);
+extern struct serial_device bfin_serial0_device;
+extern struct serial_device bfin_serial1_device;
+extern struct serial_device bfin_serial2_device;
+extern struct serial_device bfin_serial3_device;
+#endif
+
+extern void serial_register(struct serial_device *);
extern void serial_initialize(void);
extern void serial_stdio_init(void);
extern int serial_assign(char * name);
#include <xilinx.h>
-extern int Spartan2_load( Xilinx_desc *desc, void *image, size_t size );
-extern int Spartan2_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-extern int Spartan2_info( Xilinx_desc *desc );
+extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int Spartan2_info(Xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
#include <xilinx.h>
-extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size );
-extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-extern int Spartan3_info( Xilinx_desc *desc );
+extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int Spartan3_info(Xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
#ifndef __VERSION_H__
#define __VERSION_H__
+#include <timestamp.h>
+
#ifndef DO_DEPS_ONLY
#include "version_autogenerated.h"
#endif
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
+ U_BOOT_TIME ")" CONFIG_IDENT_STRING
+
+#ifndef __ASSEMBLY__
+extern const char version_string[];
+#endif /* __ASSEMBLY__ */
#endif /* __VERSION_H__ */
#include <xilinx.h>
-extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size );
-extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-extern int Virtex2_info( Xilinx_desc *desc );
+extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int Virtex2_info(Xilinx_desc *desc);
/*
* Slave SelectMap Implementation function table.
/* Generic Xilinx Functions
*********************************************************************/
-extern int xilinx_load( Xilinx_desc *desc, void *image, size_t size );
-extern int xilinx_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-extern int xilinx_info( Xilinx_desc *desc );
+extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int xilinx_info(Xilinx_desc *desc);
/* Board specific implementation specific function types
*********************************************************************/
#include <config.h>
#include <common.h>
+#include <version.h>
#include <linux/ctype.h>
#include <asm/io.h>
int display_options (void)
{
- extern char version_string[];
-
#if defined(BUILD_TAG)
printf ("\n\n%s, Build: %s\n\n", version_string, BUILD_TAG);
#else
if (htab->table[i].used > 0) {
ENTRY *ep = &htab->table[i].entry;
- free(ep->key);
+ free((void *)ep->key);
free(ep->data);
}
}
/* free used ENTRY */
debug("hdelete: DELETING key \"%s\"\n", key);
- free(ep->key);
+ free((void *)ep->key);
free(ep->data);
htab->table[idx].used = -1;
* export sorted list of result data
*/
for (i = 0, p = res; i < n; ++i) {
- char *s;
+ const char *s;
s = list[i]->key;
while (*s)
udelay (100000); /* allow messages to go out */
do_reset (NULL, 0, 0, NULL);
#endif
+ while (1)
+ ;
}
echo "/* Automatically generated - do not edit */" >>config.h
for i in ${TARGETS} ; do
- i="`echo ${i} | sed '/=/ {s/=/\t/;q } ; { s/$/\t1/ }'`"
+ i="`echo ${i} | sed '/=/ {s/=/ /;q; } ; { s/$/ 1/; }'`"
echo "#define CONFIG_${i}" >>config.h ;
done
@rm -f $@
@touch $@
@for f in $(SRCS); do \
- g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
+ g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \
$(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
done
@for f in $(HOSTSRCS); do \
- g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
+ g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \
$(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
done
CONFIG_LCD_LOGO = y
CONFIG_CMD_LOADS = y
CONFIG_CMD_NET = y
-CONFIG_INCA_IP = y
+CONFIG_XWAY_SWAP_BYTES = y
CONFIG_NETCONSOLE = y
CONFIG_SHA1_CHECK_UB_IMG = y
endif
BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
-BIN_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes$(SFX)
+BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
BIN_FILES-y += mkimage$(SFX)
BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
NOPED_OBJ_FILES-y += fit_image.o
OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
-OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
+OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
NOPED_OBJ_FILES-y += kwbimage.o
NOPED_OBJ_FILES-y += imximage.o
NOPED_OBJ_FILES-y += mkimage.o
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(HOSTSTRIP) $@
-$(obj)inca-swap-bytes$(SFX): $(obj)inca-swap-bytes.o
+$(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(HOSTSTRIP) $@
+++ /dev/null
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#ifndef BUFSIZ
-# define BUFSIZ 4096
-#endif
-
-#undef BUFSIZ
-# define BUFSIZ 64
-int main (void)
-{
- short ibuff[BUFSIZ], obuff[BUFSIZ];
- int rc, i, len;
-
- while ((rc = read (0, ibuff, sizeof (ibuff))) > 0) {
- memset (obuff, 0, sizeof (obuff));
- for (i = 0; i < (rc + 1) / 2; i++) {
- obuff[i] = ibuff[i ^ 1];
- }
-
- len = (rc + 1) & ~1;
-
- if (write (1, obuff, len) != len) {
- perror ("read error");
- return (EXIT_FAILURE);
- }
-
- memset (ibuff, 0, sizeof (ibuff));
- }
-
- if (rc < 0) {
- perror ("read error");
- return (EXIT_FAILURE);
- }
- return (EXIT_SUCCESS);
-}
--- /dev/null
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#ifndef BUFSIZ
+# define BUFSIZ 4096
+#endif
+
+#undef BUFSIZ
+# define BUFSIZ 64
+int main (void)
+{
+ short ibuff[BUFSIZ], obuff[BUFSIZ];
+ int rc, i, len;
+
+ while ((rc = read (0, ibuff, sizeof (ibuff))) > 0) {
+ memset (obuff, 0, sizeof (obuff));
+ for (i = 0; i < (rc + 1) / 2; i++) {
+ obuff[i] = ibuff[i ^ 1];
+ }
+
+ len = (rc + 1) & ~1;
+
+ if (write (1, obuff, len) != len) {
+ perror ("read error");
+ return (EXIT_FAILURE);
+ }
+
+ memset (ibuff, 0, sizeof (ibuff));
+ }
+
+ if (rc < 0) {
+ perror ("read error");
+ return (EXIT_FAILURE);
+ }
+ return (EXIT_SUCCESS);
+}
projects / u-boot / commitdiff