int setup_sata(void)
{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
-struct iomuxc_base_regs {
- u32 gpr[14]; /* 0x000 */
- u32 obsrv[5]; /* 0x038 */
- u32 swmux_ctl[197]; /* 0x04c */
- u32 swpad_ctl[250]; /* 0x360 */
- u32 swgrp[26]; /* 0x748 */
- u32 daisy[104]; /* 0x7b0..94c */
-};
-
struct wdog_regs {
u16 wcr; /* Control */
u16 wsr; /* Service */
int board_init(void)
{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
static int setup_fec(void)
{
- struct iomuxc_base_regs *iomuxc_regs =
- (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
int board_init(void)
{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
int board_eth_init(bd_t *bis)
{
- struct iomuxc_base_regs *const iomuxc_regs =
- (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret = enable_fec_anatop_clock(ENET_25MHz);
if (ret)