]> git.sur5r.net Git - u-boot/commitdiff
ARM: imx6: Add DHCOM i.MX6 PDK board support
authorMarek Vasut <marex@denx.de>
Mon, 9 Oct 2017 19:51:10 +0000 (21:51 +0200)
committerStefano Babic <sbabic@denx.de>
Thu, 12 Oct 2017 16:01:06 +0000 (18:01 +0200)
Add support for the DHCOM i.MX6 PDK board. This board has:
- FEC ethernet
- EHCI USB host
- 3x SDMMC

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
arch/arm/mach-imx/mx6/Kconfig
board/dhelectronics/dh_imx6/Kconfig [new file with mode: 0644]
board/dhelectronics/dh_imx6/MAINTAINERS [new file with mode: 0644]
board/dhelectronics/dh_imx6/Makefile [new file with mode: 0644]
board/dhelectronics/dh_imx6/dh_imx6.c [new file with mode: 0644]
board/dhelectronics/dh_imx6/dh_imx6_spl.c [new file with mode: 0644]
configs/dh_imx6_defconfig [new file with mode: 0644]
include/configs/dh_imx6.h [new file with mode: 0644]

index 540f2b29b12f321164a6e2011604b84fd420e4b2..b82db3af22f6dfa33715b6745629fab830fafe3b 100644 (file)
@@ -129,6 +129,15 @@ config TARGET_COLIBRI_IMX6
        select DM_SERIAL
        select DM_THERMAL
 
+config TARGET_DHCOMIMX6
+       bool "dh_imx6"
+       select BOARD_LATE_INIT
+       select BOARD_EARLY_INIT_F
+       select SUPPORT_SPL
+       select DM
+       select DM_THERMAL
+       imply CMD_SPL
+
 config TARGET_EMBESTMX6BOARDS
        bool "embestmx6boards"
        select BOARD_LATE_INIT
@@ -428,6 +437,7 @@ source "board/boundary/nitrogen6x/Kconfig"
 source "board/ccv/xpress/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
+source "board/dhelectronics/dh_imx6/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/engicam/geam6ul/Kconfig"
diff --git a/board/dhelectronics/dh_imx6/Kconfig b/board/dhelectronics/dh_imx6/Kconfig
new file mode 100644 (file)
index 0000000..0cfef9b
--- /dev/null
@@ -0,0 +1,12 @@
+if TARGET_DHCOMIMX6
+
+config SYS_BOARD
+       default "dh_imx6"
+
+config SYS_VENDOR
+       default "dhelectronics"
+
+config SYS_CONFIG_NAME
+       default "dh_imx6"
+
+endif
diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS b/board/dhelectronics/dh_imx6/MAINTAINERS
new file mode 100644 (file)
index 0000000..e54bd60
--- /dev/null
@@ -0,0 +1,7 @@
+DH_IMX6 BOARD
+M:     Andreas Geisreiter <ageisreiter@dh-electronics.de>, Ludwig Zenz <lzenz@dh-electronics.de>
+S:     Maintained
+F:     board/dhelectronics/dh_imx6/
+F:     include/configs/dh_imx6.h
+F:     configs/dh_mx6q_defconfig
+F:     configs/dh_mx6dl_defconfig
diff --git a/board/dhelectronics/dh_imx6/Makefile b/board/dhelectronics/dh_imx6/Makefile
new file mode 100644 (file)
index 0000000..bddc8d8
--- /dev/null
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2017 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y  := dh_imx6_spl.o
+else
+obj-y  := dh_imx6.o
+endif
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
new file mode 100644 (file)
index 0000000..c76da4d
--- /dev/null
@@ -0,0 +1,437 @@
+/*
+ * DHCOM DH-iMX6 PDK board support
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <errno.h>
+#include <fsl_esdhc.h>
+#include <fuse.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_PAD_CTRL                                                   \
+       (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
+       PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define EEPROM_I2C_ADDRESS     0x50
+
+#define PC                     MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
+       .scl = {
+               .i2c_mode  = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+               .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+               .gp = IMX_GPIO_NR(3, 21)
+       },
+       .sda = {
+                .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+                .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
+                .gp = IMX_GPIO_NR(3, 28)
+        }
+};
+
+static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
+       .scl = {
+               .i2c_mode  = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+               .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
+               .gp = IMX_GPIO_NR(4, 12)
+       },
+       .sda = {
+                .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+                .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+                .gp = IMX_GPIO_NR(4, 13)
+        }
+};
+
+static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
+       .scl = {
+               .i2c_mode  = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+               .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+               .gp = IMX_GPIO_NR(1, 3)
+       },
+       .sda = {
+                .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
+                .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
+                .gp = IMX_GPIO_NR(1, 6)
+        }
+};
+
+static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
+       .scl = {
+               .i2c_mode  = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+               .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
+               .gp = IMX_GPIO_NR(3, 21)
+       },
+       .sda = {
+                .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+                .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+                .gp = IMX_GPIO_NR(3, 28)
+        }
+};
+
+static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
+       .scl = {
+               .i2c_mode  = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+               .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
+               .gp = IMX_GPIO_NR(4, 12)
+       },
+       .sda = {
+                .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+                .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+                .gp = IMX_GPIO_NR(4, 13)
+        }
+};
+
+static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
+       .scl = {
+               .i2c_mode  = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+               .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+               .gp = IMX_GPIO_NR(1, 3)
+       },
+       .sda = {
+                .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+                .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+                .gp = IMX_GPIO_NR(1, 6)
+        }
+};
+
+int dram_init(void)
+{
+       gd->ram_size = imx_ddr_size();
+       return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+       return 1;
+}
+
+#ifdef CONFIG_FEC_MXC
+static void eth_phy_reset(void)
+{
+       /* Reset PHY */
+       gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
+       udelay(500);
+       gpio_set_value(IMX_GPIO_NR(5, 0), 1);
+
+       /* Enable VIO */
+       gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
+
+       /*
+        * KSZ9021 PHY needs at least 10 mSec after PHY reset
+        * is released to stabilize
+        */
+       mdelay(10);
+}
+
+static int setup_fec_clock(void)
+{
+       struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       /* set gpr1[21] to select anatop clock */
+       clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
+
+       return enable_fec_anatop_clock(0, ENET_50MHZ);
+}
+
+int board_eth_init(bd_t *bis)
+{
+       uint32_t base = IMX_FEC_BASE;
+       struct mii_dev *bus = NULL;
+       struct phy_device *phydev = NULL;
+
+       setup_fec_clock();
+
+       eth_phy_reset();
+
+       bus = fec_get_miibus(base, -1);
+       if (!bus)
+               return -EINVAL;
+
+       /* Scan PHY 0 */
+       phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
+       if (!phydev) {
+               printf("Ethernet PHY not found!\n");
+               return -EINVAL;
+       }
+
+       return fec_probe(bis, -1, base, bus, phydev);
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 16)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 8)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+       { USDHC2_BASE_ADDR },
+       { USDHC3_BASE_ADDR },
+       { USDHC4_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+       switch (cfg->esdhc_base) {
+       case USDHC2_BASE_ADDR:
+               return gpio_get_value(USDHC2_CD_GPIO);
+       case USDHC3_BASE_ADDR:
+               return !gpio_get_value(USDHC3_CD_GPIO);
+       case USDHC4_BASE_ADDR:
+               return 1; /* eMMC/uSDHC4 is always present */
+       }
+
+       return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       int i, ret;
+
+       /*
+        * According to the board_mmc_init() the following map is done:
+        * (U-Boot device node)    (Physical Port)
+        * mmc0                    SD interface
+        * mmc1                    micro SD
+        * mmc2                    eMMC
+        */
+       gpio_direction_input(USDHC2_CD_GPIO);
+       gpio_direction_input(USDHC3_CD_GPIO);
+
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+static void setup_usb(void)
+{
+       /*
+        * Set daisy chain for otg_pin_id on MX6Q.
+        * For MX6DL, this bit is reserved.
+        */
+       imx_iomux_set_gpr_register(1, 13, 1, 0);
+}
+
+int board_usb_phy_mode(int port)
+{
+       return USB_INIT_HOST;
+}
+
+/* Use only Port 1 == DHCOM USB Host 1 */
+int board_ehci_hcd_init(int port)
+{
+       if (port == 1)
+               return 0;
+       else
+               return -ENODEV;
+}
+
+int board_ehci_power(int port, int on)
+{
+       switch (port) {
+       case 0:
+               break;
+       case 1:
+               gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
+               break;
+       default:
+               printf("MXC USB port %d not yet supported\n", port);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+#endif
+
+static int setup_dhcom_mac_from_fuse(void)
+{
+       unsigned char enetaddr[6];
+       int ret;
+
+       ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+       if (ret)        /* ethaddr is already set */
+               return 0;
+
+       imx_get_mac_from_fuse(0, enetaddr);
+
+       if (is_valid_ethaddr(enetaddr)) {
+               eth_env_set_enetaddr("ethaddr", enetaddr);
+               return 0;
+       }
+
+       ret = i2c_set_bus_num(2);
+       if (ret) {
+               printf("Error switching I2C bus!\n");
+               return ret;
+       }
+
+       ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
+       if (ret) {
+               printf("Error reading configuration EEPROM!\n");
+               return ret;
+       }
+
+       if (is_valid_ethaddr(enetaddr))
+               eth_env_set_enetaddr("ethaddr", enetaddr);
+
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_USB_EHCI_MX6
+       setup_usb();
+#endif
+
+       return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+       if (bus == 0 && cs == 0)
+               return IMX_GPIO_NR(2, 30);
+       else
+               return -1;
+}
+#endif
+
+int board_init(void)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       /* Enable eim_slow clocks */
+       setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
+
+#ifdef CONFIG_SYS_I2C_MXC
+       if (is_mx6dq()) {
+               setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
+               setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
+               setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
+       } else {
+               setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
+               setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
+               setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
+       }
+#endif
+
+#ifdef CONFIG_SATA
+       setup_sata();
+#endif
+
+       setup_dhcom_mac_from_fuse();
+
+       return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+       /* 4 bit bus width */
+       {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+       {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+       /* 8 bit bus width */
+       {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+       {NULL,   0},
+};
+#endif
+
+#define HW_CODE_BIT_0  IMX_GPIO_NR(2, 19)
+#define HW_CODE_BIT_1  IMX_GPIO_NR(6, 6)
+#define HW_CODE_BIT_2  IMX_GPIO_NR(2, 16)
+
+static int board_get_hwcode(void)
+{
+       int hw_code;
+
+       gpio_direction_input(HW_CODE_BIT_0);
+       gpio_direction_input(HW_CODE_BIT_1);
+       gpio_direction_input(HW_CODE_BIT_2);
+
+       /* HW 100 + HW 200 = 00b; HW 300 = 01b */
+       hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
+                  (gpio_get_value(HW_CODE_BIT_1) << 1) |
+                   gpio_get_value(HW_CODE_BIT_0)) + 2;
+
+       return hw_code;
+}
+
+int board_late_init(void)
+{
+       u32 hw_code;
+       char buf[16];
+
+       hw_code = board_get_hwcode();
+
+       switch (get_cpu_type()) {
+       case MXC_CPU_MX6SOLO:
+               snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
+               break;
+       case MXC_CPU_MX6DL:
+               snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
+               break;
+       case MXC_CPU_MX6D:
+               snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
+               break;
+       case MXC_CPU_MX6Q:
+               snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
+               break;
+       default:
+               snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
+               break;
+       }
+
+       env_set("dhcom", buf);
+
+#ifdef CONFIG_CMD_BMODE
+       add_board_boot_modes(board_boot_modes);
+#endif
+       return 0;
+}
+
+int checkboard(void)
+{
+       puts("Board: DHCOM i.MX6\n");
+       return 0;
+}
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
new file mode 100644 (file)
index 0000000..e22ff5c
--- /dev/null
@@ -0,0 +1,399 @@
+/*
+ * DHCOM DH-iMX6 PDK SPL support
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <fuse.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <spl.h>
+
+#define ENET_PAD_CTRL                                                  \
+       (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
+        PAD_CTL_HYS)
+
+#define GPIO_PAD_CTRL                                                  \
+       (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define SPI_PAD_CTRL                                                   \
+       (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |          \
+       PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL                                                  \
+       (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
+        PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL                                                 \
+       (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |   \
+        PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
+       .dram_sdclk_0   = 0x00020030,
+       .dram_sdclk_1   = 0x00020030,
+       .dram_cas       = 0x00020030,
+       .dram_ras       = 0x00020030,
+       .dram_reset     = 0x00020030,
+       .dram_sdcke0    = 0x00003000,
+       .dram_sdcke1    = 0x00003000,
+       .dram_sdba2     = 0x00000000,
+       .dram_sdodt0    = 0x00003030,
+       .dram_sdodt1    = 0x00003030,
+       .dram_sdqs0     = 0x00000030,
+       .dram_sdqs1     = 0x00000030,
+       .dram_sdqs2     = 0x00000030,
+       .dram_sdqs3     = 0x00000030,
+       .dram_sdqs4     = 0x00000030,
+       .dram_sdqs5     = 0x00000030,
+       .dram_sdqs6     = 0x00000030,
+       .dram_sdqs7     = 0x00000030,
+       .dram_dqm0      = 0x00020030,
+       .dram_dqm1      = 0x00020030,
+       .dram_dqm2      = 0x00020030,
+       .dram_dqm3      = 0x00020030,
+       .dram_dqm4      = 0x00020030,
+       .dram_dqm5      = 0x00020030,
+       .dram_dqm6      = 0x00020030,
+       .dram_dqm7      = 0x00020030,
+};
+
+static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
+       .grp_ddr_type   = 0x000C0000,
+       .grp_ddrmode_ctl = 0x00020000,
+       .grp_ddrpke     = 0x00000000,
+       .grp_addds      = 0x00000030,
+       .grp_ctlds      = 0x00000030,
+       .grp_ddrmode    = 0x00020000,
+       .grp_b0ds       = 0x00000030,
+       .grp_b1ds       = 0x00000030,
+       .grp_b2ds       = 0x00000030,
+       .grp_b3ds       = 0x00000030,
+       .grp_b4ds       = 0x00000030,
+       .grp_b5ds       = 0x00000030,
+       .grp_b6ds       = 0x00000030,
+       .grp_b7ds       = 0x00000030,
+};
+
+static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
+       .dram_sdclk_0   = 0x00020030,
+       .dram_sdclk_1   = 0x00020030,
+       .dram_cas       = 0x00020030,
+       .dram_ras       = 0x00020030,
+       .dram_reset     = 0x00020030,
+       .dram_sdcke0    = 0x00003000,
+       .dram_sdcke1    = 0x00003000,
+       .dram_sdba2     = 0x00000000,
+       .dram_sdodt0    = 0x00003030,
+       .dram_sdodt1    = 0x00003030,
+       .dram_sdqs0     = 0x00000030,
+       .dram_sdqs1     = 0x00000030,
+       .dram_sdqs2     = 0x00000030,
+       .dram_sdqs3     = 0x00000030,
+       .dram_sdqs4     = 0x00000030,
+       .dram_sdqs5     = 0x00000030,
+       .dram_sdqs6     = 0x00000030,
+       .dram_sdqs7     = 0x00000030,
+       .dram_dqm0      = 0x00020030,
+       .dram_dqm1      = 0x00020030,
+       .dram_dqm2      = 0x00020030,
+       .dram_dqm3      = 0x00020030,
+       .dram_dqm4      = 0x00020030,
+       .dram_dqm5      = 0x00020030,
+       .dram_dqm6      = 0x00020030,
+       .dram_dqm7      = 0x00020030,
+};
+
+static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
+       .grp_ddr_type   = 0x000C0000,
+       .grp_ddrmode_ctl = 0x00020000,
+       .grp_ddrpke     = 0x00000000,
+       .grp_addds      = 0x00000030,
+       .grp_ctlds      = 0x00000030,
+       .grp_ddrmode    = 0x00020000,
+       .grp_b0ds       = 0x00000030,
+       .grp_b1ds       = 0x00000030,
+       .grp_b2ds       = 0x00000030,
+       .grp_b3ds       = 0x00000030,
+       .grp_b4ds       = 0x00000030,
+       .grp_b5ds       = 0x00000030,
+       .grp_b6ds       = 0x00000030,
+       .grp_b7ds       = 0x00000030,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
+       .p0_mpwldectrl0 = 0x001F001F,
+       .p0_mpwldectrl1 = 0x001F001F,
+       .p1_mpwldectrl0 = 0x00440044,
+       .p1_mpwldectrl1 = 0x00440044,
+       .p0_mpdgctrl0   = 0x434B0350,
+       .p0_mpdgctrl1   = 0x034C0359,
+       .p1_mpdgctrl0   = 0x434B0350,
+       .p1_mpdgctrl1   = 0x03650348,
+       .p0_mprddlctl   = 0x4436383B,
+       .p1_mprddlctl   = 0x39393341,
+       .p0_mpwrdlctl   = 0x35373933,
+       .p1_mpwrdlctl   = 0x48254A36,
+};
+
+static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
+       .mem_speed      = 1600,
+       .density        = 4,
+       .width          = 64,
+       .banks          = 8,
+       .rowaddr        = 14,
+       .coladdr        = 10,
+       .pagesz         = 2,
+       .trcd           = 1375,
+       .trcmin         = 4875,
+       .trasmin        = 3500,
+};
+
+static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
+       /* width of data bus:0=16,1=32,2=64 */
+       .dsize          = 2,
+       /* config for full 4GB range so that get_mem_size() works */
+       .cs_density     = 32,   /* 32Gb per CS */
+       .ncs            = 1,    /* single chip select */
+       .cs1_mirror     = 0,
+       .rtt_wr         = 1,    /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+       .rtt_nom        = 1,    /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+       .walat          = 1,    /* Write additional latency */
+       .ralat          = 5,    /* Read additional latency */
+       .mif3_mode      = 3,    /* Command prediction working mode */
+       .bi_on          = 1,    /* Bank interleaving enabled */
+       .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
+       .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
+};
+
+static void ccgr_init(void)
+{
+       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       writel(0x00C03F3F, &ccm->CCGR0);
+       writel(0x0030FC03, &ccm->CCGR1);
+       writel(0x0FFFC000, &ccm->CCGR2);
+       writel(0x3FF00000, &ccm->CCGR3);
+       writel(0x00FFF300, &ccm->CCGR4);
+       writel(0x0F0000C3, &ccm->CCGR5);
+       writel(0x000003FF, &ccm->CCGR6);
+}
+
+/* Board ID */
+static iomux_v3_cfg_t const hwcode_pads[] = {
+       IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_boardid(void)
+{
+       /* HW code pins: Setup alternate function and configure pads */
+       SETUP_IOMUX_PADS(hwcode_pads);
+}
+
+/* GPIO */
+static iomux_v3_cfg_t const gpio_pads[] = {
+       IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03   | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21   | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18  | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+       IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_gpio(void)
+{
+       SETUP_IOMUX_PADS(gpio_pads);
+}
+
+/* Ethernet */
+static iomux_v3_cfg_t const enet_pads[] = {
+       IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+       /* SMSC PHY Reset */
+       IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00     | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       /* ENET_VIO_GPIO */
+       IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07       | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       /* ENET_Interrupt - (not used) */
+       IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_enet(void)
+{
+       SETUP_IOMUX_PADS(enet_pads);
+}
+
+/* SD interface */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+       IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_CLK__SD2_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_CMD__SD2_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+/* onboard microSD */
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+       IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_CLK__SD3_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_CMD__SD3_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08      | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+/* eMMC */
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+       IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_CLK__SD4_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_CMD__SD4_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+/* SD */
+static void setup_iomux_sd(void)
+{
+       SETUP_IOMUX_PADS(usdhc2_pads);
+       SETUP_IOMUX_PADS(usdhc3_pads);
+       SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+/* SPI */
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+       /* SS0 */
+       IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30      | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+};
+
+static void setup_iomux_spi(void)
+{
+       SETUP_IOMUX_PADS(ecspi1_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+       if (bus == 0 && cs == 0)
+               return IMX_GPIO_NR(2, 30);
+       else
+               return -1;
+}
+
+/* UART */
+static iomux_v3_cfg_t const uart1_pads[] = {
+       IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+       SETUP_IOMUX_PADS(uart1_pads);
+}
+
+/* USB */
+static iomux_v3_cfg_t const usb_pads[] = {
+       IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID       | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31      | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_usb(void)
+{
+       SETUP_IOMUX_PADS(usb_pads);
+}
+
+void board_init_f(ulong dummy)
+{
+       /* setup AIPS and disable watchdog */
+       arch_cpu_init();
+
+       ccgr_init();
+       gpr_init();
+
+       /* setup GP timer */
+       timer_init();
+
+       setup_iomux_boardid();
+       setup_iomux_gpio();
+       setup_iomux_enet();
+       setup_iomux_sd();
+       setup_iomux_spi();
+       setup_iomux_uart();
+       setup_iomux_usb();
+
+       /* UART clocks enabled and gd valid - init serial console */
+       preloader_console_init();
+
+       /* Start the DDR DRAM */
+       if (is_mx6dq())
+               mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
+                                &dhcom6dq_grp_ioregs);
+       else
+               mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
+                                 &dhcom6sdl_grp_ioregs);
+       mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
+
+       /* Perform DDR DRAM calibration */
+       udelay(100);
+       mmdc_do_write_level_calibration(&dhcom_ddr_info);
+       mmdc_do_dqs_calibration(&dhcom_ddr_info);
+
+       /* Clear the BSS. */
+       memset(__bss_start, 0, __bss_end - __bss_start);
+
+       /* load/boot image from boot device */
+       board_init_r(NULL, 0);
+}
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
new file mode 100644 (file)
index 0000000..5125260
--- /dev/null
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_DHCOMIMX6=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
new file mode 100644 (file)
index 0000000..0595f60
--- /dev/null
@@ -0,0 +1,191 @@
+/*
+ * DHCOM DH-iMX6 PDK board configuration
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DH_IMX6_CONFIG_H
+#define __DH_IMX6_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+/*
+ * SPI NOR layout:
+ * 0x00_0000-0x00_ffff ... U-Boot SPL
+ * 0x01_0000-0x0f_ffff ... U-Boot
+ * 0x10_0000-0x10_ffff ... U-Boot env #1
+ * 0x11_0000-0x11_ffff ... U-Boot env #2
+ * 0x12_0000-0x1f_ffff ... UNUSED
+ */
+
+/* SPL */
+#include "imx6_spl.h"                  /* common IMX6 SPL configuration */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x11400
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.imx"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SUPPORT_RAW_INITRD      /* bootz raw initrd support */
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_BZIP2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (4 * SZ_1M)
+
+/* Bootcounter */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR      IRAM_BASE_ADDR
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* FEC ethernet */
+#define CONFIG_MII
+#define IMX_FEC_BASE                   ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE            RMII
+#define CONFIG_ETHPRIME                        "FEC"
+#define CONFIG_FEC_MXC_PHYADDR         0
+#define CONFIG_ARP_TIMEOUT             200UL
+
+/* Fuses */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED           100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       3
+#define CONFIG_SYS_MMC_ENV_DEV         2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
+
+/* SATA Configs */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE     1
+#define CONFIG_DWC_AHSATA_PORT_ID      0
+#define CONFIG_DWC_AHSATA_BASE_ADDR    SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* SPI Flash Configs */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS          0
+#define CONFIG_SF_DEFAULT_CS           0
+#define CONFIG_SF_DEFAULT_SPEED                25000000
+#define CONFIG_SF_DEFAULT_MODE         (SPI_MODE_0)
+#endif
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE           UART1_BASE
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                        115200
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC          (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS           0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        2 /* Enabled USB controller number */
+#endif
+
+/* Watchdog */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS  60000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_TEXT_BASE           0x17800000
+#define CONFIG_LOADADDR                        0x12000000
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS      \
+       "console=ttymxc0,115200\0"      \
+       "fdt_addr=0x18000000\0"         \
+       "fdt_high=0xffffffff\0"         \
+       "initrd_high=0xffffffff\0"      \
+       "kernel_addr_r=0x10008000\0"    \
+       "fdt_addr_r=0x13000000\0"       \
+       "ramdisk_addr_r=0x18000000\0"   \
+       "scriptaddr=0x14000000\0"       \
+       "fdtfile=imx6q-dhcom-pdk2.dtb\0"\
+       BOOTENV
+
+#define CONFIG_BOOTCOMMAND             "run distro_bootcmd"
+
+#define BOOT_TARGET_DEVICES(func) \
+       func(MMC, mmc, 0) \
+       func(MMC, mmc, 2) \
+       func(USB, usb, 1) \
+       func(SATA, sata, 0) \
+       func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x20000000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+/* Environment */
+#define CONFIG_ENV_SIZE                        (16 * 1024)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET              (1024 * 1024)
+#define CONFIG_ENV_SECT_SIZE           (64 * 1024)
+#define CONFIG_ENV_OFFSET_REDUND       \
+       (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
+#endif
+
+#endif /* __DH_IMX6_CONFIG_H */