This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
select CPU_ARM1136
select SUPPORT_SPL
-config TARGET_TT01
- bool "Support tt01"
- select CPU_ARM1136
-
config TARGET_WOODBURN
bool "Support woodburn"
select CPU_ARM1136
source "board/freescale/vf610twr/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
-source "board/hale/tt01/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
+++ /dev/null
-if TARGET_TT01
-
-config SYS_BOARD
- default "tt01"
-
-config SYS_VENDOR
- default "hale"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "tt01"
-
-endif
+++ /dev/null
-TT01 BOARD
-M: Helmut Raiger <helmut.raiger@hale.at>
-S: Maintained
-F: board/hale/tt01/
-F: include/configs/tt01.h
-F: configs/tt01_defconfig
+++ /dev/null
-#
-# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at>
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := tt01.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
- /* Also setup the Peripheral Port Remap register inside the core */
- ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
- mcr p15, 0, r0, c15, c2, 4
- mov pc, lr
+++ /dev/null
-/*
- * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <command.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mc13783.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BOARD_STRING "Board: HALE TT-01"
-
-/* Clock configuration */
-#define CCM_CCMR_SETUP 0x074B0BF5
-
-static void board_setup_clocks(void)
-{
- struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
- volatile int wait = 0x10000;
-
- writel(CCM_CCMR_SETUP, &ccm->ccmr);
- while (wait--)
- ;
-
- writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
- writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
-
- /* Set up clock to 532MHz */
- writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
- PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
- PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
- PDR0_MCU_PODF(0), &ccm->pdr0);
- writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
- &ccm->mpctl);
- writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
- &ccm->spctl);
-}
-
-/* DRAM configuration */
-
-#define ESDMISC_MDDR_SETUP 0x00000004
-#define ESDMISC_MDDR_RESET_DL 0x0000000c
-/*
- * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
- * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
- * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
- * tRCD = 011, tRC = 010
- * note: all but tWTR (1), tRC (111) are reset defaults,
- * the same values work in the jtag configuration
- *
- * Bluetechnix setup has 0x75e73a (for 128MB) =
- * 0b 0111 0101 1110 0111 0011 1010
- * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
- * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
- * tRCD = 011, tRC = 010
- */
-#define ESDCFG0_MDDR_SETUP 0x006ac73a
-#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
-#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
- ESDCTL_DSIZ(2) | ESDCTL_BL(1))
-#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
-#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
-#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
-#define ESDCTL_RW ESDCTL_SETTINGS
-
-static void board_setup_sdram(void)
-{
- u32 *pad;
- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-
- /*
- * setup pad control for the controller pins
- * no loopback, no pull, no keeper, no open drain,
- * standard input, standard drive, slow slew rate
- */
- for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
- pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
- *pad = 0;
-
- /* set up MX31 DDR Memory Controller */
- writel(ESDMISC_MDDR_SETUP, &esdc->misc);
- writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
-
- /* perform DDR init sequence for CSD0 */
- writel(ESDCTL_PRECHARGE, &esdc->ctl0);
- writel(0x12344321, CSD0_BASE+0x0f00);
- writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
- writel(0x12344321, CSD0_BASE);
- writel(0x12344321, CSD0_BASE);
- writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
- writeb(0xda, CSD0_BASE+0x33);
- writeb(0xff, CSD0_BASE+0x1000000);
- writel(ESDCTL_RW, &esdc->ctl0);
- writel(0xDEADBEEF, CSD0_BASE);
- writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
-}
-
-static void tt01_spi3_hw_init(void)
-{
- /* CSPI3 */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
- /* CSPI3, SS0 = Atlas */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
-
- /* start CSPI3 clock (3 = always on except if PLL off) */
- setbits_le32(CCM_CGR0, 3 << 16);
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* CS4: FPGA incl. network controller */
- struct mxc_weimcs cs4 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
- };
-
- /* this seems essential, won't start without, but why? */
- writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
-
- board_setup_clocks();
- board_setup_sdram();
- mxc_setup_weimcs(4, &cs4);
-
- /* Setup UART2 and SPI3 pins */
- mx31_uart2_hw_init();
- tt01_spi3_hw_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_HW_WATCHDOG
- hw_watchdog_init();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts(BOARD_STRING "\n");
- return 0;
-}
-
-#ifdef CONFIG_MXC_MMC
-int board_mmc_init(bd_t *bis)
-{
- u32 val;
- struct pmic *p;
- int ret;
-
- /*
- * this is the first driver to use the pmic, so call
- * pmic_init() here. board_late_init() is too late for
- * the MMC driver.
- */
-
- ret = pmic_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return -ENODEV;
-
- /* configure pins for SDHC1 only */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
-
- /* turn on power V_MMC1 */
- if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
- pmic_reg_write(p, REG_MODE_1, val | VMMC1EN);
-
- return mxc_mmc_init(bis);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-void video_get_info_str(int line_number, char *info)
-{
- u32 srev = get_cpu_rev();
-
- switch (line_number) {
- case 2:
- sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz",
- (srev & 0xF0) >> 4, (srev & 0x0F),
- ((srev & 0x8000) ? " unknown" : ""),
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
- break;
- case 3:
- strcpy(info, " " BOARD_STRING);
- break;
- default:
- info[0] = 0;
- }
-}
-#endif
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_TT01=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="TT01> "
+++ /dev/null
-/*
- * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
- * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * Configuration settings for the HALE TT-01 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-#define CONFIG_MX31
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
-#define CONFIG_SYS_TEXT_BASE 0xA0000000
-
-
-/*
- * Physical Memory Map:
- * CS settings are defined by i.MX31:
- * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
- * - CS0 and CS1 are 128MB each, at A0000000 and A8000000
- * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
- *
- * HALE set-up of the bluetechnix board for now is:
- * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
- * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
- * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
- * the flash chip is a mirrorbit S29WS256N !
- * - the PSRAM is hooked to CS5 (0xB6000000)
- * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
- * - 64Mbit = 8MByte (will go away in the production set-up)
- * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
- * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
- * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
- *
- * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
- * is not used right now. We should be able to reduce the SOM to NAND flash
- * only and boot from there.
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
-
-/* default load address, 1MB up the road */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
-
-/* Size of malloc() pool, make sure possible frame buffer fits */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
-
-/* memtest works on all but the last 1MB (u-boot) and malloc area */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END \
- (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
-
-/* CFI FLASH driver setup */
-#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
-#define CONFIG_FLASH_SPANSION_S29WS_N
-/*
- * TODO: Bluetechnix (the supplier of the SOM) did define these values
- * in their original version of u-boot (1.2 or so). This should be
- * reviewed.
- *
- * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- * #define CONFIG_SYS_FLASH_PROTECTION
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
-
-/*
- * FLASH and environment organization, only the Spansion chip is supported:
- * - it has 254 * 128kB + 8 * 32kB blocks
- * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
- * and 2 sectors with 128k as environment =
- * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
- * - this could be less, but this is only for developer versions of the board
- * and no-one is going to use the NOR flash anyway.
- *
- * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
- * way to large, but it avoids ENV overwrite (when updating u-boot) in case
- * size breaks the next boundary (as it has with 128k).
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE (128 * 1024)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/* Hardware drivers */
-
-/*
- * on TT-01 UART1 pins are used by Audio, so we use UART2
- * TT-01 implements a hardware that turns off components depending on
- * the power level. In PL=1 the RS232 transceiver is usually off,
- * make sure that the transceiver is enabled during PL=1 for testing!
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART2_BASE
-
-#define CONFIG_MXC_SPI
-#define CONFIG_MXC_GPIO
-
-/* MC13783 connected to CSPI3 and SS0 */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-
-#define CONFIG_FSL_PMIC_BUS 2
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-
-#define CONFIG_RTC_MC13XXX
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-/* console is UART2 on TT-01 */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* ethernet setup for the onboard smc9118 */
-#define CONFIG_MII
-#define CONFIG_SMC911X
-/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
-#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
-#define CONFIG_SMC911X_16_BIT
-
-/* mmc driver */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MXC_MMC
-#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR
-
-/* video support */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_MX3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-/* splash image won't work with NAND boot, use preboot script */
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
-#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
-
-/* allow stdin, stdout and stderr variables to redirect output */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */
-#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */
-#define CONFIG_PREBOOT
-
-/* allow decompressing max. 4MB */
-#define CONFIG_VIDEO_BMP_GZIP
-/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
-
-/*
- * Command definition
- */
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NAND
-/*
- * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
- * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
- * a software locking scheme.
- */
-#define CONFIG_CMD_BMP
-
-#define CONFIG_BOOTDELAY 3
-
-/*
- * currently a default setting for booting via script is implemented
- * set user to login name and serverip to tftp host, define your
- * boot behaviour in bootscript.loginname
- *
- * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
- *
- * This set-up is for the L5F30947T04 by Epson, which is
- * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
- * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"videomode=epson\0" \
-"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
- "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
-"bootcmd=dhcp bootscript.${user}; source\0"
-
-#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
-#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_CMDLINE_EDITING
-
-/* MMC boot support */
-#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-#define CONFIG_NAND_MXC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/*
- * actually this is nothing someone wants to configure!
- * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
- * is not used by the driver.
- */
-#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
-#define CONFIG_MXC_NAND_HWECC
-
-/* the current u-boot driver does not use the nand flash setup! */
-#define CONFIG_SYS_NAND_LARGEPAGE
-/*
- * it's not 16 bit:
- * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
- * the current u-boot mxc_nand.c tries to auto-detect, but this only
- * reads the boot settings during reset (which might be wrong)
- */
-
-#endif /* __CONFIG_H */
projects / u-boot / commitdiff