(1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
},
[LAW_TRGT_IF_PCIE_2] = {
- .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
- (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
- (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
- (1 << 0x18) | (1 << 0x1c),
+ .cfg = (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
+ (1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
+ (1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
},
[LAW_TRGT_IF_PCIE_3] = {
- .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
- (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
- (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
+ .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
+ (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) |
+ (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c),
},
};
#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#define MPC85xx_PORDEVSR_PCI1 0x00800000
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
+#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
+#endif
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000