Exynos: Split 5250 and 5420 memory bank configuration

Since snow has a different memory configuration than peach, split the
configuration between the 5250 and 5420. Exynos 5420 supports runtime
memory configuration detection, and can make the determination between 4
and 7 banks at runtime.

Include the bank size with the number of banks for context to make the
number of banks meaningful.

Signed-off-by: Michael Pratt <mpratt@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index 3c51650bf0e0890bc361877ea78cb859dd9b29d3..e36a0313c13cf5fbf07c6d4ba832ad008e18e140 100644 (file)
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -161,8 +161,6 @@
 
 #define CONFIG_RD_LVL
 
-#define CONFIG_NR_DRAM_BANKS   8
-#define SDRAM_BANK_SIZE                (256UL << 20UL) /* 256 MB */
 #define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE      SDRAM_BANK_SIZE
 #define PHYS_SDRAM_2           (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)

diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 3982010b4b6bcdd87a799d9def813c51022b9461..74e72a5dc1ce478ca8ff17ae98ec712f2097e608 100644 (file)
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -65,4 +65,9 @@
 #define LCD_YRES                       1600
 #define LCD_BPP                        LCD_COLOR16
 #endif
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS   8
+#define SDRAM_BANK_SIZE                (256UL << 20UL) /* 256 MB */
+
 #endif  /* __CONFIG_5250_H */

diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h
index 2ffe5ee5cfdbae2251dd06d3e6c35e78d4993477..d2a95567a8951bf26c10278d06659689e5f15c14 100644 (file)
--- a/include/configs/exynos5420.h
+++ b/include/configs/exynos5420.h
@@ -45,4 +45,8 @@
  */
 #define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_IRAM_TOP - 0x800)
 
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS   7
+#define SDRAM_BANK_SIZE                (512UL << 20UL) /* 512 MB */
+
 #endif /* __CONFIG_EXYNOS5420_H */