-//*****************************************************************************\r
-//\r
-// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/\r
-//\r
-// Redistribution and use in source and binary forms, with or without\r
-// modification, are permitted provided that the following conditions\r
-// are met:\r
-//\r
-// Redistributions of source code must retain the above copyright\r
-// notice, this list of conditions and the following disclaimer.\r
-//\r
-// Redistributions in binary form must reproduce the above copyright\r
-// notice, this list of conditions and the following disclaimer in the\r
-// documentation and/or other materials provided with the\r
-// distribution.\r
-//\r
-// Neither the name of Texas Instruments Incorporated nor the names of\r
-// its contributors may be used to endorse or promote products derived\r
-// from this software without specific prior written permission.\r
-//\r
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-//\r
-// MSP432P401R Register Definitions\r
-//\r
-// This file includes definitions that are compatible with MSP430 code,\r
-// and additionally CMSIS compliant definitions\r
-//\r
-// When using MSP430 definitions the physical registers can be directly\r
-// accessed, e.g.\r
-// - ADC14CTL0 |= ADC14SSEL__ACLK;\r
-//\r
-// When using CMSIS definitions, the register and bit defines have been\r
-// reformatted and shortened.\r
-// - Registers: ModuleName[ModuleInstance]->rRegisterName.r\r
-// - Bits: ModuleName[ModuleInstance]->rRegisterName.b.bBitName\r
-// - Alternate Bits: ModuleName[ModuleInstance]->rRegisterName.a.bBitName\r
-//\r
-// Writing to CMSIS bit fields can be done through both register level\r
-// access or bit level access, e.g.\r
-// - ADC14->rCTL0.r |= ADC14SSEL__ACLK;\r
-// - ADC14->rCTL0.b.bSSEL = ADC14SSEL__ACLK >> ADC14SSEL_OFS;\r
-//\r
-// File creation date: 2015-01-05\r
-//\r
-//****************************************************************************\r
+/******************************************************************************\r
+*\r
+* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/\r
+*\r
+* Redistribution and use in source and binary forms, with or without\r
+* modification, are permitted provided that the following conditions\r
+* are met:\r
+*\r
+* Redistributions of source code must retain the above copyright\r
+* notice, this list of conditions and the following disclaimer.\r
+*\r
+* Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in the\r
+* documentation and/or other materials provided with the\r
+* distribution.\r
+*\r
+* Neither the name of Texas Instruments Incorporated nor the names of\r
+* its contributors may be used to endorse or promote products derived\r
+* from this software without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*\r
+* MSP432P401R Register Definitions\r
+*\r
+* This file includes CMSIS compliant component and register definitions\r
+*\r
+* For legacy components the definitions that are compatible with MSP430 code,\r
+* are included with msp432p401r_classic.h\r
+* \r
+* With CMSIS definitions, the register defines have been reformatted:\r
+* ModuleName[ModuleInstance]->RegisterName\r
+*\r
+* Writing to CMSIS bit fields can be done through register level\r
+* or via bitband area access:\r
+* - ADC14->CTL0 |= ADC14_CTL0_ENC;\r
+* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1;\r
+*\r
+* File creation date: 2015-10-26\r
+*\r
+******************************************************************************/\r
\r
#ifndef __MSP432P401R_H__\r
#define __MSP432P401R_H__\r
\r
-// Use standard integer types with explicit width\r
+/* Use standard integer types with explicit width */\r
#include <stdint.h>\r
\r
-// Remap MSP430 intrinsics to ARM equivalents\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#define __MSP432_HEADER_VERSION__ 2000\r
+\r
+/* Remap MSP432 intrinsics to ARM equivalents */\r
#include "msp_compatibility.h"\r
\r
-//*****************************************************************************\r
-// CMSIS-compatible Interrupt Number Definition\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* include MSP430 legacy definitions to make porting of code from MSP430 *\r
+* code base easier *\r
+* With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in *\r
+* your project to omit including the classic defines *\r
+******************************************************************************/\r
+#ifndef NO_MSP_CLASSIC_DEFINES\r
+#include "msp432p401r_classic.h"\r
+#endif\r
+\r
#ifndef __CMSIS_CONFIG__\r
#define __CMSIS_CONFIG__\r
\r
+/** @addtogroup MSP432P401R_Definitions MSP432P401R Definitions\r
+ This file defines all structures and symbols for MSP432P401R:\r
+ - components and registers\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - Peripheral definitions\r
+ @{\r
+*/\r
+\r
+/******************************************************************************\r
+* Processor and Core Peripherals *\r
+******************************************************************************/\r
+/** @addtogroup MSP432P401R_CMSIS Device CMSIS Definitions\r
+ Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ @{\r
+*/\r
+\r
+/******************************************************************************\r
+* CMSIS-compatible Interrupt Number Definition *\r
+******************************************************************************/\r
typedef enum IRQn\r
{\r
- // Cortex-M4 Processor Exceptions Numbers\r
+ /* Cortex-M4 Processor Exceptions Numbers */\r
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */\r
HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */\r
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */\r
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */\r
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */\r
SysTick_IRQn = -1, /* 15 System Tick Interrupt */\r
- // Peripheral Exceptions Numbers\r
+ /* Peripheral Exceptions Numbers */\r
PSS_IRQn = 0, /* 16 PSS Interrupt */\r
CS_IRQn = 1, /* 17 CS Interrupt */\r
PCM_IRQn = 2, /* 18 PCM Interrupt */\r
PORT6_IRQn = 40 /* 56 PORT6 Interrupt */\r
} IRQn_Type;\r
\r
-//*****************************************************************************\r
-// CMSIS-compatible configuration of the Cortex-M4 Processor and Core Peripherals\r
-//*****************************************************************************\r
-#define __MPU_PRESENT 1 // MPU present or not\r
-#define __NVIC_PRIO_BITS 3 // Number of Bits used for Prio Levels\r
-#define __FPU_PRESENT 1 // FPU present or not\r
-\r
-#endif // __CMSIS_CONFIG__\r
-\r
-// Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
-#ifdef __TMS470__\r
+/******************************************************************************\r
+* Processor and Core Peripheral Section *\r
+******************************************************************************/\r
+#define __CM4_REV 0x0001 /* Core revision r0p1 */\r
+#define __MPU_PRESENT 1 /* MPU present or not */\r
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */\r
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /* FPU present or not */\r
+\r
+/******************************************************************************\r
+* Available Peripherals *\r
+******************************************************************************/\r
+#define __MCU_HAS_ADC14__ /**< Module ADC14 is available */\r
+#define __MCU_HAS_AES256__ /**< Module AES256 is available */\r
+#define __MCU_HAS_CAPTIO0__ /**< Module CAPTIO0 is available */\r
+#define __MCU_HAS_CAPTIO1__ /**< Module CAPTIO1 is available */\r
+#define __MCU_HAS_COMP_E0__ /**< Module COMP_E0 is available */\r
+#define __MCU_HAS_COMP_E1__ /**< Module COMP_E1 is available */\r
+#define __MCU_HAS_CRC32__ /**< Module CRC32 is available */\r
+#define __MCU_HAS_CS__ /**< Module CS is available */\r
+#define __MCU_HAS_DIO__ /**< Module DIO is available */\r
+#define __MCU_HAS_DMA__ /**< Module DMA is available */\r
+#define __MCU_HAS_EUSCI_A0__ /**< Module EUSCI_A0 is available */\r
+#define __MCU_HAS_EUSCI_A1__ /**< Module EUSCI_A1 is available */\r
+#define __MCU_HAS_EUSCI_A2__ /**< Module EUSCI_A2 is available */\r
+#define __MCU_HAS_EUSCI_A3__ /**< Module EUSCI_A3 is available */\r
+#define __MCU_HAS_EUSCI_B0__ /**< Module EUSCI_B0 is available */\r
+#define __MCU_HAS_EUSCI_B1__ /**< Module EUSCI_B1 is available */\r
+#define __MCU_HAS_EUSCI_B2__ /**< Module EUSCI_B2 is available */\r
+#define __MCU_HAS_EUSCI_B3__ /**< Module EUSCI_B3 is available */\r
+#define __MCU_HAS_FLCTL__ /**< Module FLCTL is available */\r
+#define __MCU_HAS_PCM__ /**< Module PCM is available */\r
+#define __MCU_HAS_PMAP__ /**< Module PMAP is available */\r
+#define __MCU_HAS_PSS__ /**< Module PSS is available */\r
+#define __MCU_HAS_REF_A__ /**< Module REF_A is available */\r
+#define __MCU_HAS_RSTCTL__ /**< Module RSTCTL is available */\r
+#define __MCU_HAS_RTC_C__ /**< Module RTC_C is available */\r
+#define __MCU_HAS_SYSCTL__ /**< Module SYSCTL is available */\r
+#define __MCU_HAS_TIMER32__ /**< Module TIMER32 is available */\r
+#define __MCU_HAS_TIMER_A0__ /**< Module TIMER_A0 is available */\r
+#define __MCU_HAS_TIMER_A1__ /**< Module TIMER_A1 is available */\r
+#define __MCU_HAS_TIMER_A2__ /**< Module TIMER_A2 is available */\r
+#define __MCU_HAS_TIMER_A3__ /**< Module TIMER_A3 is available */\r
+#define __MCU_HAS_TLV__ /**< Module TLV is available */\r
+#define __MCU_HAS_WDT_A__ /**< Module WDT_A is available */\r
+\r
+/* Definitions to show that specific ports are available */\r
+\r
+#define __MSP432_HAS_PORTA_R__\r
+#define __MSP432_HAS_PORTB_R__\r
+#define __MSP432_HAS_PORTC_R__\r
+#define __MSP432_HAS_PORTD_R__\r
+#define __MSP432_HAS_PORTE_R__\r
+#define __MSP432_HAS_PORTJ_R__\r
+\r
+#define __MSP432_HAS_PORT1_R__\r
+#define __MSP432_HAS_PORT2_R__\r
+#define __MSP432_HAS_PORT3_R__\r
+#define __MSP432_HAS_PORT4_R__\r
+#define __MSP432_HAS_PORT5_R__\r
+#define __MSP432_HAS_PORT6_R__\r
+#define __MSP432_HAS_PORT7_R__\r
+#define __MSP432_HAS_PORT8_R__\r
+#define __MSP432_HAS_PORT9_R__\r
+#define __MSP432_HAS_PORT10_R__\r
+\r
+\r
+/*@}*/ /* end of group MSP432P401R_CMSIS */\r
+\r
+/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */\r
+#ifdef __TI_ARM__\r
+/* disable the TI ULP advisor check for the core header file definitions */\r
#pragma diag_push\r
#pragma CHECK_ULP("none")\r
#include "core_cm4.h"\r
#include "core_cm4.h"\r
#endif\r
\r
-//*****************************************************************************\r
-// Definition of standard bits\r
-//*****************************************************************************\r
-#define BIT0 (0x0001u)\r
-#define BIT1 (0x0002u)\r
-#define BIT2 (0x0004u)\r
-#define BIT3 (0x0008u)\r
-#define BIT4 (0x0010u)\r
-#define BIT5 (0x0020u)\r
-#define BIT6 (0x0040u)\r
-#define BIT7 (0x0080u)\r
-#define BIT8 (0x0100u)\r
-#define BIT9 (0x0200u)\r
-#define BITA (0x0400u)\r
-#define BITB (0x0800u)\r
-#define BITC (0x1000u)\r
-#define BITD (0x2000u)\r
-#define BITE (0x4000u)\r
-#define BITF (0x8000u)\r
-#define BIT(x) (1 << (x))\r
-\r
-//*****************************************************************************\r
-// Definitions for 8/16/32-bit wide memory access\r
-//*****************************************************************************\r
-#define HWREG8(x) (*((volatile uint8_t *)(x)))\r
-#define HWREG16(x) (*((volatile uint16_t *)(x)))\r
-#define HWREG32(x) (*((volatile uint32_t *)(x)))\r
-#define HWREG(x) (HWREG16(x))\r
-#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))\r
-#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))\r
-#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))\r
-#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))\r
-\r
-//*****************************************************************************\r
-// Definitions for 8/16/32-bit wide bit band access\r
-//*****************************************************************************\r
-#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))\r
-#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))\r
-#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))\r
-#define BITBAND_SRAM(x, b) (*((volatile uint8_t *) (0x22000000 + (((uint32_t)(uint32_t *)&x) - 0x20000000)*32 + b*4)))\r
-#define BITBAND_PERI(x, b) (*((volatile uint8_t *) (0x42000000 + (((uint32_t)(uint32_t *)&x) - 0x40000000)*32 + b*4)))\r
-\r
-//*****************************************************************************\r
-// Device memory map\r
-//*****************************************************************************\r
-#define __MAIN_MEMORY_START__ (0x00000000) /* Main Flash memory start address */\r
-#define __MAIN_MEMORY_END__ (0x0003FFFF) /* Main Flash memory end address */\r
-#define __BSL_MEMORY_START__ (0x00202000) /* BSL memory start address */\r
-#define __BSL_MEMORY_END__ (0x00203FFF) /* BSL memory end address */\r
-#define __SRAM_START__ (0x20000000) /* SRAM memory start address */\r
-#define __SRAM_END__ (0x2000FFFF) /* SRAM memory end address */\r
-\r
-//*****************************************************************************\r
-// Peripheral memory map\r
-//*****************************************************************************\r
-#define __MCU_HAS_ADC14__ /* Module is available */\r
-#define __MCU_HAS_AES256__ /* Module is available */\r
-#define __MCU_HAS_CAPTIO0__ /* Module is available */\r
-#define __MCU_HAS_CAPTIO1__ /* Module is available */\r
-#define __MCU_HAS_COMP_E0__ /* Module is available */\r
-#define __MCU_HAS_COMP_E1__ /* Module is available */\r
-#define __MCU_HAS_CRC32__ /* Module is available */\r
-#define __MCU_HAS_CS__ /* Module is available */\r
-#define __MCU_HAS_DIO__ /* Module is available */\r
-#define __MCU_HAS_DMA__ /* Module is available */\r
-#define __MCU_HAS_EUSCI_A0__ /* Module is available */\r
-#define __MCU_HAS_EUSCI_A1__ /* Module is available */\r
-#define __MCU_HAS_EUSCI_A2__ /* Module is available */\r
-#define __MCU_HAS_EUSCI_A3__ /* Module is available */\r
-#define __MCU_HAS_EUSCI_B0__ /* Module is available */\r
-#define __MCU_HAS_EUSCI_B1__ /* Module is available */\r
-#define __MCU_HAS_EUSCI_B2__ /* Module is available */\r
-#define __MCU_HAS_EUSCI_B3__ /* Module is available */\r
-#define __MCU_HAS_FLCTL__ /* Module is available */\r
-#define __MCU_HAS_FPB__ /* Module is available */\r
-#define __MCU_HAS_PCM__ /* Module is available */\r
-#define __MCU_HAS_PMAP__ /* Module is available */\r
-#define __MCU_HAS_PSS__ /* Module is available */\r
-#define __MCU_HAS_REF_A__ /* Module is available */\r
-#define __MCU_HAS_RSTCTL__ /* Module is available */\r
-#define __MCU_HAS_RTC_C__ /* Module is available */\r
-#define __MCU_HAS_SYSCTL__ /* Module is available */\r
-#define __MCU_HAS_TIMER32__ /* Module is available */\r
-#define __MCU_HAS_TIMER_A0__ /* Module is available */\r
-#define __MCU_HAS_TIMER_A1__ /* Module is available */\r
-#define __MCU_HAS_TIMER_A2__ /* Module is available */\r
-#define __MCU_HAS_TIMER_A3__ /* Module is available */\r
-#define __MCU_HAS_TLV__ /* Module is available */\r
-#define __MCU_HAS_WDT_A__ /* Module is available */\r
-\r
-#define ADC14_BASE (0x40012000) /* Base address of module registers */\r
-#define ADC14_MODULE (0x40012000) /* Base address of module registers */\r
-#define AES256_BASE (0x40003C00) /* Base address of module registers */\r
-#define AES256_MODULE (0x40003C00) /* Base address of module registers */\r
-#define CAPTIO0_BASE (0x40005400) /* Base address of module registers */\r
-#define CAPTIO0_MODULE (0x40005400) /* Base address of module registers */\r
-#define CAPTIO1_BASE (0x40005800) /* Base address of module registers */\r
-#define CAPTIO1_MODULE (0x40005800) /* Base address of module registers */\r
-#define COMP_E0_BASE (0x40003400) /* Base address of module registers */\r
-#define COMP_E0_MODULE (0x40003400) /* Base address of module registers */\r
-#define COMP_E1_BASE (0x40003800) /* Base address of module registers */\r
-#define COMP_E1_MODULE (0x40003800) /* Base address of module registers */\r
-#define CRC32_BASE (0x40004000) /* Base address of module registers */\r
-#define CRC32_MODULE (0x40004000) /* Base address of module registers */\r
-#define CS_BASE (0x40010400) /* Base address of module registers */\r
-#define CS_MODULE (0x40010400) /* Base address of module registers */\r
-#define DIO_BASE (0x40004C00) /* Base address of module registers */\r
-#define DIO_MODULE (0x40004C00) /* Base address of module registers */\r
-#define DMA_BASE (0x4000E000) /* Base address of module registers */\r
-#define DMA_MODULE (0x4000E000) /* Base address of module registers */\r
-#define EUSCI_A0_BASE (0x40001000) /* Base address of module registers */\r
-#define EUSCI_A0_MODULE (0x40001000) /* Base address of module registers */\r
-#define EUSCI_A1_BASE (0x40001400) /* Base address of module registers */\r
-#define EUSCI_A1_MODULE (0x40001400) /* Base address of module registers */\r
-#define EUSCI_A2_BASE (0x40001800) /* Base address of module registers */\r
-#define EUSCI_A2_MODULE (0x40001800) /* Base address of module registers */\r
-#define EUSCI_A3_BASE (0x40001C00) /* Base address of module registers */\r
-#define EUSCI_A3_MODULE (0x40001C00) /* Base address of module registers */\r
-#define EUSCI_B0_BASE (0x40002000) /* Base address of module registers */\r
-#define EUSCI_B0_MODULE (0x40002000) /* Base address of module registers */\r
-#define EUSCI_B1_BASE (0x40002400) /* Base address of module registers */\r
-#define EUSCI_B1_MODULE (0x40002400) /* Base address of module registers */\r
-#define EUSCI_B2_BASE (0x40002800) /* Base address of module registers */\r
-#define EUSCI_B2_MODULE (0x40002800) /* Base address of module registers */\r
-#define EUSCI_B3_BASE (0x40002C00) /* Base address of module registers */\r
-#define EUSCI_B3_MODULE (0x40002C00) /* Base address of module registers */\r
-#define FLCTL_BASE (0x40011000) /* Base address of module registers */\r
-#define FLCTL_MODULE (0x40011000) /* Base address of module registers */\r
-#define FPB_BASE (0xE0002000) /* Base address of module registers */\r
-#define FPB_MODULE (0xE0002000) /* Base address of module registers */\r
-#define PCM_BASE (0x40010000) /* Base address of module registers */\r
-#define PCM_MODULE (0x40010000) /* Base address of module registers */\r
-#define PMAP_BASE (0x40005000) /* Base address of module registers */\r
-#define PMAP_MODULE (0x40005000) /* Base address of module registers */\r
-#define PSS_BASE (0x40010800) /* Base address of module registers */\r
-#define PSS_MODULE (0x40010800) /* Base address of module registers */\r
-#define REF_A_BASE (0x40003000) /* Base address of module registers */\r
-#define REF_A_MODULE (0x40003000) /* Base address of module registers */\r
-#define RSTCTL_BASE (0xE0042000) /* Base address of module registers */\r
-#define RSTCTL_MODULE (0xE0042000) /* Base address of module registers */\r
-#define RTC_C_BASE (0x40004400) /* Base address of module registers */\r
-#define RTC_C_MODULE (0x40004400) /* Base address of module registers */\r
-#define SYSCTL_BASE (0xE0043000) /* Base address of module registers */\r
-#define SYSCTL_MODULE (0xE0043000) /* Base address of module registers */\r
-#define TIMER32_BASE (0x4000C000) /* Base address of module registers */\r
-#define TIMER32_MODULE (0x4000C000) /* Base address of module registers */\r
-#define TIMER_A0_BASE (0x40000000) /* Base address of module registers */\r
-#define TIMER_A0_MODULE (0x40000000) /* Base address of module registers */\r
-#define TIMER_A1_BASE (0x40000400) /* Base address of module registers */\r
-#define TIMER_A1_MODULE (0x40000400) /* Base address of module registers */\r
-#define TIMER_A2_BASE (0x40000800) /* Base address of module registers */\r
-#define TIMER_A2_MODULE (0x40000800) /* Base address of module registers */\r
-#define TIMER_A3_BASE (0x40000C00) /* Base address of module registers */\r
-#define TIMER_A3_MODULE (0x40000C00) /* Base address of module registers */\r
-#define TLV_BASE (0x00201000) /* Base address of module registers */\r
-#define TLV_MODULE (0x00201000) /* Base address of module registers */\r
-#define WDT_A_BASE (0x40004800) /* Base address of module registers */\r
-#define WDT_A_MODULE (0x40004800) /* Base address of module registers */\r
-\r
-#define ADC14 ((ADC14_Type *) ADC14_BASE) \r
-#define AES256 ((AES256_Type *) AES256_BASE) \r
-#define CAPTIO0 ((CAPTIO0_Type *) CAPTIO0_BASE)\r
-#define CAPTIO1 ((CAPTIO1_Type *) CAPTIO1_BASE)\r
-#define COMP_E0 ((COMP_E0_Type *) COMP_E0_BASE)\r
-#define COMP_E1 ((COMP_E1_Type *) COMP_E1_BASE)\r
-#define CRC32 ((CRC32_Type *) CRC32_BASE) \r
-#define CS ((CS_Type *) CS_BASE) \r
-#define DIO ((DIO_Type *) DIO_BASE) \r
-#define DMA ((DMA_Type *) DMA_BASE) \r
-#define EUSCI_A0 ((EUSCI_A0_Type *) EUSCI_A0_BASE)\r
-#define EUSCI_A1 ((EUSCI_A1_Type *) EUSCI_A1_BASE)\r
-#define EUSCI_A2 ((EUSCI_A2_Type *) EUSCI_A2_BASE)\r
-#define EUSCI_A3 ((EUSCI_A3_Type *) EUSCI_A3_BASE)\r
-#define EUSCI_B0 ((EUSCI_B0_Type *) EUSCI_B0_BASE)\r
-#define EUSCI_B1 ((EUSCI_B1_Type *) EUSCI_B1_BASE)\r
-#define EUSCI_B2 ((EUSCI_B2_Type *) EUSCI_B2_BASE)\r
-#define EUSCI_B3 ((EUSCI_B3_Type *) EUSCI_B3_BASE)\r
-#define FLCTL ((FLCTL_Type *) FLCTL_BASE) \r
-#define FPB ((FPB_Type *) FPB_BASE) \r
-#define PCM ((PCM_Type *) PCM_BASE) \r
-#define PMAP ((PMAP_Type *) PMAP_BASE) \r
-#define PSS ((PSS_Type *) PSS_BASE) \r
-#define REF_A ((REF_A_Type *) REF_A_BASE) \r
-#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) \r
-#define RTC_C ((RTC_C_Type *) RTC_C_BASE) \r
-#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE) \r
-#define TIMER32 ((TIMER32_Type *) TIMER32_BASE)\r
-#define TIMER_A0 ((TIMER_A0_Type *) TIMER_A0_BASE)\r
-#define TIMER_A1 ((TIMER_A1_Type *) TIMER_A1_BASE)\r
-#define TIMER_A2 ((TIMER_A2_Type *) TIMER_A2_BASE)\r
-#define TIMER_A3 ((TIMER_A3_Type *) TIMER_A3_BASE)\r
-#define TLV ((TLV_Type *) TLV_BASE) \r
-#define WDT_A ((WDT_A_Type *) WDT_A_BASE) \r
-\r
-\r
-//*****************************************************************************\r
-// MSP-format peripheral registers\r
-//*****************************************************************************\r
-\r
-//*****************************************************************************\r
-// ADC14 Registers\r
-//*****************************************************************************\r
-#define ADC14CTL0 (HWREG32(0x40012000)) /* Control 0 Register */\r
-#define ADC14CTL1 (HWREG32(0x40012004)) /* Control 1 Register */\r
-#define ADC14LO0 (HWREG32(0x40012008)) /* Window Comparator Low Threshold 0 Register */\r
-#define ADC14HI0 (HWREG32(0x4001200C)) /* Window Comparator High Threshold 0 Register */\r
-#define ADC14LO1 (HWREG32(0x40012010)) /* Window Comparator Low Threshold 1 Register */\r
-#define ADC14HI1 (HWREG32(0x40012014)) /* Window Comparator High Threshold 1 Register */\r
-#define ADC14MCTL0 (HWREG32(0x40012018)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL1 (HWREG32(0x4001201C)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL2 (HWREG32(0x40012020)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL3 (HWREG32(0x40012024)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL4 (HWREG32(0x40012028)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL5 (HWREG32(0x4001202C)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL6 (HWREG32(0x40012030)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL7 (HWREG32(0x40012034)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL8 (HWREG32(0x40012038)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL9 (HWREG32(0x4001203C)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL10 (HWREG32(0x40012040)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL11 (HWREG32(0x40012044)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL12 (HWREG32(0x40012048)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL13 (HWREG32(0x4001204C)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL14 (HWREG32(0x40012050)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL15 (HWREG32(0x40012054)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL16 (HWREG32(0x40012058)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL17 (HWREG32(0x4001205C)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL18 (HWREG32(0x40012060)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL19 (HWREG32(0x40012064)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL20 (HWREG32(0x40012068)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL21 (HWREG32(0x4001206C)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL22 (HWREG32(0x40012070)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL23 (HWREG32(0x40012074)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL24 (HWREG32(0x40012078)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL25 (HWREG32(0x4001207C)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL26 (HWREG32(0x40012080)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL27 (HWREG32(0x40012084)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL28 (HWREG32(0x40012088)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL29 (HWREG32(0x4001208C)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL30 (HWREG32(0x40012090)) /* Conversion Memory Control Register */\r
-#define ADC14MCTL31 (HWREG32(0x40012094)) /* Conversion Memory Control Register */\r
-#define ADC14MEM0 (HWREG32(0x40012098)) /* Conversion Memory Register */\r
-#define ADC14MEM1 (HWREG32(0x4001209C)) /* Conversion Memory Register */\r
-#define ADC14MEM2 (HWREG32(0x400120A0)) /* Conversion Memory Register */\r
-#define ADC14MEM3 (HWREG32(0x400120A4)) /* Conversion Memory Register */\r
-#define ADC14MEM4 (HWREG32(0x400120A8)) /* Conversion Memory Register */\r
-#define ADC14MEM5 (HWREG32(0x400120AC)) /* Conversion Memory Register */\r
-#define ADC14MEM6 (HWREG32(0x400120B0)) /* Conversion Memory Register */\r
-#define ADC14MEM7 (HWREG32(0x400120B4)) /* Conversion Memory Register */\r
-#define ADC14MEM8 (HWREG32(0x400120B8)) /* Conversion Memory Register */\r
-#define ADC14MEM9 (HWREG32(0x400120BC)) /* Conversion Memory Register */\r
-#define ADC14MEM10 (HWREG32(0x400120C0)) /* Conversion Memory Register */\r
-#define ADC14MEM11 (HWREG32(0x400120C4)) /* Conversion Memory Register */\r
-#define ADC14MEM12 (HWREG32(0x400120C8)) /* Conversion Memory Register */\r
-#define ADC14MEM13 (HWREG32(0x400120CC)) /* Conversion Memory Register */\r
-#define ADC14MEM14 (HWREG32(0x400120D0)) /* Conversion Memory Register */\r
-#define ADC14MEM15 (HWREG32(0x400120D4)) /* Conversion Memory Register */\r
-#define ADC14MEM16 (HWREG32(0x400120D8)) /* Conversion Memory Register */\r
-#define ADC14MEM17 (HWREG32(0x400120DC)) /* Conversion Memory Register */\r
-#define ADC14MEM18 (HWREG32(0x400120E0)) /* Conversion Memory Register */\r
-#define ADC14MEM19 (HWREG32(0x400120E4)) /* Conversion Memory Register */\r
-#define ADC14MEM20 (HWREG32(0x400120E8)) /* Conversion Memory Register */\r
-#define ADC14MEM21 (HWREG32(0x400120EC)) /* Conversion Memory Register */\r
-#define ADC14MEM22 (HWREG32(0x400120F0)) /* Conversion Memory Register */\r
-#define ADC14MEM23 (HWREG32(0x400120F4)) /* Conversion Memory Register */\r
-#define ADC14MEM24 (HWREG32(0x400120F8)) /* Conversion Memory Register */\r
-#define ADC14MEM25 (HWREG32(0x400120FC)) /* Conversion Memory Register */\r
-#define ADC14MEM26 (HWREG32(0x40012100)) /* Conversion Memory Register */\r
-#define ADC14MEM27 (HWREG32(0x40012104)) /* Conversion Memory Register */\r
-#define ADC14MEM28 (HWREG32(0x40012108)) /* Conversion Memory Register */\r
-#define ADC14MEM29 (HWREG32(0x4001210C)) /* Conversion Memory Register */\r
-#define ADC14MEM30 (HWREG32(0x40012110)) /* Conversion Memory Register */\r
-#define ADC14MEM31 (HWREG32(0x40012114)) /* Conversion Memory Register */\r
-#define ADC14IER0 (HWREG32(0x4001213C)) /* Interrupt Enable 0 Register */\r
-#define ADC14IER1 (HWREG32(0x40012140)) /* Interrupt Enable 1 Register */\r
-#define ADC14IFGR0 (HWREG32(0x40012144)) /* Interrupt Flag 0 Register */\r
-#define ADC14IFGR1 (HWREG32(0x40012148)) /* Interrupt Flag 1 Register */\r
-#define ADC14CLRIFGR0 (HWREG32(0x4001214C)) /* Clear Interrupt Flag 0 Register */\r
-#define ADC14CLRIFGR1 (HWREG32(0x40012150)) /* Clear Interrupt Flag 1 Register */\r
-#define ADC14IV (HWREG32(0x40012154)) /* Interrupt Vector Register */\r
-\r
-/* Register offsets from ADC14_BASE address */\r
-#define OFS_ADC14CTL0 (0x00000000) /* Control 0 Register */\r
-#define OFS_ADC14CTL1 (0x00000004) /* Control 1 Register */\r
-#define OFS_ADC14LO0 (0x00000008) /* Window Comparator Low Threshold 0 Register */\r
-#define OFS_ADC14HI0 (0x0000000c) /* Window Comparator High Threshold 0 Register */\r
-#define OFS_ADC14LO1 (0x00000010) /* Window Comparator Low Threshold 1 Register */\r
-#define OFS_ADC14HI1 (0x00000014) /* Window Comparator High Threshold 1 Register */\r
-#define OFS_ADC14MCTL0 (0x00000018) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL1 (0x0000001C) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL2 (0x00000020) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL3 (0x00000024) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL4 (0x00000028) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL5 (0x0000002C) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL6 (0x00000030) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL7 (0x00000034) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL8 (0x00000038) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL9 (0x0000003C) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL10 (0x00000040) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL11 (0x00000044) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL12 (0x00000048) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL13 (0x0000004C) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL14 (0x00000050) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL15 (0x00000054) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL16 (0x00000058) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL17 (0x0000005C) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL18 (0x00000060) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL19 (0x00000064) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL20 (0x00000068) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL21 (0x0000006C) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL22 (0x00000070) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL23 (0x00000074) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL24 (0x00000078) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL25 (0x0000007C) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL26 (0x00000080) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL27 (0x00000084) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL28 (0x00000088) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL29 (0x0000008C) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL30 (0x00000090) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MCTL31 (0x00000094) /* Conversion Memory Control Register */\r
-#define OFS_ADC14MEM0 (0x00000098) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM1 (0x0000009C) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM2 (0x000000A0) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM3 (0x000000A4) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM4 (0x000000A8) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM5 (0x000000AC) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM6 (0x000000B0) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM7 (0x000000B4) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM8 (0x000000B8) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM9 (0x000000BC) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM10 (0x000000C0) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM11 (0x000000C4) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM12 (0x000000C8) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM13 (0x000000CC) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM14 (0x000000D0) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM15 (0x000000D4) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM16 (0x000000D8) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM17 (0x000000DC) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM18 (0x000000E0) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM19 (0x000000E4) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM20 (0x000000E8) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM21 (0x000000EC) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM22 (0x000000F0) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM23 (0x000000F4) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM24 (0x000000F8) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM25 (0x000000FC) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM26 (0x00000100) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM27 (0x00000104) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM28 (0x00000108) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM29 (0x0000010C) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM30 (0x00000110) /* Conversion Memory Register */\r
-#define OFS_ADC14MEM31 (0x00000114) /* Conversion Memory Register */\r
-#define OFS_ADC14IER0 (0x0000013c) /* Interrupt Enable 0 Register */\r
-#define OFS_ADC14IER1 (0x00000140) /* Interrupt Enable 1 Register */\r
-#define OFS_ADC14IFGR0 (0x00000144) /* Interrupt Flag 0 Register */\r
-#define OFS_ADC14IFGR1 (0x00000148) /* Interrupt Flag 1 Register */\r
-#define OFS_ADC14CLRIFGR0 (0x0000014c) /* Clear Interrupt Flag 0 Register */\r
-#define OFS_ADC14CLRIFGR1 (0x00000150) /* Clear Interrupt Flag 1 Register */\r
-#define OFS_ADC14IV (0x00000154) /* Interrupt Vector Register */\r
-\r
-\r
-//*****************************************************************************\r
-// AES256 Registers\r
-//*****************************************************************************\r
-#define AESACTL0 (HWREG16(0x40003C00)) /* AES Accelerator Control Register 0 */\r
-#define AESACTL1 (HWREG16(0x40003C02)) /* AES Accelerator Control Register 1 */\r
-#define AESASTAT (HWREG16(0x40003C04)) /* AES Accelerator Status Register */\r
-#define AESAKEY (HWREG16(0x40003C06)) /* AES Accelerator Key Register */\r
-#define AESADIN (HWREG16(0x40003C08)) /* AES Accelerator Data In Register */\r
-#define AESADOUT (HWREG16(0x40003C0A)) /* AES Accelerator Data Out Register */\r
-#define AESAXDIN (HWREG16(0x40003C0C)) /* AES Accelerator XORed Data In Register */\r
-#define AESAXIN (HWREG16(0x40003C0E)) /* AES Accelerator XORed Data In Register */\r
-\r
-/* Register offsets from AES256_BASE address */\r
-#define OFS_AESACTL0 (0x0000) /* AES Accelerator Control Register 0 */\r
-#define OFS_AESACTL1 (0x0002) /* AES Accelerator Control Register 1 */\r
-#define OFS_AESASTAT (0x0004) /* AES Accelerator Status Register */\r
-#define OFS_AESAKEY (0x0006) /* AES Accelerator Key Register */\r
-#define OFS_AESADIN (0x0008) /* AES Accelerator Data In Register */\r
-#define OFS_AESADOUT (0x000a) /* AES Accelerator Data Out Register */\r
-#define OFS_AESAXDIN (0x000c) /* AES Accelerator XORed Data In Register */\r
-#define OFS_AESAXIN (0x000e) /* AES Accelerator XORed Data In Register */\r
-\r
-\r
-//*****************************************************************************\r
-// CAPTIO0 Registers\r
-//*****************************************************************************\r
-#define CAPTIO0CTL (HWREG16(0x4000540E)) /* Capacitive Touch IO x Control Register */\r
-\r
-/* Register offsets from CAPTIO0_BASE address */\r
-#define OFS_CAPTIO0CTL (0x000e) /* Capacitive Touch IO x Control Register */\r
-\r
-#define CAPTIO0CTL_L (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */\r
-#define CAPTIO0CTL_H (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */\r
-\r
-//*****************************************************************************\r
-// CAPTIO1 Registers\r
-//*****************************************************************************\r
-#define CAPTIO1CTL (HWREG16(0x4000580E)) /* Capacitive Touch IO x Control Register */\r
-\r
-/* Register offsets from CAPTIO1_BASE address */\r
-#define OFS_CAPTIO1CTL (0x000e) /* Capacitive Touch IO x Control Register */\r
-\r
-#define CAPTIO1CTL_L (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */\r
-#define CAPTIO1CTL_H (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */\r
-\r
-//*****************************************************************************\r
-// COMP_E0 Registers\r
-//*****************************************************************************\r
-#define CE0CTL0 (HWREG16(0x40003400)) /* Comparator Control Register 0 */\r
-#define CE0CTL1 (HWREG16(0x40003402)) /* Comparator Control Register 1 */\r
-#define CE0CTL2 (HWREG16(0x40003404)) /* Comparator Control Register 2 */\r
-#define CE0CTL3 (HWREG16(0x40003406)) /* Comparator Control Register 3 */\r
-#define CE0INT (HWREG16(0x4000340C)) /* Comparator Interrupt Control Register */\r
-#define CE0IV (HWREG16(0x4000340E)) /* Comparator Interrupt Vector Word Register */\r
-\r
-/* Register offsets from COMP_E0_BASE address */\r
-#define OFS_CE0CTL0 (0x0000) /* Comparator Control Register 0 */\r
-#define OFS_CE0CTL1 (0x0002) /* Comparator Control Register 1 */\r
-#define OFS_CE0CTL2 (0x0004) /* Comparator Control Register 2 */\r
-#define OFS_CE0CTL3 (0x0006) /* Comparator Control Register 3 */\r
-#define OFS_CE0INT (0x000c) /* Comparator Interrupt Control Register */\r
-#define OFS_CE0IV (0x000e) /* Comparator Interrupt Vector Word Register */\r
-\r
-\r
-//*****************************************************************************\r
-// COMP_E1 Registers\r
-//*****************************************************************************\r
-#define CE1CTL0 (HWREG16(0x40003800)) /* Comparator Control Register 0 */\r
-#define CE1CTL1 (HWREG16(0x40003802)) /* Comparator Control Register 1 */\r
-#define CE1CTL2 (HWREG16(0x40003804)) /* Comparator Control Register 2 */\r
-#define CE1CTL3 (HWREG16(0x40003806)) /* Comparator Control Register 3 */\r
-#define CE1INT (HWREG16(0x4000380C)) /* Comparator Interrupt Control Register */\r
-#define CE1IV (HWREG16(0x4000380E)) /* Comparator Interrupt Vector Word Register */\r
-\r
-/* Register offsets from COMP_E1_BASE address */\r
-#define OFS_CE1CTL0 (0x0000) /* Comparator Control Register 0 */\r
-#define OFS_CE1CTL1 (0x0002) /* Comparator Control Register 1 */\r
-#define OFS_CE1CTL2 (0x0004) /* Comparator Control Register 2 */\r
-#define OFS_CE1CTL3 (0x0006) /* Comparator Control Register 3 */\r
-#define OFS_CE1INT (0x000c) /* Comparator Interrupt Control Register */\r
-#define OFS_CE1IV (0x000e) /* Comparator Interrupt Vector Word Register */\r
-\r
-\r
-//*****************************************************************************\r
-// COREDEBUG Registers\r
-//*****************************************************************************\r
-#define COREDEBUG_DHCSR (HWREG32(0xE000EDF0)) /* Debug Halting Control and Status Register */\r
-#define COREDEBUG_DCRSR (HWREG32(0xE000EDF4)) /* Deubg Core Register Selector Register */\r
-#define COREDEBUG_DCRDR (HWREG32(0xE000EDF8)) /* Debug Core Register Data Register */\r
-#define COREDEBUG_DEMCR (HWREG32(0xE000EDFC)) /* Debug Exception and Monitor Control Register */\r
-\r
-/* Register offsets from COREDEBUG_BASE address */\r
-#define OFS_COREDEBUG_DHCSR (0x00000DF0) /* Debug Halting Control and Status Register */\r
-#define OFS_COREDEBUG_DCRSR (0x00000DF4) /* Deubg Core Register Selector Register */\r
-#define OFS_COREDEBUG_DCRDR (0x00000DF8) /* Debug Core Register Data Register */\r
-#define OFS_COREDEBUG_DEMCR (0x00000DFC) /* Debug Exception and Monitor Control Register */\r
-\r
-\r
-//*****************************************************************************\r
-// CRC32 Registers\r
-//*****************************************************************************\r
-#define CRC32DI (HWREG16(0x40004000)) /* Data Input for CRC32 Signature Computation */\r
-#define CRC32DIRB (HWREG16(0x40004004)) /* Data In Reverse for CRC32 Computation */\r
-#define CRC32INIRES_LO (HWREG16(0x40004008)) /* CRC32 Initialization and Result, lower 16 bits */\r
-#define CRC32INIRES_HI (HWREG16(0x4000400A)) /* CRC32 Initialization and Result, upper 16 bits */\r
-#define CRC32RESR_LO (HWREG16(0x4000400C)) /* CRC32 Result Reverse, lower 16 bits */\r
-#define CRC32RESR_HI (HWREG16(0x4000400E)) /* CRC32 Result Reverse, Upper 16 bits */\r
-#define CRC16DI (HWREG16(0x40004010)) /* Data Input for CRC16 computation */\r
-#define CRC16DIRB (HWREG16(0x40004014)) /* CRC16 Data In Reverse */\r
-#define CRC16INIRES (HWREG16(0x40004018)) /* CRC16 Initialization and Result register */\r
-#define CRC16RESR (HWREG16(0x4000401E)) /* CRC16 Result Reverse */\r
-\r
-/* Register offsets from CRC32_BASE address */\r
-#define OFS_CRC32DI (0x0000) /* Data Input for CRC32 Signature Computation */\r
-#define OFS_CRC32DIRB (0x0004) /* Data In Reverse for CRC32 Computation */\r
-#define OFS_CRC32INIRES_LO (0x0008) /* CRC32 Initialization and Result, lower 16 bits */\r
-#define OFS_CRC32INIRES_HI (0x000a) /* CRC32 Initialization and Result, upper 16 bits */\r
-#define OFS_CRC32RESR_LO (0x000c) /* CRC32 Result Reverse, lower 16 bits */\r
-#define OFS_CRC32RESR_HI (0x000e) /* CRC32 Result Reverse, Upper 16 bits */\r
-#define OFS_CRC16DI (0x0010) /* Data Input for CRC16 computation */\r
-#define OFS_CRC16DIRB (0x0014) /* CRC16 Data In Reverse */\r
-#define OFS_CRC16INIRES (0x0018) /* CRC16 Initialization and Result register */\r
-#define OFS_CRC16RESR (0x001e) /* CRC16 Result Reverse */\r
-\r
-\r
-//*****************************************************************************\r
-// CS Registers\r
-//*****************************************************************************\r
-#define CSKEY (HWREG32(0x40010400)) /* Key Register */\r
-#define CSCTL0 (HWREG32(0x40010404)) /* Control 0 Register */\r
-#define CSCTL1 (HWREG32(0x40010408)) /* Control 1 Register */\r
-#define CSCTL2 (HWREG32(0x4001040C)) /* Control 2 Register */\r
-#define CSCTL3 (HWREG32(0x40010410)) /* Control 3 Register */\r
-#define CSCTL4 (HWREG32(0x40010414)) /* Control 4 Register */\r
-#define CSCTL5 (HWREG32(0x40010418)) /* Control 5 Register */\r
-#define CSCTL6 (HWREG32(0x4001041C)) /* Control 6 Register */\r
-#define CSCTL7 (HWREG32(0x40010420)) /* Control 7 Register */\r
-#define CSCLKEN (HWREG32(0x40010430)) /* Clock Enable Register */\r
-#define CSSTAT (HWREG32(0x40010434)) /* Status Register */\r
-#define CSIE (HWREG32(0x40010440)) /* Interrupt Enable Register */\r
-#define CSIFG (HWREG32(0x40010448)) /* Interrupt Flag Register */\r
-#define CSCLRIFG (HWREG32(0x40010450)) /* Clear Interrupt Flag Register */\r
-#define CSSETIFG (HWREG32(0x40010458)) /* Set Interrupt Flag Register */\r
-#define CSDCOERCAL (HWREG32(0x40010460)) /* DCO external resistor cailbration register */\r
-\r
-/* Register offsets from CS_BASE address */\r
-#define OFS_CSKEY (0x00000000) /* Key Register */\r
-#define OFS_CSCTL0 (0x00000004) /* Control 0 Register */\r
-#define OFS_CSCTL1 (0x00000008) /* Control 1 Register */\r
-#define OFS_CSCTL2 (0x0000000c) /* Control 2 Register */\r
-#define OFS_CSCTL3 (0x00000010) /* Control 3 Register */\r
-#define OFS_CSCTL4 (0x00000014) /* Control 4 Register */\r
-#define OFS_CSCTL5 (0x00000018) /* Control 5 Register */\r
-#define OFS_CSCTL6 (0x0000001c) /* Control 6 Register */\r
-#define OFS_CSCTL7 (0x00000020) /* Control 7 Register */\r
-#define OFS_CSCLKEN (0x00000030) /* Clock Enable Register */\r
-#define OFS_CSSTAT (0x00000034) /* Status Register */\r
-#define OFS_CSIE (0x00000040) /* Interrupt Enable Register */\r
-#define OFS_CSIFG (0x00000048) /* Interrupt Flag Register */\r
-#define OFS_CSCLRIFG (0x00000050) /* Clear Interrupt Flag Register */\r
-#define OFS_CSSETIFG (0x00000058) /* Set Interrupt Flag Register */\r
-#define OFS_CSDCOERCAL (0x00000060) /* DCO external resistor cailbration register */\r
-\r
-\r
-//*****************************************************************************\r
-// DIO Registers\r
-//*****************************************************************************\r
-#define PAIN (HWREG16(0x40004C00)) /* Port A Input */\r
-#define PAOUT (HWREG16(0x40004C02)) /* Port A Output */\r
-#define PADIR (HWREG16(0x40004C04)) /* Port A Direction */\r
-#define PAREN (HWREG16(0x40004C06)) /* Port A Resistor Enable */\r
-#define PADS (HWREG16(0x40004C08)) /* Port A Drive Strength */\r
-#define PASEL0 (HWREG16(0x40004C0A)) /* Port A Select 0 */\r
-#define PASEL1 (HWREG16(0x40004C0C)) /* Port A Select 1 */\r
-#define P1IV (HWREG16(0x40004C0E)) /* Port 1 Interrupt Vector Register */\r
-#define PASELC (HWREG16(0x40004C16)) /* Port A Complement Select */\r
-#define PAIES (HWREG16(0x40004C18)) /* Port A Interrupt Edge Select */\r
-#define PAIE (HWREG16(0x40004C1A)) /* Port A Interrupt Enable */\r
-#define PAIFG (HWREG16(0x40004C1C)) /* Port A Interrupt Flag */\r
-#define P2IV (HWREG16(0x40004C1E)) /* Port 2 Interrupt Vector Register */\r
-#define PBIN (HWREG16(0x40004C20)) /* Port B Input */\r
-#define PBOUT (HWREG16(0x40004C22)) /* Port B Output */\r
-#define PBDIR (HWREG16(0x40004C24)) /* Port B Direction */\r
-#define PBREN (HWREG16(0x40004C26)) /* Port B Resistor Enable */\r
-#define PBDS (HWREG16(0x40004C28)) /* Port B Drive Strength */\r
-#define PBSEL0 (HWREG16(0x40004C2A)) /* Port B Select 0 */\r
-#define PBSEL1 (HWREG16(0x40004C2C)) /* Port B Select 1 */\r
-#define P3IV (HWREG16(0x40004C2E)) /* Port 3 Interrupt Vector Register */\r
-#define PBSELC (HWREG16(0x40004C36)) /* Port B Complement Select */\r
-#define PBIES (HWREG16(0x40004C38)) /* Port B Interrupt Edge Select */\r
-#define PBIE (HWREG16(0x40004C3A)) /* Port B Interrupt Enable */\r
-#define PBIFG (HWREG16(0x40004C3C)) /* Port B Interrupt Flag */\r
-#define P4IV (HWREG16(0x40004C3E)) /* Port 4 Interrupt Vector Register */\r
-#define PCIN (HWREG16(0x40004C40)) /* Port C Input */\r
-#define PCOUT (HWREG16(0x40004C42)) /* Port C Output */\r
-#define PCDIR (HWREG16(0x40004C44)) /* Port C Direction */\r
-#define PCREN (HWREG16(0x40004C46)) /* Port C Resistor Enable */\r
-#define PCDS (HWREG16(0x40004C48)) /* Port C Drive Strength */\r
-#define PCSEL0 (HWREG16(0x40004C4A)) /* Port C Select 0 */\r
-#define PCSEL1 (HWREG16(0x40004C4C)) /* Port C Select 1 */\r
-#define P5IV (HWREG16(0x40004C4E)) /* Port 5 Interrupt Vector Register */\r
-#define PCSELC (HWREG16(0x40004C56)) /* Port C Complement Select */\r
-#define PCIES (HWREG16(0x40004C58)) /* Port C Interrupt Edge Select */\r
-#define PCIE (HWREG16(0x40004C5A)) /* Port C Interrupt Enable */\r
-#define PCIFG (HWREG16(0x40004C5C)) /* Port C Interrupt Flag */\r
-#define P6IV (HWREG16(0x40004C5E)) /* Port 6 Interrupt Vector Register */\r
-#define PDIN (HWREG16(0x40004C60)) /* Port D Input */\r
-#define PDOUT (HWREG16(0x40004C62)) /* Port D Output */\r
-#define PDDIR (HWREG16(0x40004C64)) /* Port D Direction */\r
-#define PDREN (HWREG16(0x40004C66)) /* Port D Resistor Enable */\r
-#define PDDS (HWREG16(0x40004C68)) /* Port D Drive Strength */\r
-#define PDSEL0 (HWREG16(0x40004C6A)) /* Port D Select 0 */\r
-#define PDSEL1 (HWREG16(0x40004C6C)) /* Port D Select 1 */\r
-#define P7IV (HWREG16(0x40004C6E)) /* Port 7 Interrupt Vector Register */\r
-#define PDSELC (HWREG16(0x40004C76)) /* Port D Complement Select */\r
-#define PDIES (HWREG16(0x40004C78)) /* Port D Interrupt Edge Select */\r
-#define PDIE (HWREG16(0x40004C7A)) /* Port D Interrupt Enable */\r
-#define PDIFG (HWREG16(0x40004C7C)) /* Port D Interrupt Flag */\r
-#define P8IV (HWREG16(0x40004C7E)) /* Port 8 Interrupt Vector Register */\r
-#define PEIN (HWREG16(0x40004C80)) /* Port E Input */\r
-#define PEOUT (HWREG16(0x40004C82)) /* Port E Output */\r
-#define PEDIR (HWREG16(0x40004C84)) /* Port E Direction */\r
-#define PEREN (HWREG16(0x40004C86)) /* Port E Resistor Enable */\r
-#define PEDS (HWREG16(0x40004C88)) /* Port E Drive Strength */\r
-#define PESEL0 (HWREG16(0x40004C8A)) /* Port E Select 0 */\r
-#define PESEL1 (HWREG16(0x40004C8C)) /* Port E Select 1 */\r
-#define P9IV (HWREG16(0x40004C8E)) /* Port 9 Interrupt Vector Register */\r
-#define PESELC (HWREG16(0x40004C96)) /* Port E Complement Select */\r
-#define PEIES (HWREG16(0x40004C98)) /* Port E Interrupt Edge Select */\r
-#define PEIE (HWREG16(0x40004C9A)) /* Port E Interrupt Enable */\r
-#define PEIFG (HWREG16(0x40004C9C)) /* Port E Interrupt Flag */\r
-#define P10IV (HWREG16(0x40004C9E)) /* Port 10 Interrupt Vector Register */\r
-#define PJIN (HWREG16(0x40004D20)) /* Port J Input */\r
-#define PJOUT (HWREG16(0x40004D22)) /* Port J Output */\r
-#define PJDIR (HWREG16(0x40004D24)) /* Port J Direction */\r
-#define PJREN (HWREG16(0x40004D26)) /* Port J Resistor Enable */\r
-#define PJDS (HWREG16(0x40004D28)) /* Port J Drive Strength */\r
-#define PJSEL0 (HWREG16(0x40004D2A)) /* Port J Select 0 */\r
-#define PJSEL1 (HWREG16(0x40004D2C)) /* Port J Select 1 */\r
-#define PJSELC (HWREG16(0x40004D36)) /* Port J Complement Select */\r
-#define P1IN (HWREG8(0x40004C00)) /* Port 1 Input */\r
-#define P2IN (HWREG8(0x40004C01)) /* Port 2 Input */\r
-#define P2OUT (HWREG8(0x40004C03)) /* Port 2 Output */\r
-#define P1OUT (HWREG8(0x40004C02)) /* Port 1 Output */\r
-#define P1DIR (HWREG8(0x40004C04)) /* Port 1 Direction */\r
-#define P2DIR (HWREG8(0x40004C05)) /* Port 2 Direction */\r
-#define P1REN (HWREG8(0x40004C06)) /* Port 1 Resistor Enable */\r
-#define P2REN (HWREG8(0x40004C07)) /* Port 2 Resistor Enable */\r
-#define P1DS (HWREG8(0x40004C08)) /* Port 1 Drive Strength */\r
-#define P2DS (HWREG8(0x40004C09)) /* Port 2 Drive Strength */\r
-#define P1SEL0 (HWREG8(0x40004C0A)) /* Port 1 Select 0 */\r
-#define P2SEL0 (HWREG8(0x40004C0B)) /* Port 2 Select 0 */\r
-#define P1SEL1 (HWREG8(0x40004C0C)) /* Port 1 Select 1 */\r
-#define P2SEL1 (HWREG8(0x40004C0D)) /* Port 2 Select 1 */\r
-#define P1SELC (HWREG8(0x40004C16)) /* Port 1 Complement Select */\r
-#define P2SELC (HWREG8(0x40004C17)) /* Port 2 Complement Select */\r
-#define P1IES (HWREG8(0x40004C18)) /* Port 1 Interrupt Edge Select */\r
-#define P2IES (HWREG8(0x40004C19)) /* Port 2 Interrupt Edge Select */\r
-#define P1IE (HWREG8(0x40004C1A)) /* Port 1 Interrupt Enable */\r
-#define P2IE (HWREG8(0x40004C1B)) /* Port 2 Interrupt Enable */\r
-#define P1IFG (HWREG8(0x40004C1C)) /* Port 1 Interrupt Flag */\r
-#define P2IFG (HWREG8(0x40004C1D)) /* Port 2 Interrupt Flag */\r
-#define P3IN (HWREG8(0x40004C20)) /* Port 3 Input */\r
-#define P4IN (HWREG8(0x40004C21)) /* Port 4 Input */\r
-#define P3OUT (HWREG8(0x40004C22)) /* Port 3 Output */\r
-#define P4OUT (HWREG8(0x40004C23)) /* Port 4 Output */\r
-#define P3DIR (HWREG8(0x40004C24)) /* Port 3 Direction */\r
-#define P4DIR (HWREG8(0x40004C25)) /* Port 4 Direction */\r
-#define P3REN (HWREG8(0x40004C26)) /* Port 3 Resistor Enable */\r
-#define P4REN (HWREG8(0x40004C27)) /* Port 4 Resistor Enable */\r
-#define P3DS (HWREG8(0x40004C28)) /* Port 3 Drive Strength */\r
-#define P4DS (HWREG8(0x40004C29)) /* Port 4 Drive Strength */\r
-#define P4SEL0 (HWREG8(0x40004C2B)) /* Port 4 Select 0 */\r
-#define P3SEL0 (HWREG8(0x40004C2A)) /* Port 3 Select 0 */\r
-#define P3SEL1 (HWREG8(0x40004C2C)) /* Port 3 Select 1 */\r
-#define P4SEL1 (HWREG8(0x40004C2D)) /* Port 4 Select 1 */\r
-#define P3SELC (HWREG8(0x40004C36)) /* Port 3 Complement Select */\r
-#define P4SELC (HWREG8(0x40004C37)) /* Port 4 Complement Select */\r
-#define P3IES (HWREG8(0x40004C38)) /* Port 3 Interrupt Edge Select */\r
-#define P4IES (HWREG8(0x40004C39)) /* Port 4 Interrupt Edge Select */\r
-#define P3IE (HWREG8(0x40004C3A)) /* Port 3 Interrupt Enable */\r
-#define P4IE (HWREG8(0x40004C3B)) /* Port 4 Interrupt Enable */\r
-#define P3IFG (HWREG8(0x40004C3C)) /* Port 3 Interrupt Flag */\r
-#define P4IFG (HWREG8(0x40004C3D)) /* Port 4 Interrupt Flag */\r
-#define P5IN (HWREG8(0x40004C40)) /* Port 5 Input */\r
-#define P6IN (HWREG8(0x40004C41)) /* Port 6 Input */\r
-#define P5OUT (HWREG8(0x40004C42)) /* Port 5 Output */\r
-#define P6OUT (HWREG8(0x40004C43)) /* Port 6 Output */\r
-#define P5DIR (HWREG8(0x40004C44)) /* Port 5 Direction */\r
-#define P6DIR (HWREG8(0x40004C45)) /* Port 6 Direction */\r
-#define P5REN (HWREG8(0x40004C46)) /* Port 5 Resistor Enable */\r
-#define P6REN (HWREG8(0x40004C47)) /* Port 6 Resistor Enable */\r
-#define P5DS (HWREG8(0x40004C48)) /* Port 5 Drive Strength */\r
-#define P6DS (HWREG8(0x40004C49)) /* Port 6 Drive Strength */\r
-#define P5SEL0 (HWREG8(0x40004C4A)) /* Port 5 Select 0 */\r
-#define P6SEL0 (HWREG8(0x40004C4B)) /* Port 6 Select 0 */\r
-#define P5SEL1 (HWREG8(0x40004C4C)) /* Port 5 Select 1 */\r
-#define P6SEL1 (HWREG8(0x40004C4D)) /* Port 6 Select 1 */\r
-#define P5SELC (HWREG8(0x40004C56)) /* Port 5 Complement Select */\r
-#define P6SELC (HWREG8(0x40004C57)) /* Port 6 Complement Select */\r
-#define P5IES (HWREG8(0x40004C58)) /* Port 5 Interrupt Edge Select */\r
-#define P6IES (HWREG8(0x40004C59)) /* Port 6 Interrupt Edge Select */\r
-#define P5IE (HWREG8(0x40004C5A)) /* Port 5 Interrupt Enable */\r
-#define P6IE (HWREG8(0x40004C5B)) /* Port 6 Interrupt Enable */\r
-#define P5IFG (HWREG8(0x40004C5C)) /* Port 5 Interrupt Flag */\r
-#define P6IFG (HWREG8(0x40004C5D)) /* Port 6 Interrupt Flag */\r
-#define P7IN (HWREG8(0x40004C60)) /* Port 7 Input */\r
-#define P8IN (HWREG8(0x40004C61)) /* Port 8 Input */\r
-#define P7OUT (HWREG8(0x40004C62)) /* Port 7 Output */\r
-#define P8OUT (HWREG8(0x40004C63)) /* Port 8 Output */\r
-#define P7DIR (HWREG8(0x40004C64)) /* Port 7 Direction */\r
-#define P8DIR (HWREG8(0x40004C65)) /* Port 8 Direction */\r
-#define P7REN (HWREG8(0x40004C66)) /* Port 7 Resistor Enable */\r
-#define P8REN (HWREG8(0x40004C67)) /* Port 8 Resistor Enable */\r
-#define P7DS (HWREG8(0x40004C68)) /* Port 7 Drive Strength */\r
-#define P8DS (HWREG8(0x40004C69)) /* Port 8 Drive Strength */\r
-#define P7SEL0 (HWREG8(0x40004C6A)) /* Port 7 Select 0 */\r
-#define P8SEL0 (HWREG8(0x40004C6B)) /* Port 8 Select 0 */\r
-#define P7SEL1 (HWREG8(0x40004C6C)) /* Port 7 Select 1 */\r
-#define P8SEL1 (HWREG8(0x40004C6D)) /* Port 8 Select 1 */\r
-#define P7SELC (HWREG8(0x40004C76)) /* Port 7 Complement Select */\r
-#define P8SELC (HWREG8(0x40004C77)) /* Port 8 Complement Select */\r
-#define P7IES (HWREG8(0x40004C78)) /* Port 7 Interrupt Edge Select */\r
-#define P8IES (HWREG8(0x40004C79)) /* Port 8 Interrupt Edge Select */\r
-#define P7IE (HWREG8(0x40004C7A)) /* Port 7 Interrupt Enable */\r
-#define P8IE (HWREG8(0x40004C7B)) /* Port 8 Interrupt Enable */\r
-#define P7IFG (HWREG8(0x40004C7C)) /* Port 7 Interrupt Flag */\r
-#define P8IFG (HWREG8(0x40004C7D)) /* Port 8 Interrupt Flag */\r
-#define P9IN (HWREG8(0x40004C80)) /* Port 9 Input */\r
-#define P10IN (HWREG8(0x40004C81)) /* Port 10 Input */\r
-#define P9OUT (HWREG8(0x40004C82)) /* Port 9 Output */\r
-#define P10OUT (HWREG8(0x40004C83)) /* Port 10 Output */\r
-#define P9DIR (HWREG8(0x40004C84)) /* Port 9 Direction */\r
-#define P10DIR (HWREG8(0x40004C85)) /* Port 10 Direction */\r
-#define P9REN (HWREG8(0x40004C86)) /* Port 9 Resistor Enable */\r
-#define P10REN (HWREG8(0x40004C87)) /* Port 10 Resistor Enable */\r
-#define P9DS (HWREG8(0x40004C88)) /* Port 9 Drive Strength */\r
-#define P10DS (HWREG8(0x40004C89)) /* Port 10 Drive Strength */\r
-#define P9SEL0 (HWREG8(0x40004C8A)) /* Port 9 Select 0 */\r
-#define P10SEL0 (HWREG8(0x40004C8B)) /* Port 10 Select 0 */\r
-#define P9SEL1 (HWREG8(0x40004C8C)) /* Port 9 Select 1 */\r
-#define P10SEL1 (HWREG8(0x40004C8D)) /* Port 10 Select 1 */\r
-#define P9SELC (HWREG8(0x40004C96)) /* Port 9 Complement Select */\r
-#define P10SELC (HWREG8(0x40004C97)) /* Port 10 Complement Select */\r
-#define P9IES (HWREG8(0x40004C98)) /* Port 9 Interrupt Edge Select */\r
-#define P10IES (HWREG8(0x40004C99)) /* Port 10 Interrupt Edge Select */\r
-#define P9IE (HWREG8(0x40004C9A)) /* Port 9 Interrupt Enable */\r
-#define P10IE (HWREG8(0x40004C9B)) /* Port 10 Interrupt Enable */\r
-#define P9IFG (HWREG8(0x40004C9C)) /* Port 9 Interrupt Flag */\r
-#define P10IFG (HWREG8(0x40004C9D)) /* Port 10 Interrupt Flag */\r
-\r
-/* Register offsets from DIO_BASE address */\r
-#define OFS_PAIN (0x0000) /* Port A Input */\r
-#define OFS_PAOUT (0x0002) /* Port A Output */\r
-#define OFS_PADIR (0x0004) /* Port A Direction */\r
-#define OFS_PAREN (0x0006) /* Port A Resistor Enable */\r
-#define OFS_PADS (0x0008) /* Port A Drive Strength */\r
-#define OFS_PASEL0 (0x000a) /* Port A Select 0 */\r
-#define OFS_PASEL1 (0x000c) /* Port A Select 1 */\r
-#define OFS_P1IV (0x000e) /* Port 1 Interrupt Vector Register */\r
-#define OFS_PASELC (0x0016) /* Port A Complement Select */\r
-#define OFS_PAIES (0x0018) /* Port A Interrupt Edge Select */\r
-#define OFS_PAIE (0x001a) /* Port A Interrupt Enable */\r
-#define OFS_PAIFG (0x001c) /* Port A Interrupt Flag */\r
-#define OFS_P2IV (0x001e) /* Port 2 Interrupt Vector Register */\r
-#define OFS_PBIN (0x0020) /* Port B Input */\r
-#define OFS_PBOUT (0x0022) /* Port B Output */\r
-#define OFS_PBDIR (0x0024) /* Port B Direction */\r
-#define OFS_PBREN (0x0026) /* Port B Resistor Enable */\r
-#define OFS_PBDS (0x0028) /* Port B Drive Strength */\r
-#define OFS_PBSEL0 (0x002a) /* Port B Select 0 */\r
-#define OFS_PBSEL1 (0x002c) /* Port B Select 1 */\r
-#define OFS_P3IV (0x002e) /* Port 3 Interrupt Vector Register */\r
-#define OFS_PBSELC (0x0036) /* Port B Complement Select */\r
-#define OFS_PBIES (0x0038) /* Port B Interrupt Edge Select */\r
-#define OFS_PBIE (0x003a) /* Port B Interrupt Enable */\r
-#define OFS_PBIFG (0x003c) /* Port B Interrupt Flag */\r
-#define OFS_P4IV (0x003e) /* Port 4 Interrupt Vector Register */\r
-#define OFS_PCIN (0x0040) /* Port C Input */\r
-#define OFS_PCOUT (0x0042) /* Port C Output */\r
-#define OFS_PCDIR (0x0044) /* Port C Direction */\r
-#define OFS_PCREN (0x0046) /* Port C Resistor Enable */\r
-#define OFS_PCDS (0x0048) /* Port C Drive Strength */\r
-#define OFS_PCSEL0 (0x004a) /* Port C Select 0 */\r
-#define OFS_PCSEL1 (0x004c) /* Port C Select 1 */\r
-#define OFS_P5IV (0x004e) /* Port 5 Interrupt Vector Register */\r
-#define OFS_PCSELC (0x0056) /* Port C Complement Select */\r
-#define OFS_PCIES (0x0058) /* Port C Interrupt Edge Select */\r
-#define OFS_PCIE (0x005a) /* Port C Interrupt Enable */\r
-#define OFS_PCIFG (0x005c) /* Port C Interrupt Flag */\r
-#define OFS_P6IV (0x005e) /* Port 6 Interrupt Vector Register */\r
-#define OFS_PDIN (0x0060) /* Port D Input */\r
-#define OFS_PDOUT (0x0062) /* Port D Output */\r
-#define OFS_PDDIR (0x0064) /* Port D Direction */\r
-#define OFS_PDREN (0x0066) /* Port D Resistor Enable */\r
-#define OFS_PDDS (0x0068) /* Port D Drive Strength */\r
-#define OFS_PDSEL0 (0x006a) /* Port D Select 0 */\r
-#define OFS_PDSEL1 (0x006c) /* Port D Select 1 */\r
-#define OFS_P7IV (0x006e) /* Port 7 Interrupt Vector Register */\r
-#define OFS_PDSELC (0x0076) /* Port D Complement Select */\r
-#define OFS_PDIES (0x0078) /* Port D Interrupt Edge Select */\r
-#define OFS_PDIE (0x007a) /* Port D Interrupt Enable */\r
-#define OFS_PDIFG (0x007c) /* Port D Interrupt Flag */\r
-#define OFS_P8IV (0x007e) /* Port 8 Interrupt Vector Register */\r
-#define OFS_PEIN (0x0080) /* Port E Input */\r
-#define OFS_PEOUT (0x0082) /* Port E Output */\r
-#define OFS_PEDIR (0x0084) /* Port E Direction */\r
-#define OFS_PEREN (0x0086) /* Port E Resistor Enable */\r
-#define OFS_PEDS (0x0088) /* Port E Drive Strength */\r
-#define OFS_PESEL0 (0x008a) /* Port E Select 0 */\r
-#define OFS_PESEL1 (0x008c) /* Port E Select 1 */\r
-#define OFS_P9IV (0x008e) /* Port 9 Interrupt Vector Register */\r
-#define OFS_PESELC (0x0096) /* Port E Complement Select */\r
-#define OFS_PEIES (0x0098) /* Port E Interrupt Edge Select */\r
-#define OFS_PEIE (0x009a) /* Port E Interrupt Enable */\r
-#define OFS_PEIFG (0x009c) /* Port E Interrupt Flag */\r
-#define OFS_P10IV (0x009e) /* Port 10 Interrupt Vector Register */\r
-#define OFS_PJIN (0x0120) /* Port J Input */\r
-#define OFS_PJOUT (0x0122) /* Port J Output */\r
-#define OFS_PJDIR (0x0124) /* Port J Direction */\r
-#define OFS_PJREN (0x0126) /* Port J Resistor Enable */\r
-#define OFS_PJDS (0x0128) /* Port J Drive Strength */\r
-#define OFS_PJSEL0 (0x012a) /* Port J Select 0 */\r
-#define OFS_PJSEL1 (0x012c) /* Port J Select 1 */\r
-#define OFS_PJSELC (0x0136) /* Port J Complement Select */\r
-#define OFS_P1IN (0x0000) /* Port 1 Input */\r
-#define OFS_P2IN (0x0000) /* Port 2 Input */\r
-#define OFS_P2OUT (0x0002) /* Port 2 Output */\r
-#define OFS_P1OUT (0x0002) /* Port 1 Output */\r
-#define OFS_P1DIR (0x0004) /* Port 1 Direction */\r
-#define OFS_P2DIR (0x0004) /* Port 2 Direction */\r
-#define OFS_P1REN (0x0006) /* Port 1 Resistor Enable */\r
-#define OFS_P2REN (0x0006) /* Port 2 Resistor Enable */\r
-#define OFS_P1DS (0x0008) /* Port 1 Drive Strength */\r
-#define OFS_P2DS (0x0008) /* Port 2 Drive Strength */\r
-#define OFS_P1SEL0 (0x000a) /* Port 1 Select 0 */\r
-#define OFS_P2SEL0 (0x000a) /* Port 2 Select 0 */\r
-#define OFS_P1SEL1 (0x000c) /* Port 1 Select 1 */\r
-#define OFS_P2SEL1 (0x000c) /* Port 2 Select 1 */\r
-#define OFS_P1SELC (0x0016) /* Port 1 Complement Select */\r
-#define OFS_P2SELC (0x0016) /* Port 2 Complement Select */\r
-#define OFS_P1IES (0x0018) /* Port 1 Interrupt Edge Select */\r
-#define OFS_P2IES (0x0018) /* Port 2 Interrupt Edge Select */\r
-#define OFS_P1IE (0x001a) /* Port 1 Interrupt Enable */\r
-#define OFS_P2IE (0x001a) /* Port 2 Interrupt Enable */\r
-#define OFS_P1IFG (0x001c) /* Port 1 Interrupt Flag */\r
-#define OFS_P2IFG (0x001c) /* Port 2 Interrupt Flag */\r
-#define OFS_P3IN (0x0020) /* Port 3 Input */\r
-#define OFS_P4IN (0x0020) /* Port 4 Input */\r
-#define OFS_P3OUT (0x0022) /* Port 3 Output */\r
-#define OFS_P4OUT (0x0022) /* Port 4 Output */\r
-#define OFS_P3DIR (0x0024) /* Port 3 Direction */\r
-#define OFS_P4DIR (0x0024) /* Port 4 Direction */\r
-#define OFS_P3REN (0x0026) /* Port 3 Resistor Enable */\r
-#define OFS_P4REN (0x0026) /* Port 4 Resistor Enable */\r
-#define OFS_P3DS (0x0028) /* Port 3 Drive Strength */\r
-#define OFS_P4DS (0x0028) /* Port 4 Drive Strength */\r
-#define OFS_P4SEL0 (0x002a) /* Port 4 Select 0 */\r
-#define OFS_P3SEL0 (0x002a) /* Port 3 Select 0 */\r
-#define OFS_P3SEL1 (0x002c) /* Port 3 Select 1 */\r
-#define OFS_P4SEL1 (0x002c) /* Port 4 Select 1 */\r
-#define OFS_P3SELC (0x0036) /* Port 3 Complement Select */\r
-#define OFS_P4SELC (0x0036) /* Port 4 Complement Select */\r
-#define OFS_P3IES (0x0038) /* Port 3 Interrupt Edge Select */\r
-#define OFS_P4IES (0x0038) /* Port 4 Interrupt Edge Select */\r
-#define OFS_P3IE (0x003a) /* Port 3 Interrupt Enable */\r
-#define OFS_P4IE (0x003a) /* Port 4 Interrupt Enable */\r
-#define OFS_P3IFG (0x003c) /* Port 3 Interrupt Flag */\r
-#define OFS_P4IFG (0x003c) /* Port 4 Interrupt Flag */\r
-#define OFS_P5IN (0x0040) /* Port 5 Input */\r
-#define OFS_P6IN (0x0040) /* Port 6 Input */\r
-#define OFS_P5OUT (0x0042) /* Port 5 Output */\r
-#define OFS_P6OUT (0x0042) /* Port 6 Output */\r
-#define OFS_P5DIR (0x0044) /* Port 5 Direction */\r
-#define OFS_P6DIR (0x0044) /* Port 6 Direction */\r
-#define OFS_P5REN (0x0046) /* Port 5 Resistor Enable */\r
-#define OFS_P6REN (0x0046) /* Port 6 Resistor Enable */\r
-#define OFS_P5DS (0x0048) /* Port 5 Drive Strength */\r
-#define OFS_P6DS (0x0048) /* Port 6 Drive Strength */\r
-#define OFS_P5SEL0 (0x004a) /* Port 5 Select 0 */\r
-#define OFS_P6SEL0 (0x004a) /* Port 6 Select 0 */\r
-#define OFS_P5SEL1 (0x004c) /* Port 5 Select 1 */\r
-#define OFS_P6SEL1 (0x004c) /* Port 6 Select 1 */\r
-#define OFS_P5SELC (0x0056) /* Port 5 Complement Select */\r
-#define OFS_P6SELC (0x0056) /* Port 6 Complement Select */\r
-#define OFS_P5IES (0x0058) /* Port 5 Interrupt Edge Select */\r
-#define OFS_P6IES (0x0058) /* Port 6 Interrupt Edge Select */\r
-#define OFS_P5IE (0x005a) /* Port 5 Interrupt Enable */\r
-#define OFS_P6IE (0x005a) /* Port 6 Interrupt Enable */\r
-#define OFS_P5IFG (0x005c) /* Port 5 Interrupt Flag */\r
-#define OFS_P6IFG (0x005c) /* Port 6 Interrupt Flag */\r
-#define OFS_P7IN (0x0060) /* Port 7 Input */\r
-#define OFS_P8IN (0x0060) /* Port 8 Input */\r
-#define OFS_P7OUT (0x0062) /* Port 7 Output */\r
-#define OFS_P8OUT (0x0062) /* Port 8 Output */\r
-#define OFS_P7DIR (0x0064) /* Port 7 Direction */\r
-#define OFS_P8DIR (0x0064) /* Port 8 Direction */\r
-#define OFS_P7REN (0x0066) /* Port 7 Resistor Enable */\r
-#define OFS_P8REN (0x0066) /* Port 8 Resistor Enable */\r
-#define OFS_P7DS (0x0068) /* Port 7 Drive Strength */\r
-#define OFS_P8DS (0x0068) /* Port 8 Drive Strength */\r
-#define OFS_P7SEL0 (0x006a) /* Port 7 Select 0 */\r
-#define OFS_P8SEL0 (0x006a) /* Port 8 Select 0 */\r
-#define OFS_P7SEL1 (0x006c) /* Port 7 Select 1 */\r
-#define OFS_P8SEL1 (0x006c) /* Port 8 Select 1 */\r
-#define OFS_P7SELC (0x0076) /* Port 7 Complement Select */\r
-#define OFS_P8SELC (0x0076) /* Port 8 Complement Select */\r
-#define OFS_P7IES (0x0078) /* Port 7 Interrupt Edge Select */\r
-#define OFS_P8IES (0x0078) /* Port 8 Interrupt Edge Select */\r
-#define OFS_P7IE (0x007a) /* Port 7 Interrupt Enable */\r
-#define OFS_P8IE (0x007a) /* Port 8 Interrupt Enable */\r
-#define OFS_P7IFG (0x007c) /* Port 7 Interrupt Flag */\r
-#define OFS_P8IFG (0x007c) /* Port 8 Interrupt Flag */\r
-#define OFS_P9IN (0x0080) /* Port 9 Input */\r
-#define OFS_P10IN (0x0080) /* Port 10 Input */\r
-#define OFS_P9OUT (0x0082) /* Port 9 Output */\r
-#define OFS_P10OUT (0x0082) /* Port 10 Output */\r
-#define OFS_P9DIR (0x0084) /* Port 9 Direction */\r
-#define OFS_P10DIR (0x0084) /* Port 10 Direction */\r
-#define OFS_P9REN (0x0086) /* Port 9 Resistor Enable */\r
-#define OFS_P10REN (0x0086) /* Port 10 Resistor Enable */\r
-#define OFS_P9DS (0x0088) /* Port 9 Drive Strength */\r
-#define OFS_P10DS (0x0088) /* Port 10 Drive Strength */\r
-#define OFS_P9SEL0 (0x008a) /* Port 9 Select 0 */\r
-#define OFS_P10SEL0 (0x008a) /* Port 10 Select 0 */\r
-#define OFS_P9SEL1 (0x008c) /* Port 9 Select 1 */\r
-#define OFS_P10SEL1 (0x008c) /* Port 10 Select 1 */\r
-#define OFS_P9SELC (0x0096) /* Port 9 Complement Select */\r
-#define OFS_P10SELC (0x0096) /* Port 10 Complement Select */\r
-#define OFS_P9IES (0x0098) /* Port 9 Interrupt Edge Select */\r
-#define OFS_P10IES (0x0098) /* Port 10 Interrupt Edge Select */\r
-#define OFS_P9IE (0x009a) /* Port 9 Interrupt Enable */\r
-#define OFS_P10IE (0x009a) /* Port 10 Interrupt Enable */\r
-#define OFS_P9IFG (0x009c) /* Port 9 Interrupt Flag */\r
-#define OFS_P10IFG (0x009c) /* Port 10 Interrupt Flag */\r
-\r
-\r
-//*****************************************************************************\r
-// DMA Registers\r
-//*****************************************************************************\r
-#define DMA_DEVICE_CFG (HWREG32(0x4000E000)) /* Device Configuration Status */\r
-#define DMA_SW_CHTRIG (HWREG32(0x4000E004)) /* Software Channel Trigger Register */\r
-#define DMA_CH0_SRCCFG (HWREG32(0x4000E010)) /* Channel n Source Configuration Register */\r
-#define DMA_CH1_SRCCFG (HWREG32(0x4000E014)) /* Channel n Source Configuration Register */\r
-#define DMA_CH2_SRCCFG (HWREG32(0x4000E018)) /* Channel n Source Configuration Register */\r
-#define DMA_CH3_SRCCFG (HWREG32(0x4000E01C)) /* Channel n Source Configuration Register */\r
-#define DMA_CH4_SRCCFG (HWREG32(0x4000E020)) /* Channel n Source Configuration Register */\r
-#define DMA_CH5_SRCCFG (HWREG32(0x4000E024)) /* Channel n Source Configuration Register */\r
-#define DMA_CH6_SRCCFG (HWREG32(0x4000E028)) /* Channel n Source Configuration Register */\r
-#define DMA_CH7_SRCCFG (HWREG32(0x4000E02C)) /* Channel n Source Configuration Register */\r
-#define DMA_CH8_SRCCFG (HWREG32(0x4000E030)) /* Channel n Source Configuration Register */\r
-#define DMA_CH9_SRCCFG (HWREG32(0x4000E034)) /* Channel n Source Configuration Register */\r
-#define DMA_CH10_SRCCFG (HWREG32(0x4000E038)) /* Channel n Source Configuration Register */\r
-#define DMA_CH11_SRCCFG (HWREG32(0x4000E03C)) /* Channel n Source Configuration Register */\r
-#define DMA_CH12_SRCCFG (HWREG32(0x4000E040)) /* Channel n Source Configuration Register */\r
-#define DMA_CH13_SRCCFG (HWREG32(0x4000E044)) /* Channel n Source Configuration Register */\r
-#define DMA_CH14_SRCCFG (HWREG32(0x4000E048)) /* Channel n Source Configuration Register */\r
-#define DMA_CH15_SRCCFG (HWREG32(0x4000E04C)) /* Channel n Source Configuration Register */\r
-#define DMA_CH16_SRCCFG (HWREG32(0x4000E050)) /* Channel n Source Configuration Register */\r
-#define DMA_CH17_SRCCFG (HWREG32(0x4000E054)) /* Channel n Source Configuration Register */\r
-#define DMA_CH18_SRCCFG (HWREG32(0x4000E058)) /* Channel n Source Configuration Register */\r
-#define DMA_CH19_SRCCFG (HWREG32(0x4000E05C)) /* Channel n Source Configuration Register */\r
-#define DMA_CH20_SRCCFG (HWREG32(0x4000E060)) /* Channel n Source Configuration Register */\r
-#define DMA_CH21_SRCCFG (HWREG32(0x4000E064)) /* Channel n Source Configuration Register */\r
-#define DMA_CH22_SRCCFG (HWREG32(0x4000E068)) /* Channel n Source Configuration Register */\r
-#define DMA_CH23_SRCCFG (HWREG32(0x4000E06C)) /* Channel n Source Configuration Register */\r
-#define DMA_CH24_SRCCFG (HWREG32(0x4000E070)) /* Channel n Source Configuration Register */\r
-#define DMA_CH25_SRCCFG (HWREG32(0x4000E074)) /* Channel n Source Configuration Register */\r
-#define DMA_CH26_SRCCFG (HWREG32(0x4000E078)) /* Channel n Source Configuration Register */\r
-#define DMA_CH27_SRCCFG (HWREG32(0x4000E07C)) /* Channel n Source Configuration Register */\r
-#define DMA_CH28_SRCCFG (HWREG32(0x4000E080)) /* Channel n Source Configuration Register */\r
-#define DMA_CH29_SRCCFG (HWREG32(0x4000E084)) /* Channel n Source Configuration Register */\r
-#define DMA_CH30_SRCCFG (HWREG32(0x4000E088)) /* Channel n Source Configuration Register */\r
-#define DMA_CH31_SRCCFG (HWREG32(0x4000E08C)) /* Channel n Source Configuration Register */\r
-#define DMA_INT1_SRCCFG (HWREG32(0x4000E100)) /* Interrupt 1 Source Channel Configuration */\r
-#define DMA_INT2_SRCCFG (HWREG32(0x4000E104)) /* Interrupt 2 Source Channel Configuration Register */\r
-#define DMA_INT3_SRCCFG (HWREG32(0x4000E108)) /* Interrupt 3 Source Channel Configuration Register */\r
-#define DMA_INT0_SRCFLG (HWREG32(0x4000E110)) /* Interrupt 0 Source Channel Flag Register */\r
-#define DMA_INT0_CLRFLG (HWREG32(0x4000E114)) /* Interrupt 0 Source Channel Clear Flag Register */\r
-#define DMA_STAT (HWREG32(0x4000F000)) /* Status Register */\r
-#define DMA_CFG (HWREG32(0x4000F004)) /* Configuration Register */\r
-#define DMA_CTLBASE (HWREG32(0x4000F008)) /* Channel Control Data Base Pointer Register */\r
-#define DMA_ATLBASE (HWREG32(0x4000F00C)) /* Channel Alternate Control Data Base Pointer Register */\r
-#define DMA_WAITSTAT (HWREG32(0x4000F010)) /* Channel Wait on Request Status Register */\r
-#define DMA_SWREQ (HWREG32(0x4000F014)) /* Channel Software Request Register */\r
-#define DMA_USEBURSTSET (HWREG32(0x4000F018)) /* Channel Useburst Set Register */\r
-#define DMA_USEBURSTCLR (HWREG32(0x4000F01C)) /* Channel Useburst Clear Register */\r
-#define DMA_REQMASKSET (HWREG32(0x4000F020)) /* Channel Request Mask Set Register */\r
-#define DMA_REQMASKCLR (HWREG32(0x4000F024)) /* Channel Request Mask Clear Register */\r
-#define DMA_ENASET (HWREG32(0x4000F028)) /* Channel Enable Set Register */\r
-#define DMA_ENACLR (HWREG32(0x4000F02C)) /* Channel Enable Clear Register */\r
-#define DMA_ALTSET (HWREG32(0x4000F030)) /* Channel Primary-Alternate Set Register */\r
-#define DMA_ALTCLR (HWREG32(0x4000F034)) /* Channel Primary-Alternate Clear Register */\r
-#define DMA_PRIOSET (HWREG32(0x4000F038)) /* Channel Priority Set Register */\r
-#define DMA_PRIOCLR (HWREG32(0x4000F03C)) /* Channel Priority Clear Register */\r
-#define DMA_ERRCLR (HWREG32(0x4000F04C)) /* Bus Error Clear Register */\r
-\r
-/* Register offsets from DMA_BASE address */\r
-#define OFS_DMA_DEVICE_CFG (0x00000000) /* Device Configuration Status */\r
-#define OFS_DMA_SW_CHTRIG (0x00000004) /* Software Channel Trigger Register */\r
-#define OFS_DMA_CH0_SRCCFG (0x00000010) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH1_SRCCFG (0x00000014) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH2_SRCCFG (0x00000018) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH3_SRCCFG (0x0000001C) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH4_SRCCFG (0x00000020) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH5_SRCCFG (0x00000024) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH6_SRCCFG (0x00000028) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH7_SRCCFG (0x0000002C) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH8_SRCCFG (0x00000030) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH9_SRCCFG (0x00000034) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH10_SRCCFG (0x00000038) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH11_SRCCFG (0x0000003C) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH12_SRCCFG (0x00000040) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH13_SRCCFG (0x00000044) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH14_SRCCFG (0x00000048) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH15_SRCCFG (0x0000004C) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH16_SRCCFG (0x00000050) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH17_SRCCFG (0x00000054) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH18_SRCCFG (0x00000058) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH19_SRCCFG (0x0000005C) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH20_SRCCFG (0x00000060) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH21_SRCCFG (0x00000064) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH22_SRCCFG (0x00000068) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH23_SRCCFG (0x0000006C) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH24_SRCCFG (0x00000070) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH25_SRCCFG (0x00000074) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH26_SRCCFG (0x00000078) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH27_SRCCFG (0x0000007C) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH28_SRCCFG (0x00000080) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH29_SRCCFG (0x00000084) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH30_SRCCFG (0x00000088) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_CH31_SRCCFG (0x0000008C) /* Channel n Source Configuration Register */\r
-#define OFS_DMA_INT1_SRCCFG (0x00000100) /* Interrupt 1 Source Channel Configuration */\r
-#define OFS_DMA_INT2_SRCCFG (0x00000104) /* Interrupt 2 Source Channel Configuration Register */\r
-#define OFS_DMA_INT3_SRCCFG (0x00000108) /* Interrupt 3 Source Channel Configuration Register */\r
-#define OFS_DMA_INT0_SRCFLG (0x00000110) /* Interrupt 0 Source Channel Flag Register */\r
-#define OFS_DMA_INT0_CLRFLG (0x00000114) /* Interrupt 0 Source Channel Clear Flag Register */\r
-#define OFS_DMA_STAT (0x00001000) /* Status Register */\r
-#define OFS_DMA_CFG (0x00001004) /* Configuration Register */\r
-#define OFS_DMA_CTLBASE (0x00001008) /* Channel Control Data Base Pointer Register */\r
-#define OFS_DMA_ATLBASE (0x0000100c) /* Channel Alternate Control Data Base Pointer Register */\r
-#define OFS_DMA_WAITSTAT (0x00001010) /* Channel Wait on Request Status Register */\r
-#define OFS_DMA_SWREQ (0x00001014) /* Channel Software Request Register */\r
-#define OFS_DMA_USEBURSTSET (0x00001018) /* Channel Useburst Set Register */\r
-#define OFS_DMA_USEBURSTCLR (0x0000101c) /* Channel Useburst Clear Register */\r
-#define OFS_DMA_REQMASKSET (0x00001020) /* Channel Request Mask Set Register */\r
-#define OFS_DMA_REQMASKCLR (0x00001024) /* Channel Request Mask Clear Register */\r
-#define OFS_DMA_ENASET (0x00001028) /* Channel Enable Set Register */\r
-#define OFS_DMA_ENACLR (0x0000102c) /* Channel Enable Clear Register */\r
-#define OFS_DMA_ALTSET (0x00001030) /* Channel Primary-Alternate Set Register */\r
-#define OFS_DMA_ALTCLR (0x00001034) /* Channel Primary-Alternate Clear Register */\r
-#define OFS_DMA_PRIOSET (0x00001038) /* Channel Priority Set Register */\r
-#define OFS_DMA_PRIOCLR (0x0000103c) /* Channel Priority Clear Register */\r
-#define OFS_DMA_ERRCLR (0x0000104c) /* Bus Error Clear Register */\r
-\r
-\r
-//*****************************************************************************\r
-// DWT Registers\r
-//*****************************************************************************\r
-#define DWT_CTRL (HWREG32(0xE0001000)) /* DWT Control Register */\r
-#define DWT_CYCCNT (HWREG32(0xE0001004)) /* DWT Current PC Sampler Cycle Count Register */\r
-#define DWT_CPICNT (HWREG32(0xE0001008)) /* DWT CPI Count Register */\r
-#define DWT_EXCCNT (HWREG32(0xE000100C)) /* DWT Exception Overhead Count Register */\r
-#define DWT_SLEEPCNT (HWREG32(0xE0001010)) /* DWT Sleep Count Register */\r
-#define DWT_LSUCNT (HWREG32(0xE0001014)) /* DWT LSU Count Register */\r
-#define DWT_FOLDCNT (HWREG32(0xE0001018)) /* DWT Fold Count Register */\r
-#define DWT_PCSR (HWREG32(0xE000101C)) /* DWT Program Counter Sample Register */\r
-#define DWT_COMP0 (HWREG32(0xE0001020)) /* DWT Comparator Register 0 */\r
-#define DWT_MASK0 (HWREG32(0xE0001024)) /* DWT Mask Register 0 */\r
-#define DWT_FUNCTION0 (HWREG32(0xE0001028)) /* DWT Function Register 0 */\r
-#define DWT_COMP1 (HWREG32(0xE0001030)) /* DWT Comparator Register 1 */\r
-#define DWT_MASK1 (HWREG32(0xE0001034)) /* DWT Mask Register 1 */\r
-#define DWT_FUNCTION1 (HWREG32(0xE0001038)) /* DWT Function Register 1 */\r
-#define DWT_COMP2 (HWREG32(0xE0001040)) /* DWT Comparator Register 2 */\r
-#define DWT_MASK2 (HWREG32(0xE0001044)) /* DWT Mask Register 2 */\r
-#define DWT_FUNCTION2 (HWREG32(0xE0001048)) /* DWT Function Register 2 */\r
-#define DWT_COMP3 (HWREG32(0xE0001050)) /* DWT Comparator Register 3 */\r
-#define DWT_MASK3 (HWREG32(0xE0001054)) /* DWT Mask Register 3 */\r
-#define DWT_FUNCTION3 (HWREG32(0xE0001058)) /* DWT Function Register 3 */\r
-\r
-/* Register offsets from DWT_BASE address */\r
-#define OFS_DWT_CTRL (0x00000000) /* DWT Control Register */\r
-#define OFS_DWT_CYCCNT (0x00000004) /* DWT Current PC Sampler Cycle Count Register */\r
-#define OFS_DWT_CPICNT (0x00000008) /* DWT CPI Count Register */\r
-#define OFS_DWT_EXCCNT (0x0000000C) /* DWT Exception Overhead Count Register */\r
-#define OFS_DWT_SLEEPCNT (0x00000010) /* DWT Sleep Count Register */\r
-#define OFS_DWT_LSUCNT (0x00000014) /* DWT LSU Count Register */\r
-#define OFS_DWT_FOLDCNT (0x00000018) /* DWT Fold Count Register */\r
-#define OFS_DWT_PCSR (0x0000001C) /* DWT Program Counter Sample Register */\r
-#define OFS_DWT_COMP0 (0x00000020) /* DWT Comparator Register 0 */\r
-#define OFS_DWT_MASK0 (0x00000024) /* DWT Mask Register 0 */\r
-#define OFS_DWT_FUNCTION0 (0x00000028) /* DWT Function Register 0 */\r
-#define OFS_DWT_COMP1 (0x00000030) /* DWT Comparator Register 1 */\r
-#define OFS_DWT_MASK1 (0x00000034) /* DWT Mask Register 1 */\r
-#define OFS_DWT_FUNCTION1 (0x00000038) /* DWT Function Register 1 */\r
-#define OFS_DWT_COMP2 (0x00000040) /* DWT Comparator Register 2 */\r
-#define OFS_DWT_MASK2 (0x00000044) /* DWT Mask Register 2 */\r
-#define OFS_DWT_FUNCTION2 (0x00000048) /* DWT Function Register 2 */\r
-#define OFS_DWT_COMP3 (0x00000050) /* DWT Comparator Register 3 */\r
-#define OFS_DWT_MASK3 (0x00000054) /* DWT Mask Register 3 */\r
-#define OFS_DWT_FUNCTION3 (0x00000058) /* DWT Function Register 3 */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A0 Registers\r
-//*****************************************************************************\r
-#define UCA0CTLW0 (HWREG16(0x40001000)) /* eUSCI_Ax Control Word Register 0 */\r
-#define UCA0CTLW0_SPI (HWREG16(0x40001000)) /* */\r
-#define UCA0CTLW1 (HWREG16(0x40001002)) /* eUSCI_Ax Control Word Register 1 */\r
-#define UCA0BRW (HWREG16(0x40001006)) /* eUSCI_Ax Baud Rate Control Word Register */\r
-#define UCA0BRW_SPI (HWREG16(0x40001006)) /* */\r
-#define UCA0MCTLW (HWREG16(0x40001008)) /* eUSCI_Ax Modulation Control Word Register */\r
-#define UCA0STATW (HWREG16(0x4000100A)) /* eUSCI_Ax Status Register */\r
-#define UCA0STATW_SPI (HWREG16(0x4000100A)) /* */\r
-#define UCA0RXBUF (HWREG16(0x4000100C)) /* eUSCI_Ax Receive Buffer Register */\r
-#define UCA0RXBUF_SPI (HWREG16(0x4000100C)) /* */\r
-#define UCA0TXBUF (HWREG16(0x4000100E)) /* eUSCI_Ax Transmit Buffer Register */\r
-#define UCA0TXBUF_SPI (HWREG16(0x4000100E)) /* */\r
-#define UCA0ABCTL (HWREG16(0x40001010)) /* eUSCI_Ax Auto Baud Rate Control Register */\r
-#define UCA0IRCTL (HWREG16(0x40001012)) /* eUSCI_Ax IrDA Control Word Register */\r
-#define UCA0IE (HWREG16(0x4000101A)) /* eUSCI_Ax Interrupt Enable Register */\r
-#define UCA0IE_SPI (HWREG16(0x4000101A)) /* */\r
-#define UCA0IFG (HWREG16(0x4000101C)) /* eUSCI_Ax Interrupt Flag Register */\r
-#define UCA0IFG_SPI (HWREG16(0x4000101C)) /* */\r
-#define UCA0IV (HWREG16(0x4000101E)) /* eUSCI_Ax Interrupt Vector Register */\r
-#define UCA0IV_SPI (HWREG16(0x4000101E)) /* */\r
-\r
-/* Register offsets from EUSCI_A0_BASE address */\r
-#define OFS_UCA0CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */\r
-#define OFS_UCA0CTLW0_SPI (0x0000) /* */\r
-#define OFS_UCA0CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */\r
-#define OFS_UCA0BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */\r
-#define OFS_UCA0BRW_SPI (0x0006) /* */\r
-#define OFS_UCA0MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */\r
-#define OFS_UCA0STATW (0x000a) /* eUSCI_Ax Status Register */\r
-#define OFS_UCA0STATW_SPI (0x000a) /* */\r
-#define OFS_UCA0RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */\r
-#define OFS_UCA0RXBUF_SPI (0x000c) /* */\r
-#define OFS_UCA0TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */\r
-#define OFS_UCA0TXBUF_SPI (0x000e) /* */\r
-#define OFS_UCA0ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */\r
-#define OFS_UCA0IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */\r
-#define OFS_UCA0IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */\r
-#define OFS_UCA0IE_SPI (0x001a) /* */\r
-#define OFS_UCA0IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */\r
-#define OFS_UCA0IFG_SPI (0x001c) /* */\r
-#define OFS_UCA0IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */\r
-#define OFS_UCA0IV_SPI (0x001e) /* */\r
-\r
-#define UCA0CTL0 (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */\r
-#define UCA0CTL1 (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */\r
-#define UCA0BR0 (HWREG8_L(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 0 */\r
-#define UCA0BR1 (HWREG8_H(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 1 */\r
-#define UCA0IRTCTL (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */\r
-#define UCA0IRRCTL (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */\r
-\r
-//*****************************************************************************\r
-// EUSCI_A1 Registers\r
-//*****************************************************************************\r
-#define UCA1CTLW0 (HWREG16(0x40001400)) /* eUSCI_Ax Control Word Register 0 */\r
-#define UCA1CTLW0_SPI (HWREG16(0x40001400)) /* */\r
-#define UCA1CTLW1 (HWREG16(0x40001402)) /* eUSCI_Ax Control Word Register 1 */\r
-#define UCA1BRW (HWREG16(0x40001406)) /* eUSCI_Ax Baud Rate Control Word Register */\r
-#define UCA1BRW_SPI (HWREG16(0x40001406)) /* */\r
-#define UCA1MCTLW (HWREG16(0x40001408)) /* eUSCI_Ax Modulation Control Word Register */\r
-#define UCA1STATW (HWREG16(0x4000140A)) /* eUSCI_Ax Status Register */\r
-#define UCA1STATW_SPI (HWREG16(0x4000140A)) /* */\r
-#define UCA1RXBUF (HWREG16(0x4000140C)) /* eUSCI_Ax Receive Buffer Register */\r
-#define UCA1RXBUF_SPI (HWREG16(0x4000140C)) /* */\r
-#define UCA1TXBUF (HWREG16(0x4000140E)) /* eUSCI_Ax Transmit Buffer Register */\r
-#define UCA1TXBUF_SPI (HWREG16(0x4000140E)) /* */\r
-#define UCA1ABCTL (HWREG16(0x40001410)) /* eUSCI_Ax Auto Baud Rate Control Register */\r
-#define UCA1IRCTL (HWREG16(0x40001412)) /* eUSCI_Ax IrDA Control Word Register */\r
-#define UCA1IE (HWREG16(0x4000141A)) /* eUSCI_Ax Interrupt Enable Register */\r
-#define UCA1IE_SPI (HWREG16(0x4000141A)) /* */\r
-#define UCA1IFG (HWREG16(0x4000141C)) /* eUSCI_Ax Interrupt Flag Register */\r
-#define UCA1IFG_SPI (HWREG16(0x4000141C)) /* */\r
-#define UCA1IV (HWREG16(0x4000141E)) /* eUSCI_Ax Interrupt Vector Register */\r
-#define UCA1IV_SPI (HWREG16(0x4000141E)) /* */\r
-\r
-/* Register offsets from EUSCI_A1_BASE address */\r
-#define OFS_UCA1CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */\r
-#define OFS_UCA1CTLW0_SPI (0x0000) /* */\r
-#define OFS_UCA1CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */\r
-#define OFS_UCA1BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */\r
-#define OFS_UCA1BRW_SPI (0x0006) /* */\r
-#define OFS_UCA1MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */\r
-#define OFS_UCA1STATW (0x000a) /* eUSCI_Ax Status Register */\r
-#define OFS_UCA1STATW_SPI (0x000a) /* */\r
-#define OFS_UCA1RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */\r
-#define OFS_UCA1RXBUF_SPI (0x000c) /* */\r
-#define OFS_UCA1TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */\r
-#define OFS_UCA1TXBUF_SPI (0x000e) /* */\r
-#define OFS_UCA1ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */\r
-#define OFS_UCA1IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */\r
-#define OFS_UCA1IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */\r
-#define OFS_UCA1IE_SPI (0x001a) /* */\r
-#define OFS_UCA1IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */\r
-#define OFS_UCA1IFG_SPI (0x001c) /* */\r
-#define OFS_UCA1IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */\r
-#define OFS_UCA1IV_SPI (0x001e) /* */\r
-\r
-#define UCA1CTL0 (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */\r
-#define UCA1CTL1 (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */\r
-#define UCA1BR0 (HWREG8_L(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 0 */\r
-#define UCA1BR1 (HWREG8_H(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 1 */\r
-#define UCA1IRTCTL (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */\r
-#define UCA1IRRCTL (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */\r
-\r
-//*****************************************************************************\r
-// EUSCI_A2 Registers\r
-//*****************************************************************************\r
-#define UCA2CTLW0 (HWREG16(0x40001800)) /* eUSCI_Ax Control Word Register 0 */\r
-#define UCA2CTLW0_SPI (HWREG16(0x40001800)) /* */\r
-#define UCA2CTLW1 (HWREG16(0x40001802)) /* eUSCI_Ax Control Word Register 1 */\r
-#define UCA2BRW (HWREG16(0x40001806)) /* eUSCI_Ax Baud Rate Control Word Register */\r
-#define UCA2BRW_SPI (HWREG16(0x40001806)) /* */\r
-#define UCA2MCTLW (HWREG16(0x40001808)) /* eUSCI_Ax Modulation Control Word Register */\r
-#define UCA2STATW (HWREG16(0x4000180A)) /* eUSCI_Ax Status Register */\r
-#define UCA2STATW_SPI (HWREG16(0x4000180A)) /* */\r
-#define UCA2RXBUF (HWREG16(0x4000180C)) /* eUSCI_Ax Receive Buffer Register */\r
-#define UCA2RXBUF_SPI (HWREG16(0x4000180C)) /* */\r
-#define UCA2TXBUF (HWREG16(0x4000180E)) /* eUSCI_Ax Transmit Buffer Register */\r
-#define UCA2TXBUF_SPI (HWREG16(0x4000180E)) /* */\r
-#define UCA2ABCTL (HWREG16(0x40001810)) /* eUSCI_Ax Auto Baud Rate Control Register */\r
-#define UCA2IRCTL (HWREG16(0x40001812)) /* eUSCI_Ax IrDA Control Word Register */\r
-#define UCA2IE (HWREG16(0x4000181A)) /* eUSCI_Ax Interrupt Enable Register */\r
-#define UCA2IE_SPI (HWREG16(0x4000181A)) /* */\r
-#define UCA2IFG (HWREG16(0x4000181C)) /* eUSCI_Ax Interrupt Flag Register */\r
-#define UCA2IFG_SPI (HWREG16(0x4000181C)) /* */\r
-#define UCA2IV (HWREG16(0x4000181E)) /* eUSCI_Ax Interrupt Vector Register */\r
-#define UCA2IV_SPI (HWREG16(0x4000181E)) /* */\r
-\r
-/* Register offsets from EUSCI_A2_BASE address */\r
-#define OFS_UCA2CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */\r
-#define OFS_UCA2CTLW0_SPI (0x0000) /* */\r
-#define OFS_UCA2CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */\r
-#define OFS_UCA2BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */\r
-#define OFS_UCA2BRW_SPI (0x0006) /* */\r
-#define OFS_UCA2MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */\r
-#define OFS_UCA2STATW (0x000a) /* eUSCI_Ax Status Register */\r
-#define OFS_UCA2STATW_SPI (0x000a) /* */\r
-#define OFS_UCA2RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */\r
-#define OFS_UCA2RXBUF_SPI (0x000c) /* */\r
-#define OFS_UCA2TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */\r
-#define OFS_UCA2TXBUF_SPI (0x000e) /* */\r
-#define OFS_UCA2ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */\r
-#define OFS_UCA2IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */\r
-#define OFS_UCA2IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */\r
-#define OFS_UCA2IE_SPI (0x001a) /* */\r
-#define OFS_UCA2IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */\r
-#define OFS_UCA2IFG_SPI (0x001c) /* */\r
-#define OFS_UCA2IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */\r
-#define OFS_UCA2IV_SPI (0x001e) /* */\r
-\r
-#define UCA2CTL0 (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */\r
-#define UCA2CTL1 (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */\r
-#define UCA2BR0 (HWREG8_L(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 0 */\r
-#define UCA2BR1 (HWREG8_H(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 1 */\r
-#define UCA2IRTCTL (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */\r
-#define UCA2IRRCTL (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */\r
-\r
-//*****************************************************************************\r
-// EUSCI_A3 Registers\r
-//*****************************************************************************\r
-#define UCA3CTLW0 (HWREG16(0x40001C00)) /* eUSCI_Ax Control Word Register 0 */\r
-#define UCA3CTLW0_SPI (HWREG16(0x40001C00)) /* */\r
-#define UCA3CTLW1 (HWREG16(0x40001C02)) /* eUSCI_Ax Control Word Register 1 */\r
-#define UCA3BRW (HWREG16(0x40001C06)) /* eUSCI_Ax Baud Rate Control Word Register */\r
-#define UCA3BRW_SPI (HWREG16(0x40001C06)) /* */\r
-#define UCA3MCTLW (HWREG16(0x40001C08)) /* eUSCI_Ax Modulation Control Word Register */\r
-#define UCA3STATW (HWREG16(0x40001C0A)) /* eUSCI_Ax Status Register */\r
-#define UCA3STATW_SPI (HWREG16(0x40001C0A)) /* */\r
-#define UCA3RXBUF (HWREG16(0x40001C0C)) /* eUSCI_Ax Receive Buffer Register */\r
-#define UCA3RXBUF_SPI (HWREG16(0x40001C0C)) /* */\r
-#define UCA3TXBUF (HWREG16(0x40001C0E)) /* eUSCI_Ax Transmit Buffer Register */\r
-#define UCA3TXBUF_SPI (HWREG16(0x40001C0E)) /* */\r
-#define UCA3ABCTL (HWREG16(0x40001C10)) /* eUSCI_Ax Auto Baud Rate Control Register */\r
-#define UCA3IRCTL (HWREG16(0x40001C12)) /* eUSCI_Ax IrDA Control Word Register */\r
-#define UCA3IE (HWREG16(0x40001C1A)) /* eUSCI_Ax Interrupt Enable Register */\r
-#define UCA3IE_SPI (HWREG16(0x40001C1A)) /* */\r
-#define UCA3IFG (HWREG16(0x40001C1C)) /* eUSCI_Ax Interrupt Flag Register */\r
-#define UCA3IFG_SPI (HWREG16(0x40001C1C)) /* */\r
-#define UCA3IV (HWREG16(0x40001C1E)) /* eUSCI_Ax Interrupt Vector Register */\r
-#define UCA3IV_SPI (HWREG16(0x40001C1E)) /* */\r
-\r
-/* Register offsets from EUSCI_A3_BASE address */\r
-#define OFS_UCA3CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */\r
-#define OFS_UCA3CTLW0_SPI (0x0000) /* */\r
-#define OFS_UCA3CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */\r
-#define OFS_UCA3BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */\r
-#define OFS_UCA3BRW_SPI (0x0006) /* */\r
-#define OFS_UCA3MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */\r
-#define OFS_UCA3STATW (0x000a) /* eUSCI_Ax Status Register */\r
-#define OFS_UCA3STATW_SPI (0x000a) /* */\r
-#define OFS_UCA3RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */\r
-#define OFS_UCA3RXBUF_SPI (0x000c) /* */\r
-#define OFS_UCA3TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */\r
-#define OFS_UCA3TXBUF_SPI (0x000e) /* */\r
-#define OFS_UCA3ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */\r
-#define OFS_UCA3IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */\r
-#define OFS_UCA3IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */\r
-#define OFS_UCA3IE_SPI (0x001a) /* */\r
-#define OFS_UCA3IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */\r
-#define OFS_UCA3IFG_SPI (0x001c) /* */\r
-#define OFS_UCA3IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */\r
-#define OFS_UCA3IV_SPI (0x001e) /* */\r
-\r
-#define UCA3CTL0 (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */\r
-#define UCA3CTL1 (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */\r
-#define UCA3BR0 (HWREG8_L(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 0 */\r
-#define UCA3BR1 (HWREG8_H(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 1 */\r
-#define UCA3IRTCTL (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */\r
-#define UCA3IRRCTL (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */\r
-\r
-//*****************************************************************************\r
-// EUSCI_B0 Registers\r
-//*****************************************************************************\r
-#define UCB0CTLW0 (HWREG16(0x40002000)) /* eUSCI_Bx Control Word Register 0 */\r
-#define UCB0CTLW0_SPI (HWREG16(0x40002000)) /* */\r
-#define UCB0CTLW1 (HWREG16(0x40002002)) /* eUSCI_Bx Control Word Register 1 */\r
-#define UCB0BRW (HWREG16(0x40002006)) /* eUSCI_Bx Baud Rate Control Word Register */\r
-#define UCB0BRW_SPI (HWREG16(0x40002006)) /* */\r
-#define UCB0STATW (HWREG16(0x40002008)) /* eUSCI_Bx Status Register */\r
-#define UCB0STATW_SPI (HWREG16(0x40002008)) /* */\r
-#define UCB0TBCNT (HWREG16(0x4000200A)) /* eUSCI_Bx Byte Counter Threshold Register */\r
-#define UCB0RXBUF (HWREG16(0x4000200C)) /* eUSCI_Bx Receive Buffer Register */\r
-#define UCB0RXBUF_SPI (HWREG16(0x4000200C)) /* */\r
-#define UCB0TXBUF (HWREG16(0x4000200E)) /* eUSCI_Bx Transmit Buffer Register */\r
-#define UCB0TXBUF_SPI (HWREG16(0x4000200E)) /* */\r
-#define UCB0I2COA0 (HWREG16(0x40002014)) /* eUSCI_Bx I2C Own Address 0 Register */\r
-#define UCB0I2COA1 (HWREG16(0x40002016)) /* eUSCI_Bx I2C Own Address 1 Register */\r
-#define UCB0I2COA2 (HWREG16(0x40002018)) /* eUSCI_Bx I2C Own Address 2 Register */\r
-#define UCB0I2COA3 (HWREG16(0x4000201A)) /* eUSCI_Bx I2C Own Address 3 Register */\r
-#define UCB0ADDRX (HWREG16(0x4000201C)) /* eUSCI_Bx I2C Received Address Register */\r
-#define UCB0ADDMASK (HWREG16(0x4000201E)) /* eUSCI_Bx I2C Address Mask Register */\r
-#define UCB0I2CSA (HWREG16(0x40002020)) /* eUSCI_Bx I2C Slave Address Register */\r
-#define UCB0IE (HWREG16(0x4000202A)) /* eUSCI_Bx Interrupt Enable Register */\r
-#define UCB0IE_SPI (HWREG16(0x4000202A)) /* */\r
-#define UCB0IFG (HWREG16(0x4000202C)) /* eUSCI_Bx Interrupt Flag Register */\r
-#define UCB0IFG_SPI (HWREG16(0x4000202C)) /* */\r
-#define UCB0IV (HWREG16(0x4000202E)) /* eUSCI_Bx Interrupt Vector Register */\r
-#define UCB0IV_SPI (HWREG16(0x4000202E)) /* */\r
-\r
-/* Register offsets from EUSCI_B0_BASE address */\r
-#define OFS_UCB0CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */\r
-#define OFS_UCB0CTLW0_SPI (0x0000) /* */\r
-#define OFS_UCB0CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */\r
-#define OFS_UCB0BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */\r
-#define OFS_UCB0BRW_SPI (0x0006) /* */\r
-#define OFS_UCB0STATW (0x0008) /* eUSCI_Bx Status Register */\r
-#define OFS_UCB0STATW_SPI (0x0008) /* */\r
-#define OFS_UCB0TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */\r
-#define OFS_UCB0RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */\r
-#define OFS_UCB0RXBUF_SPI (0x000c) /* */\r
-#define OFS_UCB0TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */\r
-#define OFS_UCB0TXBUF_SPI (0x000e) /* */\r
-#define OFS_UCB0I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */\r
-#define OFS_UCB0I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */\r
-#define OFS_UCB0I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */\r
-#define OFS_UCB0I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */\r
-#define OFS_UCB0ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */\r
-#define OFS_UCB0ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */\r
-#define OFS_UCB0I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */\r
-#define OFS_UCB0IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */\r
-#define OFS_UCB0IE_SPI (0x002a) /* */\r
-#define OFS_UCB0IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */\r
-#define OFS_UCB0IFG_SPI (0x002c) /* */\r
-#define OFS_UCB0IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */\r
-#define OFS_UCB0IV_SPI (0x002e) /* */\r
-\r
-#define UCB0CTL0 (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */\r
-#define UCB0CTL1 (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */\r
-#define UCB0BR0 (HWREG8_L(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 0 */\r
-#define UCB0BR1 (HWREG8_H(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 1 */\r
-#define UCB0STAT (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */\r
-#define UCB0BCNT (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */\r
-\r
-//*****************************************************************************\r
-// EUSCI_B1 Registers\r
-//*****************************************************************************\r
-#define UCB1CTLW0 (HWREG16(0x40002400)) /* eUSCI_Bx Control Word Register 0 */\r
-#define UCB1CTLW0_SPI (HWREG16(0x40002400)) /* */\r
-#define UCB1CTLW1 (HWREG16(0x40002402)) /* eUSCI_Bx Control Word Register 1 */\r
-#define UCB1BRW (HWREG16(0x40002406)) /* eUSCI_Bx Baud Rate Control Word Register */\r
-#define UCB1BRW_SPI (HWREG16(0x40002406)) /* */\r
-#define UCB1STATW (HWREG16(0x40002408)) /* eUSCI_Bx Status Register */\r
-#define UCB1STATW_SPI (HWREG16(0x40002408)) /* */\r
-#define UCB1TBCNT (HWREG16(0x4000240A)) /* eUSCI_Bx Byte Counter Threshold Register */\r
-#define UCB1RXBUF (HWREG16(0x4000240C)) /* eUSCI_Bx Receive Buffer Register */\r
-#define UCB1RXBUF_SPI (HWREG16(0x4000240C)) /* */\r
-#define UCB1TXBUF (HWREG16(0x4000240E)) /* eUSCI_Bx Transmit Buffer Register */\r
-#define UCB1TXBUF_SPI (HWREG16(0x4000240E)) /* */\r
-#define UCB1I2COA0 (HWREG16(0x40002414)) /* eUSCI_Bx I2C Own Address 0 Register */\r
-#define UCB1I2COA1 (HWREG16(0x40002416)) /* eUSCI_Bx I2C Own Address 1 Register */\r
-#define UCB1I2COA2 (HWREG16(0x40002418)) /* eUSCI_Bx I2C Own Address 2 Register */\r
-#define UCB1I2COA3 (HWREG16(0x4000241A)) /* eUSCI_Bx I2C Own Address 3 Register */\r
-#define UCB1ADDRX (HWREG16(0x4000241C)) /* eUSCI_Bx I2C Received Address Register */\r
-#define UCB1ADDMASK (HWREG16(0x4000241E)) /* eUSCI_Bx I2C Address Mask Register */\r
-#define UCB1I2CSA (HWREG16(0x40002420)) /* eUSCI_Bx I2C Slave Address Register */\r
-#define UCB1IE (HWREG16(0x4000242A)) /* eUSCI_Bx Interrupt Enable Register */\r
-#define UCB1IE_SPI (HWREG16(0x4000242A)) /* */\r
-#define UCB1IFG (HWREG16(0x4000242C)) /* eUSCI_Bx Interrupt Flag Register */\r
-#define UCB1IFG_SPI (HWREG16(0x4000242C)) /* */\r
-#define UCB1IV (HWREG16(0x4000242E)) /* eUSCI_Bx Interrupt Vector Register */\r
-#define UCB1IV_SPI (HWREG16(0x4000242E)) /* */\r
-\r
-/* Register offsets from EUSCI_B1_BASE address */\r
-#define OFS_UCB1CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */\r
-#define OFS_UCB1CTLW0_SPI (0x0000) /* */\r
-#define OFS_UCB1CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */\r
-#define OFS_UCB1BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */\r
-#define OFS_UCB1BRW_SPI (0x0006) /* */\r
-#define OFS_UCB1STATW (0x0008) /* eUSCI_Bx Status Register */\r
-#define OFS_UCB1STATW_SPI (0x0008) /* */\r
-#define OFS_UCB1TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */\r
-#define OFS_UCB1RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */\r
-#define OFS_UCB1RXBUF_SPI (0x000c) /* */\r
-#define OFS_UCB1TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */\r
-#define OFS_UCB1TXBUF_SPI (0x000e) /* */\r
-#define OFS_UCB1I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */\r
-#define OFS_UCB1I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */\r
-#define OFS_UCB1I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */\r
-#define OFS_UCB1I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */\r
-#define OFS_UCB1ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */\r
-#define OFS_UCB1ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */\r
-#define OFS_UCB1I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */\r
-#define OFS_UCB1IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */\r
-#define OFS_UCB1IE_SPI (0x002a) /* */\r
-#define OFS_UCB1IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */\r
-#define OFS_UCB1IFG_SPI (0x002c) /* */\r
-#define OFS_UCB1IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */\r
-#define OFS_UCB1IV_SPI (0x002e) /* */\r
-\r
-#define UCB1CTL0 (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */\r
-#define UCB1CTL1 (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */\r
-#define UCB1BR0 (HWREG8_L(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 0 */\r
-#define UCB1BR1 (HWREG8_H(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 1 */\r
-#define UCB1STAT (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */\r
-#define UCB1BCNT (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */\r
-\r
-//*****************************************************************************\r
-// EUSCI_B2 Registers\r
-//*****************************************************************************\r
-#define UCB2CTLW0 (HWREG16(0x40002800)) /* eUSCI_Bx Control Word Register 0 */\r
-#define UCB2CTLW0_SPI (HWREG16(0x40002800)) /* */\r
-#define UCB2CTLW1 (HWREG16(0x40002802)) /* eUSCI_Bx Control Word Register 1 */\r
-#define UCB2BRW (HWREG16(0x40002806)) /* eUSCI_Bx Baud Rate Control Word Register */\r
-#define UCB2BRW_SPI (HWREG16(0x40002806)) /* */\r
-#define UCB2STATW (HWREG16(0x40002808)) /* eUSCI_Bx Status Register */\r
-#define UCB2STATW_SPI (HWREG16(0x40002808)) /* */\r
-#define UCB2TBCNT (HWREG16(0x4000280A)) /* eUSCI_Bx Byte Counter Threshold Register */\r
-#define UCB2RXBUF (HWREG16(0x4000280C)) /* eUSCI_Bx Receive Buffer Register */\r
-#define UCB2RXBUF_SPI (HWREG16(0x4000280C)) /* */\r
-#define UCB2TXBUF (HWREG16(0x4000280E)) /* eUSCI_Bx Transmit Buffer Register */\r
-#define UCB2TXBUF_SPI (HWREG16(0x4000280E)) /* */\r
-#define UCB2I2COA0 (HWREG16(0x40002814)) /* eUSCI_Bx I2C Own Address 0 Register */\r
-#define UCB2I2COA1 (HWREG16(0x40002816)) /* eUSCI_Bx I2C Own Address 1 Register */\r
-#define UCB2I2COA2 (HWREG16(0x40002818)) /* eUSCI_Bx I2C Own Address 2 Register */\r
-#define UCB2I2COA3 (HWREG16(0x4000281A)) /* eUSCI_Bx I2C Own Address 3 Register */\r
-#define UCB2ADDRX (HWREG16(0x4000281C)) /* eUSCI_Bx I2C Received Address Register */\r
-#define UCB2ADDMASK (HWREG16(0x4000281E)) /* eUSCI_Bx I2C Address Mask Register */\r
-#define UCB2I2CSA (HWREG16(0x40002820)) /* eUSCI_Bx I2C Slave Address Register */\r
-#define UCB2IE (HWREG16(0x4000282A)) /* eUSCI_Bx Interrupt Enable Register */\r
-#define UCB2IE_SPI (HWREG16(0x4000282A)) /* */\r
-#define UCB2IFG (HWREG16(0x4000282C)) /* eUSCI_Bx Interrupt Flag Register */\r
-#define UCB2IFG_SPI (HWREG16(0x4000282C)) /* */\r
-#define UCB2IV (HWREG16(0x4000282E)) /* eUSCI_Bx Interrupt Vector Register */\r
-#define UCB2IV_SPI (HWREG16(0x4000282E)) /* */\r
-\r
-/* Register offsets from EUSCI_B2_BASE address */\r
-#define OFS_UCB2CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */\r
-#define OFS_UCB2CTLW0_SPI (0x0000) /* */\r
-#define OFS_UCB2CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */\r
-#define OFS_UCB2BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */\r
-#define OFS_UCB2BRW_SPI (0x0006) /* */\r
-#define OFS_UCB2STATW (0x0008) /* eUSCI_Bx Status Register */\r
-#define OFS_UCB2STATW_SPI (0x0008) /* */\r
-#define OFS_UCB2TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */\r
-#define OFS_UCB2RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */\r
-#define OFS_UCB2RXBUF_SPI (0x000c) /* */\r
-#define OFS_UCB2TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */\r
-#define OFS_UCB2TXBUF_SPI (0x000e) /* */\r
-#define OFS_UCB2I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */\r
-#define OFS_UCB2I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */\r
-#define OFS_UCB2I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */\r
-#define OFS_UCB2I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */\r
-#define OFS_UCB2ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */\r
-#define OFS_UCB2ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */\r
-#define OFS_UCB2I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */\r
-#define OFS_UCB2IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */\r
-#define OFS_UCB2IE_SPI (0x002a) /* */\r
-#define OFS_UCB2IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */\r
-#define OFS_UCB2IFG_SPI (0x002c) /* */\r
-#define OFS_UCB2IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */\r
-#define OFS_UCB2IV_SPI (0x002e) /* */\r
-\r
-#define UCB2CTL0 (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */\r
-#define UCB2CTL1 (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */\r
-#define UCB2BR0 (HWREG8_L(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 0 */\r
-#define UCB2BR1 (HWREG8_H(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 1 */\r
-#define UCB2STAT (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */\r
-#define UCB2BCNT (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */\r
-\r
-//*****************************************************************************\r
-// EUSCI_B3 Registers\r
-//*****************************************************************************\r
-#define UCB3CTLW0 (HWREG16(0x40002C00)) /* eUSCI_Bx Control Word Register 0 */\r
-#define UCB3CTLW0_SPI (HWREG16(0x40002C00)) /* */\r
-#define UCB3CTLW1 (HWREG16(0x40002C02)) /* eUSCI_Bx Control Word Register 1 */\r
-#define UCB3BRW (HWREG16(0x40002C06)) /* eUSCI_Bx Baud Rate Control Word Register */\r
-#define UCB3BRW_SPI (HWREG16(0x40002C06)) /* */\r
-#define UCB3STATW (HWREG16(0x40002C08)) /* eUSCI_Bx Status Register */\r
-#define UCB3STATW_SPI (HWREG16(0x40002C08)) /* */\r
-#define UCB3TBCNT (HWREG16(0x40002C0A)) /* eUSCI_Bx Byte Counter Threshold Register */\r
-#define UCB3RXBUF (HWREG16(0x40002C0C)) /* eUSCI_Bx Receive Buffer Register */\r
-#define UCB3RXBUF_SPI (HWREG16(0x40002C0C)) /* */\r
-#define UCB3TXBUF (HWREG16(0x40002C0E)) /* eUSCI_Bx Transmit Buffer Register */\r
-#define UCB3TXBUF_SPI (HWREG16(0x40002C0E)) /* */\r
-#define UCB3I2COA0 (HWREG16(0x40002C14)) /* eUSCI_Bx I2C Own Address 0 Register */\r
-#define UCB3I2COA1 (HWREG16(0x40002C16)) /* eUSCI_Bx I2C Own Address 1 Register */\r
-#define UCB3I2COA2 (HWREG16(0x40002C18)) /* eUSCI_Bx I2C Own Address 2 Register */\r
-#define UCB3I2COA3 (HWREG16(0x40002C1A)) /* eUSCI_Bx I2C Own Address 3 Register */\r
-#define UCB3ADDRX (HWREG16(0x40002C1C)) /* eUSCI_Bx I2C Received Address Register */\r
-#define UCB3ADDMASK (HWREG16(0x40002C1E)) /* eUSCI_Bx I2C Address Mask Register */\r
-#define UCB3I2CSA (HWREG16(0x40002C20)) /* eUSCI_Bx I2C Slave Address Register */\r
-#define UCB3IE (HWREG16(0x40002C2A)) /* eUSCI_Bx Interrupt Enable Register */\r
-#define UCB3IE_SPI (HWREG16(0x40002C2A)) /* */\r
-#define UCB3IFG (HWREG16(0x40002C2C)) /* eUSCI_Bx Interrupt Flag Register */\r
-#define UCB3IFG_SPI (HWREG16(0x40002C2C)) /* */\r
-#define UCB3IV (HWREG16(0x40002C2E)) /* eUSCI_Bx Interrupt Vector Register */\r
-#define UCB3IV_SPI (HWREG16(0x40002C2E)) /* */\r
-\r
-/* Register offsets from EUSCI_B3_BASE address */\r
-#define OFS_UCB3CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */\r
-#define OFS_UCB3CTLW0_SPI (0x0000) /* */\r
-#define OFS_UCB3CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */\r
-#define OFS_UCB3BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */\r
-#define OFS_UCB3BRW_SPI (0x0006) /* */\r
-#define OFS_UCB3STATW (0x0008) /* eUSCI_Bx Status Register */\r
-#define OFS_UCB3STATW_SPI (0x0008) /* */\r
-#define OFS_UCB3TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */\r
-#define OFS_UCB3RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */\r
-#define OFS_UCB3RXBUF_SPI (0x000c) /* */\r
-#define OFS_UCB3TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */\r
-#define OFS_UCB3TXBUF_SPI (0x000e) /* */\r
-#define OFS_UCB3I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */\r
-#define OFS_UCB3I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */\r
-#define OFS_UCB3I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */\r
-#define OFS_UCB3I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */\r
-#define OFS_UCB3ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */\r
-#define OFS_UCB3ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */\r
-#define OFS_UCB3I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */\r
-#define OFS_UCB3IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */\r
-#define OFS_UCB3IE_SPI (0x002a) /* */\r
-#define OFS_UCB3IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */\r
-#define OFS_UCB3IFG_SPI (0x002c) /* */\r
-#define OFS_UCB3IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */\r
-#define OFS_UCB3IV_SPI (0x002e) /* */\r
-\r
-#define UCB3CTL0 (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */\r
-#define UCB3CTL1 (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */\r
-#define UCB3BR0 (HWREG8_L(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 0 */\r
-#define UCB3BR1 (HWREG8_H(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 1 */\r
-#define UCB3STAT (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */\r
-#define UCB3BCNT (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */\r
-\r
-//*****************************************************************************\r
-// FLCTL Registers\r
-//*****************************************************************************\r
-#define FLCTL_POWER_STAT (HWREG32(0x40011000)) /* Power Status Register */\r
-#define FLCTL_BANK0_RDCTL (HWREG32(0x40011010)) /* Bank0 Read Control Register */\r
-#define FLCTL_BANK1_RDCTL (HWREG32(0x40011014)) /* Bank1 Read Control Register */\r
-#define FLCTL_RDBRST_CTLSTAT (HWREG32(0x40011020)) /* Read Burst/Compare Control and Status Register */\r
-#define FLCTL_RDBRST_STARTADDR (HWREG32(0x40011024)) /* Read Burst/Compare Start Address Register */\r
-#define FLCTL_RDBRST_LEN (HWREG32(0x40011028)) /* Read Burst/Compare Length Register */\r
-#define FLCTL_RDBRST_FAILADDR (HWREG32(0x4001103C)) /* Read Burst/Compare Fail Address Register */\r
-#define FLCTL_RDBRST_FAILCNT (HWREG32(0x40011040)) /* Read Burst/Compare Fail Count Register */\r
-#define FLCTL_PRG_CTLSTAT (HWREG32(0x40011050)) /* Program Control and Status Register */\r
-#define FLCTL_PRGBRST_CTLSTAT (HWREG32(0x40011054)) /* Program Burst Control and Status Register */\r
-#define FLCTL_PRGBRST_STARTADDR (HWREG32(0x40011058)) /* Program Burst Start Address Register */\r
-#define FLCTL_PRGBRST_DATA0_0 (HWREG32(0x40011060)) /* Program Burst Data0 Register0 */\r
-#define FLCTL_PRGBRST_DATA0_1 (HWREG32(0x40011064)) /* Program Burst Data0 Register1 */\r
-#define FLCTL_PRGBRST_DATA0_2 (HWREG32(0x40011068)) /* Program Burst Data0 Register2 */\r
-#define FLCTL_PRGBRST_DATA0_3 (HWREG32(0x4001106C)) /* Program Burst Data0 Register3 */\r
-#define FLCTL_PRGBRST_DATA1_0 (HWREG32(0x40011070)) /* Program Burst Data1 Register0 */\r
-#define FLCTL_PRGBRST_DATA1_1 (HWREG32(0x40011074)) /* Program Burst Data1 Register1 */\r
-#define FLCTL_PRGBRST_DATA1_2 (HWREG32(0x40011078)) /* Program Burst Data1 Register2 */\r
-#define FLCTL_PRGBRST_DATA1_3 (HWREG32(0x4001107C)) /* Program Burst Data1 Register3 */\r
-#define FLCTL_PRGBRST_DATA2_0 (HWREG32(0x40011080)) /* Program Burst Data2 Register0 */\r
-#define FLCTL_PRGBRST_DATA2_1 (HWREG32(0x40011084)) /* Program Burst Data2 Register1 */\r
-#define FLCTL_PRGBRST_DATA2_2 (HWREG32(0x40011088)) /* Program Burst Data2 Register2 */\r
-#define FLCTL_PRGBRST_DATA2_3 (HWREG32(0x4001108C)) /* Program Burst Data2 Register3 */\r
-#define FLCTL_PRGBRST_DATA3_0 (HWREG32(0x40011090)) /* Program Burst Data3 Register0 */\r
-#define FLCTL_PRGBRST_DATA3_1 (HWREG32(0x40011094)) /* Program Burst Data3 Register1 */\r
-#define FLCTL_PRGBRST_DATA3_2 (HWREG32(0x40011098)) /* Program Burst Data3 Register2 */\r
-#define FLCTL_PRGBRST_DATA3_3 (HWREG32(0x4001109C)) /* Program Burst Data3 Register3 */\r
-#define FLCTL_ERASE_CTLSTAT (HWREG32(0x400110A0)) /* Erase Control and Status Register */\r
-#define FLCTL_ERASE_SECTADDR (HWREG32(0x400110A4)) /* Erase Sector Address Register */\r
-#define FLCTL_BANK0_INFO_WEPROT (HWREG32(0x400110B0)) /* Information Memory Bank0 Write/Erase Protection Register */\r
-#define FLCTL_BANK0_MAIN_WEPROT (HWREG32(0x400110B4)) /* Main Memory Bank0 Write/Erase Protection Register */\r
-#define FLCTL_BANK1_INFO_WEPROT (HWREG32(0x400110C0)) /* Information Memory Bank1 Write/Erase Protection Register */\r
-#define FLCTL_BANK1_MAIN_WEPROT (HWREG32(0x400110C4)) /* Main Memory Bank1 Write/Erase Protection Register */\r
-#define FLCTL_BMRK_CTLSTAT (HWREG32(0x400110D0)) /* Benchmark Control and Status Register */\r
-#define FLCTL_BMRK_IFETCH (HWREG32(0x400110D4)) /* Benchmark Instruction Fetch Count Register */\r
-#define FLCTL_BMRK_DREAD (HWREG32(0x400110D8)) /* Benchmark Data Read Count Register */\r
-#define FLCTL_BMRK_CMP (HWREG32(0x400110DC)) /* Benchmark Count Compare Register */\r
-#define FLCTL_IFG (HWREG32(0x400110F0)) /* Interrupt Flag Register */\r
-#define FLCTL_IE (HWREG32(0x400110F4)) /* Interrupt Enable Register */\r
-#define FLCTL_CLRIFG (HWREG32(0x400110F8)) /* Clear Interrupt Flag Register */\r
-#define FLCTL_SETIFG (HWREG32(0x400110FC)) /* Set Interrupt Flag Register */\r
-#define FLCTL_READ_TIMCTL (HWREG32(0x40011100)) /* Read Timing Control Register */\r
-#define FLCTL_READMARGIN_TIMCTL (HWREG32(0x40011104)) /* Read Margin Timing Control Register */\r
-#define FLCTL_PRGVER_TIMCTL (HWREG32(0x40011108)) /* Program Verify Timing Control Register */\r
-#define FLCTL_ERSVER_TIMCTL (HWREG32(0x4001110C)) /* Erase Verify Timing Control Register */\r
-#define FLCTL_LKGVER_TIMCTL (HWREG32(0x40011110)) /* Leakage Verify Timing Control Register */\r
-#define FLCTL_PROGRAM_TIMCTL (HWREG32(0x40011114)) /* Program Timing Control Register */\r
-#define FLCTL_ERASE_TIMCTL (HWREG32(0x40011118)) /* Erase Timing Control Register */\r
-#define FLCTL_MASSERASE_TIMCTL (HWREG32(0x4001111C)) /* Mass Erase Timing Control Register */\r
-#define FLCTL_BURSTPRG_TIMCTL (HWREG32(0x40011120)) /* Burst Program Timing Control Register */\r
-\r
-/* Register offsets from FLCTL_BASE address */\r
-#define OFS_FLCTL_POWER_STAT (0x00000000) /* Power Status Register */\r
-#define OFS_FLCTL_BANK0_RDCTL (0x00000010) /* Bank0 Read Control Register */\r
-#define OFS_FLCTL_BANK1_RDCTL (0x00000014) /* Bank1 Read Control Register */\r
-#define OFS_FLCTL_RDBRST_CTLSTAT (0x00000020) /* Read Burst/Compare Control and Status Register */\r
-#define OFS_FLCTL_RDBRST_STARTADDR (0x00000024) /* Read Burst/Compare Start Address Register */\r
-#define OFS_FLCTL_RDBRST_LEN (0x00000028) /* Read Burst/Compare Length Register */\r
-#define OFS_FLCTL_RDBRST_FAILADDR (0x0000003C) /* Read Burst/Compare Fail Address Register */\r
-#define OFS_FLCTL_RDBRST_FAILCNT (0x00000040) /* Read Burst/Compare Fail Count Register */\r
-#define OFS_FLCTL_PRG_CTLSTAT (0x00000050) /* Program Control and Status Register */\r
-#define OFS_FLCTL_PRGBRST_CTLSTAT (0x00000054) /* Program Burst Control and Status Register */\r
-#define OFS_FLCTL_PRGBRST_STARTADDR (0x00000058) /* Program Burst Start Address Register */\r
-#define OFS_FLCTL_PRGBRST_DATA0_0 (0x00000060) /* Program Burst Data0 Register0 */\r
-#define OFS_FLCTL_PRGBRST_DATA0_1 (0x00000064) /* Program Burst Data0 Register1 */\r
-#define OFS_FLCTL_PRGBRST_DATA0_2 (0x00000068) /* Program Burst Data0 Register2 */\r
-#define OFS_FLCTL_PRGBRST_DATA0_3 (0x0000006C) /* Program Burst Data0 Register3 */\r
-#define OFS_FLCTL_PRGBRST_DATA1_0 (0x00000070) /* Program Burst Data1 Register0 */\r
-#define OFS_FLCTL_PRGBRST_DATA1_1 (0x00000074) /* Program Burst Data1 Register1 */\r
-#define OFS_FLCTL_PRGBRST_DATA1_2 (0x00000078) /* Program Burst Data1 Register2 */\r
-#define OFS_FLCTL_PRGBRST_DATA1_3 (0x0000007C) /* Program Burst Data1 Register3 */\r
-#define OFS_FLCTL_PRGBRST_DATA2_0 (0x00000080) /* Program Burst Data2 Register0 */\r
-#define OFS_FLCTL_PRGBRST_DATA2_1 (0x00000084) /* Program Burst Data2 Register1 */\r
-#define OFS_FLCTL_PRGBRST_DATA2_2 (0x00000088) /* Program Burst Data2 Register2 */\r
-#define OFS_FLCTL_PRGBRST_DATA2_3 (0x0000008C) /* Program Burst Data2 Register3 */\r
-#define OFS_FLCTL_PRGBRST_DATA3_0 (0x00000090) /* Program Burst Data3 Register0 */\r
-#define OFS_FLCTL_PRGBRST_DATA3_1 (0x00000094) /* Program Burst Data3 Register1 */\r
-#define OFS_FLCTL_PRGBRST_DATA3_2 (0x00000098) /* Program Burst Data3 Register2 */\r
-#define OFS_FLCTL_PRGBRST_DATA3_3 (0x0000009C) /* Program Burst Data3 Register3 */\r
-#define OFS_FLCTL_ERASE_CTLSTAT (0x000000A0) /* Erase Control and Status Register */\r
-#define OFS_FLCTL_ERASE_SECTADDR (0x000000A4) /* Erase Sector Address Register */\r
-#define OFS_FLCTL_BANK0_INFO_WEPROT (0x000000B0) /* Information Memory Bank0 Write/Erase Protection Register */\r
-#define OFS_FLCTL_BANK0_MAIN_WEPROT (0x000000B4) /* Main Memory Bank0 Write/Erase Protection Register */\r
-#define OFS_FLCTL_BANK1_INFO_WEPROT (0x000000C0) /* Information Memory Bank1 Write/Erase Protection Register */\r
-#define OFS_FLCTL_BANK1_MAIN_WEPROT (0x000000C4) /* Main Memory Bank1 Write/Erase Protection Register */\r
-#define OFS_FLCTL_BMRK_CTLSTAT (0x000000D0) /* Benchmark Control and Status Register */\r
-#define OFS_FLCTL_BMRK_IFETCH (0x000000D4) /* Benchmark Instruction Fetch Count Register */\r
-#define OFS_FLCTL_BMRK_DREAD (0x000000D8) /* Benchmark Data Read Count Register */\r
-#define OFS_FLCTL_BMRK_CMP (0x000000DC) /* Benchmark Count Compare Register */\r
-#define OFS_FLCTL_IFG (0x000000F0) /* Interrupt Flag Register */\r
-#define OFS_FLCTL_IE (0x000000F4) /* Interrupt Enable Register */\r
-#define OFS_FLCTL_CLRIFG (0x000000F8) /* Clear Interrupt Flag Register */\r
-#define OFS_FLCTL_SETIFG (0x000000FC) /* Set Interrupt Flag Register */\r
-#define OFS_FLCTL_READ_TIMCTL (0x00000100) /* Read Timing Control Register */\r
-#define OFS_FLCTL_READMARGIN_TIMCTL (0x00000104) /* Read Margin Timing Control Register */\r
-#define OFS_FLCTL_PRGVER_TIMCTL (0x00000108) /* Program Verify Timing Control Register */\r
-#define OFS_FLCTL_ERSVER_TIMCTL (0x0000010C) /* Erase Verify Timing Control Register */\r
-#define OFS_FLCTL_LKGVER_TIMCTL (0x00000110) /* Leakage Verify Timing Control Register */\r
-#define OFS_FLCTL_PROGRAM_TIMCTL (0x00000114) /* Program Timing Control Register */\r
-#define OFS_FLCTL_ERASE_TIMCTL (0x00000118) /* Erase Timing Control Register */\r
-#define OFS_FLCTL_MASSERASE_TIMCTL (0x0000011C) /* Mass Erase Timing Control Register */\r
-#define OFS_FLCTL_BURSTPRG_TIMCTL (0x00000120) /* Burst Program Timing Control Register */\r
-\r
-\r
-//*****************************************************************************\r
-// FPB Registers\r
-//*****************************************************************************\r
-#define FPB_FP_CTRL (HWREG32(0xE0002000)) /* Flash Patch Control Register */\r
-#define FPB_FP_REMAP (HWREG32(0xE0002004)) /* Flash Patch Remap Register */\r
-#define FPB_FP_COMP0 (HWREG32(0xE0002008)) /* Flash Patch Comparator Registers */\r
-#define FPB_FP_COMP1 (HWREG32(0xE000200C)) /* Flash Patch Comparator Registers */\r
-#define FPB_FP_COMP2 (HWREG32(0xE0002010)) /* Flash Patch Comparator Registers */\r
-#define FPB_FP_COMP3 (HWREG32(0xE0002014)) /* Flash Patch Comparator Registers */\r
-#define FPB_FP_COMP4 (HWREG32(0xE0002018)) /* Flash Patch Comparator Registers */\r
-#define FPB_FP_COMP5 (HWREG32(0xE000201C)) /* Flash Patch Comparator Registers */\r
-#define FPB_FP_COMP6 (HWREG32(0xE0002020)) /* Flash Patch Comparator Registers */\r
-#define FPB_FP_COMP7 (HWREG32(0xE0002024)) /* Flash Patch Comparator Registers */\r
-\r
-/* Register offsets from FPB_BASE address */\r
-#define OFS_FPB_FP_CTRL (0x00000000) /* Flash Patch Control Register */\r
-#define OFS_FPB_FP_REMAP (0x00000004) /* Flash Patch Remap Register */\r
-#define OFS_FPB_FP_COMP0 (0x00000008) /* Flash Patch Comparator Registers */\r
-#define OFS_FPB_FP_COMP1 (0x0000000C) /* Flash Patch Comparator Registers */\r
-#define OFS_FPB_FP_COMP2 (0x00000010) /* Flash Patch Comparator Registers */\r
-#define OFS_FPB_FP_COMP3 (0x00000014) /* Flash Patch Comparator Registers */\r
-#define OFS_FPB_FP_COMP4 (0x00000018) /* Flash Patch Comparator Registers */\r
-#define OFS_FPB_FP_COMP5 (0x0000001C) /* Flash Patch Comparator Registers */\r
-#define OFS_FPB_FP_COMP6 (0x00000020) /* Flash Patch Comparator Registers */\r
-#define OFS_FPB_FP_COMP7 (0x00000024) /* Flash Patch Comparator Registers */\r
-\r
-\r
-//*****************************************************************************\r
-// FPU Registers\r
-//*****************************************************************************\r
-#define FPU_FPCCR (HWREG32(0xE000EF34)) /* Floating Point Context Control Register */\r
-#define FPU_FPCAR (HWREG32(0xE000EF38)) /* Floating-Point Context Address Register */\r
-#define FPU_FPDSCR (HWREG32(0xE000EF3C)) /* Floating Point Default Status Control Register */\r
-#define FPU_MVFR0 (HWREG32(0xE000EF40)) /* Media and FP Feature Register 0 (MVFR0) */\r
-#define FPU_MVFR1 (HWREG32(0xE000EF44)) /* Media and FP Feature Register 1 (MVFR1) */\r
-\r
-/* Register offsets from FPU_BASE address */\r
-#define OFS_FPU_FPCCR (0x00000F34) /* Floating Point Context Control Register */\r
-#define OFS_FPU_FPCAR (0x00000F38) /* Floating-Point Context Address Register */\r
-#define OFS_FPU_FPDSCR (0x00000F3C) /* Floating Point Default Status Control Register */\r
-#define OFS_FPU_MVFR0 (0x00000F40) /* Media and FP Feature Register 0 (MVFR0) */\r
-#define OFS_FPU_MVFR1 (0x00000F44) /* Media and FP Feature Register 1 (MVFR1) */\r
-\r
-\r
-//*****************************************************************************\r
-// ITM Registers\r
-//*****************************************************************************\r
-#define ITM_STIM0 (HWREG32(0xE0000000)) /* ITM Stimulus Port 0 */\r
-#define ITM_STIM1 (HWREG32(0xE0000004)) /* ITM Stimulus Port 1 */\r
-#define ITM_STIM2 (HWREG32(0xE0000008)) /* ITM Stimulus Port 2 */\r
-#define ITM_STIM3 (HWREG32(0xE000000C)) /* ITM Stimulus Port 3 */\r
-#define ITM_STIM4 (HWREG32(0xE0000010)) /* ITM Stimulus Port 4 */\r
-#define ITM_STIM5 (HWREG32(0xE0000014)) /* ITM Stimulus Port 5 */\r
-#define ITM_STIM6 (HWREG32(0xE0000018)) /* ITM Stimulus Port 6 */\r
-#define ITM_STIM7 (HWREG32(0xE000001C)) /* ITM Stimulus Port 7 */\r
-#define ITM_STIM8 (HWREG32(0xE0000020)) /* ITM Stimulus Port 8 */\r
-#define ITM_STIM9 (HWREG32(0xE0000024)) /* ITM Stimulus Port 9 */\r
-#define ITM_STIM10 (HWREG32(0xE0000028)) /* ITM Stimulus Port 10 */\r
-#define ITM_STIM11 (HWREG32(0xE000002C)) /* ITM Stimulus Port 11 */\r
-#define ITM_STIM12 (HWREG32(0xE0000030)) /* ITM Stimulus Port 12 */\r
-#define ITM_STIM13 (HWREG32(0xE0000034)) /* ITM Stimulus Port 13 */\r
-#define ITM_STIM14 (HWREG32(0xE0000038)) /* ITM Stimulus Port 14 */\r
-#define ITM_STIM15 (HWREG32(0xE000003C)) /* ITM Stimulus Port 15 */\r
-#define ITM_STIM16 (HWREG32(0xE0000040)) /* ITM Stimulus Port 16 */\r
-#define ITM_STIM17 (HWREG32(0xE0000044)) /* ITM Stimulus Port 17 */\r
-#define ITM_STIM18 (HWREG32(0xE0000048)) /* ITM Stimulus Port 18 */\r
-#define ITM_STIM19 (HWREG32(0xE000004C)) /* ITM Stimulus Port 19 */\r
-#define ITM_STIM20 (HWREG32(0xE0000050)) /* ITM Stimulus Port 20 */\r
-#define ITM_STIM21 (HWREG32(0xE0000054)) /* ITM Stimulus Port 21 */\r
-#define ITM_STIM22 (HWREG32(0xE0000058)) /* ITM Stimulus Port 22 */\r
-#define ITM_STIM23 (HWREG32(0xE000005C)) /* ITM Stimulus Port 23 */\r
-#define ITM_STIM24 (HWREG32(0xE0000060)) /* ITM Stimulus Port 24 */\r
-#define ITM_STIM25 (HWREG32(0xE0000064)) /* ITM Stimulus Port 25 */\r
-#define ITM_STIM26 (HWREG32(0xE0000068)) /* ITM Stimulus Port 26 */\r
-#define ITM_STIM27 (HWREG32(0xE000006C)) /* ITM Stimulus Port 27 */\r
-#define ITM_STIM28 (HWREG32(0xE0000070)) /* ITM Stimulus Port 28 */\r
-#define ITM_STIM29 (HWREG32(0xE0000074)) /* ITM Stimulus Port 29 */\r
-#define ITM_STIM30 (HWREG32(0xE0000078)) /* ITM Stimulus Port 30 */\r
-#define ITM_STIM31 (HWREG32(0xE000007C)) /* ITM Stimulus Port 31 */\r
-#define ITM_TER (HWREG32(0xE0000E00)) /* ITM Trace Enable Register */\r
-#define ITM_TPR (HWREG32(0xE0000E40)) /* ITM Trace Privilege Register */\r
-#define ITM_TCR (HWREG32(0xE0000E80)) /* ITM Trace Control Register */\r
-#define ITM_IWR (HWREG32(0xE0000EF8)) /* ITM Integration Write Register */\r
-#define ITM_IMCR (HWREG32(0xE0000F00)) /* ITM Integration Mode Control Register */\r
-#define ITM_LAR (HWREG32(0xE0000FB0)) /* ITM Lock Access Register */\r
-#define ITM_LSR (HWREG32(0xE0000FB4)) /* ITM Lock Status Register */\r
-\r
-/* Register offsets from ITM_BASE address */\r
-#define OFS_ITM_STIM0 (0x00000000) /* ITM Stimulus Port 0 */\r
-#define OFS_ITM_STIM1 (0x00000004) /* ITM Stimulus Port 1 */\r
-#define OFS_ITM_STIM2 (0x00000008) /* ITM Stimulus Port 2 */\r
-#define OFS_ITM_STIM3 (0x0000000C) /* ITM Stimulus Port 3 */\r
-#define OFS_ITM_STIM4 (0x00000010) /* ITM Stimulus Port 4 */\r
-#define OFS_ITM_STIM5 (0x00000014) /* ITM Stimulus Port 5 */\r
-#define OFS_ITM_STIM6 (0x00000018) /* ITM Stimulus Port 6 */\r
-#define OFS_ITM_STIM7 (0x0000001C) /* ITM Stimulus Port 7 */\r
-#define OFS_ITM_STIM8 (0x00000020) /* ITM Stimulus Port 8 */\r
-#define OFS_ITM_STIM9 (0x00000024) /* ITM Stimulus Port 9 */\r
-#define OFS_ITM_STIM10 (0x00000028) /* ITM Stimulus Port 10 */\r
-#define OFS_ITM_STIM11 (0x0000002C) /* ITM Stimulus Port 11 */\r
-#define OFS_ITM_STIM12 (0x00000030) /* ITM Stimulus Port 12 */\r
-#define OFS_ITM_STIM13 (0x00000034) /* ITM Stimulus Port 13 */\r
-#define OFS_ITM_STIM14 (0x00000038) /* ITM Stimulus Port 14 */\r
-#define OFS_ITM_STIM15 (0x0000003C) /* ITM Stimulus Port 15 */\r
-#define OFS_ITM_STIM16 (0x00000040) /* ITM Stimulus Port 16 */\r
-#define OFS_ITM_STIM17 (0x00000044) /* ITM Stimulus Port 17 */\r
-#define OFS_ITM_STIM18 (0x00000048) /* ITM Stimulus Port 18 */\r
-#define OFS_ITM_STIM19 (0x0000004C) /* ITM Stimulus Port 19 */\r
-#define OFS_ITM_STIM20 (0x00000050) /* ITM Stimulus Port 20 */\r
-#define OFS_ITM_STIM21 (0x00000054) /* ITM Stimulus Port 21 */\r
-#define OFS_ITM_STIM22 (0x00000058) /* ITM Stimulus Port 22 */\r
-#define OFS_ITM_STIM23 (0x0000005C) /* ITM Stimulus Port 23 */\r
-#define OFS_ITM_STIM24 (0x00000060) /* ITM Stimulus Port 24 */\r
-#define OFS_ITM_STIM25 (0x00000064) /* ITM Stimulus Port 25 */\r
-#define OFS_ITM_STIM26 (0x00000068) /* ITM Stimulus Port 26 */\r
-#define OFS_ITM_STIM27 (0x0000006C) /* ITM Stimulus Port 27 */\r
-#define OFS_ITM_STIM28 (0x00000070) /* ITM Stimulus Port 28 */\r
-#define OFS_ITM_STIM29 (0x00000074) /* ITM Stimulus Port 29 */\r
-#define OFS_ITM_STIM30 (0x00000078) /* ITM Stimulus Port 30 */\r
-#define OFS_ITM_STIM31 (0x0000007C) /* ITM Stimulus Port 31 */\r
-#define OFS_ITM_TER (0x00000E00) /* ITM Trace Enable Register */\r
-#define OFS_ITM_TPR (0x00000E40) /* ITM Trace Privilege Register */\r
-#define OFS_ITM_TCR (0x00000E80) /* ITM Trace Control Register */\r
-#define OFS_ITM_IWR (0x00000EF8) /* ITM Integration Write Register */\r
-#define OFS_ITM_IMCR (0x00000F00) /* ITM Integration Mode Control Register */\r
-#define OFS_ITM_LAR (0x00000FB0) /* ITM Lock Access Register */\r
-#define OFS_ITM_LSR (0x00000FB4) /* ITM Lock Status Register */\r
-\r
-\r
-//*****************************************************************************\r
-// MPU Registers\r
-//*****************************************************************************\r
-#define MPU_TYPE (HWREG32(0xE000ED90)) /* MPU Type Register */\r
-#define MPU_CTRL (HWREG32(0xE000ED94)) /* MPU Control Register */\r
-#define MPU_RNR (HWREG32(0xE000ED98)) /* MPU Region Number Register */\r
-#define MPU_RBAR (HWREG32(0xE000ED9C)) /* MPU Region Base Address Register */\r
-#define MPU_RASR (HWREG32(0xE000EDA0)) /* MPU Region Attribute and Size Register */\r
-#define MPU_RBAR_A1 (HWREG32(0xE000EDA4)) /* MPU Alias 1 Region Base Address register */\r
-#define MPU_RASR_A1 (HWREG32(0xE000EDA8)) /* MPU Alias 1 Region Attribute and Size register */\r
-#define MPU_RBAR_A2 (HWREG32(0xE000EDAC)) /* MPU Alias 2 Region Base Address register */\r
-#define MPU_RASR_A2 (HWREG32(0xE000EDB0)) /* MPU Alias 2 Region Attribute and Size register */\r
-#define MPU_RBAR_A3 (HWREG32(0xE000EDB4)) /* MPU Alias 3 Region Base Address register */\r
-#define MPU_RASR_A3 (HWREG32(0xE000EDB8)) /* MPU Alias 3 Region Attribute and Size register */\r
-\r
-/* Register offsets from MPU_BASE address */\r
-#define OFS_MPU_TYPE (0x00000D90) /* MPU Type Register */\r
-#define OFS_MPU_CTRL (0x00000D94) /* MPU Control Register */\r
-#define OFS_MPU_RNR (0x00000D98) /* MPU Region Number Register */\r
-#define OFS_MPU_RBAR (0x00000D9C) /* MPU Region Base Address Register */\r
-#define OFS_MPU_RASR (0x00000DA0) /* MPU Region Attribute and Size Register */\r
-#define OFS_MPU_RBAR_A1 (0x00000DA4) /* MPU Alias 1 Region Base Address register */\r
-#define OFS_MPU_RASR_A1 (0x00000DA8) /* MPU Alias 1 Region Attribute and Size register */\r
-#define OFS_MPU_RBAR_A2 (0x00000DAC) /* MPU Alias 2 Region Base Address register */\r
-#define OFS_MPU_RASR_A2 (0x00000DB0) /* MPU Alias 2 Region Attribute and Size register */\r
-#define OFS_MPU_RBAR_A3 (0x00000DB4) /* MPU Alias 3 Region Base Address register */\r
-#define OFS_MPU_RASR_A3 (0x00000DB8) /* MPU Alias 3 Region Attribute and Size register */\r
-\r
-\r
-//*****************************************************************************\r
-// NVIC Registers\r
-//*****************************************************************************\r
-#define NVIC_ISER0 (HWREG32(0xE000E100)) /* Irq 0 to 31 Set Enable Register */\r
-#define NVIC_ISER1 (HWREG32(0xE000E104)) /* Irq 32 to 63 Set Enable Register */\r
-#define NVIC_ICER0 (HWREG32(0xE000E180)) /* Irq 0 to 31 Clear Enable Register */\r
-#define NVIC_ICER1 (HWREG32(0xE000E184)) /* Irq 32 to 63 Clear Enable Register */\r
-#define NVIC_ISPR0 (HWREG32(0xE000E200)) /* Irq 0 to 31 Set Pending Register */\r
-#define NVIC_ISPR1 (HWREG32(0xE000E204)) /* Irq 32 to 63 Set Pending Register */\r
-#define NVIC_ICPR0 (HWREG32(0xE000E280)) /* Irq 0 to 31 Clear Pending Register */\r
-#define NVIC_ICPR1 (HWREG32(0xE000E284)) /* Irq 32 to 63 Clear Pending Register */\r
-#define NVIC_IABR0 (HWREG32(0xE000E300)) /* Irq 0 to 31 Active Bit Register */\r
-#define NVIC_IABR1 (HWREG32(0xE000E304)) /* Irq 32 to 63 Active Bit Register */\r
-#define NVIC_IPR0 (HWREG32(0xE000E400)) /* Irq 0 to 3 Priority Register */\r
-#define NVIC_IPR1 (HWREG32(0xE000E404)) /* Irq 4 to 7 Priority Register */\r
-#define NVIC_IPR2 (HWREG32(0xE000E408)) /* Irq 8 to 11 Priority Register */\r
-#define NVIC_IPR3 (HWREG32(0xE000E40C)) /* Irq 12 to 15 Priority Register */\r
-#define NVIC_IPR4 (HWREG32(0xE000E410)) /* Irq 16 to 19 Priority Register */\r
-#define NVIC_IPR5 (HWREG32(0xE000E414)) /* Irq 20 to 23 Priority Register */\r
-#define NVIC_IPR6 (HWREG32(0xE000E418)) /* Irq 24 to 27 Priority Register */\r
-#define NVIC_IPR7 (HWREG32(0xE000E41C)) /* Irq 28 to 31 Priority Register */\r
-#define NVIC_IPR8 (HWREG32(0xE000E420)) /* Irq 32 to 35 Priority Register */\r
-#define NVIC_IPR9 (HWREG32(0xE000E424)) /* Irq 36 to 39 Priority Register */\r
-#define NVIC_IPR10 (HWREG32(0xE000E428)) /* Irq 40 to 43 Priority Register */\r
-#define NVIC_IPR11 (HWREG32(0xE000E42C)) /* Irq 44 to 47 Priority Register */\r
-#define NVIC_IPR12 (HWREG32(0xE000E430)) /* Irq 48 to 51 Priority Register */\r
-#define NVIC_IPR13 (HWREG32(0xE000E434)) /* Irq 52 to 55 Priority Register */\r
-#define NVIC_IPR14 (HWREG32(0xE000E438)) /* Irq 56 to 59 Priority Register */\r
-#define NVIC_IPR15 (HWREG32(0xE000E43C)) /* Irq 60 to 63 Priority Register */\r
-#define NVIC_STIR (HWREG32(0xE000EF00)) /* Software Trigger Interrupt Register */\r
-\r
-/* Register offsets from NVIC_BASE address */\r
-#define OFS_NVIC_ISER0 (0x00000100) /* Irq 0 to 31 Set Enable Register */\r
-#define OFS_NVIC_ISER1 (0x00000104) /* Irq 32 to 63 Set Enable Register */\r
-#define OFS_NVIC_ICER0 (0x00000180) /* Irq 0 to 31 Clear Enable Register */\r
-#define OFS_NVIC_ICER1 (0x00000184) /* Irq 32 to 63 Clear Enable Register */\r
-#define OFS_NVIC_ISPR0 (0x00000200) /* Irq 0 to 31 Set Pending Register */\r
-#define OFS_NVIC_ISPR1 (0x00000204) /* Irq 32 to 63 Set Pending Register */\r
-#define OFS_NVIC_ICPR0 (0x00000280) /* Irq 0 to 31 Clear Pending Register */\r
-#define OFS_NVIC_ICPR1 (0x00000284) /* Irq 32 to 63 Clear Pending Register */\r
-#define OFS_NVIC_IABR0 (0x00000300) /* Irq 0 to 31 Active Bit Register */\r
-#define OFS_NVIC_IABR1 (0x00000304) /* Irq 32 to 63 Active Bit Register */\r
-#define OFS_NVIC_IPR0 (0x00000400) /* Irq 0 to 3 Priority Register */\r
-#define OFS_NVIC_IPR1 (0x00000404) /* Irq 4 to 7 Priority Register */\r
-#define OFS_NVIC_IPR2 (0x00000408) /* Irq 8 to 11 Priority Register */\r
-#define OFS_NVIC_IPR3 (0x0000040C) /* Irq 12 to 15 Priority Register */\r
-#define OFS_NVIC_IPR4 (0x00000410) /* Irq 16 to 19 Priority Register */\r
-#define OFS_NVIC_IPR5 (0x00000414) /* Irq 20 to 23 Priority Register */\r
-#define OFS_NVIC_IPR6 (0x00000418) /* Irq 24 to 27 Priority Register */\r
-#define OFS_NVIC_IPR7 (0x0000041C) /* Irq 28 to 31 Priority Register */\r
-#define OFS_NVIC_IPR8 (0x00000420) /* Irq 32 to 35 Priority Register */\r
-#define OFS_NVIC_IPR9 (0x00000424) /* Irq 36 to 39 Priority Register */\r
-#define OFS_NVIC_IPR10 (0x00000428) /* Irq 40 to 43 Priority Register */\r
-#define OFS_NVIC_IPR11 (0x0000042C) /* Irq 44 to 47 Priority Register */\r
-#define OFS_NVIC_IPR12 (0x00000430) /* Irq 48 to 51 Priority Register */\r
-#define OFS_NVIC_IPR13 (0x00000434) /* Irq 52 to 55 Priority Register */\r
-#define OFS_NVIC_IPR14 (0x00000438) /* Irq 56 to 59 Priority Register */\r
-#define OFS_NVIC_IPR15 (0x0000043C) /* Irq 60 to 63 Priority Register */\r
-#define OFS_NVIC_STIR (0x00000F00) /* Software Trigger Interrupt Register */\r
-\r
-\r
-//*****************************************************************************\r
-// PCM Registers\r
-//*****************************************************************************\r
-#define PCMCTL0 (HWREG32(0x40010000)) /* Control 0 Register */\r
-#define PCMCTL1 (HWREG32(0x40010004)) /* Control 1 Register */\r
-#define PCMIE (HWREG32(0x40010008)) /* Interrupt Enable Register */\r
-#define PCMIFG (HWREG32(0x4001000C)) /* Interrupt Flag Register */\r
-#define PCMCLRIFG (HWREG32(0x40010010)) /* Clear Interrupt Flag Register */\r
-\r
-/* Register offsets from PCM_BASE address */\r
-#define OFS_PCMCTL0 (0x00000000) /* Control 0 Register */\r
-#define OFS_PCMCTL1 (0x00000004) /* Control 1 Register */\r
-#define OFS_PCMIE (0x00000008) /* Interrupt Enable Register */\r
-#define OFS_PCMIFG (0x0000000c) /* Interrupt Flag Register */\r
-#define OFS_PCMCLRIFG (0x00000010) /* Clear Interrupt Flag Register */\r
-\r
-\r
-//*****************************************************************************\r
-// PMAP Registers\r
-//*****************************************************************************\r
-#define PMAPKEYID (HWREG16(0x40005000)) /* Port Mapping Key Register */\r
-#define PMAPCTL (HWREG16(0x40005002)) /* Port Mapping Control Register */\r
-#define P1MAP01 (HWREG16(0x40005008)) /* Port mapping register, P1.0 and P1.1 */\r
-#define P1MAP23 (HWREG16(0x4000500A)) /* Port mapping register, P1.2 and P1.3 */\r
-#define P1MAP45 (HWREG16(0x4000500C)) /* Port mapping register, P1.4 and P1.5 */\r
-#define P1MAP67 (HWREG16(0x4000500E)) /* Port mapping register, P1.6 and P1.7 */\r
-#define P2MAP01 (HWREG16(0x40005010)) /* Port mapping register, P2.0 and P2.1 */\r
-#define P2MAP23 (HWREG16(0x40005012)) /* Port mapping register, P2.2 and P2.3 */\r
-#define P2MAP45 (HWREG16(0x40005014)) /* Port mapping register, P2.4 and P2.5 */\r
-#define P2MAP67 (HWREG16(0x40005016)) /* Port mapping register, P2.6 and P2.7 */\r
-#define P3MAP01 (HWREG16(0x40005018)) /* Port mapping register, P3.0 and P3.1 */\r
-#define P3MAP23 (HWREG16(0x4000501A)) /* Port mapping register, P3.2 and P3.3 */\r
-#define P3MAP45 (HWREG16(0x4000501C)) /* Port mapping register, P3.4 and P3.5 */\r
-#define P3MAP67 (HWREG16(0x4000501E)) /* Port mapping register, P3.6 and P3.7 */\r
-#define P4MAP01 (HWREG16(0x40005020)) /* Port mapping register, P4.0 and P4.1 */\r
-#define P4MAP23 (HWREG16(0x40005022)) /* Port mapping register, P4.2 and P4.3 */\r
-#define P4MAP45 (HWREG16(0x40005024)) /* Port mapping register, P4.4 and P4.5 */\r
-#define P4MAP67 (HWREG16(0x40005026)) /* Port mapping register, P4.6 and P4.7 */\r
-#define P5MAP01 (HWREG16(0x40005028)) /* Port mapping register, P5.0 and P5.1 */\r
-#define P5MAP23 (HWREG16(0x4000502A)) /* Port mapping register, P5.2 and P5.3 */\r
-#define P5MAP45 (HWREG16(0x4000502C)) /* Port mapping register, P5.4 and P5.5 */\r
-#define P5MAP67 (HWREG16(0x4000502E)) /* Port mapping register, P5.6 and P5.7 */\r
-#define P6MAP01 (HWREG16(0x40005030)) /* Port mapping register, P6.0 and P6.1 */\r
-#define P6MAP23 (HWREG16(0x40005032)) /* Port mapping register, P6.2 and P6.3 */\r
-#define P6MAP45 (HWREG16(0x40005034)) /* Port mapping register, P6.4 and P6.5 */\r
-#define P6MAP67 (HWREG16(0x40005036)) /* Port mapping register, P6.6 and P6.7 */\r
-#define P7MAP01 (HWREG16(0x40005038)) /* Port mapping register, P7.0 and P7.1 */\r
-#define P7MAP23 (HWREG16(0x4000503A)) /* Port mapping register, P7.2 and P7.3 */\r
-#define P7MAP45 (HWREG16(0x4000503C)) /* Port mapping register, P7.4 and P7.5 */\r
-#define P7MAP67 (HWREG16(0x4000503E)) /* Port mapping register, P7.6 and P7.7 */\r
-\r
-/* Register offsets from PMAP_BASE address */\r
-#define OFS_PMAPKEYID (0x0000) /* Port Mapping Key Register */\r
-#define OFS_PMAPCTL (0x0002) /* Port Mapping Control Register */\r
-#define OFS_P1MAP01 (0x0008) /* Port mapping register, P1.0 and P1.1 */\r
-#define OFS_P1MAP23 (0x000a) /* Port mapping register, P1.2 and P1.3 */\r
-#define OFS_P1MAP45 (0x000c) /* Port mapping register, P1.4 and P1.5 */\r
-#define OFS_P1MAP67 (0x000e) /* Port mapping register, P1.6 and P1.7 */\r
-#define OFS_P2MAP01 (0x0010) /* Port mapping register, P2.0 and P2.1 */\r
-#define OFS_P2MAP23 (0x0012) /* Port mapping register, P2.2 and P2.3 */\r
-#define OFS_P2MAP45 (0x0014) /* Port mapping register, P2.4 and P2.5 */\r
-#define OFS_P2MAP67 (0x0016) /* Port mapping register, P2.6 and P2.7 */\r
-#define OFS_P3MAP01 (0x0018) /* Port mapping register, P3.0 and P3.1 */\r
-#define OFS_P3MAP23 (0x001a) /* Port mapping register, P3.2 and P3.3 */\r
-#define OFS_P3MAP45 (0x001c) /* Port mapping register, P3.4 and P3.5 */\r
-#define OFS_P3MAP67 (0x001e) /* Port mapping register, P3.6 and P3.7 */\r
-#define OFS_P4MAP01 (0x0020) /* Port mapping register, P4.0 and P4.1 */\r
-#define OFS_P4MAP23 (0x0022) /* Port mapping register, P4.2 and P4.3 */\r
-#define OFS_P4MAP45 (0x0024) /* Port mapping register, P4.4 and P4.5 */\r
-#define OFS_P4MAP67 (0x0026) /* Port mapping register, P4.6 and P4.7 */\r
-#define OFS_P5MAP01 (0x0028) /* Port mapping register, P5.0 and P5.1 */\r
-#define OFS_P5MAP23 (0x002a) /* Port mapping register, P5.2 and P5.3 */\r
-#define OFS_P5MAP45 (0x002c) /* Port mapping register, P5.4 and P5.5 */\r
-#define OFS_P5MAP67 (0x002e) /* Port mapping register, P5.6 and P5.7 */\r
-#define OFS_P6MAP01 (0x0030) /* Port mapping register, P6.0 and P6.1 */\r
-#define OFS_P6MAP23 (0x0032) /* Port mapping register, P6.2 and P6.3 */\r
-#define OFS_P6MAP45 (0x0034) /* Port mapping register, P6.4 and P6.5 */\r
-#define OFS_P6MAP67 (0x0036) /* Port mapping register, P6.6 and P6.7 */\r
-#define OFS_P7MAP01 (0x0038) /* Port mapping register, P7.0 and P7.1 */\r
-#define OFS_P7MAP23 (0x003a) /* Port mapping register, P7.2 and P7.3 */\r
-#define OFS_P7MAP45 (0x003c) /* Port mapping register, P7.4 and P7.5 */\r
-#define OFS_P7MAP67 (0x003e) /* Port mapping register, P7.6 and P7.7 */\r
-\r
-\r
-//*****************************************************************************\r
-// PSS Registers\r
-//*****************************************************************************\r
-#define PSSKEY (HWREG32(0x40010800)) /* Key Register */\r
-#define PSSCTL0 (HWREG32(0x40010804)) /* Control 0 Register */\r
-#define PSSIE (HWREG32(0x40010834)) /* Interrupt Enable Register */\r
-#define PSSIFG (HWREG32(0x40010838)) /* Interrupt Flag Register */\r
-#define PSSCLRIFG (HWREG32(0x4001083C)) /* Clear Interrupt Flag Register */\r
-\r
-/* Register offsets from PSS_BASE address */\r
-#define OFS_PSSKEY (0x00000000) /* Key Register */\r
-#define OFS_PSSCTL0 (0x00000004) /* Control 0 Register */\r
-#define OFS_PSSIE (0x00000034) /* Interrupt Enable Register */\r
-#define OFS_PSSIFG (0x00000038) /* Interrupt Flag Register */\r
-#define OFS_PSSCLRIFG (0x0000003c) /* Clear Interrupt Flag Register */\r
-\r
-\r
-//*****************************************************************************\r
-// REF_A Registers\r
-//*****************************************************************************\r
-#define REFCTL0 (HWREG16(0x40003000)) /* REF Control Register 0 */\r
-\r
-/* Register offsets from REF_A_BASE address */\r
-#define OFS_REFCTL0 (0x0000) /* REF Control Register 0 */\r
-\r
-#define REFCTL0_L (HWREG8_L(REFCTL0)) /* REF Control Register 0 */\r
-#define REFCTL0_H (HWREG8_H(REFCTL0)) /* REF Control Register 0 */\r
-\r
-//*****************************************************************************\r
-// RSTCTL Registers\r
-//*****************************************************************************\r
-#define RSTCTL_RESET_REQ (HWREG32(0xE0042000)) /* Reset Request Register */\r
-#define RSTCTL_HARDRESET_CLR (HWREG32(0xE0042008)) /* Hard Reset Status Clear Register */\r
-#define RSTCTL_HARDRESET_SET (HWREG32(0xE004200C)) /* Hard Reset Status Set Register */\r
-#define RSTCTL_SOFTRESET_STAT (HWREG32(0xE0042010)) /* Soft Reset Status Register */\r
-#define RSTCTL_SOFTRESET_CLR (HWREG32(0xE0042014)) /* Soft Reset Status Clear Register */\r
-#define RSTCTL_SOFTRESET_SET (HWREG32(0xE0042018)) /* Soft Reset Status Set Register */\r
-#define RSTCTL_PSSRESET_STAT (HWREG32(0xE0042100)) /* PSS Reset Status Register */\r
-#define RSTCTL_PSSRESET_CLR (HWREG32(0xE0042104)) /* PSS Reset Status Clear Register */\r
-#define RSTCTL_PCMRESET_STAT (HWREG32(0xE0042108)) /* PCM Reset Status Register */\r
-#define RSTCTL_PCMRESET_CLR (HWREG32(0xE004210C)) /* PCM Reset Status Clear Register */\r
-#define RSTCTL_PINRESET_STAT (HWREG32(0xE0042110)) /* Pin Reset Status Register */\r
-#define RSTCTL_PINRESET_CLR (HWREG32(0xE0042114)) /* Pin Reset Status Clear Register */\r
-#define RSTCTL_REBOOTRESET_STAT (HWREG32(0xE0042118)) /* Reboot Reset Status Register */\r
-#define RSTCTL_REBOOTRESET_CLR (HWREG32(0xE004211C)) /* Reboot Reset Status Clear Register */\r
-\r
-/* Register offsets from RSTCTL_BASE address */\r
-#define OFS_RSTCTL_RESET_REQ (0x00000000) /* Reset Request Register */\r
-#define OFS_RSTCTL_HARDRESET_CLR (0x00000008) /* Hard Reset Status Clear Register */\r
-#define OFS_RSTCTL_HARDRESET_SET (0x0000000c) /* Hard Reset Status Set Register */\r
-#define OFS_RSTCTL_SOFTRESET_STAT (0x00000010) /* Soft Reset Status Register */\r
-#define OFS_RSTCTL_SOFTRESET_CLR (0x00000014) /* Soft Reset Status Clear Register */\r
-#define OFS_RSTCTL_SOFTRESET_SET (0x00000018) /* Soft Reset Status Set Register */\r
-#define OFS_RSTCTL_PSSRESET_STAT (0x00000100) /* PSS Reset Status Register */\r
-#define OFS_RSTCTL_PSSRESET_CLR (0x00000104) /* PSS Reset Status Clear Register */\r
-#define OFS_RSTCTL_PCMRESET_STAT (0x00000108) /* PCM Reset Status Register */\r
-#define OFS_RSTCTL_PCMRESET_CLR (0x0000010c) /* PCM Reset Status Clear Register */\r
-#define OFS_RSTCTL_PINRESET_STAT (0x00000110) /* Pin Reset Status Register */\r
-#define OFS_RSTCTL_PINRESET_CLR (0x00000114) /* Pin Reset Status Clear Register */\r
-#define OFS_RSTCTL_REBOOTRESET_STAT (0x00000118) /* Reboot Reset Status Register */\r
-#define OFS_RSTCTL_REBOOTRESET_CLR (0x0000011c) /* Reboot Reset Status Clear Register */\r
-\r
-\r
-//*****************************************************************************\r
-// RTC_C Registers\r
-//*****************************************************************************\r
-#define RTCCTL0 (HWREG16(0x40004400)) /* RTCCTL0 Register */\r
-#define RTCCTL13 (HWREG16(0x40004402)) /* RTCCTL13 Register */\r
-#define RTCOCAL (HWREG16(0x40004404)) /* RTCOCAL Register */\r
-#define RTCTCMP (HWREG16(0x40004406)) /* RTCTCMP Register */\r
-#define RTCPS0CTL (HWREG16(0x40004408)) /* Real-Time Clock Prescale Timer 0 Control Register */\r
-#define RTCPS1CTL (HWREG16(0x4000440A)) /* Real-Time Clock Prescale Timer 1 Control Register */\r
-#define RTCPS (HWREG16(0x4000440C)) /* Real-Time Clock Prescale Timer Counter Register */\r
-#define RTCIV (HWREG16(0x4000440E)) /* Real-Time Clock Interrupt Vector Register */\r
-#define RTCTIM0 (HWREG16(0x40004410)) /* RTCTIM0 Register ? Hexadecimal Format */\r
-#define RTCTIM0_BCD (HWREG16(0x40004410)) /* */\r
-#define RTCTIM1 (HWREG16(0x40004412)) /* Real-Time Clock Hour, Day of Week */\r
-#define RTCTIM1_BCD (HWREG16(0x40004412)) /* */\r
-#define RTCDATE (HWREG16(0x40004414)) /* RTCDATE - Hexadecimal Format */\r
-#define RTCDATE_BCD (HWREG16(0x40004414)) /* */\r
-#define RTCYEAR (HWREG16(0x40004416)) /* RTCYEAR Register ? Hexadecimal Format */\r
-#define RTCYEAR_BCD (HWREG16(0x40004416)) /* */\r
-#define RTCAMINHR (HWREG16(0x40004418)) /* RTCMINHR - Hexadecimal Format */\r
-#define RTCAMINHR_BCD (HWREG16(0x40004418)) /* */\r
-#define RTCADOWDAY (HWREG16(0x4000441A)) /* RTCADOWDAY - Hexadecimal Format */\r
-#define RTCADOWDAY_BCD (HWREG16(0x4000441A)) /* */\r
-#define RTCBIN2BCD (HWREG16(0x4000441C)) /* Binary-to-BCD Conversion Register */\r
-#define RTCBCD2BIN (HWREG16(0x4000441E)) /* BCD-to-Binary Conversion Register */\r
-\r
-/* Register offsets from RTC_C_BASE address */\r
-#define OFS_RTCCTL0 (0x0000) /* RTCCTL0 Register */\r
-#define OFS_RTCCTL13 (0x0002) /* RTCCTL13 Register */\r
-#define OFS_RTCOCAL (0x0004) /* RTCOCAL Register */\r
-#define OFS_RTCTCMP (0x0006) /* RTCTCMP Register */\r
-#define OFS_RTCPS0CTL (0x0008) /* Real-Time Clock Prescale Timer 0 Control Register */\r
-#define OFS_RTCPS1CTL (0x000a) /* Real-Time Clock Prescale Timer 1 Control Register */\r
-#define OFS_RTCPS (0x000c) /* Real-Time Clock Prescale Timer Counter Register */\r
-#define OFS_RTCIV (0x000e) /* Real-Time Clock Interrupt Vector Register */\r
-#define OFS_RTCTIM0 (0x0010) /* RTCTIM0 Register ? Hexadecimal Format */\r
-#define OFS_RTCTIM0_BCD (0x0010) /* */\r
-#define OFS_RTCTIM1 (0x0012) /* Real-Time Clock Hour, Day of Week */\r
-#define OFS_RTCTIM1_BCD (0x0012) /* */\r
-#define OFS_RTCDATE (0x0014) /* RTCDATE - Hexadecimal Format */\r
-#define OFS_RTCDATE_BCD (0x0014) /* */\r
-#define OFS_RTCYEAR (0x0016) /* RTCYEAR Register ? Hexadecimal Format */\r
-#define OFS_RTCYEAR_BCD (0x0016) /* */\r
-#define OFS_RTCAMINHR (0x0018) /* RTCMINHR - Hexadecimal Format */\r
-#define OFS_RTCAMINHR_BCD (0x0018) /* */\r
-#define OFS_RTCADOWDAY (0x001a) /* RTCADOWDAY - Hexadecimal Format */\r
-#define OFS_RTCADOWDAY_BCD (0x001a) /* */\r
-#define OFS_RTCBIN2BCD (0x001c) /* Binary-to-BCD Conversion Register */\r
-#define OFS_RTCBCD2BIN (0x001e) /* BCD-to-Binary Conversion Register */\r
-\r
-#define RTCCTL0_L (HWREG8_L(RTCCTL0)) /* RTCCTL0 Register */\r
-#define RTCCTL0_H (HWREG8_H(RTCCTL0)) /* RTCCTL0 Register */\r
-#define RTCCTL1 (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */\r
-#define RTCCTL13_L (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */\r
-#define RTCCTL3 (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */\r
-#define RTCCTL13_H (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */\r
-#define RTCOCAL_L (HWREG8_L(RTCOCAL)) /* RTCOCAL Register */\r
-#define RTCOCAL_H (HWREG8_H(RTCOCAL)) /* RTCOCAL Register */\r
-#define RTCTCMP_L (HWREG8_L(RTCTCMP)) /* RTCTCMP Register */\r
-#define RTCTCMP_H (HWREG8_H(RTCTCMP)) /* RTCTCMP Register */\r
-#define RTCPS0CTL_L (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */\r
-#define RTCPS0CTL_H (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */\r
-#define RTCPS1CTL_L (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */\r
-#define RTCPS1CTL_H (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */\r
-#define RTCPS0 (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */\r
-#define RTCPS_L (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */\r
-#define RTCPS1 (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */\r
-#define RTCPS_H (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */\r
-#define RTCSEC (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */\r
-#define RTCTIM0_L (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */\r
-#define RTCMIN (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */\r
-#define RTCTIM0_H (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */\r
-#define RTCHOUR (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */\r
-#define RTCTIM1_L (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */\r
-#define RTCDOW (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */\r
-#define RTCTIM1_H (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */\r
-#define RTCDAY (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */\r
-#define RTCDATE_L (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */\r
-#define RTCMON (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */\r
-#define RTCDATE_H (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */\r
-#define RTCAMIN (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */\r
-#define RTCAMINHR_L (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */\r
-#define RTCAHOUR (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */\r
-#define RTCAMINHR_H (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */\r
-#define RTCADOW (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */\r
-#define RTCADOWDAY_L (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */\r
-#define RTCADAY (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */\r
-#define RTCADOWDAY_H (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */\r
-\r
-//*****************************************************************************\r
-// SCB Registers\r
-//*****************************************************************************\r
-#define SCB_CPUID (HWREG32(0xE000ED00)) /* CPUID Base Register */\r
-#define SCB_ICSR (HWREG32(0xE000ED04)) /* Interrupt Control State Register */\r
-#define SCB_VTOR (HWREG32(0xE000ED08)) /* Vector Table Offset Register */\r
-#define SCB_AIRCR (HWREG32(0xE000ED0C)) /* Application Interrupt/Reset Control Register */\r
-#define SCB_SCR (HWREG32(0xE000ED10)) /* System Control Register */\r
-#define SCB_CCR (HWREG32(0xE000ED14)) /* Configuration Control Register */\r
-#define SCB_SHPR1 (HWREG32(0xE000ED18)) /* System Handlers 4-7 Priority Register */\r
-#define SCB_SHPR2 (HWREG32(0xE000ED1C)) /* System Handlers 8-11 Priority Register */\r
-#define SCB_SHPR3 (HWREG32(0xE000ED20)) /* System Handlers 12-15 Priority Register */\r
-#define SCB_SHCSR (HWREG32(0xE000ED24)) /* System Handler Control and State Register */\r
-#define SCB_CFSR (HWREG32(0xE000ED28)) /* Configurable Fault Status Registers */\r
-#define SCB_HFSR (HWREG32(0xE000ED2C)) /* Hard Fault Status Register */\r
-#define SCB_DFSR (HWREG32(0xE000ED30)) /* Debug Fault Status Register */\r
-#define SCB_MMFAR (HWREG32(0xE000ED34)) /* Mem Manage Fault Address Register */\r
-#define SCB_BFAR (HWREG32(0xE000ED38)) /* Bus Fault Address Register */\r
-#define SCB_AFSR (HWREG32(0xE000ED3C)) /* Auxiliary Fault Status Register */\r
-#define SCB_PFR0 (HWREG32(0xE000ED40)) /* Processor Feature register0 */\r
-#define SCB_PFR1 (HWREG32(0xE000ED44)) /* Processor Feature register1 */\r
-#define SCB_DFR0 (HWREG32(0xE000ED48)) /* Debug Feature register0 */\r
-#define SCB_AFR0 (HWREG32(0xE000ED4C)) /* Auxiliary Feature register0 */\r
-#define SCB_MMFR0 (HWREG32(0xE000ED50)) /* Memory Model Feature register0 */\r
-#define SCB_MMFR1 (HWREG32(0xE000ED54)) /* Memory Model Feature register1 */\r
-#define SCB_MMFR2 (HWREG32(0xE000ED58)) /* Memory Model Feature register2 */\r
-#define SCB_MMFR3 (HWREG32(0xE000ED5C)) /* Memory Model Feature register3 */\r
-#define SCB_ISAR0 (HWREG32(0xE000ED60)) /* ISA Feature register0 */\r
-#define SCB_ISAR1 (HWREG32(0xE000ED64)) /* ISA Feature register1 */\r
-#define SCB_ISAR2 (HWREG32(0xE000ED68)) /* ISA Feature register2 */\r
-#define SCB_ISAR3 (HWREG32(0xE000ED6C)) /* ISA Feature register3 */\r
-#define SCB_ISAR4 (HWREG32(0xE000ED70)) /* ISA Feature register4 */\r
-#define SCB_CPACR (HWREG32(0xE000ED88)) /* Coprocessor Access Control Register */\r
-\r
-/* Register offsets from SCB_BASE address */\r
-#define OFS_SCB_CPUID (0x00000D00) /* CPUID Base Register */\r
-#define OFS_SCB_ICSR (0x00000D04) /* Interrupt Control State Register */\r
-#define OFS_SCB_VTOR (0x00000D08) /* Vector Table Offset Register */\r
-#define OFS_SCB_AIRCR (0x00000D0C) /* Application Interrupt/Reset Control Register */\r
-#define OFS_SCB_SCR (0x00000D10) /* System Control Register */\r
-#define OFS_SCB_CCR (0x00000D14) /* Configuration Control Register */\r
-#define OFS_SCB_SHPR1 (0x00000D18) /* System Handlers 4-7 Priority Register */\r
-#define OFS_SCB_SHPR2 (0x00000D1C) /* System Handlers 8-11 Priority Register */\r
-#define OFS_SCB_SHPR3 (0x00000D20) /* System Handlers 12-15 Priority Register */\r
-#define OFS_SCB_SHCSR (0x00000D24) /* System Handler Control and State Register */\r
-#define OFS_SCB_CFSR (0x00000D28) /* Configurable Fault Status Registers */\r
-#define OFS_SCB_HFSR (0x00000D2C) /* Hard Fault Status Register */\r
-#define OFS_SCB_DFSR (0x00000D30) /* Debug Fault Status Register */\r
-#define OFS_SCB_MMFAR (0x00000D34) /* Mem Manage Fault Address Register */\r
-#define OFS_SCB_BFAR (0x00000D38) /* Bus Fault Address Register */\r
-#define OFS_SCB_AFSR (0x00000D3C) /* Auxiliary Fault Status Register */\r
-#define OFS_SCB_PFR0 (0x00000D40) /* Processor Feature register0 */\r
-#define OFS_SCB_PFR1 (0x00000D44) /* Processor Feature register1 */\r
-#define OFS_SCB_DFR0 (0x00000D48) /* Debug Feature register0 */\r
-#define OFS_SCB_AFR0 (0x00000D4C) /* Auxiliary Feature register0 */\r
-#define OFS_SCB_MMFR0 (0x00000D50) /* Memory Model Feature register0 */\r
-#define OFS_SCB_MMFR1 (0x00000D54) /* Memory Model Feature register1 */\r
-#define OFS_SCB_MMFR2 (0x00000D58) /* Memory Model Feature register2 */\r
-#define OFS_SCB_MMFR3 (0x00000D5C) /* Memory Model Feature register3 */\r
-#define OFS_SCB_ISAR0 (0x00000D60) /* ISA Feature register0 */\r
-#define OFS_SCB_ISAR1 (0x00000D64) /* ISA Feature register1 */\r
-#define OFS_SCB_ISAR2 (0x00000D68) /* ISA Feature register2 */\r
-#define OFS_SCB_ISAR3 (0x00000D6C) /* ISA Feature register3 */\r
-#define OFS_SCB_ISAR4 (0x00000D70) /* ISA Feature register4 */\r
-#define OFS_SCB_CPACR (0x00000D88) /* Coprocessor Access Control Register */\r
-\r
-\r
-//*****************************************************************************\r
-// SCnSCB Registers\r
-//*****************************************************************************\r
-#define SCnSCB_ICTR (HWREG32(0xE000E004)) /* Interrupt Control Type Register */\r
-#define SCnSCB_ACTLR (HWREG32(0xE000E008)) /* Auxiliary Control Register */\r
-\r
-/* Register offsets from SCnSCB_BASE address */\r
-#define OFS_SCnSCB_ICTR (0x00000004) /* Interrupt Control Type Register */\r
-#define OFS_SCnSCB_ACTLR (0x00000008) /* Auxiliary Control Register */\r
-\r
-\r
-//*****************************************************************************\r
-// SYSCTL Registers\r
-//*****************************************************************************\r
-#define SYSCTL_REBOOT_CTL (HWREG32(0xE0043000)) /* Reboot Control Register */\r
-#define SYSCTL_NMI_CTLSTAT (HWREG32(0xE0043004)) /* NMI Control and Status Register */\r
-#define SYSCTL_WDTRESET_CTL (HWREG32(0xE0043008)) /* Watchdog Reset Control Register */\r
-#define SYSCTL_PERIHALT_CTL (HWREG32(0xE004300C)) /* Peripheral Halt Control Register */\r
-#define SYSCTL_SRAM_SIZE (HWREG32(0xE0043010)) /* SRAM Size Register */\r
-#define SYSCTL_SRAM_BANKEN (HWREG32(0xE0043014)) /* SRAM Bank Enable Register */\r
-#define SYSCTL_SRAM_BANKRET (HWREG32(0xE0043018)) /* SRAM Bank Retention Control Register */\r
-#define SYSCTL_FLASH_SIZE (HWREG32(0xE0043020)) /* Flash Size Register */\r
-#define SYSCTL_DIO_GLTFLT_CTL (HWREG32(0xE0043030)) /* Digital I/O Glitch Filter Control Register */\r
-#define SYSCTL_SECDATA_UNLOCK (HWREG32(0xE0043040)) /* IP Protected Secure Zone Data Access Unlock Register */\r
-#define SYSCTL_MASTER_UNLOCK (HWREG32(0xE0044000)) /* Master Unlock Register */\r
-#define SYSCTL_BOOTOVER_REQ0 (HWREG32(0xE0044004)) /* Boot Override Request Register */\r
-#define SYSCTL_BOOTOVER_REQ1 (HWREG32(0xE0044008)) /* Boot Override Request Register */\r
-#define SYSCTL_BOOTOVER_ACK (HWREG32(0xE004400C)) /* Boot Override Acknowledge Register */\r
-#define SYSCTL_RESET_REQ (HWREG32(0xE0044010)) /* Reset Request Register */\r
-#define SYSCTL_RESET_STATOVER (HWREG32(0xE0044014)) /* Reset Status and Override Register */\r
-#define SYSCTL_SYSTEM_STAT (HWREG32(0xE0044020)) /* System Status Register */\r
-\r
-/* Register offsets from SYSCTL_BASE address */\r
-#define OFS_SYSCTL_REBOOT_CTL (0x00000000) /* Reboot Control Register */\r
-#define OFS_SYSCTL_NMI_CTLSTAT (0x00000004) /* NMI Control and Status Register */\r
-#define OFS_SYSCTL_WDTRESET_CTL (0x00000008) /* Watchdog Reset Control Register */\r
-#define OFS_SYSCTL_PERIHALT_CTL (0x0000000c) /* Peripheral Halt Control Register */\r
-#define OFS_SYSCTL_SRAM_SIZE (0x00000010) /* SRAM Size Register */\r
-#define OFS_SYSCTL_SRAM_BANKEN (0x00000014) /* SRAM Bank Enable Register */\r
-#define OFS_SYSCTL_SRAM_BANKRET (0x00000018) /* SRAM Bank Retention Control Register */\r
-#define OFS_SYSCTL_FLASH_SIZE (0x00000020) /* Flash Size Register */\r
-#define OFS_SYSCTL_DIO_GLTFLT_CTL (0x00000030) /* Digital I/O Glitch Filter Control Register */\r
-#define OFS_SYSCTL_SECDATA_UNLOCK (0x00000040) /* IP Protected Secure Zone Data Access Unlock Register */\r
-#define OFS_SYSCTL_MASTER_UNLOCK (0x00001000) /* Master Unlock Register */\r
-#define OFS_SYSCTL_BOOTOVER_REQ0 (0x00001004) /* Boot Override Request Register */\r
-#define OFS_SYSCTL_BOOTOVER_REQ1 (0x00001008) /* Boot Override Request Register */\r
-#define OFS_SYSCTL_BOOTOVER_ACK (0x0000100c) /* Boot Override Acknowledge Register */\r
-#define OFS_SYSCTL_RESET_REQ (0x00001010) /* Reset Request Register */\r
-#define OFS_SYSCTL_RESET_STATOVER (0x00001014) /* Reset Status and Override Register */\r
-#define OFS_SYSCTL_SYSTEM_STAT (0x00001020) /* System Status Register */\r
-\r
-\r
-//*****************************************************************************\r
-// SYSTICK Registers\r
-//*****************************************************************************\r
-#define SYSTICK_STCSR (HWREG32(0xE000E010)) /* SysTick Control and Status Register */\r
-#define SYSTICK_STRVR (HWREG32(0xE000E014)) /* SysTick Reload Value Register */\r
-#define SYSTICK_STCVR (HWREG32(0xE000E018)) /* SysTick Current Value Register */\r
-#define SYSTICK_STCR (HWREG32(0xE000E01C)) /* SysTick Calibration Value Register */\r
-\r
-/* Register offsets from SYSTICK_BASE address */\r
-#define OFS_SYSTICK_STCSR (0x00000010) /* SysTick Control and Status Register */\r
-#define OFS_SYSTICK_STRVR (0x00000014) /* SysTick Reload Value Register */\r
-#define OFS_SYSTICK_STCVR (0x00000018) /* SysTick Current Value Register */\r
-#define OFS_SYSTICK_STCR (0x0000001C) /* SysTick Calibration Value Register */\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER32 Registers\r
-//*****************************************************************************\r
-#define TIMER32_LOAD1 (HWREG32(0x4000C000)) /* Timer 1 Load Register */\r
-#define TIMER32_VALUE1 (HWREG32(0x4000C004)) /* Timer 1 Current Value Register */\r
-#define TIMER32_CONTROL1 (HWREG32(0x4000C008)) /* Timer 1 Timer Control Register */\r
-#define TIMER32_INTCLR1 (HWREG32(0x4000C00C)) /* Timer 1 Interrupt Clear Register */\r
-#define TIMER32_RIS1 (HWREG32(0x4000C010)) /* Timer 1 Raw Interrupt Status Register */\r
-#define TIMER32_MIS1 (HWREG32(0x4000C014)) /* Timer 1 Interrupt Status Register */\r
-#define TIMER32_BGLOAD1 (HWREG32(0x4000C018)) /* Timer 1 Background Load Register */\r
-#define TIMER32_LOAD2 (HWREG32(0x4000C020)) /* Timer 2 Load Register */\r
-#define TIMER32_VALUE2 (HWREG32(0x4000C024)) /* Timer 2 Current Value Register */\r
-#define TIMER32_CONTROL2 (HWREG32(0x4000C028)) /* Timer 2 Timer Control Register */\r
-#define TIMER32_INTCLR2 (HWREG32(0x4000C02C)) /* Timer 2 Interrupt Clear Register */\r
-#define TIMER32_RIS2 (HWREG32(0x4000C030)) /* Timer 2 Raw Interrupt Status Register */\r
-#define TIMER32_MIS2 (HWREG32(0x4000C034)) /* Timer 2 Interrupt Status Register */\r
-#define TIMER32_BGLOAD2 (HWREG32(0x4000C038)) /* Timer 2 Background Load Register */\r
-\r
-/* Register offsets from TIMER32_BASE address */\r
-#define OFS_TIMER32_LOAD1 (0x00000000) /* Timer 1 Load Register */\r
-#define OFS_TIMER32_VALUE1 (0x00000004) /* Timer 1 Current Value Register */\r
-#define OFS_TIMER32_CONTROL1 (0x00000008) /* Timer 1 Timer Control Register */\r
-#define OFS_TIMER32_INTCLR1 (0x0000000C) /* Timer 1 Interrupt Clear Register */\r
-#define OFS_TIMER32_RIS1 (0x00000010) /* Timer 1 Raw Interrupt Status Register */\r
-#define OFS_TIMER32_MIS1 (0x00000014) /* Timer 1 Interrupt Status Register */\r
-#define OFS_TIMER32_BGLOAD1 (0x00000018) /* Timer 1 Background Load Register */\r
-#define OFS_TIMER32_LOAD2 (0x00000020) /* Timer 2 Load Register */\r
-#define OFS_TIMER32_VALUE2 (0x00000024) /* Timer 2 Current Value Register */\r
-#define OFS_TIMER32_CONTROL2 (0x00000028) /* Timer 2 Timer Control Register */\r
-#define OFS_TIMER32_INTCLR2 (0x0000002C) /* Timer 2 Interrupt Clear Register */\r
-#define OFS_TIMER32_RIS2 (0x00000030) /* Timer 2 Raw Interrupt Status Register */\r
-#define OFS_TIMER32_MIS2 (0x00000034) /* Timer 2 Interrupt Status Register */\r
-#define OFS_TIMER32_BGLOAD2 (0x00000038) /* Timer 2 Background Load Register */\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A0 Registers\r
-//*****************************************************************************\r
-#define TA0CTL (HWREG16(0x40000000)) /* TimerAx Control Register */\r
-#define TA0CCTL0 (HWREG16(0x40000002)) /* Timer_A Capture/Compare Control Register */\r
-#define TA0CCTL1 (HWREG16(0x40000004)) /* Timer_A Capture/Compare Control Register */\r
-#define TA0CCTL2 (HWREG16(0x40000006)) /* Timer_A Capture/Compare Control Register */\r
-#define TA0CCTL3 (HWREG16(0x40000008)) /* Timer_A Capture/Compare Control Register */\r
-#define TA0CCTL4 (HWREG16(0x4000000A)) /* Timer_A Capture/Compare Control Register */\r
-#define TA0CCTL5 (HWREG16(0x4000000C)) /* Timer_A Capture/Compare Control Register */\r
-#define TA0CCTL6 (HWREG16(0x4000000E)) /* Timer_A Capture/Compare Control Register */\r
-#define TA0R (HWREG16(0x40000010)) /* TimerA register */\r
-#define TA0CCR0 (HWREG16(0x40000012)) /* Timer_A Capture/Compare Register */\r
-#define TA0CCR1 (HWREG16(0x40000014)) /* Timer_A Capture/Compare Register */\r
-#define TA0CCR2 (HWREG16(0x40000016)) /* Timer_A Capture/Compare Register */\r
-#define TA0CCR3 (HWREG16(0x40000018)) /* Timer_A Capture/Compare Register */\r
-#define TA0CCR4 (HWREG16(0x4000001A)) /* Timer_A Capture/Compare Register */\r
-#define TA0CCR5 (HWREG16(0x4000001C)) /* Timer_A Capture/Compare Register */\r
-#define TA0CCR6 (HWREG16(0x4000001E)) /* Timer_A Capture/Compare Register */\r
-#define TA0EX0 (HWREG16(0x40000020)) /* TimerAx Expansion 0 Register */\r
-#define TA0IV (HWREG16(0x4000002E)) /* TimerAx Interrupt Vector Register */\r
-\r
-/* Register offsets from TIMER_A0_BASE address */\r
-#define OFS_TA0CTL (0x0000) /* TimerAx Control Register */\r
-#define OFS_TA0CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA0CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA0CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA0CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA0CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA0CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA0CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA0R (0x0010) /* TimerA register */\r
-#define OFS_TA0CCR0 (0x0012) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA0CCR1 (0x0014) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA0CCR2 (0x0016) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA0CCR3 (0x0018) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA0CCR4 (0x001A) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA0CCR5 (0x001C) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA0CCR6 (0x001E) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA0EX0 (0x0020) /* TimerAx Expansion 0 Register */\r
-#define OFS_TA0IV (0x002e) /* TimerAx Interrupt Vector Register */\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A1 Registers\r
-//*****************************************************************************\r
-#define TA1CTL (HWREG16(0x40000400)) /* TimerAx Control Register */\r
-#define TA1CCTL0 (HWREG16(0x40000402)) /* Timer_A Capture/Compare Control Register */\r
-#define TA1CCTL1 (HWREG16(0x40000404)) /* Timer_A Capture/Compare Control Register */\r
-#define TA1CCTL2 (HWREG16(0x40000406)) /* Timer_A Capture/Compare Control Register */\r
-#define TA1CCTL3 (HWREG16(0x40000408)) /* Timer_A Capture/Compare Control Register */\r
-#define TA1CCTL4 (HWREG16(0x4000040A)) /* Timer_A Capture/Compare Control Register */\r
-#define TA1CCTL5 (HWREG16(0x4000040C)) /* Timer_A Capture/Compare Control Register */\r
-#define TA1CCTL6 (HWREG16(0x4000040E)) /* Timer_A Capture/Compare Control Register */\r
-#define TA1R (HWREG16(0x40000410)) /* TimerA register */\r
-#define TA1CCR0 (HWREG16(0x40000412)) /* Timer_A Capture/Compare Register */\r
-#define TA1CCR1 (HWREG16(0x40000414)) /* Timer_A Capture/Compare Register */\r
-#define TA1CCR2 (HWREG16(0x40000416)) /* Timer_A Capture/Compare Register */\r
-#define TA1CCR3 (HWREG16(0x40000418)) /* Timer_A Capture/Compare Register */\r
-#define TA1CCR4 (HWREG16(0x4000041A)) /* Timer_A Capture/Compare Register */\r
-#define TA1CCR5 (HWREG16(0x4000041C)) /* Timer_A Capture/Compare Register */\r
-#define TA1CCR6 (HWREG16(0x4000041E)) /* Timer_A Capture/Compare Register */\r
-#define TA1EX0 (HWREG16(0x40000420)) /* TimerAx Expansion 0 Register */\r
-#define TA1IV (HWREG16(0x4000042E)) /* TimerAx Interrupt Vector Register */\r
-\r
-/* Register offsets from TIMER_A1_BASE address */\r
-#define OFS_TA1CTL (0x0000) /* TimerAx Control Register */\r
-#define OFS_TA1CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA1CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA1CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA1CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA1CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA1CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA1CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA1R (0x0010) /* TimerA register */\r
-#define OFS_TA1CCR0 (0x0012) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA1CCR1 (0x0014) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA1CCR2 (0x0016) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA1CCR3 (0x0018) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA1CCR4 (0x001A) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA1CCR5 (0x001C) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA1CCR6 (0x001E) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA1EX0 (0x0020) /* TimerAx Expansion 0 Register */\r
-#define OFS_TA1IV (0x002e) /* TimerAx Interrupt Vector Register */\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A2 Registers\r
-//*****************************************************************************\r
-#define TA2CTL (HWREG16(0x40000800)) /* TimerAx Control Register */\r
-#define TA2CCTL0 (HWREG16(0x40000802)) /* Timer_A Capture/Compare Control Register */\r
-#define TA2CCTL1 (HWREG16(0x40000804)) /* Timer_A Capture/Compare Control Register */\r
-#define TA2CCTL2 (HWREG16(0x40000806)) /* Timer_A Capture/Compare Control Register */\r
-#define TA2CCTL3 (HWREG16(0x40000808)) /* Timer_A Capture/Compare Control Register */\r
-#define TA2CCTL4 (HWREG16(0x4000080A)) /* Timer_A Capture/Compare Control Register */\r
-#define TA2CCTL5 (HWREG16(0x4000080C)) /* Timer_A Capture/Compare Control Register */\r
-#define TA2CCTL6 (HWREG16(0x4000080E)) /* Timer_A Capture/Compare Control Register */\r
-#define TA2R (HWREG16(0x40000810)) /* TimerA register */\r
-#define TA2CCR0 (HWREG16(0x40000812)) /* Timer_A Capture/Compare Register */\r
-#define TA2CCR1 (HWREG16(0x40000814)) /* Timer_A Capture/Compare Register */\r
-#define TA2CCR2 (HWREG16(0x40000816)) /* Timer_A Capture/Compare Register */\r
-#define TA2CCR3 (HWREG16(0x40000818)) /* Timer_A Capture/Compare Register */\r
-#define TA2CCR4 (HWREG16(0x4000081A)) /* Timer_A Capture/Compare Register */\r
-#define TA2CCR5 (HWREG16(0x4000081C)) /* Timer_A Capture/Compare Register */\r
-#define TA2CCR6 (HWREG16(0x4000081E)) /* Timer_A Capture/Compare Register */\r
-#define TA2EX0 (HWREG16(0x40000820)) /* TimerAx Expansion 0 Register */\r
-#define TA2IV (HWREG16(0x4000082E)) /* TimerAx Interrupt Vector Register */\r
-\r
-/* Register offsets from TIMER_A2_BASE address */\r
-#define OFS_TA2CTL (0x0000) /* TimerAx Control Register */\r
-#define OFS_TA2CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA2CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA2CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA2CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA2CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA2CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA2CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA2R (0x0010) /* TimerA register */\r
-#define OFS_TA2CCR0 (0x0012) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA2CCR1 (0x0014) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA2CCR2 (0x0016) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA2CCR3 (0x0018) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA2CCR4 (0x001A) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA2CCR5 (0x001C) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA2CCR6 (0x001E) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA2EX0 (0x0020) /* TimerAx Expansion 0 Register */\r
-#define OFS_TA2IV (0x002e) /* TimerAx Interrupt Vector Register */\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A3 Registers\r
-//*****************************************************************************\r
-#define TA3CTL (HWREG16(0x40000C00)) /* TimerAx Control Register */\r
-#define TA3CCTL0 (HWREG16(0x40000C02)) /* Timer_A Capture/Compare Control Register */\r
-#define TA3CCTL1 (HWREG16(0x40000C04)) /* Timer_A Capture/Compare Control Register */\r
-#define TA3CCTL2 (HWREG16(0x40000C06)) /* Timer_A Capture/Compare Control Register */\r
-#define TA3CCTL3 (HWREG16(0x40000C08)) /* Timer_A Capture/Compare Control Register */\r
-#define TA3CCTL4 (HWREG16(0x40000C0A)) /* Timer_A Capture/Compare Control Register */\r
-#define TA3CCTL5 (HWREG16(0x40000C0C)) /* Timer_A Capture/Compare Control Register */\r
-#define TA3CCTL6 (HWREG16(0x40000C0E)) /* Timer_A Capture/Compare Control Register */\r
-#define TA3R (HWREG16(0x40000C10)) /* TimerA register */\r
-#define TA3CCR0 (HWREG16(0x40000C12)) /* Timer_A Capture/Compare Register */\r
-#define TA3CCR1 (HWREG16(0x40000C14)) /* Timer_A Capture/Compare Register */\r
-#define TA3CCR2 (HWREG16(0x40000C16)) /* Timer_A Capture/Compare Register */\r
-#define TA3CCR3 (HWREG16(0x40000C18)) /* Timer_A Capture/Compare Register */\r
-#define TA3CCR4 (HWREG16(0x40000C1A)) /* Timer_A Capture/Compare Register */\r
-#define TA3CCR5 (HWREG16(0x40000C1C)) /* Timer_A Capture/Compare Register */\r
-#define TA3CCR6 (HWREG16(0x40000C1E)) /* Timer_A Capture/Compare Register */\r
-#define TA3EX0 (HWREG16(0x40000C20)) /* TimerAx Expansion 0 Register */\r
-#define TA3IV (HWREG16(0x40000C2E)) /* TimerAx Interrupt Vector Register */\r
-\r
-/* Register offsets from TIMER_A3_BASE address */\r
-#define OFS_TA3CTL (0x0000) /* TimerAx Control Register */\r
-#define OFS_TA3CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA3CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA3CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA3CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA3CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA3CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA3CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */\r
-#define OFS_TA3R (0x0010) /* TimerA register */\r
-#define OFS_TA3CCR0 (0x0012) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA3CCR1 (0x0014) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA3CCR2 (0x0016) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA3CCR3 (0x0018) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA3CCR4 (0x001A) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA3CCR5 (0x001C) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA3CCR6 (0x001E) /* Timer_A Capture/Compare Register */\r
-#define OFS_TA3EX0 (0x0020) /* TimerAx Expansion 0 Register */\r
-#define OFS_TA3IV (0x002e) /* TimerAx Interrupt Vector Register */\r
-\r
-\r
-//*****************************************************************************\r
-// TLV Registers\r
-//*****************************************************************************\r
-#define TLV_TLV_CHECKSUM (HWREG32(0x00201000)) /* TLV Checksum */\r
-#define TLV_DEVICE_INFO_TAG (HWREG32(0x00201004)) /* Device Info Tag */\r
-#define TLV_DEVICE_INFO_LEN (HWREG32(0x00201008)) /* Device Info Length */\r
-#define TLV_DEVICE_ID (HWREG32(0x0020100C)) /* Device ID */\r
-#define TLV_HWREV (HWREG32(0x00201010)) /* HW Revision */\r
-#define TLV_BCREV (HWREG32(0x00201014)) /* Boot Code Revision */\r
-#define TLV_ROM_DRVLIB_REV (HWREG32(0x00201018)) /* ROM Driver Library Revision */\r
-#define TLV_DIE_REC_TAG (HWREG32(0x0020101C)) /* Die Record Tag */\r
-#define TLV_DIE_REC_LEN (HWREG32(0x00201020)) /* Die Record Length */\r
-#define TLV_DIE_XPOS (HWREG32(0x00201024)) /* Die X-Position */\r
-#define TLV_DIE_YPOS (HWREG32(0x00201028)) /* Die Y-Position */\r
-#define TLV_WAFER_ID (HWREG32(0x0020102C)) /* Wafer ID */\r
-#define TLV_LOT_ID (HWREG32(0x00201030)) /* Lot ID */\r
-#define TLV_RESERVED0 (HWREG32(0x00201034)) /* Reserved */\r
-#define TLV_RESERVED1 (HWREG32(0x00201038)) /* Reserved */\r
-#define TLV_RESERVED2 (HWREG32(0x0020103C)) /* Reserved */\r
-#define TLV_TEST_RESULTS (HWREG32(0x00201040)) /* Test Results */\r
-#define TLV_CS_CAL_TAG (HWREG32(0x00201044)) /* Clock System Calibration Tag */\r
-#define TLV_CS_CAL_LEN (HWREG32(0x00201048)) /* Clock System Calibration Length */\r
-#define TLV_DCOIR_FCAL_RSEL04 (HWREG32(0x0020104C)) /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */\r
-#define TLV_DCOIR_FCAL_RSEL5 (HWREG32(0x00201050)) /* DCO IR mode: Frequency calibration for DCORSEL 5 */\r
-#define TLV_DCOIR_MAXPOSTUNE_RSEL04 (HWREG32(0x00201054)) /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */\r
-#define TLV_DCOIR_MAXNEGTUNE_RSEL04 (HWREG32(0x00201058)) /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */\r
-#define TLV_DCOIR_MAXPOSTUNE_RSEL5 (HWREG32(0x0020105C)) /* DCO IR mode: Max Positive Tune for DCORSEL 5 */\r
-#define TLV_DCOIR_MAXNEGTUNE_RSEL5 (HWREG32(0x00201060)) /* DCO IR mode: Max Negative Tune for DCORSEL 5 */\r
-#define TLV_DCOIR_CONSTK_RSEL04 (HWREG32(0x00201064)) /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */\r
-#define TLV_DCOIR_CONSTK_RSEL5 (HWREG32(0x00201068)) /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */\r
-#define TLV_DCOER_FCAL_RSEL04 (HWREG32(0x0020106C)) /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */\r
-#define TLV_DCOER_FCAL_RSEL5 (HWREG32(0x00201070)) /* DCO ER mode: Frequency calibration for DCORSEL 5 */\r
-#define TLV_DCOER_MAXPOSTUNE_RSEL04 (HWREG32(0x00201074)) /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */\r
-#define TLV_DCOER_MAXNEGTUNE_RSEL04 (HWREG32(0x00201078)) /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */\r
-#define TLV_DCOER_MAXPOSTUNE_RSEL5 (HWREG32(0x0020107C)) /* DCO ER mode: Max Positive Tune for DCORSEL 5 */\r
-#define TLV_DCOER_MAXNEGTUNE_RSEL5 (HWREG32(0x00201080)) /* DCO ER mode: Max Negative Tune for DCORSEL 5 */\r
-#define TLV_DCOER_CONSTK_RSEL04 (HWREG32(0x00201084)) /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */\r
-#define TLV_DCOER_CONSTK_RSEL5 (HWREG32(0x00201088)) /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */\r
-#define TLV_ADC14_CAL_TAG (HWREG32(0x0020108C)) /* ADC14 Calibration Tag */\r
-#define TLV_ADC14_CAL_LEN (HWREG32(0x00201090)) /* ADC14 Calibration Length */\r
-#define TLV_ADC14_GF_EXTREF30C (HWREG32(0x00201094)) /* ADC14 Gain Factor for External Reference 30°C */\r
-#define TLV_ADC14_GF_EXTREF85C (HWREG32(0x00201098)) /* ADC14 Gain Factor for External Reference 85°C */\r
-#define TLV_ADC14_GF_BUF_EXTREF30C (HWREG32(0x0020109C)) /* ADC14 Gain Factor for Buffered External Reference 30°C */\r
-#define TLV_ADC14_GF_BUF_EXTREF85C (HWREG32(0x002010A0)) /* ADC14 Gain Factor for Buffered External Reference 85°C */\r
-#define TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT0 (HWREG32(0x002010A4)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */\r
-#define TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT0 (HWREG32(0x002010A8)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */\r
-#define TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT1 (HWREG32(0x002010AC)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */\r
-#define TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT1 (HWREG32(0x002010B0)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */\r
-#define TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT0 (HWREG32(0x002010B4)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */\r
-#define TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT0 (HWREG32(0x002010B8)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */\r
-#define TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT1 (HWREG32(0x002010BC)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */\r
-#define TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT1 (HWREG32(0x002010C0)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */\r
-#define TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT0 (HWREG32(0x002010C4)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */\r
-#define TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT0 (HWREG32(0x002010C8)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */\r
-#define TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT1 (HWREG32(0x002010CC)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */\r
-#define TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT1 (HWREG32(0x002010D0)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */\r
-#define TLV_ADC14_OFFSET_VRSEL_1 (HWREG32(0x002010D4)) /* ADC14 Offset (ADC14VRSEL = 1h) */\r
-#define TLV_ADC14_OFFSET_VRSEL_E (HWREG32(0x002010D8)) /* ADC14 Offset (ADC14VRSEL = Eh) */\r
-#define TLV_ADC14_REF1P2V_TS30C (HWREG32(0x002010DC)) /* ADC14 1.2V Reference Temp. Sensor 30°C */\r
-#define TLV_ADC14_REF1P2V_TS85C (HWREG32(0x002010E0)) /* ADC14 1.2V Reference Temp. Sensor 85°C */\r
-#define TLV_ADC14_REF1P45V_TS30C (HWREG32(0x002010E4)) /* ADC14 1.45V Reference Temp. Sensor 30°C */\r
-#define TLV_ADC14_REF1P45V_TS85C (HWREG32(0x002010E8)) /* ADC14 1.45V Reference Temp. Sensor 85°C */\r
-#define TLV_ADC14_REF2P5V_TS30C (HWREG32(0x002010EC)) /* ADC14 2.5V Reference Temp. Sensor 30°C */\r
-#define TLV_ADC14_REF2P5V_TS85C (HWREG32(0x002010F0)) /* ADC14 2.5V Reference Temp. Sensor 85°C */\r
-#define TLV_REF_CAL_TAG (HWREG32(0x002010F4)) /* REF Calibration Tag */\r
-#define TLV_REF_CAL_LEN (HWREG32(0x002010F8)) /* REF Calibration Length */\r
-#define TLV_REF_1P2V (HWREG32(0x002010FC)) /* REF 1.2V Reference */\r
-#define TLV_REF_1P45V (HWREG32(0x00201100)) /* REF 1.45V Reference */\r
-#define TLV_REF_2P5V (HWREG32(0x00201104)) /* REF 2.5V Reference */\r
-#define TLV_RANDOM_NUM_TAG (HWREG32(0x00201108)) /* 128-bit Random Number Tag */\r
-#define TLV_RANDOM_NUM_LEN (HWREG32(0x0020110C)) /* 128-bit Random Number Length */\r
-#define TLV_RANDOM_NUM_1 (HWREG32(0x00201110)) /* 32-bit Random Number 1 */\r
-#define TLV_RANDOM_NUM_2 (HWREG32(0x00201114)) /* 32-bit Random Number 2 */\r
-#define TLV_RANDOM_NUM_3 (HWREG32(0x00201118)) /* 32-bit Random Number 3 */\r
-#define TLV_RANDOM_NUM_4 (HWREG32(0x0020111C)) /* 32-bit Random Number 4 */\r
-#define TLV_BSL_CFG_TAG (HWREG32(0x00201120)) /* BSL Configuration Tag */\r
-#define TLV_BSL_CFG_LEN (HWREG32(0x00201124)) /* BSL Configuration Length */\r
-#define TLV_BSL_PERIPHIF_SEL (HWREG32(0x00201128)) /* BSL Peripheral Interface Selection */\r
-#define TLV_BSL_PORTIF_CFG_UART (HWREG32(0x0020112C)) /* BSL Port Interface Configuration for UART */\r
-#define TLV_BSL_PORTIF_CFG_SPI (HWREG32(0x00201130)) /* BSL Port Interface Configuration for SPI */\r
-#define TLV_BSL_PORTIF_CFG_I2C (HWREG32(0x00201134)) /* BSL Port Interface Configuration for I2C */\r
-#define TLV_TLV_END (HWREG32(0x00201138)) /* TLV End Word */\r
-\r
-/* Register offsets from TLV_BASE address */\r
-#define OFS_TLV_TLV_CHECKSUM (0x00000000) /* TLV Checksum */\r
-#define OFS_TLV_DEVICE_INFO_TAG (0x00000004) /* Device Info Tag */\r
-#define OFS_TLV_DEVICE_INFO_LEN (0x00000008) /* Device Info Length */\r
-#define OFS_TLV_DEVICE_ID (0x0000000C) /* Device ID */\r
-#define OFS_TLV_HWREV (0x00000010) /* HW Revision */\r
-#define OFS_TLV_BCREV (0x00000014) /* Boot Code Revision */\r
-#define OFS_TLV_ROM_DRVLIB_REV (0x00000018) /* ROM Driver Library Revision */\r
-#define OFS_TLV_DIE_REC_TAG (0x0000001C) /* Die Record Tag */\r
-#define OFS_TLV_DIE_REC_LEN (0x00000020) /* Die Record Length */\r
-#define OFS_TLV_DIE_XPOS (0x00000024) /* Die X-Position */\r
-#define OFS_TLV_DIE_YPOS (0x00000028) /* Die Y-Position */\r
-#define OFS_TLV_WAFER_ID (0x0000002C) /* Wafer ID */\r
-#define OFS_TLV_LOT_ID (0x00000030) /* Lot ID */\r
-#define OFS_TLV_RESERVED0 (0x00000034) /* Reserved */\r
-#define OFS_TLV_RESERVED1 (0x00000038) /* Reserved */\r
-#define OFS_TLV_RESERVED2 (0x0000003c) /* Reserved */\r
-#define OFS_TLV_TEST_RESULTS (0x00000040) /* Test Results */\r
-#define OFS_TLV_CS_CAL_TAG (0x00000044) /* Clock System Calibration Tag */\r
-#define OFS_TLV_CS_CAL_LEN (0x00000048) /* Clock System Calibration Length */\r
-#define OFS_TLV_DCOIR_FCAL_RSEL04 (0x0000004c) /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */\r
-#define OFS_TLV_DCOIR_FCAL_RSEL5 (0x00000050) /* DCO IR mode: Frequency calibration for DCORSEL 5 */\r
-#define OFS_TLV_DCOIR_MAXPOSTUNE_RSEL04 (0x00000054) /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */\r
-#define OFS_TLV_DCOIR_MAXNEGTUNE_RSEL04 (0x00000058) /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */\r
-#define OFS_TLV_DCOIR_MAXPOSTUNE_RSEL5 (0x0000005c) /* DCO IR mode: Max Positive Tune for DCORSEL 5 */\r
-#define OFS_TLV_DCOIR_MAXNEGTUNE_RSEL5 (0x00000060) /* DCO IR mode: Max Negative Tune for DCORSEL 5 */\r
-#define OFS_TLV_DCOIR_CONSTK_RSEL04 (0x00000064) /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */\r
-#define OFS_TLV_DCOIR_CONSTK_RSEL5 (0x00000068) /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */\r
-#define OFS_TLV_DCOER_FCAL_RSEL04 (0x0000006c) /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */\r
-#define OFS_TLV_DCOER_FCAL_RSEL5 (0x00000070) /* DCO ER mode: Frequency calibration for DCORSEL 5 */\r
-#define OFS_TLV_DCOER_MAXPOSTUNE_RSEL04 (0x00000074) /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */\r
-#define OFS_TLV_DCOER_MAXNEGTUNE_RSEL04 (0x00000078) /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */\r
-#define OFS_TLV_DCOER_MAXPOSTUNE_RSEL5 (0x0000007c) /* DCO ER mode: Max Positive Tune for DCORSEL 5 */\r
-#define OFS_TLV_DCOER_MAXNEGTUNE_RSEL5 (0x00000080) /* DCO ER mode: Max Negative Tune for DCORSEL 5 */\r
-#define OFS_TLV_DCOER_CONSTK_RSEL04 (0x00000084) /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */\r
-#define OFS_TLV_DCOER_CONSTK_RSEL5 (0x00000088) /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */\r
-#define OFS_TLV_ADC14_CAL_TAG (0x0000008C) /* ADC14 Calibration Tag */\r
-#define OFS_TLV_ADC14_CAL_LEN (0x00000090) /* ADC14 Calibration Length */\r
-#define OFS_TLV_ADC14_GF_EXTREF30C (0x00000094) /* ADC14 Gain Factor for External Reference 30°C */\r
-#define OFS_TLV_ADC14_GF_EXTREF85C (0x00000098) /* ADC14 Gain Factor for External Reference 85°C */\r
-#define OFS_TLV_ADC14_GF_BUF_EXTREF30C (0x0000009C) /* ADC14 Gain Factor for Buffered External Reference 30°C */\r
-#define OFS_TLV_ADC14_GF_BUF_EXTREF85C (0x000000A0) /* ADC14 Gain Factor for Buffered External Reference 85°C */\r
-#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT0 (0x000000A4) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */\r
-#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT0 (0x000000A8) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */\r
-#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT1 (0x000000AC) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */\r
-#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT1 (0x000000B0) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */\r
-#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT0 (0x000000B4) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */\r
-#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT0 (0x000000B8) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */\r
-#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT1 (0x000000BC) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */\r
-#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT1 (0x000000C0) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */\r
-#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT0 (0x000000C4) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */\r
-#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT0 (0x000000C8) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */\r
-#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT1 (0x000000CC) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */\r
-#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT1 (0x000000D0) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */\r
-#define OFS_TLV_ADC14_OFFSET_VRSEL_1 (0x000000D4) /* ADC14 Offset (ADC14VRSEL = 1h) */\r
-#define OFS_TLV_ADC14_OFFSET_VRSEL_E (0x000000D8) /* ADC14 Offset (ADC14VRSEL = Eh) */\r
-#define OFS_TLV_ADC14_REF1P2V_TS30C (0x000000DC) /* ADC14 1.2V Reference Temp. Sensor 30°C */\r
-#define OFS_TLV_ADC14_REF1P2V_TS85C (0x000000E0) /* ADC14 1.2V Reference Temp. Sensor 85°C */\r
-#define OFS_TLV_ADC14_REF1P45V_TS30C (0x000000E4) /* ADC14 1.45V Reference Temp. Sensor 30°C */\r
-#define OFS_TLV_ADC14_REF1P45V_TS85C (0x000000E8) /* ADC14 1.45V Reference Temp. Sensor 85°C */\r
-#define OFS_TLV_ADC14_REF2P5V_TS30C (0x000000EC) /* ADC14 2.5V Reference Temp. Sensor 30°C */\r
-#define OFS_TLV_ADC14_REF2P5V_TS85C (0x000000F0) /* ADC14 2.5V Reference Temp. Sensor 85°C */\r
-#define OFS_TLV_REF_CAL_TAG (0x000000F4) /* REF Calibration Tag */\r
-#define OFS_TLV_REF_CAL_LEN (0x000000F8) /* REF Calibration Length */\r
-#define OFS_TLV_REF_1P2V (0x000000FC) /* REF 1.2V Reference */\r
-#define OFS_TLV_REF_1P45V (0x00000100) /* REF 1.45V Reference */\r
-#define OFS_TLV_REF_2P5V (0x00000104) /* REF 2.5V Reference */\r
-#define OFS_TLV_RANDOM_NUM_TAG (0x00000108) /* 128-bit Random Number Tag */\r
-#define OFS_TLV_RANDOM_NUM_LEN (0x0000010C) /* 128-bit Random Number Length */\r
-#define OFS_TLV_RANDOM_NUM_1 (0x00000110) /* 32-bit Random Number 1 */\r
-#define OFS_TLV_RANDOM_NUM_2 (0x00000114) /* 32-bit Random Number 2 */\r
-#define OFS_TLV_RANDOM_NUM_3 (0x00000118) /* 32-bit Random Number 3 */\r
-#define OFS_TLV_RANDOM_NUM_4 (0x0000011C) /* 32-bit Random Number 4 */\r
-#define OFS_TLV_BSL_CFG_TAG (0x00000120) /* BSL Configuration Tag */\r
-#define OFS_TLV_BSL_CFG_LEN (0x00000124) /* BSL Configuration Length */\r
-#define OFS_TLV_BSL_PERIPHIF_SEL (0x00000128) /* BSL Peripheral Interface Selection */\r
-#define OFS_TLV_BSL_PORTIF_CFG_UART (0x0000012C) /* BSL Port Interface Configuration for UART */\r
-#define OFS_TLV_BSL_PORTIF_CFG_SPI (0x00000130) /* BSL Port Interface Configuration for SPI */\r
-#define OFS_TLV_BSL_PORTIF_CFG_I2C (0x00000134) /* BSL Port Interface Configuration for I2C */\r
-#define OFS_TLV_TLV_END (0x00000138) /* TLV End Word */\r
-\r
-\r
-//*****************************************************************************\r
-// WDT_A Registers\r
-//*****************************************************************************\r
-#define WDTCTL (HWREG16(0x4000480C)) /* Watchdog Timer Control Register */\r
-\r
-/* Register offsets from WDT_A_BASE address */\r
-#define OFS_WDTCTL (0x000c) /* Watchdog Timer Control Register */\r
-\r
+/* System Header */\r
+#include "system_msp432p401r.h"\r
+\r
+/******************************************************************************\r
+* Definition of standard bits *\r
+******************************************************************************/\r
+#define BIT0 (uint16_t)(0x0001)\r
+#define BIT1 (uint16_t)(0x0002)\r
+#define BIT2 (uint16_t)(0x0004)\r
+#define BIT3 (uint16_t)(0x0008)\r
+#define BIT4 (uint16_t)(0x0010)\r
+#define BIT5 (uint16_t)(0x0020)\r
+#define BIT6 (uint16_t)(0x0040)\r
+#define BIT7 (uint16_t)(0x0080)\r
+#define BIT8 (uint16_t)(0x0100)\r
+#define BIT9 (uint16_t)(0x0200)\r
+#define BITA (uint16_t)(0x0400)\r
+#define BITB (uint16_t)(0x0800)\r
+#define BITC (uint16_t)(0x1000)\r
+#define BITD (uint16_t)(0x2000)\r
+#define BITE (uint16_t)(0x4000)\r
+#define BITF (uint16_t)(0x8000)\r
+#define BIT(x) ((uint16_t)1 << (x))\r
+\r
+/******************************************************************************\r
+* Device and peripheral memory map *\r
+******************************************************************************/\r
+/** @addtogroup MSP432P401R_MemoryMap MSP432P401R Memory Mapping\r
+ @{\r
+*/\r
+\r
+#define FLASH_BASE ((uint32_t)0x00000000) /**< Main Flash memory start address */\r
+#define SRAM_BASE ((uint32_t)0x20000000) /**< SRAM memory start address */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /**< Peripherals start address */\r
+#define PERIPH_BASE2 ((uint32_t)0xE0000000) /**< Peripherals start address */\r
+\r
+#define ADC14_BASE (PERIPH_BASE +0x00012000) /**< Base address of module ADC14 registers */\r
+#define AES256_BASE (PERIPH_BASE +0x00003C00) /**< Base address of module AES256 registers */\r
+#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /**< Base address of module CAPTIO0 registers */\r
+#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /**< Base address of module CAPTIO1 registers */\r
+#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /**< Base address of module COMP_E0 registers */\r
+#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /**< Base address of module COMP_E1 registers */\r
+#define CRC32_BASE (PERIPH_BASE +0x00004000) /**< Base address of module CRC32 registers */\r
+#define CS_BASE (PERIPH_BASE +0x00010400) /**< Base address of module CS registers */\r
+#define DIO_BASE (PERIPH_BASE +0x00004C00) /**< Base address of module DIO registers */\r
+#define DMA_BASE (PERIPH_BASE +0x0000E000) /**< Base address of module DMA registers */\r
+#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /**< Base address of module EUSCI_A0 registers */\r
+#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /**< Base address of module EUSCI_A0 registers */\r
+#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /**< Base address of module EUSCI_A1 registers */\r
+#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /**< Base address of module EUSCI_A1 registers */\r
+#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /**< Base address of module EUSCI_A2 registers */\r
+#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /**< Base address of module EUSCI_A2 registers */\r
+#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /**< Base address of module EUSCI_A3 registers */\r
+#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /**< Base address of module EUSCI_A3 registers */\r
+#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /**< Base address of module EUSCI_B0 registers */\r
+#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /**< Base address of module EUSCI_B0 registers */\r
+#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /**< Base address of module EUSCI_B1 registers */\r
+#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /**< Base address of module EUSCI_B1 registers */\r
+#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /**< Base address of module EUSCI_B2 registers */\r
+#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /**< Base address of module EUSCI_B2 registers */\r
+#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /**< Base address of module EUSCI_B3 registers */\r
+#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /**< Base address of module EUSCI_B3 registers */\r
+#define FLCTL_BASE (PERIPH_BASE +0x00011000) /**< Base address of module FLCTL registers */\r
+#define PCM_BASE (PERIPH_BASE +0x00010000) /**< Base address of module PCM registers */\r
+#define PMAP_BASE (PERIPH_BASE +0x00005000) /**< Base address of module PMAP registers */\r
+#define PSS_BASE (PERIPH_BASE +0x00010800) /**< Base address of module PSS registers */\r
+#define REF_A_BASE (PERIPH_BASE +0x00003000) /**< Base address of module REF_A registers */\r
+#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /**< Base address of module RSTCTL registers */\r
+#define RTC_C_BASE (PERIPH_BASE +0x00004400) /**< Base address of module RTC_C registers */\r
+#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /**< Base address of module RTC_C registers */\r
+#define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /**< Base address of module SYSCTL registers */\r
+#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /**< Base address of module TIMER32 registers */\r
+#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /**< Base address of module TIMER_A0 registers */\r
+#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /**< Base address of module TIMER_A1 registers */\r
+#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /**< Base address of module TIMER_A2 registers */\r
+#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /**< Base address of module TIMER_A3 registers */\r
+#define TLV_BASE ((uint32_t)0x00201000) /**< Base address of module TLV registers */\r
+#define WDT_A_BASE (PERIPH_BASE +0x00004800) /**< Base address of module WDT_A registers */\r
+\r
+\r
+/*@}*/ /* end of group MSP432P401R_MemoryMap */\r
+\r
+/******************************************************************************\r
+* Definitions for bit band access *\r
+******************************************************************************/\r
+#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000))\r
+#define BITBAND_PERI_BASE ((uint32_t)(0x42000000))\r
+\r
+/* SRAM allows 32 bit bit band access */\r
+#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&x) - SRAM_BASE )*32 + b*4)))\r
+/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */\r
+#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&x) - PERIPH_BASE)*32 + b*4)))\r
+\r
+/******************************************************************************\r
+* Peripheral register definitions *\r
+******************************************************************************/\r
+/** @addtogroup MSP432P401R_Peripherals MSP432P401R Peripherals\r
+ MSP432P401R Device Specific Peripheral registers structures\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM )\r
+#pragma anon_unions\r
+#endif\r
\r
-//*****************************************************************************\r
-// CMSIS-format peripheral registers\r
-//*****************************************************************************\r
\r
-//*****************************************************************************\r
-// ADC14 Registers\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* ADC14 Registers\r
+******************************************************************************/\r
+/** @addtogroup ADC14 MSP432P401R (ADC14)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* ADC14CTL0 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14CTL0 Bits */\r
- __IO uint32_t bSC : 1; /* ADC14 start conversion */\r
- __IO uint32_t bENC : 1; /* ADC14 enable conversion */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bON : 1; /* ADC14 on */\r
- __I uint32_t bRESERVED1 : 2; /* Reserved */\r
- __IO uint32_t bMSC : 1; /* ADC14 multiple sample and conversion */\r
- __IO uint32_t bSHT0 : 4; /* ADC14 sample-and-hold time */\r
- __IO uint32_t bSHT1 : 4; /* ADC14 sample-and-hold time */\r
- __I uint32_t bBUSY : 1; /* ADC14 busy */\r
- __IO uint32_t bCONSEQ : 2; /* ADC14 conversion sequence mode select */\r
- __IO uint32_t bSSEL : 3; /* ADC14 clock source select */\r
- __IO uint32_t bDIV : 3; /* ADC14 clock divider */\r
- __IO uint32_t bISSH : 1; /* ADC14 invert signal sample-and-hold */\r
- __IO uint32_t bSHP : 1; /* ADC14 sample-and-hold pulse-mode select */\r
- __IO uint32_t bSHS : 3; /* ADC14 sample-and-hold source select */\r
- __IO uint32_t bPDIV : 2; /* ADC14 predivider */\r
- } b;\r
- } rCTL0;\r
- union { /* ADC14CTL1 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14CTL1 Bits */\r
- __IO uint32_t bPWRMD : 2; /* ADC14 power modes */\r
- __IO uint32_t bREFBURST : 1; /* ADC14 reference buffer burst */\r
- __IO uint32_t bDF : 1; /* ADC14 data read-back format */\r
- __IO uint32_t bRES : 2; /* ADC14 resolution */\r
- __I uint32_t bRESERVED0 : 10; /* Reserved */\r
- __IO uint32_t bCSTARTADD : 5; /* ADC14 conversion start address */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bBATMAP : 1; /* Controls 1/2 AVCC ADC input channel selection */\r
- __IO uint32_t bTCMAP : 1; /* Controls temperature sensor ADC input channel selection */\r
- __IO uint32_t bCH0MAP : 1; /* Controls internal channel 0 selection to ADC input channel MAX-2 */\r
- __IO uint32_t bCH1MAP : 1; /* Controls internal channel 1 selection to ADC input channel MAX-3 */\r
- __IO uint32_t bCH2MAP : 1; /* Controls internal channel 2 selection to ADC input channel MAX-4 */\r
- __IO uint32_t bCH3MAP : 1; /* Controls internal channel 3 selection to ADC input channel MAX-5 */\r
- __I uint32_t bRESERVED2 : 4; /* Reserved */\r
- } b;\r
- } rCTL1;\r
- union { /* ADC14LO0 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14LO0 Bits */\r
- __IO uint32_t bLO0 : 16; /* Low threshold 0 */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rLO0;\r
- union { /* ADC14HI0 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14HI0 Bits */\r
- __IO uint32_t bHI0 : 16; /* High threshold 0 */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rHI0;\r
- union { /* ADC14LO1 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14LO1 Bits */\r
- __IO uint32_t bLO1 : 16; /* Low threshold 1 */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rLO1;\r
- union { /* ADC14HI1 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14HI1 Bits */\r
- __IO uint32_t bHI1 : 16; /* High threshold 1 */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rHI1;\r
- union { /* ADC14MCTL0 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL0 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL0;\r
- union { /* ADC14MCTL1 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL1 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL1;\r
- union { /* ADC14MCTL2 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL2 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL2;\r
- union { /* ADC14MCTL3 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL3 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL3;\r
- union { /* ADC14MCTL4 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL4 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL4;\r
- union { /* ADC14MCTL5 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL5 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL5;\r
- union { /* ADC14MCTL6 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL6 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL6;\r
- union { /* ADC14MCTL7 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL7 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL7;\r
- union { /* ADC14MCTL8 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL8 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL8;\r
- union { /* ADC14MCTL9 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL9 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL9;\r
- union { /* ADC14MCTL10 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL10 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL10;\r
- union { /* ADC14MCTL11 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL11 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL11;\r
- union { /* ADC14MCTL12 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL12 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL12;\r
- union { /* ADC14MCTL13 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL13 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL13;\r
- union { /* ADC14MCTL14 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL14 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL14;\r
- union { /* ADC14MCTL15 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL15 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL15;\r
- union { /* ADC14MCTL16 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL16 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL16;\r
- union { /* ADC14MCTL17 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL17 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL17;\r
- union { /* ADC14MCTL18 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL18 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL18;\r
- union { /* ADC14MCTL19 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL19 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL19;\r
- union { /* ADC14MCTL20 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL20 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL20;\r
- union { /* ADC14MCTL21 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL21 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL21;\r
- union { /* ADC14MCTL22 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL22 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL22;\r
- union { /* ADC14MCTL23 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL23 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL23;\r
- union { /* ADC14MCTL24 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL24 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL24;\r
- union { /* ADC14MCTL25 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL25 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL25;\r
- union { /* ADC14MCTL26 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL26 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL26;\r
- union { /* ADC14MCTL27 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL27 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL27;\r
- union { /* ADC14MCTL28 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL28 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL28;\r
- union { /* ADC14MCTL29 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL29 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL29;\r
- union { /* ADC14MCTL30 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL30 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL30;\r
- union { /* ADC14MCTL31 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MCTL31 Bits */\r
- __IO uint32_t bINCH : 5; /* Input channel select */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bEOS : 1; /* End of sequence */\r
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bDIF : 1; /* Differential mode */\r
- __IO uint32_t bWINC : 1; /* Comparator window enable */\r
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rMCTL31;\r
- union { /* ADC14MEM0 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM0 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM0;\r
- union { /* ADC14MEM1 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM1 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM1;\r
- union { /* ADC14MEM2 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM2 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM2;\r
- union { /* ADC14MEM3 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM3 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM3;\r
- union { /* ADC14MEM4 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM4 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM4;\r
- union { /* ADC14MEM5 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM5 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM5;\r
- union { /* ADC14MEM6 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM6 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM6;\r
- union { /* ADC14MEM7 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM7 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM7;\r
- union { /* ADC14MEM8 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM8 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM8;\r
- union { /* ADC14MEM9 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM9 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM9;\r
- union { /* ADC14MEM10 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM10 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM10;\r
- union { /* ADC14MEM11 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM11 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM11;\r
- union { /* ADC14MEM12 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM12 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM12;\r
- union { /* ADC14MEM13 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM13 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM13;\r
- union { /* ADC14MEM14 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM14 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM14;\r
- union { /* ADC14MEM15 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM15 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM15;\r
- union { /* ADC14MEM16 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM16 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM16;\r
- union { /* ADC14MEM17 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM17 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM17;\r
- union { /* ADC14MEM18 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM18 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM18;\r
- union { /* ADC14MEM19 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM19 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM19;\r
- union { /* ADC14MEM20 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM20 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM20;\r
- union { /* ADC14MEM21 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM21 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM21;\r
- union { /* ADC14MEM22 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM22 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM22;\r
- union { /* ADC14MEM23 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM23 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM23;\r
- union { /* ADC14MEM24 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM24 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM24;\r
- union { /* ADC14MEM25 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM25 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM25;\r
- union { /* ADC14MEM26 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM26 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM26;\r
- union { /* ADC14MEM27 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM27 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM27;\r
- union { /* ADC14MEM28 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM28 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM28;\r
- union { /* ADC14MEM29 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM29 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM29;\r
- union { /* ADC14MEM30 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM30 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM30;\r
- union { /* ADC14MEM31 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14MEM31 Bits */\r
- __IO uint32_t bCONVRES : 16; /* Conversion Result */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMEM31;\r
- uint8_t RESERVED0[36];\r
- union { /* ADC14IER0 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14IER0 Bits */\r
- __IO uint32_t bIE0 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE1 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE2 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE3 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE4 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE5 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE6 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE7 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE8 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE9 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE10 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE11 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE12 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE13 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE14 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE15 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE16 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE17 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE18 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE19 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE20 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE21 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE22 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE23 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE24 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE25 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE26 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE27 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE28 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE29 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE30 : 1; /* Interrupt enable */\r
- __IO uint32_t bIE31 : 1; /* Interrupt enable */\r
- } b;\r
- } rIER0;\r
- union { /* ADC14IER1 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14IER1 Bits */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bINIE : 1; /* Interrupt enable for ADC14MEMx within comparator window */\r
- __IO uint32_t bLOIE : 1; /* Interrupt enable for ADC14MEMx below comparator window */\r
- __IO uint32_t bHIIE : 1; /* Interrupt enable for ADC14MEMx above comparator window */\r
- __IO uint32_t bOVIE : 1; /* ADC14MEMx overflow-interrupt enable */\r
- __IO uint32_t bTOVIE : 1; /* ADC14 conversion-time-overflow interrupt enable */\r
- __IO uint32_t bRDYIE : 1; /* ADC14 local buffered reference ready interrupt enable */\r
- __I uint32_t bRESERVED1 : 25; /* Reserved */\r
- } b;\r
- } rIER1;\r
- union { /* ADC14IFGR0 Register */\r
- __I uint32_t r;\r
- struct { /* ADC14IFGR0 Bits */\r
- __I uint32_t bIFG0 : 1; /* ADC14MEM0 interrupt flag */\r
- __I uint32_t bIFG1 : 1; /* ADC14MEM1 interrupt flag */\r
- __I uint32_t bIFG2 : 1; /* ADC14MEM2 interrupt flag */\r
- __I uint32_t bIFG3 : 1; /* ADC14MEM3 interrupt flag */\r
- __I uint32_t bIFG4 : 1; /* ADC14MEM4 interrupt flag */\r
- __I uint32_t bIFG5 : 1; /* ADC14MEM5 interrupt flag */\r
- __I uint32_t bIFG6 : 1; /* ADC14MEM6 interrupt flag */\r
- __I uint32_t bIFG7 : 1; /* ADC14MEM7 interrupt flag */\r
- __I uint32_t bIFG8 : 1; /* ADC14MEM8 interrupt flag */\r
- __I uint32_t bIFG9 : 1; /* ADC14MEM9 interrupt flag */\r
- __I uint32_t bIFG10 : 1; /* ADC14MEM10 interrupt flag */\r
- __I uint32_t bIFG11 : 1; /* ADC14MEM11 interrupt flag */\r
- __I uint32_t bIFG12 : 1; /* ADC14MEM12 interrupt flag */\r
- __I uint32_t bIFG13 : 1; /* ADC14MEM13 interrupt flag */\r
- __I uint32_t bIFG14 : 1; /* ADC14MEM14 interrupt flag */\r
- __I uint32_t bIFG15 : 1; /* ADC14MEM15 interrupt flag */\r
- __I uint32_t bIFG16 : 1; /* ADC14MEM16 interrupt flag */\r
- __I uint32_t bIFG17 : 1; /* ADC14MEM17 interrupt flag */\r
- __I uint32_t bIFG18 : 1; /* ADC14MEM18 interrupt flag */\r
- __I uint32_t bIFG19 : 1; /* ADC14MEM19 interrupt flag */\r
- __I uint32_t bIFG20 : 1; /* ADC14MEM20 interrupt flag */\r
- __I uint32_t bIFG21 : 1; /* ADC14MEM21 interrupt flag */\r
- __I uint32_t bIFG22 : 1; /* ADC14MEM22 interrupt flag */\r
- __I uint32_t bIFG23 : 1; /* ADC14MEM23 interrupt flag */\r
- __I uint32_t bIFG24 : 1; /* ADC14MEM24 interrupt flag */\r
- __I uint32_t bIFG25 : 1; /* ADC14MEM25 interrupt flag */\r
- __I uint32_t bIFG26 : 1; /* ADC14MEM26 interrupt flag */\r
- __I uint32_t bIFG27 : 1; /* ADC14MEM27 interrupt flag */\r
- __I uint32_t bIFG28 : 1; /* ADC14MEM28 interrupt flag */\r
- __I uint32_t bIFG29 : 1; /* ADC14MEM29 interrupt flag */\r
- __I uint32_t bIFG30 : 1; /* ADC14MEM30 interrupt flag */\r
- __I uint32_t bIFG31 : 1; /* ADC14MEM31 interrupt flag */\r
- } b;\r
- } rIFGR0;\r
- union { /* ADC14IFGR1 Register */\r
- __I uint32_t r;\r
- struct { /* ADC14IFGR1 Bits */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __I uint32_t bINIFG : 1; /* Interrupt flag for ADC14MEMx within comparator window */\r
- __I uint32_t bLOIFG : 1; /* Interrupt flag for ADC14MEMx below comparator window */\r
- __I uint32_t bHIIFG : 1; /* Interrupt flag for ADC14MEMx above comparator window */\r
- __I uint32_t bOVIFG : 1; /* ADC14MEMx overflow interrupt flag */\r
- __I uint32_t bTOVIFG : 1; /* ADC14 conversion time overflow interrupt flag */\r
- __I uint32_t bRDYIFG : 1; /* ADC14 local buffered reference ready interrupt flag */\r
- __I uint32_t bRESERVED1 : 25; /* Reserved */\r
- } b;\r
- } rIFGR1;\r
- union { /* ADC14CLRIFGR0 Register */\r
- __O uint32_t r;\r
- struct { /* ADC14CLRIFGR0 Bits */\r
- __O uint32_t bCLRIFG0 : 1; /* clear ADC14IFG0 */\r
- __O uint32_t bCLRIFG1 : 1; /* clear ADC14IFG1 */\r
- __O uint32_t bCLRIFG2 : 1; /* clear ADC14IFG2 */\r
- __O uint32_t bCLRIFG3 : 1; /* clear ADC14IFG3 */\r
- __O uint32_t bCLRIFG4 : 1; /* clear ADC14IFG4 */\r
- __O uint32_t bCLRIFG5 : 1; /* clear ADC14IFG5 */\r
- __O uint32_t bCLRIFG6 : 1; /* clear ADC14IFG6 */\r
- __O uint32_t bCLRIFG7 : 1; /* clear ADC14IFG7 */\r
- __O uint32_t bCLRIFG8 : 1; /* clear ADC14IFG8 */\r
- __O uint32_t bCLRIFG9 : 1; /* clear ADC14IFG9 */\r
- __O uint32_t bCLRIFG10 : 1; /* clear ADC14IFG10 */\r
- __O uint32_t bCLRIFG11 : 1; /* clear ADC14IFG11 */\r
- __O uint32_t bCLRIFG12 : 1; /* clear ADC14IFG12 */\r
- __O uint32_t bCLRIFG13 : 1; /* clear ADC14IFG13 */\r
- __O uint32_t bCLRIFG14 : 1; /* clear ADC14IFG14 */\r
- __O uint32_t bCLRIFG15 : 1; /* clear ADC14IFG15 */\r
- __O uint32_t bCLRIFG16 : 1; /* clear ADC14IFG16 */\r
- __O uint32_t bCLRIFG17 : 1; /* clear ADC14IFG17 */\r
- __O uint32_t bCLRIFG18 : 1; /* clear ADC14IFG18 */\r
- __O uint32_t bCLRIFG19 : 1; /* clear ADC14IFG19 */\r
- __O uint32_t bCLRIFG20 : 1; /* clear ADC14IFG20 */\r
- __O uint32_t bCLRIFG21 : 1; /* clear ADC14IFG21 */\r
- __O uint32_t bCLRIFG22 : 1; /* clear ADC14IFG22 */\r
- __O uint32_t bCLRIFG23 : 1; /* clear ADC14IFG23 */\r
- __O uint32_t bCLRIFG24 : 1; /* clear ADC14IFG24 */\r
- __O uint32_t bCLRIFG25 : 1; /* clear ADC14IFG25 */\r
- __O uint32_t bCLRIFG26 : 1; /* clear ADC14IFG26 */\r
- __O uint32_t bCLRIFG27 : 1; /* clear ADC14IFG27 */\r
- __O uint32_t bCLRIFG28 : 1; /* clear ADC14IFG28 */\r
- __O uint32_t bCLRIFG29 : 1; /* clear ADC14IFG29 */\r
- __O uint32_t bCLRIFG30 : 1; /* clear ADC14IFG30 */\r
- __O uint32_t bCLRIFG31 : 1; /* clear ADC14IFG31 */\r
- } b;\r
- } rCLRIFGR0;\r
- union { /* ADC14CLRIFGR1 Register */\r
- __IO uint32_t r;\r
- struct { /* ADC14CLRIFGR1 Bits */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __O uint32_t bCLRINIFG : 1; /* clear ADC14INIFG */\r
- __O uint32_t bCLRLOIFG : 1; /* clear ADC14LOIFG */\r
- __O uint32_t bCLRHIIFG : 1; /* clear ADC14HIIFG */\r
- __O uint32_t bCLROVIFG : 1; /* clear ADC14OVIFG */\r
- __O uint32_t bCLRTOVIFG : 1; /* clear ADC14TOVIFG */\r
- __O uint32_t bCLRRDYIFG : 1; /* clear ADC14RDYIFG */\r
- __I uint32_t bRESERVED1 : 25; /* Reserved */\r
- } b;\r
- } rCLRIFGR1;\r
- __IO uint32_t rIV; /* Interrupt Vector Register */\r
+ __IO uint32_t CTL0; /**< Control 0 Register */\r
+ __IO uint32_t CTL1; /**< Control 1 Register */\r
+ __IO uint32_t LO0; /**< Window Comparator Low Threshold 0 Register */\r
+ __IO uint32_t HI0; /**< Window Comparator High Threshold 0 Register */\r
+ __IO uint32_t LO1; /**< Window Comparator Low Threshold 1 Register */\r
+ __IO uint32_t HI1; /**< Window Comparator High Threshold 1 Register */\r
+ __IO uint32_t MCTL[32]; /**< Conversion Memory Control Register */\r
+ __IO uint32_t MEM[32]; /**< Conversion Memory Register */\r
+ uint32_t RESERVED0[9];\r
+ __IO uint32_t IER0; /**< Interrupt Enable 0 Register */\r
+ __IO uint32_t IER1; /**< Interrupt Enable 1 Register */\r
+ __I uint32_t IFGR0; /**< Interrupt Flag 0 Register */\r
+ __I uint32_t IFGR1; /**< Interrupt Flag 1 Register */\r
+ __O uint32_t CLRIFGR0; /**< Clear Interrupt Flag 0 Register */\r
+ __IO uint32_t CLRIFGR1; /**< Clear Interrupt Flag 1 Register */\r
+ __IO uint32_t IV; /**< Interrupt Vector Register */\r
} ADC14_Type;\r
\r
+/*@}*/ /* end of group ADC14 */\r
+\r
\r
-//*****************************************************************************\r
-// AES256 Registers\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* AES256 Registers\r
+******************************************************************************/\r
+/** @addtogroup AES256 MSP432P401R (AES256)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* AESACTL0 Register */\r
- __IO uint16_t r;\r
- struct { /* AESACTL0 Bits */\r
- __IO uint16_t bOP : 2; /* AES operation */\r
- __IO uint16_t bKL : 2; /* AES key length */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bCM : 2; /* AES cipher mode select */\r
- __IO uint16_t bSWRST : 1; /* AES software reset */\r
- __IO uint16_t bRDYIFG : 1; /* AES ready interrupt flag */\r
- __I uint16_t bRESERVED1 : 2; /* Reserved */\r
- __IO uint16_t bERRFG : 1; /* AES error flag */\r
- __IO uint16_t bRDYIE : 1; /* AES ready interrupt enable */\r
- __I uint16_t bRESERVED2 : 2; /* Reserved */\r
- __IO uint16_t bCMEN : 1; /* AES cipher mode enable */\r
- } b;\r
- } rCTL0;\r
- union { /* AESACTL1 Register */\r
- __IO uint16_t r;\r
- struct { /* AESACTL1 Bits */\r
- __IO uint16_t bBLKCNT : 8; /* Cipher Block Counter */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- } rCTL1;\r
- union { /* AESASTAT Register */\r
- __IO uint16_t r;\r
- struct { /* AESASTAT Bits */\r
- __IO uint16_t bBUSY : 1; /* AES accelerator module busy */\r
- __IO uint16_t bKEYWR : 1; /* All 16 bytes written to AESAKEY */\r
- __IO uint16_t bDINWR : 1; /* All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */\r
- __I uint16_t bDOUTRD : 1; /* All 16 bytes read from AESADOUT */\r
- __I uint16_t bKEYCNT : 4; /* Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */\r
- __I uint16_t bDINCNT : 4; /* Bytes written via AESADIN, AESAXDIN or AESAXIN */\r
- __I uint16_t bDOUTCNT : 4; /* Bytes read via AESADOUT */\r
- } b;\r
- } rSTAT;\r
- union { /* AESAKEY Register */\r
- __O uint16_t r;\r
- struct { /* AESAKEY Bits */\r
- __O uint16_t bKEY0 : 8; /* AES key byte n when AESAKEY is written as half-word */\r
- __O uint16_t bKEY1 : 8; /* AES key byte n+1 when AESAKEY is written as half-word */\r
- } b;\r
- } rKEY;\r
- union { /* AESADIN Register */\r
- __O uint16_t r;\r
- struct { /* AESADIN Bits */\r
- __O uint16_t bDIN0 : 8; /* AES data in byte n when AESADIN is written as half-word */\r
- __O uint16_t bDIN1 : 8; /* AES data in byte n+1 when AESADIN is written as half-word */\r
- } b;\r
- } rDIN;\r
- union { /* AESADOUT Register */\r
- __O uint16_t r;\r
- struct { /* AESADOUT Bits */\r
- __O uint16_t bDOUT0 : 8; /* AES data out byte n when AESADOUT is read as half-word */\r
- __O uint16_t bDOUT1 : 8; /* AES data out byte n+1 when AESADOUT is read as half-word */\r
- } b;\r
- } rDOUT;\r
- union { /* AESAXDIN Register */\r
- __O uint16_t r;\r
- struct { /* AESAXDIN Bits */\r
- __O uint16_t bXDIN0 : 8; /* AES data in byte n when AESAXDIN is written as half-word */\r
- __O uint16_t bXDIN1 : 8; /* AES data in byte n+1 when AESAXDIN is written as half-word */\r
- } b;\r
- } rXDIN;\r
- union { /* AESAXIN Register */\r
- __O uint16_t r;\r
- struct { /* AESAXIN Bits */\r
- __O uint16_t bXIN0 : 8; /* AES data in byte n when AESAXIN is written as half-word */\r
- __O uint16_t bXIN1 : 8; /* AES data in byte n+1 when AESAXIN is written as half-word */\r
- } b;\r
- } rXIN;\r
+ __IO uint16_t CTL0; /**< AES Accelerator Control Register 0 */\r
+ __IO uint16_t CTL1; /**< AES Accelerator Control Register 1 */\r
+ __IO uint16_t STAT; /**< AES Accelerator Status Register */\r
+ __O uint16_t KEY; /**< AES Accelerator Key Register */\r
+ __O uint16_t DIN; /**< AES Accelerator Data In Register */\r
+ __O uint16_t DOUT; /**< AES Accelerator Data Out Register */\r
+ __O uint16_t XDIN; /**< AES Accelerator XORed Data In Register */\r
+ __O uint16_t XIN; /**< AES Accelerator XORed Data In Register */\r
} AES256_Type;\r
\r
-\r
-//*****************************************************************************\r
-// CAPTIO0 Registers\r
-//*****************************************************************************\r
-typedef struct {\r
- uint8_t RESERVED0[14];\r
- union { /* CAPTIO0CTL Register */\r
- __IO uint16_t r;\r
- struct { /* CAPTIO0CTL Bits */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bPISEL : 3; /* Capacitive Touch IO pin select */\r
- __IO uint16_t bPOSEL : 4; /* Capacitive Touch IO port select */\r
- __IO uint16_t bEN : 1; /* Capacitive Touch IO enable */\r
- __I uint16_t bSTATE : 1; /* Capacitive Touch IO state */\r
- __I uint16_t bRESERVED1 : 6; /* Reserved */\r
- } b;\r
- } rCTL;\r
-} CAPTIO0_Type;\r
+/*@}*/ /* end of group AES256 */\r
\r
\r
-//*****************************************************************************\r
-// CAPTIO1 Registers\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* CAPTIO Registers\r
+******************************************************************************/\r
+/** @addtogroup CAPTIO MSP432P401R (CAPTIO)\r
+ @{\r
+*/\r
typedef struct {\r
- uint8_t RESERVED0[14];\r
- union { /* CAPTIO1CTL Register */\r
- __IO uint16_t r;\r
- struct { /* CAPTIO1CTL Bits */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bPISEL : 3; /* Capacitive Touch IO pin select */\r
- __IO uint16_t bPOSEL : 4; /* Capacitive Touch IO port select */\r
- __IO uint16_t bEN : 1; /* Capacitive Touch IO enable */\r
- __I uint16_t bSTATE : 1; /* Capacitive Touch IO state */\r
- __I uint16_t bRESERVED1 : 6; /* Reserved */\r
- } b;\r
- } rCTL;\r
-} CAPTIO1_Type;\r
+ uint16_t RESERVED0[7];\r
+ __IO uint16_t CTL; /**< Capacitive Touch IO x Control Register */\r
+} CAPTIO_Type;\r
\r
-\r
-//*****************************************************************************\r
-// COMP_E0 Registers\r
-//*****************************************************************************\r
-typedef struct {\r
- union { /* CE0CTL0 Register */\r
- __IO uint16_t r;\r
- struct { /* CE0CTL0 Bits */\r
- __IO uint16_t bIPSEL : 4; /* Channel input selected for the V+ terminal */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint16_t bIPEN : 1; /* Channel input enable for the V+ terminal */\r
- __IO uint16_t bIMSEL : 4; /* Channel input selected for the - terminal */\r
- __I uint16_t bRESERVED1 : 3; /* Reserved */\r
- __IO uint16_t bIMEN : 1; /* Channel input enable for the - terminal */\r
- } b;\r
- } rCTL0;\r
- union { /* CE0CTL1 Register */\r
- __IO uint16_t r;\r
- struct { /* CE0CTL1 Bits */\r
- __IO uint16_t bOUT : 1; /* Comparator output value */\r
- __IO uint16_t bOUTPOL : 1; /* Comparator output polarity */\r
- __IO uint16_t bF : 1; /* Comparator output filter */\r
- __IO uint16_t bIES : 1; /* Interrupt edge select for CEIIFG and CEIFG */\r
- __IO uint16_t bSHORT : 1; /* Input short */\r
- __IO uint16_t bEX : 1; /* Exchange */\r
- __IO uint16_t bFDLY : 2; /* Filter delay */\r
- __IO uint16_t bPWRMD : 2; /* Power Mode */\r
- __IO uint16_t bON : 1; /* Comparator On */\r
- __IO uint16_t bMRVL : 1; /* This bit is valid of CEMRVS is set to 1 */\r
- __IO uint16_t bMRVS : 1; /* */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- } b;\r
- } rCTL1;\r
- union { /* CE0CTL2 Register */\r
- __IO uint16_t r;\r
- struct { /* CE0CTL2 Bits */\r
- __IO uint16_t bREF0 : 5; /* Reference resistor tap 0 */\r
- __IO uint16_t bRSEL : 1; /* Reference select */\r
- __IO uint16_t bRS : 2; /* Reference source */\r
- __IO uint16_t bREF1 : 5; /* Reference resistor tap 1 */\r
- __IO uint16_t bREFL : 2; /* Reference voltage level */\r
- __IO uint16_t bREFACC : 1; /* Reference accuracy */\r
- } b;\r
- } rCTL2;\r
- union { /* CE0CTL3 Register */\r
- __IO uint16_t r;\r
- struct { /* CE0CTL3 Bits */\r
- __IO uint16_t bPD0 : 1; /* Port disable */\r
- __IO uint16_t bPD1 : 1; /* Port disable */\r
- __IO uint16_t bPD2 : 1; /* Port disable */\r
- __IO uint16_t bPD3 : 1; /* Port disable */\r
- __IO uint16_t bPD4 : 1; /* Port disable */\r
- __IO uint16_t bPD5 : 1; /* Port disable */\r
- __IO uint16_t bPD6 : 1; /* Port disable */\r
- __IO uint16_t bPD7 : 1; /* Port disable */\r
- __IO uint16_t bPD8 : 1; /* Port disable */\r
- __IO uint16_t bPD9 : 1; /* Port disable */\r
- __IO uint16_t bPD10 : 1; /* Port disable */\r
- __IO uint16_t bPD11 : 1; /* Port disable */\r
- __IO uint16_t bPD12 : 1; /* Port disable */\r
- __IO uint16_t bPD13 : 1; /* Port disable */\r
- __IO uint16_t bPD14 : 1; /* Port disable */\r
- __IO uint16_t bPD15 : 1; /* Port disable */\r
- } b;\r
- } rCTL3;\r
- uint8_t RESERVED0[4];\r
- union { /* CE0INT Register */\r
- __IO uint16_t r;\r
- struct { /* CE0INT Bits */\r
- __IO uint16_t bIFG : 1; /* Comparator output interrupt flag */\r
- __IO uint16_t bIIFG : 1; /* Comparator output inverted interrupt flag */\r
- __I uint16_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint16_t bRDYIFG : 1; /* Comparator ready interrupt flag */\r
- __I uint16_t bRESERVED1 : 3; /* Reserved */\r
- __IO uint16_t bIE : 1; /* Comparator output interrupt enable */\r
- __IO uint16_t bIIE : 1; /* Comparator output interrupt enable inverted polarity */\r
- __I uint16_t bRESERVED2 : 2; /* Reserved */\r
- __IO uint16_t bRDYIE : 1; /* Comparator ready interrupt enable */\r
- __I uint16_t bRESERVED3 : 3; /* Reserved */\r
- } b;\r
- } rINT;\r
- __I uint16_t rIV; /* Comparator Interrupt Vector Word Register */\r
-} COMP_E0_Type;\r
+/*@}*/ /* end of group CAPTIO */\r
\r
\r
-//*****************************************************************************\r
-// COMP_E1 Registers\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* COMP_E Registers\r
+******************************************************************************/\r
+/** @addtogroup COMP_E MSP432P401R (COMP_E)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* CE1CTL0 Register */\r
- __IO uint16_t r;\r
- struct { /* CE1CTL0 Bits */\r
- __IO uint16_t bIPSEL : 4; /* Channel input selected for the V+ terminal */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint16_t bIPEN : 1; /* Channel input enable for the V+ terminal */\r
- __IO uint16_t bIMSEL : 4; /* Channel input selected for the - terminal */\r
- __I uint16_t bRESERVED1 : 3; /* Reserved */\r
- __IO uint16_t bIMEN : 1; /* Channel input enable for the - terminal */\r
- } b;\r
- } rCTL0;\r
- union { /* CE1CTL1 Register */\r
- __IO uint16_t r;\r
- struct { /* CE1CTL1 Bits */\r
- __IO uint16_t bOUT : 1; /* Comparator output value */\r
- __IO uint16_t bOUTPOL : 1; /* Comparator output polarity */\r
- __IO uint16_t bF : 1; /* Comparator output filter */\r
- __IO uint16_t bIES : 1; /* Interrupt edge select for CEIIFG and CEIFG */\r
- __IO uint16_t bSHORT : 1; /* Input short */\r
- __IO uint16_t bEX : 1; /* Exchange */\r
- __IO uint16_t bFDLY : 2; /* Filter delay */\r
- __IO uint16_t bPWRMD : 2; /* Power Mode */\r
- __IO uint16_t bON : 1; /* Comparator On */\r
- __IO uint16_t bMRVL : 1; /* This bit is valid of CEMRVS is set to 1 */\r
- __IO uint16_t bMRVS : 1; /* */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- } b;\r
- } rCTL1;\r
- union { /* CE1CTL2 Register */\r
- __IO uint16_t r;\r
- struct { /* CE1CTL2 Bits */\r
- __IO uint16_t bREF0 : 5; /* Reference resistor tap 0 */\r
- __IO uint16_t bRSEL : 1; /* Reference select */\r
- __IO uint16_t bRS : 2; /* Reference source */\r
- __IO uint16_t bREF1 : 5; /* Reference resistor tap 1 */\r
- __IO uint16_t bREFL : 2; /* Reference voltage level */\r
- __IO uint16_t bREFACC : 1; /* Reference accuracy */\r
- } b;\r
- } rCTL2;\r
- union { /* CE1CTL3 Register */\r
- __IO uint16_t r;\r
- struct { /* CE1CTL3 Bits */\r
- __IO uint16_t bPD0 : 1; /* Port disable */\r
- __IO uint16_t bPD1 : 1; /* Port disable */\r
- __IO uint16_t bPD2 : 1; /* Port disable */\r
- __IO uint16_t bPD3 : 1; /* Port disable */\r
- __IO uint16_t bPD4 : 1; /* Port disable */\r
- __IO uint16_t bPD5 : 1; /* Port disable */\r
- __IO uint16_t bPD6 : 1; /* Port disable */\r
- __IO uint16_t bPD7 : 1; /* Port disable */\r
- __IO uint16_t bPD8 : 1; /* Port disable */\r
- __IO uint16_t bPD9 : 1; /* Port disable */\r
- __IO uint16_t bPD10 : 1; /* Port disable */\r
- __IO uint16_t bPD11 : 1; /* Port disable */\r
- __IO uint16_t bPD12 : 1; /* Port disable */\r
- __IO uint16_t bPD13 : 1; /* Port disable */\r
- __IO uint16_t bPD14 : 1; /* Port disable */\r
- __IO uint16_t bPD15 : 1; /* Port disable */\r
- } b;\r
- } rCTL3;\r
- uint8_t RESERVED0[4];\r
- union { /* CE1INT Register */\r
- __IO uint16_t r;\r
- struct { /* CE1INT Bits */\r
- __IO uint16_t bIFG : 1; /* Comparator output interrupt flag */\r
- __IO uint16_t bIIFG : 1; /* Comparator output inverted interrupt flag */\r
- __I uint16_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint16_t bRDYIFG : 1; /* Comparator ready interrupt flag */\r
- __I uint16_t bRESERVED1 : 3; /* Reserved */\r
- __IO uint16_t bIE : 1; /* Comparator output interrupt enable */\r
- __IO uint16_t bIIE : 1; /* Comparator output interrupt enable inverted polarity */\r
- __I uint16_t bRESERVED2 : 2; /* Reserved */\r
- __IO uint16_t bRDYIE : 1; /* Comparator ready interrupt enable */\r
- __I uint16_t bRESERVED3 : 3; /* Reserved */\r
- } b;\r
- } rINT;\r
- __I uint16_t rIV; /* Comparator Interrupt Vector Word Register */\r
-} COMP_E1_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// CRC32 Registers\r
-//*****************************************************************************\r
+ __IO uint16_t CTL0; /**< Comparator Control Register 0 */\r
+ __IO uint16_t CTL1; /**< Comparator Control Register 1 */\r
+ __IO uint16_t CTL2; /**< Comparator Control Register 2 */\r
+ __IO uint16_t CTL3; /**< Comparator Control Register 3 */\r
+ uint16_t RESERVED0[2];\r
+ __IO uint16_t INT; /**< Comparator Interrupt Control Register */\r
+ __I uint16_t IV; /**< Comparator Interrupt Vector Word Register */\r
+} COMP_E_Type;\r
+\r
+/*@}*/ /* end of group COMP_E */\r
+\r
+\r
+/******************************************************************************\r
+* CRC32 Registers\r
+******************************************************************************/\r
+/** @addtogroup CRC32 MSP432P401R (CRC32)\r
+ @{\r
+*/\r
typedef struct {\r
- __IO uint16_t rCRC32DI; /* Data Input for CRC32 Signature Computation */\r
- uint8_t RESERVED0[2];\r
- __IO uint16_t rCRC32DIRB; /* Data In Reverse for CRC32 Computation */\r
- uint8_t RESERVED1[2];\r
- __IO uint16_t rCRC32INIRES_LO; /* CRC32 Initialization and Result, lower 16 bits */\r
- __IO uint16_t rCRC32INIRES_HI; /* CRC32 Initialization and Result, upper 16 bits */\r
- __IO uint16_t rCRC32RESR_LO; /* CRC32 Result Reverse, lower 16 bits */\r
- __IO uint16_t rCRC32RESR_HI; /* CRC32 Result Reverse, Upper 16 bits */\r
- __IO uint16_t rCRC16DI; /* Data Input for CRC16 computation */\r
- uint8_t RESERVED2[2];\r
- __IO uint16_t rCRC16DIRB; /* CRC16 Data In Reverse */\r
- uint8_t RESERVED3[2];\r
- __IO uint16_t rCRC16INIRES; /* CRC16 Initialization and Result register */\r
- uint8_t RESERVED4[4];\r
- __IO uint16_t rCRC16RESR; /* CRC16 Result Reverse */\r
+ __IO uint16_t DI32; /**< Data Input for CRC32 Signature Computation */\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t DIRB32; /**< Data In Reverse for CRC32 Computation */\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t INIRES32_LO; /**< CRC32 Initialization and Result, lower 16 bits */\r
+ __IO uint16_t INIRES32_HI; /**< CRC32 Initialization and Result, upper 16 bits */\r
+ __IO uint16_t RESR32_LO; /**< CRC32 Result Reverse, lower 16 bits */\r
+ __IO uint16_t RESR32_HI; /**< CRC32 Result Reverse, Upper 16 bits */\r
+ __IO uint16_t DI16; /**< Data Input for CRC16 computation */\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t DIRB16; /**< CRC16 Data In Reverse */\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t INIRES16; /**< CRC16 Initialization and Result register */\r
+ uint16_t RESERVED4[2];\r
+ __IO uint16_t RESR16; /**< CRC16 Result Reverse */\r
} CRC32_Type;\r
\r
+/*@}*/ /* end of group CRC32 */\r
\r
-//*****************************************************************************\r
-// CS Registers\r
-//*****************************************************************************\r
+\r
+/******************************************************************************\r
+* CS Registers\r
+******************************************************************************/\r
+/** @addtogroup CS MSP432P401R (CS)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* CSKEY Register */\r
- __IO uint32_t r;\r
- struct { /* CSKEY Bits */\r
- __IO uint32_t bKEY : 16; /* Write xxxx_695Ah to unlock */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rKEY;\r
- union { /* CSCTL0 Register */\r
- __IO uint32_t r;\r
- struct { /* CSCTL0 Bits */\r
- __IO uint32_t bDCOTUNE : 13; /* DCO frequency tuning select */\r
- __I uint32_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint32_t bDCORSEL : 3; /* DCO frequency range select */\r
- __I uint32_t bRESERVED1 : 3; /* Reserved */\r
- __IO uint32_t bDCORES : 1; /* Enables the DCO external resistor mode */\r
- __IO uint32_t bDCOEN : 1; /* Enables the DCO oscillator */\r
- __IO uint32_t bDIS_DCO_DELAY_CNT : 1; /* */\r
- __I uint32_t bRESERVED2 : 7; /* Reserved */\r
- } b;\r
- } rCTL0;\r
- union { /* CSCTL1 Register */\r
- __IO uint32_t r;\r
- struct { /* CSCTL1 Bits */\r
- __IO uint32_t bSELM : 3; /* Selects the MCLK source */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bSELS : 3; /* Selects the SMCLK and HSMCLK source */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bSELA : 3; /* Selects the ACLK source */\r
- __I uint32_t bRESERVED2 : 1; /* Reserved */\r
- __IO uint32_t bSELB : 1; /* Selects the BCLK source */\r
- __I uint32_t bRESERVED3 : 3; /* Reserved */\r
- __IO uint32_t bDIVM : 3; /* MCLK source divider */\r
- __I uint32_t bRESERVED4 : 1; /* Reserved */\r
- __IO uint32_t bDIVHS : 3; /* HSMCLK source divider */\r
- __I uint32_t bRESERVED5 : 1; /* Reserved */\r
- __IO uint32_t bDIVA : 3; /* ACLK source divider */\r
- __I uint32_t bRESERVED6 : 1; /* Reserved */\r
- __IO uint32_t bDIVS : 3; /* SMCLK source divider */\r
- __I uint32_t bRESERVED7 : 1; /* Reserved */\r
- } b;\r
- } rCTL1;\r
- union { /* CSCTL2 Register */\r
- __IO uint32_t r;\r
- struct { /* CSCTL2 Bits */\r
- __IO uint32_t bLFXTDRIVE : 3; /* LFXT oscillator current can be adjusted to its drive needs */\r
- __IO uint32_t bRESERVED0 : 4; /* Reserved */\r
- __IO uint32_t bLFXTAGCOFF : 1; /* Disables the automatic gain control of the LFXT crystal */\r
- __IO uint32_t bLFXT_EN : 1; /* Turns on the LFXT oscillator regardless if used as a clock resource */\r
- __IO uint32_t bLFXTBYPASS : 1; /* LFXT bypass select */\r
- __I uint32_t bRESERVED1 : 6; /* Reserved */\r
- __IO uint32_t bHFXTDRIVE : 1; /* HFXT oscillator drive selection */\r
- __IO uint32_t bRESERVED5 : 2; /* Reserved */\r
- __I uint32_t bRESERVED2 : 1; /* Reserved */\r
- __IO uint32_t bHFXTFREQ : 3; /* HFXT frequency selection */\r
- __I uint32_t bRESERVED3 : 1; /* Reserved */\r
- __IO uint32_t bHFXT_EN : 1; /* Turns on the HFXT oscillator regardless if used as a clock resource */\r
- __IO uint32_t bHFXTBYPASS : 1; /* HFXT bypass select */\r
- __I uint32_t bRESERVED4 : 6; /* Reserved */\r
- } b;\r
- } rCTL2;\r
- union { /* CSCTL3 Register */\r
- __IO uint32_t r;\r
- struct { /* CSCTL3 Bits */\r
- __IO uint32_t bFCNTLF : 2; /* Start flag counter for LFXT */\r
- __O uint32_t bRFCNTLF : 1; /* Reset start fault counter for LFXT */\r
- __IO uint32_t bFCNTLF_EN : 1; /* Enable start fault counter for LFXT */\r
- __IO uint32_t bFCNTHF : 2; /* Start flag counter for HFXT */\r
- __O uint32_t bRFCNTHF : 1; /* Reset start fault counter for HFXT */\r
- __IO uint32_t bFCNTHF_EN : 1; /* Enable start fault counter for HFXT */\r
- __IO uint32_t bFCNTHF2 : 2; /* Start flag counter for HFXT2 */\r
- __O uint32_t bRFCNTHF2 : 1; /* Reset start fault counter for HFXT2 */\r
- __IO uint32_t bFCNTHF2_EN : 1; /* Enable start fault counter for HFXT2 */\r
- __I uint32_t bRESERVED0 : 20; /* Reserved */\r
- } b;\r
- } rCTL3;\r
- union { /* CSCTL4 Register */\r
- __IO uint32_t r;\r
- struct { /* CSCTL4 Bits */\r
- __IO uint32_t bHFXT2DRIVE : 3; /* HFXT2 oscillator current can be adjusted to its drive needs */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bHFXT2FREQ : 3; /* HFXT2 frequency selection */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bHFXT2_EN : 1; /* Turns on the HFXT2 oscillator */\r
- __IO uint32_t bHFXT2BYPASS : 1; /* HFXT2 bypass select */\r
- __I uint32_t bRESERVED2 : 22; /* Reserved */\r
- } b;\r
- } rCTL4;\r
- union { /* CSCTL5 Register */\r
- __IO uint32_t r;\r
- struct { /* CSCTL5 Bits */\r
- __IO uint32_t bREFCNTSEL : 3; /* Reference counter source select */\r
- __IO uint32_t bREFCNTPS : 3; /* Reference clock prescaler */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __O uint32_t bCALSTART : 1; /* Start clock calibration counters */\r
- __IO uint32_t bPERCNTSEL : 3; /* Period counter source select */\r
- __I uint32_t bRESERVED1 : 21; /* Reserved */\r
- } b;\r
- } rCTL5;\r
- union { /* CSCTL6 Register */\r
- __IO uint32_t r;\r
- struct { /* CSCTL6 Bits */\r
- __I uint32_t bPERCNT : 16; /* Calibration period counter */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rCTL6;\r
- union { /* CSCTL7 Register */\r
- __IO uint32_t r;\r
- struct { /* CSCTL7 Bits */\r
- __IO uint32_t bREFCNT : 16; /* Calibration reference period counter */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rCTL7;\r
- uint8_t RESERVED0[12];\r
- union { /* CSCLKEN Register */\r
- __IO uint32_t r;\r
- struct { /* CSCLKEN Bits */\r
- __IO uint32_t bACLK_EN : 1; /* ACLK system clock conditional request enable */\r
- __IO uint32_t bMCLK_EN : 1; /* MCLK system clock conditional request enable */\r
- __IO uint32_t bHSMCLK_EN : 1; /* HSMCLK system clock conditional request enable */\r
- __IO uint32_t bSMCLK_EN : 1; /* SMCLK system clock conditional request enable */\r
- __I uint32_t bRESERVED0 : 4; /* Reserved */\r
- __IO uint32_t bVLO_EN : 1; /* Turns on the VLO oscillator */\r
- __IO uint32_t bREFO_EN : 1; /* Turns on the REFO oscillator */\r
- __IO uint32_t bMODOSC_EN : 1; /* Turns on the MODOSC oscillator */\r
- __I uint32_t bRESERVED1 : 4; /* Reserved */\r
- __IO uint32_t bREFOFSEL : 1; /* Selects REFO nominal frequency */\r
- __I uint32_t bRESERVED2 : 16; /* Reserved */\r
- } b;\r
- } rCLKEN;\r
- union { /* CSSTAT Register */\r
- __I uint32_t r;\r
- struct { /* CSSTAT Bits */\r
- __I uint32_t bDCO_ON : 1; /* DCO status */\r
- __I uint32_t bDCOBIAS_ON : 1; /* DCO bias status */\r
- __I uint32_t bHFXT_ON : 1; /* HFXT status */\r
- __I uint32_t bHFXT2_ON : 1; /* HFXT2 status */\r
- __I uint32_t bMODOSC_ON : 1; /* MODOSC status */\r
- __I uint32_t bVLO_ON : 1; /* VLO status */\r
- __I uint32_t bLFXT_ON : 1; /* LFXT status */\r
- __I uint32_t bREFO_ON : 1; /* REFO status */\r
- __I uint32_t bRESERVED0 : 8; /* Reserved */\r
- __I uint32_t bACLK_ON : 1; /* ACLK system clock status */\r
- __I uint32_t bMCLK_ON : 1; /* MCLK system clock status */\r
- __I uint32_t bHSMCLK_ON : 1; /* HSMCLK system clock status */\r
- __I uint32_t bSMCLK_ON : 1; /* SMCLK system clock status */\r
- __I uint32_t bMODCLK_ON : 1; /* MODCLK system clock status */\r
- __I uint32_t bVLOCLK_ON : 1; /* VLOCLK system clock status */\r
- __I uint32_t bLFXTCLK_ON : 1; /* LFXTCLK system clock status */\r
- __I uint32_t bREFOCLK_ON : 1; /* REFOCLK system clock status */\r
- __I uint32_t bACLK_READY : 1; /* ACLK Ready status */\r
- __I uint32_t bMCLK_READY : 1; /* MCLK Ready status */\r
- __I uint32_t bHSMCLK_READY : 1; /* HSMCLK Ready status */\r
- __I uint32_t bSMCLK_READY : 1; /* SMCLK Ready status */\r
- __I uint32_t bBCLK_READY : 1; /* BCLK Ready status */\r
- __I uint32_t bRESERVED1 : 3; /* Reserved */\r
- } b;\r
- } rSTAT;\r
- uint8_t RESERVED1[8];\r
- union { /* CSIE Register */\r
- __IO uint32_t r;\r
- struct { /* CSIE Bits */\r
- __IO uint32_t bLFXTIE : 1; /* LFXT oscillator fault flag interrupt enable */\r
- __IO uint32_t bHFXTIE : 1; /* HFXT oscillator fault flag interrupt enable */\r
- __IO uint32_t bHFXT2IE : 1; /* HFXT2 oscillator fault flag interrupt enable */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bDCOMINIE : 1; /* DCO minimum fault flag interrupt enable */\r
- __IO uint32_t bDCOMAXIE : 1; /* DCO maximum fault flag interrupt enable */\r
- __IO uint32_t bDCORIE : 1; /* DCO external resistor fault flag interrupt enable */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bFCNTLFIE : 1; /* Start fault counter interrupt enable LFXT */\r
- __IO uint32_t bFCNTHFIE : 1; /* Start fault counter interrupt enable HFXT */\r
- __IO uint32_t bFCNTHF2IE : 1; /* Start fault counter interrupt enable HFXT2 */\r
- __I uint32_t bRESERVED2 : 1; /* Reserved */\r
- __IO uint32_t bPLLOOLIE : 1; /* PLL out-of-lock interrupt enable */\r
- __IO uint32_t bPLLLOSIE : 1; /* PLL loss-of-signal interrupt enable */\r
- __IO uint32_t bPLLOORIE : 1; /* PLL out-of-range interrupt enable */\r
- __IO uint32_t bCALIE : 1; /* REFCNT period counter interrupt enable */\r
- __I uint32_t bRESERVED3 : 16; /* Reserved */\r
- } b;\r
- } rIE;\r
- uint8_t RESERVED2[4];\r
- union { /* CSIFG Register */\r
- __I uint32_t r;\r
- struct { /* CSIFG Bits */\r
- __I uint32_t bLFXTIFG : 1; /* LFXT oscillator fault flag */\r
- __I uint32_t bHFXTIFG : 1; /* HFXT oscillator fault flag */\r
- __I uint32_t bHFXT2IFG : 1; /* HFXT2 oscillator fault flag */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __I uint32_t bDCOMINIFG : 1; /* DCO minimum fault flag */\r
- __I uint32_t bDCOMAXIFG : 1; /* DCO maximum fault flag */\r
- __I uint32_t bDCORIFG : 1; /* DCO external resistor fault flag */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __I uint32_t bFCNTLFIFG : 1; /* Start fault counter interrupt flag LFXT */\r
- __I uint32_t bFCNTHFIFG : 1; /* Start fault counter interrupt flag HFXT */\r
- __I uint32_t bRESERVED2 : 1; /* Reserved */\r
- __I uint32_t bFCNTHF2IFG : 1; /* Start fault counter interrupt flag HFXT2 */\r
- __I uint32_t bPLLOOLIFG : 1; /* PLL out-of-lock interrupt flag */\r
- __I uint32_t bPLLLOSIFG : 1; /* PLL loss-of-signal interrupt flag */\r
- __I uint32_t bPLLOORIFG : 1; /* PLL out-of-range interrupt flag */\r
- __I uint32_t bCALIFG : 1; /* REFCNT period counter expired */\r
- __I uint32_t bRESERVED3 : 16; /* Reserved */\r
- } b;\r
- } rIFG;\r
- uint8_t RESERVED3[4];\r
- union { /* CSCLRIFG Register */\r
- __IO uint32_t r;\r
- struct { /* CSCLRIFG Bits */\r
- __O uint32_t bCLR_LFXTIFG : 1; /* Clear LFXT oscillator fault interrupt flag */\r
- __O uint32_t bCLR_HFXTIFG : 1; /* Clear HFXT oscillator fault interrupt flag */\r
- __O uint32_t bCLR_HFXT2IFG : 1; /* Clear HFXT2 oscillator fault interrupt flag */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __O uint32_t bCLR_DCOMINIFG : 1; /* Clear DCO minimum fault interrupt flag */\r
- __O uint32_t bCLR_DCOMAXIFG : 1; /* Clear DCO maximum fault interrupt flag */\r
- __O uint32_t bCLR_DCORIFG : 1; /* Clear DCO external resistor fault interrupt flag */\r
- __O uint32_t bCLR_CALIFG : 1; /* REFCNT period counter clear interrupt flag */\r
- __O uint32_t bCLR_FCNTLFIFG : 1; /* Start fault counter clear interrupt flag LFXT */\r
- __O uint32_t bCLR_FCNTHFIFG : 1; /* Start fault counter clear interrupt flag HFXT */\r
- __O uint32_t bCLR_FCNTHF2IFG : 1; /* Start fault counter clear interrupt flag HFXT2 */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __O uint32_t bCLR_PLLOOLIFG : 1; /* PLL out-of-lock clear interrupt flag */\r
- __O uint32_t bCLR_PLLLOSIFG : 1; /* PLL loss-of-signal clear interrupt flag */\r
- __O uint32_t bCLR_PLLOORIFG : 1; /* PLL out-of-range clear interrupt flag */\r
- __I uint32_t bRESERVED2 : 17; /* Reserved */\r
- } b;\r
- } rCLRIFG;\r
- uint8_t RESERVED4[4];\r
- union { /* CSSETIFG Register */\r
- __IO uint32_t r;\r
- struct { /* CSSETIFG Bits */\r
- __O uint32_t bSET_LFXTIFG : 1; /* Set LFXT oscillator fault interrupt flag */\r
- __O uint32_t bSET_HFXTIFG : 1; /* Set HFXT oscillator fault interrupt flag */\r
- __O uint32_t bSET_HFXT2IFG : 1; /* Set HFXT2 oscillator fault interrupt flag */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __O uint32_t bSET_DCOMINIFG : 1; /* Set DCO minimum fault interrupt flag */\r
- __O uint32_t bSET_DCOMAXIFG : 1; /* Set DCO maximum fault interrupt flag */\r
- __O uint32_t bSET_DCORIFG : 1; /* Set DCO external resistor fault interrupt flag */\r
- __O uint32_t bSET_CALIFG : 1; /* REFCNT period counter set interrupt flag */\r
- __O uint32_t bSET_FCNTLFIFG : 1; /* Start fault counter set interrupt flag LFXT */\r
- __O uint32_t bSET_FCNTHFIFG : 1; /* Start fault counter set interrupt flag HFXT */\r
- __O uint32_t bSET_FCNTHF2IFG : 1; /* Start fault counter set interrupt flag HFXT2 */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __O uint32_t bSET_PLLOOLIFG : 1; /* PLL out-of-lock set interrupt flag */\r
- __O uint32_t bSET_PLLLOSIFG : 1; /* PLL loss-of-signal set interrupt flag */\r
- __O uint32_t bSET_PLLOORIFG : 1; /* PLL out-of-range set interrupt flag */\r
- __I uint32_t bRESERVED2 : 17; /* Reserved */\r
- } b;\r
- } rSETIFG;\r
- uint8_t RESERVED5[4];\r
- union { /* CSDCOERCAL Register */\r
- __IO uint32_t r;\r
- struct { /* CSDCOERCAL Bits */\r
- __IO uint32_t bDCO_TCTRIM : 2; /* DCO Temperature compensation Trim */\r
- __I uint32_t bRESERVED0 : 14; /* Reserved */\r
- __IO uint32_t bDCO_FTRIM : 11; /* DCO frequency trim */\r
- __I uint32_t bRESERVED1 : 5; /* Reserved */\r
- } b;\r
- } rDCOERCAL;\r
+ __IO uint32_t KEY; /**< Key Register */\r
+ __IO uint32_t CTL0; /**< Control 0 Register */\r
+ __IO uint32_t CTL1; /**< Control 1 Register */\r
+ __IO uint32_t CTL2; /**< Control 2 Register */\r
+ __IO uint32_t CTL3; /**< Control 3 Register */\r
+ __IO uint32_t CTL4; /**< Control 4 Register */\r
+ __IO uint32_t CTL5; /**< Control 5 Register */\r
+ __IO uint32_t CTL6; /**< Control 6 Register */\r
+ __IO uint32_t CTL7; /**< Control 7 Register */\r
+ uint32_t RESERVED0[3];\r
+ __IO uint32_t CLKEN; /**< Clock Enable Register */\r
+ __I uint32_t STAT; /**< Status Register */\r
+ uint32_t RESERVED1[2];\r
+ __IO uint32_t IE; /**< Interrupt Enable Register */\r
+ uint32_t RESERVED2;\r
+ __I uint32_t IFG; /**< Interrupt Flag Register */\r
+ uint32_t RESERVED3;\r
+ __O uint32_t CLRIFG; /**< Clear Interrupt Flag Register */\r
+ uint32_t RESERVED4;\r
+ __O uint32_t SETIFG; /**< Set Interrupt Flag Register */\r
+ uint32_t RESERVED5;\r
+ __IO uint32_t DCOERCAL0; /**< DCO External Resistor Cailbration 0 Register */\r
+ __IO uint32_t DCOERCAL1; /**< DCO External Resistor Calibration 1 Register */\r
} CS_Type;\r
\r
+/*@}*/ /* end of group CS */\r
\r
-//*****************************************************************************\r
-// DIO Registers\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* DIO Registers\r
+******************************************************************************/\r
+/** @addtogroup DIO MSP432P401R (DIO)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* PAIN Register */\r
- __I uint16_t r;\r
- struct { /* PAIN Bits */\r
- __I uint16_t bP1IN : 8; /* Port 1 Input */\r
- __I uint16_t bP2IN : 8; /* Port 2 Input */\r
- } b;\r
- } rPAIN;\r
- union { /* PAOUT Register */\r
- __IO uint16_t r;\r
- struct { /* PAOUT Bits */\r
- __IO uint16_t bP1OUT : 8; /* Port 1 Output */\r
- __IO uint16_t bP2OUT : 8; /* Port 2 Output */\r
- } b;\r
- } rPAOUT;\r
- union { /* PADIR Register */\r
- __IO uint16_t r;\r
- struct { /* PADIR Bits */\r
- __IO uint16_t bP1DIR : 8; /* Port 1 Direction */\r
- __IO uint16_t bP2DIR : 8; /* Port 2 Direction */\r
- } b;\r
- } rPADIR;\r
- union { /* PAREN Register */\r
- __IO uint16_t r;\r
- struct { /* PAREN Bits */\r
- __IO uint16_t bP1REN : 8; /* Port 1 Resistor Enable */\r
- __IO uint16_t bP2REN : 8; /* Port 2 Resistor Enable */\r
- } b;\r
- } rPAREN;\r
- union { /* PADS Register */\r
- __IO uint16_t r;\r
- struct { /* PADS Bits */\r
- __IO uint16_t bP1DS : 8; /* Port 1 Drive Strength */\r
- __IO uint16_t bP2DS : 8; /* Port 2 Drive Strength */\r
- } b;\r
- } rPADS;\r
- union { /* PASEL0 Register */\r
- __IO uint16_t r;\r
- struct { /* PASEL0 Bits */\r
- __IO uint16_t bP1SEL0 : 8; /* Port 1 Select 0 */\r
- __IO uint16_t bP2SEL0 : 8; /* Port 2 Select 0 */\r
- } b;\r
- } rPASEL0;\r
- union { /* PASEL1 Register */\r
- __IO uint16_t r;\r
- struct { /* PASEL1 Bits */\r
- __IO uint16_t bP1SEL1 : 8; /* Port 1 Select 1 */\r
- __IO uint16_t bP2SEL1 : 8; /* Port 2 Select 1 */\r
- } b;\r
- } rPASEL1;\r
- union { /* P1IV Register */\r
- __I uint16_t r;\r
- struct { /* P1IV Bits */\r
- __I uint16_t bP1IV : 5; /* Port 1 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP1IV;\r
- uint8_t RESERVED0[6];\r
- union { /* PASELC Register */\r
- __IO uint16_t r;\r
- struct { /* PASELC Bits */\r
- __IO uint16_t bP1SELC : 8; /* Port 1 Complement Select */\r
- __IO uint16_t bP2SELC : 8; /* Port 2 Complement Select */\r
- } b;\r
- } rPASELC;\r
- union { /* PAIES Register */\r
- __IO uint16_t r;\r
- struct { /* PAIES Bits */\r
- __IO uint16_t bP1IES : 8; /* Port 1 Interrupt Edge Select */\r
- __IO uint16_t bP2IES : 8; /* Port 2 Interrupt Edge Select */\r
- } b;\r
- } rPAIES;\r
- union { /* PAIE Register */\r
- __IO uint16_t r;\r
- struct { /* PAIE Bits */\r
- __IO uint16_t bP1IE : 8; /* Port 1 Interrupt Enable */\r
- __IO uint16_t bP2IE : 8; /* Port 2 Interrupt Enable */\r
- } b;\r
- } rPAIE;\r
- union { /* PAIFG Register */\r
- __IO uint16_t r;\r
- struct { /* PAIFG Bits */\r
- __IO uint16_t bP1IFG : 8; /* Port 1 Interrupt Flag */\r
- __IO uint16_t bP2IFG : 8; /* Port 2 Interrupt Flag */\r
- } b;\r
- } rPAIFG;\r
- union { /* P2IV Register */\r
- __I uint16_t r;\r
- struct { /* P2IV Bits */\r
- __I uint16_t bP2IV : 5; /* Port 2 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP2IV;\r
- union { /* PBIN Register */\r
- __I uint16_t r;\r
- struct { /* PBIN Bits */\r
- __I uint16_t bP3IN : 8; /* Port 3 Input */\r
- __I uint16_t bP4IN : 8; /* Port 4 Input */\r
- } b;\r
- } rPBIN;\r
- union { /* PBOUT Register */\r
- __IO uint16_t r;\r
- struct { /* PBOUT Bits */\r
- __IO uint16_t bP3OUT : 8; /* Port 3 Output */\r
- __IO uint16_t bP4OUT : 8; /* Port 4 Output */\r
- } b;\r
- } rPBOUT;\r
- union { /* PBDIR Register */\r
- __IO uint16_t r;\r
- struct { /* PBDIR Bits */\r
- __IO uint16_t bP3DIR : 8; /* Port 3 Direction */\r
- __IO uint16_t bP4DIR : 8; /* Port 4 Direction */\r
- } b;\r
- } rPBDIR;\r
- union { /* PBREN Register */\r
- __IO uint16_t r;\r
- struct { /* PBREN Bits */\r
- __IO uint16_t bP3REN : 8; /* Port 3 Resistor Enable */\r
- __IO uint16_t bP4REN : 8; /* Port 4 Resistor Enable */\r
- } b;\r
- } rPBREN;\r
- union { /* PBDS Register */\r
- __IO uint16_t r;\r
- struct { /* PBDS Bits */\r
- __IO uint16_t bP3DS : 8; /* Port 3 Drive Strength */\r
- __IO uint16_t bP4DS : 8; /* Port 4 Drive Strength */\r
- } b;\r
- } rPBDS;\r
- union { /* PBSEL0 Register */\r
- __IO uint16_t r;\r
- struct { /* PBSEL0 Bits */\r
- __IO uint16_t bP3SEL0 : 8; /* Port 3 Select 0 */\r
- __IO uint16_t bP4SEL0 : 8; /* Port 4 Select 0 */\r
- } b;\r
- } rPBSEL0;\r
- union { /* PBSEL1 Register */\r
- __IO uint16_t r;\r
- struct { /* PBSEL1 Bits */\r
- __IO uint16_t bP3SEL1 : 8; /* Port 3 Select 1 */\r
- __IO uint16_t bP4SEL1 : 8; /* Port 4 Select 1 */\r
- } b;\r
- } rPBSEL1;\r
- union { /* P3IV Register */\r
- __I uint16_t r;\r
- struct { /* P3IV Bits */\r
- __I uint16_t bP3IV : 5; /* Port 3 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP3IV;\r
- uint8_t RESERVED1[6];\r
- union { /* PBSELC Register */\r
- __IO uint16_t r;\r
- struct { /* PBSELC Bits */\r
- __IO uint16_t bP3SELC : 8; /* Port 3 Complement Select */\r
- __IO uint16_t bP4SELC : 8; /* Port 4 Complement Select */\r
- } b;\r
- } rPBSELC;\r
- union { /* PBIES Register */\r
- __IO uint16_t r;\r
- struct { /* PBIES Bits */\r
- __IO uint16_t bP3IES : 8; /* Port 3 Interrupt Edge Select */\r
- __IO uint16_t bP4IES : 8; /* Port 4 Interrupt Edge Select */\r
- } b;\r
- } rPBIES;\r
- union { /* PBIE Register */\r
- __IO uint16_t r;\r
- struct { /* PBIE Bits */\r
- __IO uint16_t bP3IE : 8; /* Port 3 Interrupt Enable */\r
- __IO uint16_t bP4IE : 8; /* Port 4 Interrupt Enable */\r
- } b;\r
- } rPBIE;\r
- union { /* PBIFG Register */\r
- __IO uint16_t r;\r
- struct { /* PBIFG Bits */\r
- __IO uint16_t bP3IFG : 8; /* Port 3 Interrupt Flag */\r
- __IO uint16_t bP4IFG : 8; /* Port 4 Interrupt Flag */\r
- } b;\r
- } rPBIFG;\r
- union { /* P4IV Register */\r
- __I uint16_t r;\r
- struct { /* P4IV Bits */\r
- __I uint16_t bP4IV : 5; /* Port 4 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP4IV;\r
- union { /* PCIN Register */\r
- __I uint16_t r;\r
- struct { /* PCIN Bits */\r
- __I uint16_t bP5IN : 8; /* Port 5 Input */\r
- __I uint16_t bP6IN : 8; /* Port 6 Input */\r
- } b;\r
- } rPCIN;\r
- union { /* PCOUT Register */\r
- __IO uint16_t r;\r
- struct { /* PCOUT Bits */\r
- __IO uint16_t bP5OUT : 8; /* Port 5 Output */\r
- __IO uint16_t bP6OUT : 8; /* Port 6 Output */\r
- } b;\r
- } rPCOUT;\r
- union { /* PCDIR Register */\r
- __IO uint16_t r;\r
- struct { /* PCDIR Bits */\r
- __IO uint16_t bP5DIR : 8; /* Port 5 Direction */\r
- __IO uint16_t bP6DIR : 8; /* Port 6 Direction */\r
- } b;\r
- } rPCDIR;\r
- union { /* PCREN Register */\r
- __IO uint16_t r;\r
- struct { /* PCREN Bits */\r
- __IO uint16_t bP5REN : 8; /* Port 5 Resistor Enable */\r
- __IO uint16_t bP6REN : 8; /* Port 6 Resistor Enable */\r
- } b;\r
- } rPCREN;\r
- union { /* PCDS Register */\r
- __IO uint16_t r;\r
- struct { /* PCDS Bits */\r
- __IO uint16_t bP5DS : 8; /* Port 5 Drive Strength */\r
- __IO uint16_t bP6DS : 8; /* Port 6 Drive Strength */\r
- } b;\r
- } rPCDS;\r
- union { /* PCSEL0 Register */\r
- __IO uint16_t r;\r
- struct { /* PCSEL0 Bits */\r
- __IO uint16_t bP5SEL0 : 8; /* Port 5 Select 0 */\r
- __IO uint16_t bP6SEL0 : 8; /* Port 6 Select 0 */\r
- } b;\r
- } rPCSEL0;\r
- union { /* PCSEL1 Register */\r
- __IO uint16_t r;\r
- struct { /* PCSEL1 Bits */\r
- __IO uint16_t bP5SEL1 : 8; /* Port 5 Select 1 */\r
- __IO uint16_t bP6SEL1 : 8; /* Port 6 Select 1 */\r
- } b;\r
- } rPCSEL1;\r
- union { /* P5IV Register */\r
- __I uint16_t r;\r
- struct { /* P5IV Bits */\r
- __I uint16_t bP5IV : 5; /* Port 5 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP5IV;\r
- uint8_t RESERVED2[6];\r
- union { /* PCSELC Register */\r
- __IO uint16_t r;\r
- struct { /* PCSELC Bits */\r
- __IO uint16_t bP5SELC : 8; /* Port 5 Complement Select */\r
- __IO uint16_t bP6SELC : 8; /* Port 6 Complement Select */\r
- } b;\r
- } rPCSELC;\r
- union { /* PCIES Register */\r
- __IO uint16_t r;\r
- struct { /* PCIES Bits */\r
- __IO uint16_t bP5IES : 8; /* Port 5 Interrupt Edge Select */\r
- __IO uint16_t bP6IES : 8; /* Port 6 Interrupt Edge Select */\r
- } b;\r
- } rPCIES;\r
- union { /* PCIE Register */\r
- __IO uint16_t r;\r
- struct { /* PCIE Bits */\r
- __IO uint16_t bP5IE : 8; /* Port 5 Interrupt Enable */\r
- __IO uint16_t bP6IE : 8; /* Port 6 Interrupt Enable */\r
- } b;\r
- } rPCIE;\r
- union { /* PCIFG Register */\r
- __IO uint16_t r;\r
- struct { /* PCIFG Bits */\r
- __IO uint16_t bP5IFG : 8; /* Port 5 Interrupt Flag */\r
- __IO uint16_t bP6IFG : 8; /* Port 6 Interrupt Flag */\r
- } b;\r
- } rPCIFG;\r
- union { /* P6IV Register */\r
- __I uint16_t r;\r
- struct { /* P6IV Bits */\r
- __I uint16_t bP6IV : 5; /* Port 6 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP6IV;\r
- union { /* PDIN Register */\r
- __I uint16_t r;\r
- struct { /* PDIN Bits */\r
- __I uint16_t bP7IN : 8; /* Port 7 Input */\r
- __I uint16_t bP8IN : 8; /* Port 8 Input */\r
- } b;\r
- } rPDIN;\r
- union { /* PDOUT Register */\r
- __IO uint16_t r;\r
- struct { /* PDOUT Bits */\r
- __IO uint16_t bP7OUT : 8; /* Port 7 Output */\r
- __IO uint16_t bP8OUT : 8; /* Port 8 Output */\r
- } b;\r
- } rPDOUT;\r
- union { /* PDDIR Register */\r
- __IO uint16_t r;\r
- struct { /* PDDIR Bits */\r
- __IO uint16_t bP7DIR : 8; /* Port 7 Direction */\r
- __IO uint16_t bP8DIR : 8; /* Port 8 Direction */\r
- } b;\r
- } rPDDIR;\r
- union { /* PDREN Register */\r
- __IO uint16_t r;\r
- struct { /* PDREN Bits */\r
- __IO uint16_t bP7REN : 8; /* Port 7 Resistor Enable */\r
- __IO uint16_t bP8REN : 8; /* Port 8 Resistor Enable */\r
- } b;\r
- } rPDREN;\r
- union { /* PDDS Register */\r
- __IO uint16_t r;\r
- struct { /* PDDS Bits */\r
- __IO uint16_t bP7DS : 8; /* Port 7 Drive Strength */\r
- __IO uint16_t bP8DS : 8; /* Port 8 Drive Strength */\r
- } b;\r
- } rPDDS;\r
- union { /* PDSEL0 Register */\r
- __IO uint16_t r;\r
- struct { /* PDSEL0 Bits */\r
- __IO uint16_t bP7SEL0 : 8; /* Port 7 Select 0 */\r
- __IO uint16_t bP8SEL0 : 8; /* Port 8 Select 0 */\r
- } b;\r
- } rPDSEL0;\r
- union { /* PDSEL1 Register */\r
- __IO uint16_t r;\r
- struct { /* PDSEL1 Bits */\r
- __IO uint16_t bP7SEL1 : 8; /* Port 7 Select 1 */\r
- __IO uint16_t bP8SEL1 : 8; /* Port 8 Select 1 */\r
- } b;\r
- } rPDSEL1;\r
- union { /* P7IV Register */\r
- __I uint16_t r;\r
- struct { /* P7IV Bits */\r
- __I uint16_t bP7IV : 5; /* Port 7 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP7IV;\r
- uint8_t RESERVED3[6];\r
- union { /* PDSELC Register */\r
- __IO uint16_t r;\r
- struct { /* PDSELC Bits */\r
- __IO uint16_t bP7SELC : 8; /* Port 7 Complement Select */\r
- __IO uint16_t bP8SELC : 8; /* Port 8 Complement Select */\r
- } b;\r
- } rPDSELC;\r
- union { /* PDIES Register */\r
- __IO uint16_t r;\r
- struct { /* PDIES Bits */\r
- __IO uint16_t bP7IES : 8; /* Port 7 Interrupt Edge Select */\r
- __IO uint16_t bP8IES : 8; /* Port 8 Interrupt Edge Select */\r
- } b;\r
- } rPDIES;\r
- union { /* PDIE Register */\r
- __IO uint16_t r;\r
- struct { /* PDIE Bits */\r
- __IO uint16_t bP7IE : 8; /* Port 7 Interrupt Enable */\r
- __IO uint16_t bP8IE : 8; /* Port 8 Interrupt Enable */\r
- } b;\r
- } rPDIE;\r
- union { /* PDIFG Register */\r
- __IO uint16_t r;\r
- struct { /* PDIFG Bits */\r
- __IO uint16_t bP7IFG : 8; /* Port 7 Interrupt Flag */\r
- __IO uint16_t bP8IFG : 8; /* Port 8 Interrupt Flag */\r
- } b;\r
- } rPDIFG;\r
- union { /* P8IV Register */\r
- __I uint16_t r;\r
- struct { /* P8IV Bits */\r
- __I uint16_t bP8IV : 5; /* Port 8 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP8IV;\r
- union { /* PEIN Register */\r
- __I uint16_t r;\r
- struct { /* PEIN Bits */\r
- __I uint16_t bP9IN : 8; /* Port 9 Input */\r
- __I uint16_t bP10IN : 8; /* Port 10 Input */\r
- } b;\r
- } rPEIN;\r
- union { /* PEOUT Register */\r
- __IO uint16_t r;\r
- struct { /* PEOUT Bits */\r
- __IO uint16_t bP9OUT : 8; /* Port 9 Output */\r
- __IO uint16_t bP10OUT : 8; /* Port 10 Output */\r
- } b;\r
- } rPEOUT;\r
- union { /* PEDIR Register */\r
- __IO uint16_t r;\r
- struct { /* PEDIR Bits */\r
- __IO uint16_t bP9DIR : 8; /* Port 9 Direction */\r
- __IO uint16_t bP10DIR : 8; /* Port 10 Direction */\r
- } b;\r
- } rPEDIR;\r
- union { /* PEREN Register */\r
- __IO uint16_t r;\r
- struct { /* PEREN Bits */\r
- __IO uint16_t bP9REN : 8; /* Port 9 Resistor Enable */\r
- __IO uint16_t bP10REN : 8; /* Port 10 Resistor Enable */\r
- } b;\r
- } rPEREN;\r
- union { /* PEDS Register */\r
- __IO uint16_t r;\r
- struct { /* PEDS Bits */\r
- __IO uint16_t bP9DS : 8; /* Port 9 Drive Strength */\r
- __IO uint16_t bP10DS : 8; /* Port 10 Drive Strength */\r
- } b;\r
- } rPEDS;\r
- union { /* PESEL0 Register */\r
- __IO uint16_t r;\r
- struct { /* PESEL0 Bits */\r
- __IO uint16_t bP9SEL0 : 8; /* Port 9 Select 0 */\r
- __IO uint16_t bP10SEL0 : 8; /* Port 10 Select 0 */\r
- } b;\r
- } rPESEL0;\r
- union { /* PESEL1 Register */\r
- __IO uint16_t r;\r
- struct { /* PESEL1 Bits */\r
- __IO uint16_t bP9SEL1 : 8; /* Port 9 Select 1 */\r
- __IO uint16_t bP10SEL1 : 8; /* Port 10 Select 1 */\r
- } b;\r
- } rPESEL1;\r
- union { /* P9IV Register */\r
- __I uint16_t r;\r
- struct { /* P9IV Bits */\r
- __I uint16_t bP9IV : 5; /* Port 9 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP9IV;\r
- uint8_t RESERVED4[6];\r
- union { /* PESELC Register */\r
- __IO uint16_t r;\r
- struct { /* PESELC Bits */\r
- __IO uint16_t bP9SELC : 8; /* Port 9 Complement Select */\r
- __IO uint16_t bP10SELC : 8; /* Port 10 Complement Select */\r
- } b;\r
- } rPESELC;\r
- union { /* PEIES Register */\r
- __IO uint16_t r;\r
- struct { /* PEIES Bits */\r
- __IO uint16_t bP9IES : 8; /* Port 9 Interrupt Edge Select */\r
- __IO uint16_t bP10IES : 8; /* Port 10 Interrupt Edge Select */\r
- } b;\r
- } rPEIES;\r
- union { /* PEIE Register */\r
- __IO uint16_t r;\r
- struct { /* PEIE Bits */\r
- __IO uint16_t bP9IE : 8; /* Port 9 Interrupt Enable */\r
- __IO uint16_t bP10IE : 8; /* Port 10 Interrupt Enable */\r
- } b;\r
- } rPEIE;\r
- union { /* PEIFG Register */\r
- __IO uint16_t r;\r
- struct { /* PEIFG Bits */\r
- __IO uint16_t bP9IFG : 8; /* Port 9 Interrupt Flag */\r
- __IO uint16_t bP10IFG : 8; /* Port 10 Interrupt Flag */\r
- } b;\r
- } rPEIFG;\r
- union { /* P10IV Register */\r
- __I uint16_t r;\r
- struct { /* P10IV Bits */\r
- __I uint16_t bP10IV : 5; /* Port 10 interrupt vector value */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rP10IV;\r
- uint8_t RESERVED5[128];\r
- __I uint16_t rPJIN; /* Port J Input */\r
- __IO uint16_t rPJOUT; /* Port J Output */\r
- __IO uint16_t rPJDIR; /* Port J Direction */\r
- __IO uint16_t rPJREN; /* Port J Resistor Enable */\r
- __IO uint16_t rPJDS; /* Port J Drive Strength */\r
- __IO uint16_t rPJSEL0; /* Port J Select 0 */\r
- __IO uint16_t rPJSEL1; /* Port J Select 1 */\r
- uint8_t RESERVED6[8];\r
- __IO uint16_t rPJSELC; /* Port J Complement Select */\r
-} DIO_Type;\r
-\r
+ union {\r
+ __I uint16_t IN; /**< Port Pair Input */\r
+ struct {\r
+ __I uint8_t IN_L; /**< Low Port Input */\r
+ __I uint8_t IN_H; /**< High Port Input */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t OUT; /**< Port Pair Output */\r
+ struct {\r
+ __IO uint8_t OUT_L; /**< Low Port Output */\r
+ __IO uint8_t OUT_H; /**< High Port Output */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t DIR; /**< Port Pair Direction */\r
+ struct {\r
+ __IO uint8_t DIR_L; /**< Low Port Direction */\r
+ __IO uint8_t DIR_H; /**< High Port Direction */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t REN; /**< Port Pair Resistor Enable */\r
+ struct {\r
+ __IO uint8_t REN_L; /**< Low Port Resistor Enable */\r
+ __IO uint8_t REN_H; /**< High Port Resistor Enable */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t DS; /**< Port Pair Drive Strength */\r
+ struct {\r
+ __IO uint8_t DS_L; /**< Low Port Drive Strength */\r
+ __IO uint8_t DS_H; /**< High Port Drive Strength */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t SEL0; /**< Port Pair Select 0 */\r
+ struct {\r
+ __IO uint8_t SEL0_L; /**< Low Port Select 0 */\r
+ __IO uint8_t SEL0_H; /**< High Port Select 0 */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t SEL1; /**< Port Pair Select 1 */\r
+ struct {\r
+ __IO uint8_t SEL1_L; /**< Low Port Select 1 */\r
+ __IO uint8_t SEL1_H; /**< High Port Select 1 */\r
+ };\r
+ };\r
+ __I uint16_t IV_L; /**< Low Port Interrupt Vector Value */\r
+ uint16_t RESERVED0[3];\r
+ union {\r
+ __IO uint16_t SELC; /**< Port Pair Complement Select */\r
+ struct {\r
+ __IO uint8_t SELC_L; /**< Low Port Complement Select */\r
+ __IO uint8_t SELC_H; /**< High Port Complement Select */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t IES; /**< Port Pair Interrupt Edge Select */\r
+ struct {\r
+ __IO uint8_t IES_L; /**< Low Port Interrupt Edge Select */\r
+ __IO uint8_t IES_H; /**< High Port Interrupt Edge Select */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t IE; /**< Port Pair Interrupt Enable */\r
+ struct {\r
+ __IO uint8_t IE_L; /**< Low Port Interrupt Enable */\r
+ __IO uint8_t IE_H; /**< High Port Interrupt Enable */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t IFG; /**< Port Pair Interrupt Flag */\r
+ struct {\r
+ __IO uint8_t IFG_L; /**< Low Port Interrupt Flag */\r
+ __IO uint8_t IFG_H; /**< High Port Interrupt Flag */\r
+ };\r
+ };\r
+ __I uint16_t IV_H; /**< High Port Interrupt Vector Value */\r
+} DIO_PORT_Interruptable_Type;\r
\r
-//*****************************************************************************\r
-// DMA Registers\r
-//*****************************************************************************\r
typedef struct {\r
- union { /* DMA_DEVICE_CFG Register */\r
- __I uint32_t r;\r
- struct { /* DMA_DEVICE_CFG Bits */\r
- __I uint32_t bNUM_DMA_CHANNELS : 8; /* Number of DMA channels available */\r
- __I uint32_t bNUM_SRC_PER_CHANNEL : 8; /* Number of DMA sources per channel */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rDEVICE_CFG;\r
- union { /* DMA_SW_CHTRIG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_SW_CHTRIG Bits */\r
- __IO uint32_t bCH0 : 1; /* Write 1, triggers DMA_CHANNEL0 */\r
- __IO uint32_t bCH1 : 1; /* Write 1, triggers DMA_CHANNEL1 */\r
- __IO uint32_t bCH2 : 1; /* Write 1, triggers DMA_CHANNEL2 */\r
- __IO uint32_t bCH3 : 1; /* Write 1, triggers DMA_CHANNEL3 */\r
- __IO uint32_t bCH4 : 1; /* Write 1, triggers DMA_CHANNEL4 */\r
- __IO uint32_t bCH5 : 1; /* Write 1, triggers DMA_CHANNEL5 */\r
- __IO uint32_t bCH6 : 1; /* Write 1, triggers DMA_CHANNEL6 */\r
- __IO uint32_t bCH7 : 1; /* Write 1, triggers DMA_CHANNEL7 */\r
- __IO uint32_t bCH8 : 1; /* Write 1, triggers DMA_CHANNEL8 */\r
- __IO uint32_t bCH9 : 1; /* Write 1, triggers DMA_CHANNEL9 */\r
- __IO uint32_t bCH10 : 1; /* Write 1, triggers DMA_CHANNEL10 */\r
- __IO uint32_t bCH11 : 1; /* Write 1, triggers DMA_CHANNEL11 */\r
- __IO uint32_t bCH12 : 1; /* Write 1, triggers DMA_CHANNEL12 */\r
- __IO uint32_t bCH13 : 1; /* Write 1, triggers DMA_CHANNEL13 */\r
- __IO uint32_t bCH14 : 1; /* Write 1, triggers DMA_CHANNEL14 */\r
- __IO uint32_t bCH15 : 1; /* Write 1, triggers DMA_CHANNEL15 */\r
- __IO uint32_t bCH16 : 1; /* Write 1, triggers DMA_CHANNEL16 */\r
- __IO uint32_t bCH17 : 1; /* Write 1, triggers DMA_CHANNEL17 */\r
- __IO uint32_t bCH18 : 1; /* Write 1, triggers DMA_CHANNEL18 */\r
- __IO uint32_t bCH19 : 1; /* Write 1, triggers DMA_CHANNEL19 */\r
- __IO uint32_t bCH20 : 1; /* Write 1, triggers DMA_CHANNEL20 */\r
- __IO uint32_t bCH21 : 1; /* Write 1, triggers DMA_CHANNEL21 */\r
- __IO uint32_t bCH22 : 1; /* Write 1, triggers DMA_CHANNEL22 */\r
- __IO uint32_t bCH23 : 1; /* Write 1, triggers DMA_CHANNEL23 */\r
- __IO uint32_t bCH24 : 1; /* Write 1, triggers DMA_CHANNEL24 */\r
- __IO uint32_t bCH25 : 1; /* Write 1, triggers DMA_CHANNEL25 */\r
- __IO uint32_t bCH26 : 1; /* Write 1, triggers DMA_CHANNEL26 */\r
- __IO uint32_t bCH27 : 1; /* Write 1, triggers DMA_CHANNEL27 */\r
- __IO uint32_t bCH28 : 1; /* Write 1, triggers DMA_CHANNEL28 */\r
- __IO uint32_t bCH29 : 1; /* Write 1, triggers DMA_CHANNEL29 */\r
- __IO uint32_t bCH30 : 1; /* Write 1, triggers DMA_CHANNEL30 */\r
- __IO uint32_t bCH31 : 1; /* Write 1, triggers DMA_CHANNEL31 */\r
- } b;\r
- } rSW_CHTRIG;\r
- uint8_t RESERVED0[8];\r
- union { /* DMA_CH0_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH0_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH0_SRCCFG;\r
- union { /* DMA_CH1_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH1_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH1_SRCCFG;\r
- union { /* DMA_CH2_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH2_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH2_SRCCFG;\r
- union { /* DMA_CH3_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH3_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH3_SRCCFG;\r
- union { /* DMA_CH4_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH4_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH4_SRCCFG;\r
- union { /* DMA_CH5_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH5_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH5_SRCCFG;\r
- union { /* DMA_CH6_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH6_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH6_SRCCFG;\r
- union { /* DMA_CH7_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH7_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH7_SRCCFG;\r
- union { /* DMA_CH8_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH8_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH8_SRCCFG;\r
- union { /* DMA_CH9_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH9_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH9_SRCCFG;\r
- union { /* DMA_CH10_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH10_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH10_SRCCFG;\r
- union { /* DMA_CH11_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH11_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH11_SRCCFG;\r
- union { /* DMA_CH12_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH12_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH12_SRCCFG;\r
- union { /* DMA_CH13_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH13_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH13_SRCCFG;\r
- union { /* DMA_CH14_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH14_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH14_SRCCFG;\r
- union { /* DMA_CH15_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH15_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH15_SRCCFG;\r
- union { /* DMA_CH16_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH16_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH16_SRCCFG;\r
- union { /* DMA_CH17_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH17_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH17_SRCCFG;\r
- union { /* DMA_CH18_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH18_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH18_SRCCFG;\r
- union { /* DMA_CH19_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH19_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH19_SRCCFG;\r
- union { /* DMA_CH20_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH20_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH20_SRCCFG;\r
- union { /* DMA_CH21_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH21_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH21_SRCCFG;\r
- union { /* DMA_CH22_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH22_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH22_SRCCFG;\r
- union { /* DMA_CH23_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH23_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH23_SRCCFG;\r
- union { /* DMA_CH24_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH24_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH24_SRCCFG;\r
- union { /* DMA_CH25_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH25_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH25_SRCCFG;\r
- union { /* DMA_CH26_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH26_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH26_SRCCFG;\r
- union { /* DMA_CH27_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH27_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH27_SRCCFG;\r
- union { /* DMA_CH28_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH28_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH28_SRCCFG;\r
- union { /* DMA_CH29_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH29_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH29_SRCCFG;\r
- union { /* DMA_CH30_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH30_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH30_SRCCFG;\r
- union { /* DMA_CH31_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CH31_SRCCFG Bits */\r
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rCH31_SRCCFG;\r
- uint8_t RESERVED1[112];\r
- union { /* DMA_INT1_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_INT1_SRCCFG Bits */\r
- __IO uint32_t bINT_SRC : 5; /* Controls which channel's completion event is mapped as a source of this Interrupt */\r
- __IO uint32_t bEN : 1; /* Enables DMA_INT1 mapping */\r
- __I uint32_t bRESERVED0 : 26; /* Reserved */\r
- } b;\r
- } rINT1_SRCCFG;\r
- union { /* DMA_INT2_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_INT2_SRCCFG Bits */\r
- __IO uint32_t bINT_SRC : 5; /* Controls which channel's completion event is mapped as a source of this Interrupt */\r
- __IO uint32_t bEN : 1; /* Enables DMA_INT2 mapping */\r
- __I uint32_t bRESERVED0 : 26; /* Reserved */\r
- } b;\r
- } rINT2_SRCCFG;\r
- union { /* DMA_INT3_SRCCFG Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_INT3_SRCCFG Bits */\r
- __IO uint32_t bINT_SRC : 5; /* Controls which channel's completion event is mapped as a source of this Interrupt */\r
- __IO uint32_t bEN : 1; /* Enables DMA_INT3 mapping */\r
- __I uint32_t bRESERVED0 : 26; /* Reserved */\r
- } b;\r
- } rINT3_SRCCFG;\r
- uint8_t RESERVED2[4];\r
- union { /* DMA_INT0_SRCFLG Register */\r
- __I uint32_t r;\r
- struct { /* DMA_INT0_SRCFLG Bits */\r
- __I uint32_t bCH0 : 1; /* Channel 0 was the source of DMA_INT0 */\r
- __I uint32_t bCH1 : 1; /* Channel 1 was the source of DMA_INT0 */\r
- __I uint32_t bCH2 : 1; /* Channel 2 was the source of DMA_INT0 */\r
- __I uint32_t bCH3 : 1; /* Channel 3 was the source of DMA_INT0 */\r
- __I uint32_t bCH4 : 1; /* Channel 4 was the source of DMA_INT0 */\r
- __I uint32_t bCH5 : 1; /* Channel 5 was the source of DMA_INT0 */\r
- __I uint32_t bCH6 : 1; /* Channel 6 was the source of DMA_INT0 */\r
- __I uint32_t bCH7 : 1; /* Channel 7 was the source of DMA_INT0 */\r
- __I uint32_t bCH8 : 1; /* Channel 8 was the source of DMA_INT0 */\r
- __I uint32_t bCH9 : 1; /* Channel 9 was the source of DMA_INT0 */\r
- __I uint32_t bCH10 : 1; /* Channel 10 was the source of DMA_INT0 */\r
- __I uint32_t bCH11 : 1; /* Channel 11 was the source of DMA_INT0 */\r
- __I uint32_t bCH12 : 1; /* Channel 12 was the source of DMA_INT0 */\r
- __I uint32_t bCH13 : 1; /* Channel 13 was the source of DMA_INT0 */\r
- __I uint32_t bCH14 : 1; /* Channel 14 was the source of DMA_INT0 */\r
- __I uint32_t bCH15 : 1; /* Channel 15 was the source of DMA_INT0 */\r
- __I uint32_t bCH16 : 1; /* Channel 16 was the source of DMA_INT0 */\r
- __I uint32_t bCH17 : 1; /* Channel 17 was the source of DMA_INT0 */\r
- __I uint32_t bCH18 : 1; /* Channel 18 was the source of DMA_INT0 */\r
- __I uint32_t bCH19 : 1; /* Channel 19 was the source of DMA_INT0 */\r
- __I uint32_t bCH20 : 1; /* Channel 20 was the source of DMA_INT0 */\r
- __I uint32_t bCH21 : 1; /* Channel 21 was the source of DMA_INT0 */\r
- __I uint32_t bCH22 : 1; /* Channel 22 was the source of DMA_INT0 */\r
- __I uint32_t bCH23 : 1; /* Channel 23 was the source of DMA_INT0 */\r
- __I uint32_t bCH24 : 1; /* Channel 24 was the source of DMA_INT0 */\r
- __I uint32_t bCH25 : 1; /* Channel 25 was the source of DMA_INT0 */\r
- __I uint32_t bCH26 : 1; /* Channel 26 was the source of DMA_INT0 */\r
- __I uint32_t bCH27 : 1; /* Channel 27 was the source of DMA_INT0 */\r
- __I uint32_t bCH28 : 1; /* Channel 28 was the source of DMA_INT0 */\r
- __I uint32_t bCH29 : 1; /* Channel 29 was the source of DMA_INT0 */\r
- __I uint32_t bCH30 : 1; /* Channel 30 was the source of DMA_INT0 */\r
- __I uint32_t bCH31 : 1; /* Channel 31 was the source of DMA_INT0 */\r
- } b;\r
- } rINT0_SRCFLG;\r
- union { /* DMA_INT0_CLRFLG Register */\r
- __O uint32_t r;\r
- struct { /* DMA_INT0_CLRFLG Bits */\r
- __O uint32_t bCH0 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH1 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH2 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH3 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH4 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH5 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH6 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH7 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH8 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH9 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH10 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH11 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH12 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH13 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH14 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH15 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH16 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH17 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH18 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH19 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH20 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH21 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH22 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH23 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH24 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH25 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH26 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH27 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH28 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH29 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH30 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- __O uint32_t bCH31 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
- } b;\r
- } rINT0_CLRFLG;\r
- uint8_t RESERVED3[3816];\r
- union { /* DMA_STAT Register */\r
- __I uint32_t r;\r
- struct { /* DMA_STAT Bits */\r
- __I uint32_t bMASTEN : 1; /* */\r
- __I uint32_t bRESERVED0 : 3; /* Reserved */\r
- __I uint32_t b : 4; /* */\r
- __I uint32_t bRESERVED1 : 8; /* Reserved */\r
- __I uint32_t bRESERVED2 : 7; /* Reserved */\r
- } b;\r
- } rSTAT;\r
- union { /* DMA_CFG Register */\r
- __O uint32_t r;\r
- struct { /* DMA_CFG Bits */\r
- __O uint32_t b : 1; /* */\r
- __O uint32_t bRESERVED0 : 4; /* Reserved */\r
- __O uint32_t bRESERVED1 : 24; /* Reserved */\r
- } b;\r
- } rCFG;\r
- union { /* DMA_CTLBASE Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_CTLBASE Bits */\r
- __I uint32_t bRESERVED0 : 5; /* Reserved */\r
- __IO uint32_t b : 27; /* */\r
- } b;\r
- } rCTLBASE;\r
- __I uint32_t rATLBASE; /* Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t rWAITSTAT; /* Channel Wait on Request Status Register */\r
- __O uint32_t rSWREQ; /* Channel Software Request Register */\r
- __IO uint32_t rUSEBURSTSET; /* Channel Useburst Set Register */\r
- __O uint32_t rUSEBURSTCLR; /* Channel Useburst Clear Register */\r
- __IO uint32_t rREQMASKSET; /* Channel Request Mask Set Register */\r
- __O uint32_t rREQMASKCLR; /* Channel Request Mask Clear Register */\r
- __IO uint32_t rENASET; /* Channel Enable Set Register */\r
- __O uint32_t rENACLR; /* Channel Enable Clear Register */\r
- __IO uint32_t rALTSET; /* Channel Primary-Alternate Set Register */\r
- __O uint32_t rALTCLR; /* Channel Primary-Alternate Clear Register */\r
- __IO uint32_t rPRIOSET; /* Channel Priority Set Register */\r
- __O uint32_t rPRIOCLR; /* Channel Priority Clear Register */\r
- uint8_t RESERVED4[12];\r
- union { /* DMA_ERRCLR Register */\r
- __IO uint32_t r;\r
- struct { /* DMA_ERRCLR Bits */\r
- __IO uint32_t b : 1; /* */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rERRCLR;\r
-} DMA_Type;\r
+ union {\r
+ __I uint16_t IN; /**< Port Pair Input */\r
+ struct {\r
+ __I uint8_t IN_L; /**< Low Port Input */\r
+ __I uint8_t IN_H; /**< High Port Input */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t OUT; /**< Port Pair Output */\r
+ struct {\r
+ __IO uint8_t OUT_L; /**< Low Port Output */\r
+ __IO uint8_t OUT_H; /**< High Port Output */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t DIR; /**< Port Pair Direction */\r
+ struct {\r
+ __IO uint8_t DIR_L; /**< Low Port Direction */\r
+ __IO uint8_t DIR_H; /**< High Port Direction */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t REN; /**< Port Pair Resistor Enable */\r
+ struct {\r
+ __IO uint8_t REN_L; /**< Low Port Resistor Enable */\r
+ __IO uint8_t REN_H; /**< High Port Resistor Enable */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t DS; /**< Port Pair Drive Strength */\r
+ struct {\r
+ __IO uint8_t DS_L; /**< Low Port Drive Strength */\r
+ __IO uint8_t DS_H; /**< High Port Drive Strength */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t SEL0; /**< Port Pair Select 0 */\r
+ struct {\r
+ __IO uint8_t SEL0_L; /**< Low Port Select 0 */\r
+ __IO uint8_t SEL0_H; /**< High Port Select 0 */\r
+ };\r
+ };\r
+ union {\r
+ __IO uint16_t SEL1; /**< Port Pair Select 1 */\r
+ struct {\r
+ __IO uint8_t SEL1_L; /**< Low Port Select 1 */\r
+ __IO uint8_t SEL1_H; /**< High Port Select 1 */\r
+ };\r
+ };\r
+ uint16_t RESERVED0[4];\r
+ union {\r
+ __IO uint16_t SELC; /**< Port Pair Complement Select */\r
+ struct {\r
+ __IO uint8_t SELC_L; /**< Low Port Complement Select */\r
+ __IO uint8_t SELC_H; /**< High Port Complement Select */\r
+ };\r
+ };\r
+} DIO_PORT_Not_Interruptable_Type;\r
\r
\r
-//*****************************************************************************\r
-// EUSCI_A0 Registers\r
-//*****************************************************************************\r
typedef struct {\r
- union { /* UCA0CTLW0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCA0CTLW0 Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bTXBRK : 1; /* Transmit break */\r
- __IO uint16_t bTXADDR : 1; /* Transmit address */\r
- __IO uint16_t bDORM : 1; /* Dormant */\r
- __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */\r
- __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI_A mode */\r
- __IO uint16_t bSPB : 1; /* Stop bit select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bPAR : 1; /* Parity select */\r
- __IO uint16_t bPEN : 1; /* Parity enable */\r
- } b;\r
- struct { /* UCA0CTLW0_SPI Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */\r
- __I uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bCKPL : 1; /* Clock polarity select */\r
- __IO uint16_t bCKPH : 1; /* Clock phase select */\r
- } a;\r
- } rCTLW0;\r
- union { /* UCA0CTLW1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCA0CTLW1 Bits */\r
- __IO uint16_t bGLIT : 2; /* Deglitch time */\r
- __I uint16_t bRESERVED0 : 14; /* Reserved */\r
- } b;\r
- } rCTLW1;\r
- uint8_t RESERVED0[2];\r
- __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */\r
- union { /* UCA0MCTLW Register */\r
- __IO uint16_t r;\r
- struct { /* UCA0MCTLW Bits */\r
- __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint16_t bBRF : 4; /* First modulation stage select */\r
- __IO uint16_t bBRS : 8; /* Second modulation stage select */\r
- } b;\r
- } rMCTLW;\r
- union { /* UCA0STATW Register */\r
- __IO uint16_t r;\r
- struct { /* UCA0STATW Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */\r
- __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */\r
- __IO uint16_t bRXERR : 1; /* Receive error flag */\r
- __IO uint16_t bBRK : 1; /* Break detect flag */\r
- __IO uint16_t bPE : 1; /* */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA0STATW_SPI Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */\r
- __IO uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- } a;\r
- } rSTATW;\r
- union { /* UCA0RXBUF Register */\r
- __I uint16_t r;\r
- struct { /* UCA0RXBUF Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA0RXBUF_SPI Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rRXBUF;\r
- union { /* UCA0TXBUF Register */\r
- __IO uint16_t r;\r
- struct { /* UCA0TXBUF Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA0TXBUF_SPI Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rTXBUF;\r
- union { /* UCA0ABCTL Register */\r
- __IO uint16_t r;\r
- struct { /* UCA0ABCTL Bits */\r
- __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bBTOE : 1; /* Break time out error */\r
- __IO uint16_t bSTOE : 1; /* Synch field time out error */\r
- __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */\r
- __I uint16_t bRESERVED1 : 10; /* Reserved */\r
- } b;\r
- } rABCTL;\r
- union { /* UCA0IRCTL Register */\r
- __IO uint16_t r;\r
- struct { /* UCA0IRCTL Bits */\r
- __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */\r
- __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */\r
- __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */\r
- __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */\r
- __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */\r
- __IO uint16_t bIRRXFL : 4; /* Receive filter length */\r
- } b;\r
- } rIRCTL;\r
- uint8_t RESERVED1[6];\r
- union { /* UCA0IE Register */\r
- __IO uint16_t r;\r
- struct { /* UCA0IE Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */\r
- __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */\r
- __I uint16_t bRESERVED0 : 12; /* Reserved */\r
- } b;\r
- struct { /* UCA0IE_SPI Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIE;\r
- union { /* UCA0IFG Register */\r
- __IO uint16_t r;\r
- struct { /* UCA0IFG Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */\r
- __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */\r
- __I uint16_t bRESERVED0 : 12; /* Reserved */\r
- } b;\r
- struct { /* UCA0IFG_SPI Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIFG;\r
- __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */\r
-} EUSCI_A0_Type;\r
+ __I uint8_t IN; /**< Port Input */\r
+ uint8_t RESERVED0;\r
+ __IO uint8_t OUT; /**< Port Output */\r
+ uint8_t RESERVED1;\r
+ __IO uint8_t DIR; /**< Port Direction */\r
+ uint8_t RESERVED2;\r
+ __IO uint8_t REN; /**< Port Resistor Enable */\r
+ uint8_t RESERVED3;\r
+ __IO uint8_t DS; /**< Port Drive Strength */\r
+ uint8_t RESERVED4;\r
+ __IO uint8_t SEL0; /**< Port Select 0 */\r
+ uint8_t RESERVED5;\r
+ __IO uint8_t SEL1; /**< Port Select 1 */\r
+ uint8_t RESERVED6;\r
+ __I uint16_t IV; /**< Port Interrupt Vector Value */\r
+ uint8_t RESERVED7[6];\r
+ __IO uint8_t SELC; /**< Port Complement Select */\r
+ uint8_t RESERVED8;\r
+ __IO uint8_t IES; /**< Port Interrupt Edge Select */\r
+ uint8_t RESERVED9;\r
+ __IO uint8_t IE; /**< Port Interrupt Enable */\r
+ uint8_t RESERVED10;\r
+ __IO uint8_t IFG; /**< Port Interrupt Flag */\r
+} DIO_PORT_Odd_Interruptable_Type;\r
\r
-\r
-//*****************************************************************************\r
-// EUSCI_A1 Registers\r
-//*****************************************************************************\r
typedef struct {\r
- union { /* UCA1CTLW0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCA1CTLW0 Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bTXBRK : 1; /* Transmit break */\r
- __IO uint16_t bTXADDR : 1; /* Transmit address */\r
- __IO uint16_t bDORM : 1; /* Dormant */\r
- __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */\r
- __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI_A mode */\r
- __IO uint16_t bSPB : 1; /* Stop bit select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bPAR : 1; /* Parity select */\r
- __IO uint16_t bPEN : 1; /* Parity enable */\r
- } b;\r
- struct { /* UCA1CTLW0_SPI Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */\r
- __I uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bCKPL : 1; /* Clock polarity select */\r
- __IO uint16_t bCKPH : 1; /* Clock phase select */\r
- } a;\r
- } rCTLW0;\r
- union { /* UCA1CTLW1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCA1CTLW1 Bits */\r
- __IO uint16_t bGLIT : 2; /* Deglitch time */\r
- __I uint16_t bRESERVED0 : 14; /* Reserved */\r
- } b;\r
- } rCTLW1;\r
- uint8_t RESERVED0[2];\r
- __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */\r
- union { /* UCA1MCTLW Register */\r
- __IO uint16_t r;\r
- struct { /* UCA1MCTLW Bits */\r
- __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint16_t bBRF : 4; /* First modulation stage select */\r
- __IO uint16_t bBRS : 8; /* Second modulation stage select */\r
- } b;\r
- } rMCTLW;\r
- union { /* UCA1STATW Register */\r
- __IO uint16_t r;\r
- struct { /* UCA1STATW Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */\r
- __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */\r
- __IO uint16_t bRXERR : 1; /* Receive error flag */\r
- __IO uint16_t bBRK : 1; /* Break detect flag */\r
- __IO uint16_t bPE : 1; /* */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA1STATW_SPI Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */\r
- __IO uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- } a;\r
- } rSTATW;\r
- union { /* UCA1RXBUF Register */\r
- __I uint16_t r;\r
- struct { /* UCA1RXBUF Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA1RXBUF_SPI Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rRXBUF;\r
- union { /* UCA1TXBUF Register */\r
- __IO uint16_t r;\r
- struct { /* UCA1TXBUF Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA1TXBUF_SPI Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rTXBUF;\r
- union { /* UCA1ABCTL Register */\r
- __IO uint16_t r;\r
- struct { /* UCA1ABCTL Bits */\r
- __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bBTOE : 1; /* Break time out error */\r
- __IO uint16_t bSTOE : 1; /* Synch field time out error */\r
- __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */\r
- __I uint16_t bRESERVED1 : 10; /* Reserved */\r
- } b;\r
- } rABCTL;\r
- union { /* UCA1IRCTL Register */\r
- __IO uint16_t r;\r
- struct { /* UCA1IRCTL Bits */\r
- __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */\r
- __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */\r
- __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */\r
- __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */\r
- __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */\r
- __IO uint16_t bIRRXFL : 4; /* Receive filter length */\r
- } b;\r
- } rIRCTL;\r
- uint8_t RESERVED1[6];\r
- union { /* UCA1IE Register */\r
- __IO uint16_t r;\r
- struct { /* UCA1IE Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */\r
- __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */\r
- __I uint16_t bRESERVED0 : 12; /* Reserved */\r
- } b;\r
- struct { /* UCA1IE_SPI Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIE;\r
- union { /* UCA1IFG Register */\r
- __IO uint16_t r;\r
- struct { /* UCA1IFG Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */\r
- __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */\r
- __I uint16_t bRESERVED0 : 12; /* Reserved */\r
- } b;\r
- struct { /* UCA1IFG_SPI Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIFG;\r
- __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */\r
-} EUSCI_A1_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A2 Registers\r
-//*****************************************************************************\r
+ uint8_t RESERVED0;\r
+ __I uint8_t IN; /**< Port Input */\r
+ uint8_t RESERVED1;\r
+ __IO uint8_t OUT; /**< Port Output */\r
+ uint8_t RESERVED2;\r
+ __IO uint8_t DIR; /**< Port Direction */\r
+ uint8_t RESERVED3;\r
+ __IO uint8_t REN; /**< Port Resistor Enable */\r
+ uint8_t RESERVED4;\r
+ __IO uint8_t DS; /**< Port Drive Strength */\r
+ uint8_t RESERVED5;\r
+ __IO uint8_t SEL0; /**< Port Select 0 */\r
+ uint8_t RESERVED6;\r
+ __IO uint8_t SEL1; /**< Port Select 1 */\r
+ uint8_t RESERVED7[9];\r
+ __IO uint8_t SELC; /**< Port Complement Select */\r
+ uint8_t RESERVED8;\r
+ __IO uint8_t IES; /**< Port Interrupt Edge Select */\r
+ uint8_t RESERVED9;\r
+ __IO uint8_t IE; /**< Port Interrupt Enable */\r
+ uint8_t RESERVED10;\r
+ __IO uint8_t IFG; /**< Port Interrupt Flag */\r
+ __I uint16_t IV; /**< Port Interrupt Vector Value */\r
+} DIO_PORT_Even_Interruptable_Type;\r
+\r
+/*@}*/ /* end of group MSP432P401R_DIO */\r
+\r
+\r
+/******************************************************************************\r
+* DMA Registers\r
+******************************************************************************/\r
+/** @addtogroup DMA MSP432P401R (DMA)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* UCA2CTLW0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCA2CTLW0 Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bTXBRK : 1; /* Transmit break */\r
- __IO uint16_t bTXADDR : 1; /* Transmit address */\r
- __IO uint16_t bDORM : 1; /* Dormant */\r
- __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */\r
- __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI_A mode */\r
- __IO uint16_t bSPB : 1; /* Stop bit select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bPAR : 1; /* Parity select */\r
- __IO uint16_t bPEN : 1; /* Parity enable */\r
- } b;\r
- struct { /* UCA2CTLW0_SPI Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */\r
- __I uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bCKPL : 1; /* Clock polarity select */\r
- __IO uint16_t bCKPH : 1; /* Clock phase select */\r
- } a;\r
- } rCTLW0;\r
- union { /* UCA2CTLW1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCA2CTLW1 Bits */\r
- __IO uint16_t bGLIT : 2; /* Deglitch time */\r
- __I uint16_t bRESERVED0 : 14; /* Reserved */\r
- } b;\r
- } rCTLW1;\r
- uint8_t RESERVED0[2];\r
- __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */\r
- union { /* UCA2MCTLW Register */\r
- __IO uint16_t r;\r
- struct { /* UCA2MCTLW Bits */\r
- __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint16_t bBRF : 4; /* First modulation stage select */\r
- __IO uint16_t bBRS : 8; /* Second modulation stage select */\r
- } b;\r
- } rMCTLW;\r
- union { /* UCA2STATW Register */\r
- __IO uint16_t r;\r
- struct { /* UCA2STATW Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */\r
- __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */\r
- __IO uint16_t bRXERR : 1; /* Receive error flag */\r
- __IO uint16_t bBRK : 1; /* Break detect flag */\r
- __IO uint16_t bPE : 1; /* */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA2STATW_SPI Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */\r
- __IO uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- } a;\r
- } rSTATW;\r
- union { /* UCA2RXBUF Register */\r
- __I uint16_t r;\r
- struct { /* UCA2RXBUF Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA2RXBUF_SPI Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rRXBUF;\r
- union { /* UCA2TXBUF Register */\r
- __IO uint16_t r;\r
- struct { /* UCA2TXBUF Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA2TXBUF_SPI Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rTXBUF;\r
- union { /* UCA2ABCTL Register */\r
- __IO uint16_t r;\r
- struct { /* UCA2ABCTL Bits */\r
- __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bBTOE : 1; /* Break time out error */\r
- __IO uint16_t bSTOE : 1; /* Synch field time out error */\r
- __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */\r
- __I uint16_t bRESERVED1 : 10; /* Reserved */\r
- } b;\r
- } rABCTL;\r
- union { /* UCA2IRCTL Register */\r
- __IO uint16_t r;\r
- struct { /* UCA2IRCTL Bits */\r
- __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */\r
- __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */\r
- __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */\r
- __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */\r
- __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */\r
- __IO uint16_t bIRRXFL : 4; /* Receive filter length */\r
- } b;\r
- } rIRCTL;\r
- uint8_t RESERVED1[6];\r
- union { /* UCA2IE Register */\r
- __IO uint16_t r;\r
- struct { /* UCA2IE Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */\r
- __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */\r
- __I uint16_t bRESERVED0 : 12; /* Reserved */\r
- } b;\r
- struct { /* UCA2IE_SPI Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIE;\r
- union { /* UCA2IFG Register */\r
- __IO uint16_t r;\r
- struct { /* UCA2IFG Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */\r
- __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */\r
- __I uint16_t bRESERVED0 : 12; /* Reserved */\r
- } b;\r
- struct { /* UCA2IFG_SPI Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIFG;\r
- __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */\r
-} EUSCI_A2_Type;\r
+ __I uint32_t DEVICE_CFG; /**< Device Configuration Status */\r
+ __IO uint32_t SW_CHTRIG; /**< Software Channel Trigger Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t CH_SRCCFG[32]; /**< Channel n Source Configuration Register */\r
+ uint32_t RESERVED1[28];\r
+ __IO uint32_t INT1_SRCCFG; /**< Interrupt 1 Source Channel Configuration */\r
+ __IO uint32_t INT2_SRCCFG; /**< Interrupt 2 Source Channel Configuration Register */\r
+ __IO uint32_t INT3_SRCCFG; /**< Interrupt 3 Source Channel Configuration Register */\r
+ uint32_t RESERVED2;\r
+ __I uint32_t INT0_SRCFLG; /**< Interrupt 0 Source Channel Flag Register */\r
+ __O uint32_t INT0_CLRFLG; /**< Interrupt 0 Source Channel Clear Flag Register */\r
+} DMA_Channel_Type;\r
\r
-\r
-//*****************************************************************************\r
-// EUSCI_A3 Registers\r
-//*****************************************************************************\r
typedef struct {\r
- union { /* UCA3CTLW0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCA3CTLW0 Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bTXBRK : 1; /* Transmit break */\r
- __IO uint16_t bTXADDR : 1; /* Transmit address */\r
- __IO uint16_t bDORM : 1; /* Dormant */\r
- __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */\r
- __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI_A mode */\r
- __IO uint16_t bSPB : 1; /* Stop bit select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bPAR : 1; /* Parity select */\r
- __IO uint16_t bPEN : 1; /* Parity enable */\r
- } b;\r
- struct { /* UCA3CTLW0_SPI Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */\r
- __I uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bCKPL : 1; /* Clock polarity select */\r
- __IO uint16_t bCKPH : 1; /* Clock phase select */\r
- } a;\r
- } rCTLW0;\r
- union { /* UCA3CTLW1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCA3CTLW1 Bits */\r
- __IO uint16_t bGLIT : 2; /* Deglitch time */\r
- __I uint16_t bRESERVED0 : 14; /* Reserved */\r
- } b;\r
- } rCTLW1;\r
- uint8_t RESERVED0[2];\r
- __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */\r
- union { /* UCA3MCTLW Register */\r
- __IO uint16_t r;\r
- struct { /* UCA3MCTLW Bits */\r
- __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint16_t bBRF : 4; /* First modulation stage select */\r
- __IO uint16_t bBRS : 8; /* Second modulation stage select */\r
- } b;\r
- } rMCTLW;\r
- union { /* UCA3STATW Register */\r
- __IO uint16_t r;\r
- struct { /* UCA3STATW Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */\r
- __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */\r
- __IO uint16_t bRXERR : 1; /* Receive error flag */\r
- __IO uint16_t bBRK : 1; /* Break detect flag */\r
- __IO uint16_t bPE : 1; /* */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA3STATW_SPI Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */\r
- __IO uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- } a;\r
- } rSTATW;\r
- union { /* UCA3RXBUF Register */\r
- __I uint16_t r;\r
- struct { /* UCA3RXBUF Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA3RXBUF_SPI Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rRXBUF;\r
- union { /* UCA3TXBUF Register */\r
- __IO uint16_t r;\r
- struct { /* UCA3TXBUF Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCA3TXBUF_SPI Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rTXBUF;\r
- union { /* UCA3ABCTL Register */\r
- __IO uint16_t r;\r
- struct { /* UCA3ABCTL Bits */\r
- __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bBTOE : 1; /* Break time out error */\r
- __IO uint16_t bSTOE : 1; /* Synch field time out error */\r
- __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */\r
- __I uint16_t bRESERVED1 : 10; /* Reserved */\r
- } b;\r
- } rABCTL;\r
- union { /* UCA3IRCTL Register */\r
- __IO uint16_t r;\r
- struct { /* UCA3IRCTL Bits */\r
- __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */\r
- __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */\r
- __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */\r
- __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */\r
- __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */\r
- __IO uint16_t bIRRXFL : 4; /* Receive filter length */\r
- } b;\r
- } rIRCTL;\r
- uint8_t RESERVED1[6];\r
- union { /* UCA3IE Register */\r
- __IO uint16_t r;\r
- struct { /* UCA3IE Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */\r
- __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */\r
- __I uint16_t bRESERVED0 : 12; /* Reserved */\r
- } b;\r
- struct { /* UCA3IE_SPI Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIE;\r
- union { /* UCA3IFG Register */\r
- __IO uint16_t r;\r
- struct { /* UCA3IFG Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */\r
- __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */\r
- __I uint16_t bRESERVED0 : 12; /* Reserved */\r
- } b;\r
- struct { /* UCA3IFG_SPI Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIFG;\r
- __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */\r
-} EUSCI_A3_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B0 Registers\r
-//*****************************************************************************\r
+ __I uint32_t STAT; /**< Status Register */\r
+ __O uint32_t CFG; /**< Configuration Register */\r
+ __IO uint32_t CTLBASE; /**< Channel Control Data Base Pointer Register */\r
+ __I uint32_t ATLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
+ __I uint32_t WAITSTAT; /**< Channel Wait on Request Status Register */\r
+ __O uint32_t SWREQ; /**< Channel Software Request Register */\r
+ __IO uint32_t USEBURSTSET; /**< Channel Useburst Set Register */\r
+ __O uint32_t USEBURSTCLR; /**< Channel Useburst Clear Register */\r
+ __IO uint32_t REQMASKSET; /**< Channel Request Mask Set Register */\r
+ __O uint32_t REQMASKCLR; /**< Channel Request Mask Clear Register */\r
+ __IO uint32_t ENASET; /**< Channel Enable Set Register */\r
+ __O uint32_t ENACLR; /**< Channel Enable Clear Register */\r
+ __IO uint32_t ALTSET; /**< Channel Primary-Alternate Set Register */\r
+ __O uint32_t ALTCLR; /**< Channel Primary-Alternate Clear Register */\r
+ __IO uint32_t PRIOSET; /**< Channel Priority Set Register */\r
+ __O uint32_t PRIOCLR; /**< Channel Priority Clear Register */\r
+ uint32_t RESERVED4[3];\r
+ __IO uint32_t ERRCLR; /**< Bus Error Clear Register */\r
+} DMA_Control_Type;\r
+\r
+/*@}*/ /* end of group DMA */\r
+\r
+\r
+/******************************************************************************\r
+* EUSCI_A Registers\r
+******************************************************************************/\r
+/** @addtogroup EUSCI_A MSP432P401R (EUSCI_A)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* UCB0CTLW0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0CTLW0 Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */\r
- __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */\r
- __IO uint16_t bTXNACK : 1; /* Transmit a NACK */\r
- __IO uint16_t bTR : 1; /* Transmitter/receiver */\r
- __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI_B mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bMM : 1; /* Multi-master environment select */\r
- __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */\r
- __IO uint16_t bA10 : 1; /* Own addressing mode select */\r
- } b;\r
- struct { /* UCB0CTLW0_SPI Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */\r
- __I uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bCKPL : 1; /* Clock polarity select */\r
- __IO uint16_t bCKPH : 1; /* Clock phase select */\r
- } a;\r
- } rCTLW0;\r
- union { /* UCB0CTLW1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0CTLW1 Bits */\r
- __IO uint16_t bGLIT : 2; /* Deglitch time */\r
- __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */\r
- __IO uint16_t bSWACK : 1; /* SW or HW ACK control */\r
- __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */\r
- __IO uint16_t bCLTO : 2; /* Clock low timeout select */\r
- __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */\r
- __I uint16_t bRESERVED0 : 7; /* Reserved */\r
- } b;\r
- } rCTLW1;\r
- uint8_t RESERVED0[2];\r
- __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */\r
- union { /* UCB0STATW Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0STATW Bits */\r
- __I uint16_t bRESERVED1 : 4; /* Reserved */\r
- __I uint16_t bBBUSY : 1; /* Bus busy */\r
- __I uint16_t bGC : 1; /* General call address received */\r
- __I uint16_t bSCLLOW : 1; /* SCL low */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __I uint16_t bBCNT : 8; /* Hardware byte counter value */\r
- } b;\r
- struct { /* UCB0STATW_SPI Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_B busy */\r
- __IO uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- } a;\r
- } rSTATW;\r
- union { /* UCB0TBCNT Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0TBCNT Bits */\r
- __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- } rTBCNT;\r
- union { /* UCB0RXBUF Register */\r
- __I uint16_t r;\r
- struct { /* UCB0RXBUF Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCB0RXBUF_SPI Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rRXBUF;\r
- union { /* UCB0TXBUF Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0TXBUF Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCB0TXBUF_SPI Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rTXBUF;\r
- uint8_t RESERVED1[4];\r
- union { /* UCB0I2COA0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0I2COA0 Bits */\r
- __IO uint16_t bI2COA0 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 4; /* Reserved */\r
- __IO uint16_t bGCEN : 1; /* General call response enable */\r
- } b;\r
- } rI2COA0;\r
- union { /* UCB0I2COA1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0I2COA1 Bits */\r
- __IO uint16_t bI2COA1 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA1;\r
- union { /* UCB0I2COA2 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0I2COA2 Bits */\r
- __IO uint16_t bI2COA2 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA2;\r
- union { /* UCB0I2COA3 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0I2COA3 Bits */\r
- __IO uint16_t bI2COA3 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA3;\r
- union { /* UCB0ADDRX Register */\r
- __I uint16_t r;\r
- struct { /* UCB0ADDRX Bits */\r
- __I uint16_t bADDRX : 10; /* Received Address Register */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rADDRX;\r
- union { /* UCB0ADDMASK Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0ADDMASK Bits */\r
- __IO uint16_t bADDMASK : 10; /* */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rADDMASK;\r
- union { /* UCB0I2CSA Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0I2CSA Bits */\r
- __IO uint16_t bI2CSA : 10; /* I2C slave address */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rI2CSA;\r
- uint8_t RESERVED2[8];\r
- union { /* UCB0IE Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0IE Bits */\r
- __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */\r
- __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */\r
- __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */\r
- __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */\r
- __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */\r
- __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */\r
- __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */\r
- __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */\r
- __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */\r
- __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */\r
- __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */\r
- __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */\r
- __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */\r
- __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */\r
- __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- } b;\r
- struct { /* UCB0IE_SPI Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIE;\r
- union { /* UCB0IFG Register */\r
- __IO uint16_t r;\r
- struct { /* UCB0IFG Bits */\r
- __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */\r
- __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */\r
- __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */\r
- __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */\r
- __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */\r
- __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */\r
- __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */\r
- __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */\r
- __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */\r
- __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */\r
- __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */\r
- __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */\r
- __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */\r
- __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */\r
- __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- } b;\r
- struct { /* UCB0IFG_SPI Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIFG;\r
- __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */\r
-} EUSCI_B0_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B1 Registers\r
-//*****************************************************************************\r
+ __IO uint16_t CTLW0; /**< eUSCI_Ax Control Word Register 0 */\r
+ __IO uint16_t CTLW1; /**< eUSCI_Ax Control Word Register 1 */\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t BRW; /**< eUSCI_Ax Baud Rate Control Word Register */\r
+ __IO uint16_t MCTLW; /**< eUSCI_Ax Modulation Control Word Register */\r
+ __IO uint16_t STATW; /**< eUSCI_Ax Status Register */\r
+ __I uint16_t RXBUF; /**< eUSCI_Ax Receive Buffer Register */\r
+ __IO uint16_t TXBUF; /**< eUSCI_Ax Transmit Buffer Register */\r
+ __IO uint16_t ABCTL; /**< eUSCI_Ax Auto Baud Rate Control Register */\r
+ __IO uint16_t IRCTL; /**< eUSCI_Ax IrDA Control Word Register */\r
+ uint16_t RESERVED1[3];\r
+ __IO uint16_t IE; /**< eUSCI_Ax Interrupt Enable Register */\r
+ __IO uint16_t IFG; /**< eUSCI_Ax Interrupt Flag Register */\r
+ __I uint16_t IV; /**< eUSCI_Ax Interrupt Vector Register */\r
+} EUSCI_A_Type;\r
+\r
+/*@}*/ /* end of group EUSCI_A */\r
+\r
+/** @addtogroup EUSCI_A_SPI MSP432P401R (EUSCI_A_SPI)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* UCB1CTLW0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1CTLW0 Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */\r
- __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */\r
- __IO uint16_t bTXNACK : 1; /* Transmit a NACK */\r
- __IO uint16_t bTR : 1; /* Transmitter/receiver */\r
- __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI_B mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bMM : 1; /* Multi-master environment select */\r
- __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */\r
- __IO uint16_t bA10 : 1; /* Own addressing mode select */\r
- } b;\r
- struct { /* UCB1CTLW0_SPI Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */\r
- __I uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bCKPL : 1; /* Clock polarity select */\r
- __IO uint16_t bCKPH : 1; /* Clock phase select */\r
- } a;\r
- } rCTLW0;\r
- union { /* UCB1CTLW1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1CTLW1 Bits */\r
- __IO uint16_t bGLIT : 2; /* Deglitch time */\r
- __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */\r
- __IO uint16_t bSWACK : 1; /* SW or HW ACK control */\r
- __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */\r
- __IO uint16_t bCLTO : 2; /* Clock low timeout select */\r
- __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */\r
- __I uint16_t bRESERVED0 : 7; /* Reserved */\r
- } b;\r
- } rCTLW1;\r
- uint8_t RESERVED0[2];\r
- __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */\r
- union { /* UCB1STATW Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1STATW Bits */\r
- __I uint16_t bRESERVED1 : 4; /* Reserved */\r
- __I uint16_t bBBUSY : 1; /* Bus busy */\r
- __I uint16_t bGC : 1; /* General call address received */\r
- __I uint16_t bSCLLOW : 1; /* SCL low */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __I uint16_t bBCNT : 8; /* Hardware byte counter value */\r
- } b;\r
- struct { /* UCB1STATW_SPI Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_B busy */\r
- __IO uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- } a;\r
- } rSTATW;\r
- union { /* UCB1TBCNT Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1TBCNT Bits */\r
- __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- } rTBCNT;\r
- union { /* UCB1RXBUF Register */\r
- __I uint16_t r;\r
- struct { /* UCB1RXBUF Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCB1RXBUF_SPI Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rRXBUF;\r
- union { /* UCB1TXBUF Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1TXBUF Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCB1TXBUF_SPI Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rTXBUF;\r
- uint8_t RESERVED1[4];\r
- union { /* UCB1I2COA0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1I2COA0 Bits */\r
- __IO uint16_t bI2COA0 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 4; /* Reserved */\r
- __IO uint16_t bGCEN : 1; /* General call response enable */\r
- } b;\r
- } rI2COA0;\r
- union { /* UCB1I2COA1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1I2COA1 Bits */\r
- __IO uint16_t bI2COA1 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA1;\r
- union { /* UCB1I2COA2 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1I2COA2 Bits */\r
- __IO uint16_t bI2COA2 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA2;\r
- union { /* UCB1I2COA3 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1I2COA3 Bits */\r
- __IO uint16_t bI2COA3 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA3;\r
- union { /* UCB1ADDRX Register */\r
- __I uint16_t r;\r
- struct { /* UCB1ADDRX Bits */\r
- __I uint16_t bADDRX : 10; /* Received Address Register */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rADDRX;\r
- union { /* UCB1ADDMASK Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1ADDMASK Bits */\r
- __IO uint16_t bADDMASK : 10; /* */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rADDMASK;\r
- union { /* UCB1I2CSA Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1I2CSA Bits */\r
- __IO uint16_t bI2CSA : 10; /* I2C slave address */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rI2CSA;\r
- uint8_t RESERVED2[8];\r
- union { /* UCB1IE Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1IE Bits */\r
- __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */\r
- __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */\r
- __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */\r
- __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */\r
- __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */\r
- __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */\r
- __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */\r
- __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */\r
- __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */\r
- __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */\r
- __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */\r
- __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */\r
- __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */\r
- __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */\r
- __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- } b;\r
- struct { /* UCB1IE_SPI Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIE;\r
- union { /* UCB1IFG Register */\r
- __IO uint16_t r;\r
- struct { /* UCB1IFG Bits */\r
- __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */\r
- __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */\r
- __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */\r
- __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */\r
- __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */\r
- __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */\r
- __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */\r
- __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */\r
- __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */\r
- __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */\r
- __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */\r
- __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */\r
- __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */\r
- __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */\r
- __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- } b;\r
- struct { /* UCB1IFG_SPI Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIFG;\r
- __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */\r
-} EUSCI_B1_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B2 Registers\r
-//*****************************************************************************\r
+ __IO uint16_t CTLW0; /**< eUSCI_Ax Control Word Register 0 */\r
+ uint16_t RESERVED0[2];\r
+ __IO uint16_t BRW; /**< eUSCI_Ax Bit Rate Control Register 1 */\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t STATW;\r
+ __I uint16_t RXBUF; /**< eUSCI_Ax Receive Buffer Register */\r
+ __IO uint16_t TXBUF; /**< eUSCI_Ax Transmit Buffer Register */\r
+ uint16_t RESERVED2[5];\r
+ __IO uint16_t IE; /**< eUSCI_Ax Interrupt Enable Register */\r
+ __IO uint16_t IFG; /**< eUSCI_Ax Interrupt Flag Register */\r
+ __I uint16_t IV; /**< eUSCI_Ax Interrupt Vector Register */\r
+} EUSCI_A_SPI_Type;\r
+\r
+/*@}*/ /* end of group EUSCI_A_SPI */\r
+\r
+\r
+/******************************************************************************\r
+* EUSCI_B Registers\r
+******************************************************************************/\r
+/** @addtogroup EUSCI_B MSP432P401R (EUSCI_B)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* UCB2CTLW0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2CTLW0 Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */\r
- __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */\r
- __IO uint16_t bTXNACK : 1; /* Transmit a NACK */\r
- __IO uint16_t bTR : 1; /* Transmitter/receiver */\r
- __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI_B mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bMM : 1; /* Multi-master environment select */\r
- __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */\r
- __IO uint16_t bA10 : 1; /* Own addressing mode select */\r
- } b;\r
- struct { /* UCB2CTLW0_SPI Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */\r
- __I uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bCKPL : 1; /* Clock polarity select */\r
- __IO uint16_t bCKPH : 1; /* Clock phase select */\r
- } a;\r
- } rCTLW0;\r
- union { /* UCB2CTLW1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2CTLW1 Bits */\r
- __IO uint16_t bGLIT : 2; /* Deglitch time */\r
- __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */\r
- __IO uint16_t bSWACK : 1; /* SW or HW ACK control */\r
- __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */\r
- __IO uint16_t bCLTO : 2; /* Clock low timeout select */\r
- __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */\r
- __I uint16_t bRESERVED0 : 7; /* Reserved */\r
- } b;\r
- } rCTLW1;\r
- uint8_t RESERVED0[2];\r
- __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */\r
- union { /* UCB2STATW Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2STATW Bits */\r
- __I uint16_t bRESERVED1 : 4; /* Reserved */\r
- __I uint16_t bBBUSY : 1; /* Bus busy */\r
- __I uint16_t bGC : 1; /* General call address received */\r
- __I uint16_t bSCLLOW : 1; /* SCL low */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __I uint16_t bBCNT : 8; /* Hardware byte counter value */\r
- } b;\r
- struct { /* UCB2STATW_SPI Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_B busy */\r
- __IO uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- } a;\r
- } rSTATW;\r
- union { /* UCB2TBCNT Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2TBCNT Bits */\r
- __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- } rTBCNT;\r
- union { /* UCB2RXBUF Register */\r
- __I uint16_t r;\r
- struct { /* UCB2RXBUF Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCB2RXBUF_SPI Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rRXBUF;\r
- union { /* UCB2TXBUF Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2TXBUF Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCB2TXBUF_SPI Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rTXBUF;\r
- uint8_t RESERVED1[4];\r
- union { /* UCB2I2COA0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2I2COA0 Bits */\r
- __IO uint16_t bI2COA0 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 4; /* Reserved */\r
- __IO uint16_t bGCEN : 1; /* General call response enable */\r
- } b;\r
- } rI2COA0;\r
- union { /* UCB2I2COA1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2I2COA1 Bits */\r
- __IO uint16_t bI2COA1 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA1;\r
- union { /* UCB2I2COA2 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2I2COA2 Bits */\r
- __IO uint16_t bI2COA2 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA2;\r
- union { /* UCB2I2COA3 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2I2COA3 Bits */\r
- __IO uint16_t bI2COA3 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA3;\r
- union { /* UCB2ADDRX Register */\r
- __I uint16_t r;\r
- struct { /* UCB2ADDRX Bits */\r
- __I uint16_t bADDRX : 10; /* Received Address Register */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rADDRX;\r
- union { /* UCB2ADDMASK Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2ADDMASK Bits */\r
- __IO uint16_t bADDMASK : 10; /* */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rADDMASK;\r
- union { /* UCB2I2CSA Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2I2CSA Bits */\r
- __IO uint16_t bI2CSA : 10; /* I2C slave address */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rI2CSA;\r
- uint8_t RESERVED2[8];\r
- union { /* UCB2IE Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2IE Bits */\r
- __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */\r
- __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */\r
- __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */\r
- __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */\r
- __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */\r
- __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */\r
- __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */\r
- __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */\r
- __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */\r
- __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */\r
- __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */\r
- __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */\r
- __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */\r
- __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */\r
- __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- } b;\r
- struct { /* UCB2IE_SPI Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIE;\r
- union { /* UCB2IFG Register */\r
- __IO uint16_t r;\r
- struct { /* UCB2IFG Bits */\r
- __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */\r
- __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */\r
- __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */\r
- __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */\r
- __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */\r
- __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */\r
- __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */\r
- __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */\r
- __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */\r
- __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */\r
- __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */\r
- __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */\r
- __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */\r
- __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */\r
- __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- } b;\r
- struct { /* UCB2IFG_SPI Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIFG;\r
- __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */\r
-} EUSCI_B2_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B3 Registers\r
-//*****************************************************************************\r
+ __IO uint16_t CTLW0; /**< eUSCI_Bx Control Word Register 0 */\r
+ __IO uint16_t CTLW1; /**< eUSCI_Bx Control Word Register 1 */\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t BRW; /**< eUSCI_Bx Baud Rate Control Word Register */\r
+ __IO uint16_t STATW; /**< eUSCI_Bx Status Register */\r
+ __IO uint16_t TBCNT; /**< eUSCI_Bx Byte Counter Threshold Register */\r
+ __I uint16_t RXBUF; /**< eUSCI_Bx Receive Buffer Register */\r
+ __IO uint16_t TXBUF; /**< eUSCI_Bx Transmit Buffer Register */\r
+ uint16_t RESERVED1[2];\r
+ __IO uint16_t I2COA0; /**< eUSCI_Bx I2C Own Address 0 Register */\r
+ __IO uint16_t I2COA1; /**< eUSCI_Bx I2C Own Address 1 Register */\r
+ __IO uint16_t I2COA2; /**< eUSCI_Bx I2C Own Address 2 Register */\r
+ __IO uint16_t I2COA3; /**< eUSCI_Bx I2C Own Address 3 Register */\r
+ __I uint16_t ADDRX; /**< eUSCI_Bx I2C Received Address Register */\r
+ __IO uint16_t ADDMASK; /**< eUSCI_Bx I2C Address Mask Register */\r
+ __IO uint16_t I2CSA; /**< eUSCI_Bx I2C Slave Address Register */\r
+ uint16_t RESERVED2[4];\r
+ __IO uint16_t IE; /**< eUSCI_Bx Interrupt Enable Register */\r
+ __IO uint16_t IFG; /**< eUSCI_Bx Interrupt Flag Register */\r
+ __I uint16_t IV; /**< eUSCI_Bx Interrupt Vector Register */\r
+} EUSCI_B_Type;\r
+\r
+/*@}*/ /* end of group EUSCI_B */\r
+\r
+/** @addtogroup EUSCI_B_SPI MSP432P401R (EUSCI_B_SPI)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* UCB3CTLW0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3CTLW0 Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */\r
- __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */\r
- __IO uint16_t bTXNACK : 1; /* Transmit a NACK */\r
- __IO uint16_t bTR : 1; /* Transmitter/receiver */\r
- __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI_B mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bMM : 1; /* Multi-master environment select */\r
- __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */\r
- __IO uint16_t bA10 : 1; /* Own addressing mode select */\r
- } b;\r
- struct { /* UCB3CTLW0_SPI Bits */\r
- __IO uint16_t bSWRST : 1; /* Software reset enable */\r
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */\r
- __I uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */\r
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */\r
- __IO uint16_t bMODE : 2; /* eUSCI mode */\r
- __IO uint16_t bMST : 1; /* Master mode select */\r
- __IO uint16_t b7BIT : 1; /* Character length */\r
- __IO uint16_t bMSB : 1; /* MSB first select */\r
- __IO uint16_t bCKPL : 1; /* Clock polarity select */\r
- __IO uint16_t bCKPH : 1; /* Clock phase select */\r
- } a;\r
- } rCTLW0;\r
- union { /* UCB3CTLW1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3CTLW1 Bits */\r
- __IO uint16_t bGLIT : 2; /* Deglitch time */\r
- __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */\r
- __IO uint16_t bSWACK : 1; /* SW or HW ACK control */\r
- __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */\r
- __IO uint16_t bCLTO : 2; /* Clock low timeout select */\r
- __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */\r
- __I uint16_t bRESERVED0 : 7; /* Reserved */\r
- } b;\r
- } rCTLW1;\r
- uint8_t RESERVED0[2];\r
- __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */\r
- union { /* UCB3STATW Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3STATW Bits */\r
- __I uint16_t bRESERVED1 : 4; /* Reserved */\r
- __I uint16_t bBBUSY : 1; /* Bus busy */\r
- __I uint16_t bGC : 1; /* General call address received */\r
- __I uint16_t bSCLLOW : 1; /* SCL low */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __I uint16_t bBCNT : 8; /* Hardware byte counter value */\r
- } b;\r
- struct { /* UCB3STATW_SPI Bits */\r
- __I uint16_t bBUSY : 1; /* eUSCI_B busy */\r
- __IO uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bOE : 1; /* Overrun error flag */\r
- __IO uint16_t bFE : 1; /* Framing error flag */\r
- __IO uint16_t bLISTEN : 1; /* Listen enable */\r
- } a;\r
- } rSTATW;\r
- union { /* UCB3TBCNT Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3TBCNT Bits */\r
- __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- } rTBCNT;\r
- union { /* UCB3RXBUF Register */\r
- __I uint16_t r;\r
- struct { /* UCB3RXBUF Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCB3RXBUF_SPI Bits */\r
- __I uint16_t bRXBUF : 8; /* Receive data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rRXBUF;\r
- union { /* UCB3TXBUF Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3TXBUF Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- struct { /* UCB3TXBUF_SPI Bits */\r
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */\r
- __I uint16_t bRESERVED : 8; /* Reserved */\r
- } a;\r
- } rTXBUF;\r
- uint8_t RESERVED1[4];\r
- union { /* UCB3I2COA0 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3I2COA0 Bits */\r
- __IO uint16_t bI2COA0 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 4; /* Reserved */\r
- __IO uint16_t bGCEN : 1; /* General call response enable */\r
- } b;\r
- } rI2COA0;\r
- union { /* UCB3I2COA1 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3I2COA1 Bits */\r
- __IO uint16_t bI2COA1 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA1;\r
- union { /* UCB3I2COA2 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3I2COA2 Bits */\r
- __IO uint16_t bI2COA2 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA2;\r
- union { /* UCB3I2COA3 Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3I2COA3 Bits */\r
- __IO uint16_t bI2COA3 : 10; /* I2C own address */\r
- __IO uint16_t bOAEN : 1; /* Own Address enable register */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- } b;\r
- } rI2COA3;\r
- union { /* UCB3ADDRX Register */\r
- __I uint16_t r;\r
- struct { /* UCB3ADDRX Bits */\r
- __I uint16_t bADDRX : 10; /* Received Address Register */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rADDRX;\r
- union { /* UCB3ADDMASK Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3ADDMASK Bits */\r
- __IO uint16_t bADDMASK : 10; /* */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rADDMASK;\r
- union { /* UCB3I2CSA Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3I2CSA Bits */\r
- __IO uint16_t bI2CSA : 10; /* I2C slave address */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rI2CSA;\r
- uint8_t RESERVED2[8];\r
- union { /* UCB3IE Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3IE Bits */\r
- __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */\r
- __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */\r
- __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */\r
- __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */\r
- __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */\r
- __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */\r
- __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */\r
- __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */\r
- __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */\r
- __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */\r
- __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */\r
- __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */\r
- __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */\r
- __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */\r
- __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- } b;\r
- struct { /* UCB3IE_SPI Bits */\r
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */\r
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIE;\r
- union { /* UCB3IFG Register */\r
- __IO uint16_t r;\r
- struct { /* UCB3IFG Bits */\r
- __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */\r
- __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */\r
- __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */\r
- __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */\r
- __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */\r
- __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */\r
- __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */\r
- __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */\r
- __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */\r
- __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */\r
- __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */\r
- __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */\r
- __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */\r
- __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */\r
- __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- } b;\r
- struct { /* UCB3IFG_SPI Bits */\r
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */\r
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */\r
- __I uint16_t bRESERVED : 14; /* Reserved */\r
- } a;\r
- } rIFG;\r
- __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */\r
-} EUSCI_B3_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// FLCTL Registers\r
-//*****************************************************************************\r
+ __IO uint16_t CTLW0; /**< eUSCI_Bx Control Word Register 0 */\r
+ uint16_t RESERVED0[2];\r
+ __IO uint16_t BRW; /**< eUSCI_Bx Bit Rate Control Register 1 */\r
+ __IO uint16_t STATW;\r
+ uint16_t RESERVED1;\r
+ __I uint16_t RXBUF; /**< eUSCI_Bx Receive Buffer Register */\r
+ __IO uint16_t TXBUF; /**< eUSCI_Bx Transmit Buffer Register */\r
+ uint16_t RESERVED2[13];\r
+ __IO uint16_t IE; /**< eUSCI_Bx Interrupt Enable Register */\r
+ __IO uint16_t IFG; /**< eUSCI_Bx Interrupt Flag Register */\r
+ __I uint16_t IV; /**< eUSCI_Bx Interrupt Vector Register */\r
+} EUSCI_B_SPI_Type;\r
+\r
+/*@}*/ /* end of group EUSCI_B_SPI */\r
+\r
+\r
+/******************************************************************************\r
+* FLCTL Registers\r
+******************************************************************************/\r
+/** @addtogroup FLCTL MSP432P401R (FLCTL)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* FLCTL_POWER_STAT Register */\r
- __I uint32_t r;\r
- struct { /* FLCTL_POWER_STAT Bits */\r
- __I uint32_t bPSTAT : 3; /* */\r
- __I uint32_t bLDOSTAT : 1; /* PSS FLDO GOOD status */\r
- __I uint32_t bVREFSTAT : 1; /* PSS VREF stable status */\r
- __I uint32_t bIREFSTAT : 1; /* PSS IREF stable status */\r
- __I uint32_t bTRIMSTAT : 1; /* PSS trim done status */\r
- __I uint32_t bRD_2T : 1; /* Indicates if Flash is being accessed in 2T mode */\r
- __I uint32_t bRESERVED0 : 24; /* Reserved */\r
- } b;\r
- } rPOWER_STAT;\r
- uint8_t RESERVED0[12];\r
- union { /* FLCTL_BANK0_RDCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_BANK0_RDCTL Bits */\r
- __IO uint32_t bRD_MODE : 4; /* Flash read mode control setting for Bank 0 */\r
- __IO uint32_t bBUFI : 1; /* Enables read buffering feature for instruction fetches to this Bank */\r
- __IO uint32_t bBUFD : 1; /* Enables read buffering feature for data reads to this Bank */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bRESERVED2 : 1; /* Reserved */\r
- __IO uint32_t bRESERVED3 : 1; /* Reserved */\r
- __IO uint32_t bRESERVED4 : 1; /* Reserved */\r
- __IO uint32_t bWAIT : 4; /* Number of wait states for read */\r
- __I uint32_t bRD_MODE_STATUS : 4; /* Read mode */\r
- __I uint32_t bRESERVED5 : 12; /* Reserved */\r
- } b;\r
- } rBANK0_RDCTL;\r
- union { /* FLCTL_BANK1_RDCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_BANK1_RDCTL Bits */\r
- __IO uint32_t bRD_MODE : 4; /* Flash read mode control setting for Bank 0 */\r
- __IO uint32_t bBUFI : 1; /* Enables read buffering feature for instruction fetches to this Bank */\r
- __IO uint32_t bBUFD : 1; /* Enables read buffering feature for data reads to this Bank */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bRESERVED2 : 1; /* Reserved */\r
- __IO uint32_t bRESERVED3 : 1; /* Reserved */\r
- __IO uint32_t bRESERVED4 : 1; /* Reserved */\r
- __IO uint32_t bWAIT : 4; /* Number of wait states for read */\r
- __I uint32_t bRD_MODE_STATUS : 4; /* Read mode */\r
- __I uint32_t bRESERVED5 : 12; /* Reserved */\r
- } b;\r
- } rBANK1_RDCTL;\r
- uint8_t RESERVED1[8];\r
- union { /* FLCTL_RDBRST_CTLSTAT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_RDBRST_CTLSTAT Bits */\r
- __O uint32_t bSTART : 1; /* Start of burst/compare operation */\r
- __IO uint32_t bMEM_TYPE : 2; /* Type of memory that burst is carried out on */\r
- __IO uint32_t bSTOP_FAIL : 1; /* Terminate burst/compare operation */\r
- __IO uint32_t bDATA_CMP : 1; /* Data pattern used for comparison against memory read data */\r
- __IO uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bTEST_EN : 1; /* Enable comparison against test data compare registers */\r
- __I uint32_t bRESERVED1 : 9; /* Reserved */\r
- __I uint32_t bBRST_STAT : 2; /* Status of Burst/Compare operation */\r
- __I uint32_t bCMP_ERR : 1; /* Burst/Compare Operation encountered atleast one data */\r
- __I uint32_t bADDR_ERR : 1; /* Burst/Compare Operation was terminated due to access to */\r
- __I uint32_t bRESERVED2 : 3; /* Reserved */\r
- __O uint32_t bCLR_STAT : 1; /* Clear status bits 19-16 of this register */\r
- __I uint32_t bRESERVED3 : 8; /* Reserved */\r
- } b;\r
- } rRDBRST_CTLSTAT;\r
- union { /* FLCTL_RDBRST_STARTADDR Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_RDBRST_STARTADDR Bits */\r
- __IO uint32_t bSTART_ADDRESS : 21; /* Start Address of Burst Operation */\r
- __I uint32_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rRDBRST_STARTADDR;\r
- union { /* FLCTL_RDBRST_LEN Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_RDBRST_LEN Bits */\r
- __IO uint32_t bBURST_LENGTH : 21; /* Length of Burst Operation */\r
- __I uint32_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rRDBRST_LEN;\r
- uint8_t RESERVED2[16];\r
- union { /* FLCTL_RDBRST_FAILADDR Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_RDBRST_FAILADDR Bits */\r
- __IO uint32_t bFAIL_ADDRESS : 21; /* Reflects address of last failed compare */\r
- __I uint32_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rRDBRST_FAILADDR;\r
- union { /* FLCTL_RDBRST_FAILCNT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_RDBRST_FAILCNT Bits */\r
- __IO uint32_t bFAIL_COUNT : 17; /* Number of failures encountered in burst operation */\r
- __I uint32_t bRESERVED0 : 15; /* Reserved */\r
- } b;\r
- } rRDBRST_FAILCNT;\r
- uint8_t RESERVED3[12];\r
- union { /* FLCTL_PRG_CTLSTAT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_PRG_CTLSTAT Bits */\r
- __IO uint32_t bENABLE : 1; /* Master control for all word program operations */\r
- __IO uint32_t bMODE : 1; /* Write mode */\r
- __IO uint32_t bVER_PRE : 1; /* Controls automatic pre program verify operations */\r
- __IO uint32_t bVER_PST : 1; /* Controls automatic post program verify operations */\r
- __I uint32_t bRESERVED0 : 12; /* Reserved */\r
- __I uint32_t bSTATUS : 2; /* Status of program operations in the Flash memory */\r
- __I uint32_t bBNK_ACT : 1; /* Bank active */\r
- __I uint32_t bRESERVED1 : 13; /* Reserved */\r
- } b;\r
- } rPRG_CTLSTAT;\r
- union { /* FLCTL_PRGBRST_CTLSTAT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_PRGBRST_CTLSTAT Bits */\r
- __O uint32_t bSTART : 1; /* Trigger start of burst program operation */\r
- __IO uint32_t bTYPE : 2; /* Type of memory that burst program is carried out on */\r
- __IO uint32_t bLEN : 3; /* Length of burst */\r
- __IO uint32_t bAUTO_PRE : 1; /* Auto-Verify operation before the Burst Program */\r
- __IO uint32_t bAUTO_PST : 1; /* Auto-Verify operation after the Burst Program */\r
- __I uint32_t bRESERVED0 : 8; /* Reserved */\r
- __I uint32_t bBURST_STATUS : 3; /* Status of a Burst Operation */\r
- __I uint32_t bPRE_ERR : 1; /* Burst Operation encountered preprogram auto-verify errors */\r
- __I uint32_t bPST_ERR : 1; /* Burst Operation encountered postprogram auto-verify errors */\r
- __I uint32_t bADDR_ERR : 1; /* Burst Operation was terminated due to attempted program of reserved memory */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __O uint32_t bCLR_STAT : 1; /* Clear status bits 21-16 of this register */\r
- __I uint32_t bRESERVED2 : 8; /* Reserved */\r
- } b;\r
- } rPRGBRST_CTLSTAT;\r
- union { /* FLCTL_PRGBRST_STARTADDR Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_PRGBRST_STARTADDR Bits */\r
- __IO uint32_t bSTART_ADDRESS : 22; /* Start Address of Program Burst Operation */\r
- __I uint32_t bRESERVED0 : 10; /* Reserved */\r
- } b;\r
- } rPRGBRST_STARTADDR;\r
- uint8_t RESERVED4[4];\r
- __IO uint32_t rPRGBRST_DATA0_0; /* Program Burst Data0 Register0 */\r
- __IO uint32_t rPRGBRST_DATA0_1; /* Program Burst Data0 Register1 */\r
- __IO uint32_t rPRGBRST_DATA0_2; /* Program Burst Data0 Register2 */\r
- __IO uint32_t rPRGBRST_DATA0_3; /* Program Burst Data0 Register3 */\r
- __IO uint32_t rPRGBRST_DATA1_0; /* Program Burst Data1 Register0 */\r
- __IO uint32_t rPRGBRST_DATA1_1; /* Program Burst Data1 Register1 */\r
- __IO uint32_t rPRGBRST_DATA1_2; /* Program Burst Data1 Register2 */\r
- __IO uint32_t rPRGBRST_DATA1_3; /* Program Burst Data1 Register3 */\r
- __IO uint32_t rPRGBRST_DATA2_0; /* Program Burst Data2 Register0 */\r
- __IO uint32_t rPRGBRST_DATA2_1; /* Program Burst Data2 Register1 */\r
- __IO uint32_t rPRGBRST_DATA2_2; /* Program Burst Data2 Register2 */\r
- __IO uint32_t rPRGBRST_DATA2_3; /* Program Burst Data2 Register3 */\r
- __IO uint32_t rPRGBRST_DATA3_0; /* Program Burst Data3 Register0 */\r
- __IO uint32_t rPRGBRST_DATA3_1; /* Program Burst Data3 Register1 */\r
- __IO uint32_t rPRGBRST_DATA3_2; /* Program Burst Data3 Register2 */\r
- __IO uint32_t rPRGBRST_DATA3_3; /* Program Burst Data3 Register3 */\r
- union { /* FLCTL_ERASE_CTLSTAT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_ERASE_CTLSTAT Bits */\r
- __O uint32_t bSTART : 1; /* Start of Erase operation */\r
- __IO uint32_t bMODE : 1; /* Erase mode selected by application */\r
- __IO uint32_t bTYPE : 2; /* Type of memory that erase operation is carried out on */\r
- __I uint32_t bRESERVED0 : 12; /* Reserved */\r
- __I uint32_t bSTATUS : 2; /* Status of erase operations in the Flash memory */\r
- __I uint32_t bADDR_ERR : 1; /* Erase Operation was terminated due to attempted erase of reserved memory address */\r
- __O uint32_t bCLR_STAT : 1; /* Clear status bits 18-16 of this register */\r
- __I uint32_t bRESERVED1 : 12; /* Reserved */\r
- } b;\r
- } rERASE_CTLSTAT;\r
- union { /* FLCTL_ERASE_SECTADDR Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_ERASE_SECTADDR Bits */\r
- __IO uint32_t bSECT_ADDRESS : 22; /* Address of Sector being Erased */\r
- __I uint32_t bRESERVED0 : 10; /* Reserved */\r
- } b;\r
- } rERASE_SECTADDR;\r
- uint8_t RESERVED5[8];\r
- union { /* FLCTL_BANK0_INFO_WEPROT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_BANK0_INFO_WEPROT Bits */\r
- __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase */\r
- __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase */\r
- __I uint32_t bRESERVED0 : 30; /* Reserved */\r
- } b;\r
- } rBANK0_INFO_WEPROT;\r
- union { /* FLCTL_BANK0_MAIN_WEPROT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_BANK0_MAIN_WEPROT Bits */\r
- __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase */\r
- __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase */\r
- __IO uint32_t bPROT2 : 1; /* Protects Sector 2 from program or erase */\r
- __IO uint32_t bPROT3 : 1; /* Protects Sector 3 from program or erase */\r
- __IO uint32_t bPROT4 : 1; /* Protects Sector 4 from program or erase */\r
- __IO uint32_t bPROT5 : 1; /* Protects Sector 5 from program or erase */\r
- __IO uint32_t bPROT6 : 1; /* Protects Sector 6 from program or erase */\r
- __IO uint32_t bPROT7 : 1; /* Protects Sector 7 from program or erase */\r
- __IO uint32_t bPROT8 : 1; /* Protects Sector 8 from program or erase */\r
- __IO uint32_t bPROT9 : 1; /* Protects Sector 9 from program or erase */\r
- __IO uint32_t bPROT10 : 1; /* Protects Sector 10 from program or erase */\r
- __IO uint32_t bPROT11 : 1; /* Protects Sector 11 from program or erase */\r
- __IO uint32_t bPROT12 : 1; /* Protects Sector 12 from program or erase */\r
- __IO uint32_t bPROT13 : 1; /* Protects Sector 13 from program or erase */\r
- __IO uint32_t bPROT14 : 1; /* Protects Sector 14 from program or erase */\r
- __IO uint32_t bPROT15 : 1; /* Protects Sector 15 from program or erase */\r
- __IO uint32_t bPROT16 : 1; /* Protects Sector 16 from program or erase */\r
- __IO uint32_t bPROT17 : 1; /* Protects Sector 17 from program or erase */\r
- __IO uint32_t bPROT18 : 1; /* Protects Sector 18 from program or erase */\r
- __IO uint32_t bPROT19 : 1; /* Protects Sector 19 from program or erase */\r
- __IO uint32_t bPROT20 : 1; /* Protects Sector 20 from program or erase */\r
- __IO uint32_t bPROT21 : 1; /* Protects Sector 21 from program or erase */\r
- __IO uint32_t bPROT22 : 1; /* Protects Sector 22 from program or erase */\r
- __IO uint32_t bPROT23 : 1; /* Protects Sector 23 from program or erase */\r
- __IO uint32_t bPROT24 : 1; /* Protects Sector 24 from program or erase */\r
- __IO uint32_t bPROT25 : 1; /* Protects Sector 25 from program or erase */\r
- __IO uint32_t bPROT26 : 1; /* Protects Sector 26 from program or erase */\r
- __IO uint32_t bPROT27 : 1; /* Protects Sector 27 from program or erase */\r
- __IO uint32_t bPROT28 : 1; /* Protects Sector 28 from program or erase */\r
- __IO uint32_t bPROT29 : 1; /* Protects Sector 29 from program or erase */\r
- __IO uint32_t bPROT30 : 1; /* Protects Sector 30 from program or erase */\r
- __IO uint32_t bPROT31 : 1; /* Protects Sector 31 from program or erase */\r
- } b;\r
- } rBANK0_MAIN_WEPROT;\r
- uint8_t RESERVED6[8];\r
- union { /* FLCTL_BANK1_INFO_WEPROT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_BANK1_INFO_WEPROT Bits */\r
- __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase operations */\r
- __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase operations */\r
- __I uint32_t bRESERVED0 : 30; /* Reserved */\r
- } b;\r
- } rBANK1_INFO_WEPROT;\r
- union { /* FLCTL_BANK1_MAIN_WEPROT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_BANK1_MAIN_WEPROT Bits */\r
- __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase operations */\r
- __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase operations */\r
- __IO uint32_t bPROT2 : 1; /* Protects Sector 2 from program or erase operations */\r
- __IO uint32_t bPROT3 : 1; /* Protects Sector 3 from program or erase operations */\r
- __IO uint32_t bPROT4 : 1; /* Protects Sector 4 from program or erase operations */\r
- __IO uint32_t bPROT5 : 1; /* Protects Sector 5 from program or erase operations */\r
- __IO uint32_t bPROT6 : 1; /* Protects Sector 6 from program or erase operations */\r
- __IO uint32_t bPROT7 : 1; /* Protects Sector 7 from program or erase operations */\r
- __IO uint32_t bPROT8 : 1; /* Protects Sector 8 from program or erase operations */\r
- __IO uint32_t bPROT9 : 1; /* Protects Sector 9 from program or erase operations */\r
- __IO uint32_t bPROT10 : 1; /* Protects Sector 10 from program or erase operations */\r
- __IO uint32_t bPROT11 : 1; /* Protects Sector 11 from program or erase operations */\r
- __IO uint32_t bPROT12 : 1; /* Protects Sector 12 from program or erase operations */\r
- __IO uint32_t bPROT13 : 1; /* Protects Sector 13 from program or erase operations */\r
- __IO uint32_t bPROT14 : 1; /* Protects Sector 14 from program or erase operations */\r
- __IO uint32_t bPROT15 : 1; /* Protects Sector 15 from program or erase operations */\r
- __IO uint32_t bPROT16 : 1; /* Protects Sector 16 from program or erase operations */\r
- __IO uint32_t bPROT17 : 1; /* Protects Sector 17 from program or erase operations */\r
- __IO uint32_t bPROT18 : 1; /* Protects Sector 18 from program or erase operations */\r
- __IO uint32_t bPROT19 : 1; /* Protects Sector 19 from program or erase operations */\r
- __IO uint32_t bPROT20 : 1; /* Protects Sector 20 from program or erase operations */\r
- __IO uint32_t bPROT21 : 1; /* Protects Sector 21 from program or erase operations */\r
- __IO uint32_t bPROT22 : 1; /* Protects Sector 22 from program or erase operations */\r
- __IO uint32_t bPROT23 : 1; /* Protects Sector 23 from program or erase operations */\r
- __IO uint32_t bPROT24 : 1; /* Protects Sector 24 from program or erase operations */\r
- __IO uint32_t bPROT25 : 1; /* Protects Sector 25 from program or erase operations */\r
- __IO uint32_t bPROT26 : 1; /* Protects Sector 26 from program or erase operations */\r
- __IO uint32_t bPROT27 : 1; /* Protects Sector 27 from program or erase operations */\r
- __IO uint32_t bPROT28 : 1; /* Protects Sector 28 from program or erase operations */\r
- __IO uint32_t bPROT29 : 1; /* Protects Sector 29 from program or erase operations */\r
- __IO uint32_t bPROT30 : 1; /* Protects Sector 30 from program or erase operations */\r
- __IO uint32_t bPROT31 : 1; /* Protects Sector 31 from program or erase operations */\r
- } b;\r
- } rBANK1_MAIN_WEPROT;\r
- uint8_t RESERVED7[8];\r
- union { /* FLCTL_BMRK_CTLSTAT Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_BMRK_CTLSTAT Bits */\r
- __IO uint32_t bI_BMRK : 1; /* */\r
- __IO uint32_t bD_BMRK : 1; /* */\r
- __IO uint32_t bCMP_EN : 1; /* */\r
- __IO uint32_t bCMP_SEL : 1; /* */\r
- __I uint32_t bRESERVED0 : 28; /* Reserved */\r
- } b;\r
- } rBMRK_CTLSTAT;\r
- __IO uint32_t rBMRK_IFETCH; /* Benchmark Instruction Fetch Count Register */\r
- __IO uint32_t rBMRK_DREAD; /* Benchmark Data Read Count Register */\r
- __IO uint32_t rBMRK_CMP; /* Benchmark Count Compare Register */\r
- uint8_t RESERVED8[16];\r
- union { /* FLCTL_IFG Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_IFG Bits */\r
- __I uint32_t bRDBRST : 1; /* */\r
- __I uint32_t bAVPRE : 1; /* */\r
- __I uint32_t bAVPST : 1; /* */\r
- __I uint32_t bPRG : 1; /* */\r
- __I uint32_t bPRGB : 1; /* */\r
- __I uint32_t bERASE : 1; /* */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __I uint32_t bRESERVED1 : 1; /* Reserved */\r
- __I uint32_t bBMRK : 1; /* */\r
- __I uint32_t bPRG_ERR : 1; /* */\r
- __I uint32_t bRESERVED2 : 22; /* Reserved */\r
- } b;\r
- } rIFG;\r
- union { /* FLCTL_IE Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_IE Bits */\r
- __IO uint32_t bRDBRST : 1; /* */\r
- __IO uint32_t bAVPRE : 1; /* */\r
- __IO uint32_t bAVPST : 1; /* */\r
- __IO uint32_t bPRG : 1; /* */\r
- __IO uint32_t bPRGB : 1; /* */\r
- __IO uint32_t bERASE : 1; /* */\r
- __IO uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bRESERVED1 : 1; /* Reserved */\r
- __IO uint32_t bBMRK : 1; /* */\r
- __IO uint32_t bPRG_ERR : 1; /* */\r
- __I uint32_t bRESERVED2 : 22; /* Reserved */\r
- } b;\r
- } rIE;\r
- union { /* FLCTL_CLRIFG Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_CLRIFG Bits */\r
- __O uint32_t bRDBRST : 1; /* */\r
- __O uint32_t bAVPRE : 1; /* */\r
- __O uint32_t bAVPST : 1; /* */\r
- __O uint32_t bPRG : 1; /* */\r
- __O uint32_t bPRGB : 1; /* */\r
- __O uint32_t bERASE : 1; /* */\r
- __O uint32_t bRESERVED0 : 1; /* Reserved */\r
- __O uint32_t bRESERVED1 : 1; /* Reserved */\r
- __O uint32_t bBMRK : 1; /* */\r
- __O uint32_t bPRG_ERR : 1; /* */\r
- __I uint32_t bRESERVED2 : 22; /* Reserved */\r
- } b;\r
- } rCLRIFG;\r
- union { /* FLCTL_SETIFG Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_SETIFG Bits */\r
- __O uint32_t bRDBRST : 1; /* */\r
- __O uint32_t bAVPRE : 1; /* */\r
- __O uint32_t bAVPST : 1; /* */\r
- __O uint32_t bPRG : 1; /* */\r
- __O uint32_t bPRGB : 1; /* */\r
- __O uint32_t bERASE : 1; /* */\r
- __O uint32_t bRESERVED0 : 1; /* Reserved */\r
- __O uint32_t bRESERVED1 : 1; /* Reserved */\r
- __O uint32_t bBMRK : 1; /* */\r
- __O uint32_t bPRG_ERR : 1; /* */\r
- __I uint32_t bRESERVED2 : 22; /* Reserved */\r
- } b;\r
- } rSETIFG;\r
- union { /* FLCTL_READ_TIMCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_READ_TIMCTL Bits */\r
- __IO uint32_t bSETUP : 8; /* */\r
- __IO uint32_t bHOLD : 4; /* */\r
- __IO uint32_t bIREF_BOOST1 : 4; /* */\r
- __IO uint32_t bSETUP_LONG : 8; /* */\r
- __I uint32_t bRESERVED0 : 8; /* Reserved */\r
- } b;\r
- } rREAD_TIMCTL;\r
- union { /* FLCTL_READMARGIN_TIMCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_READMARGIN_TIMCTL Bits */\r
- __IO uint32_t bSETUP : 8; /* */\r
- __IO uint32_t bHOLD : 4; /* */\r
- __I uint32_t bRESERVED0 : 4; /* Reserved */\r
- __I uint32_t bRESERVED1 : 16; /* Reserved */\r
- } b;\r
- } rREADMARGIN_TIMCTL;\r
- union { /* FLCTL_PRGVER_TIMCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_PRGVER_TIMCTL Bits */\r
- __IO uint32_t bSETUP : 8; /* */\r
- __IO uint32_t bACTIVE : 4; /* */\r
- __IO uint32_t bHOLD : 4; /* */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rPRGVER_TIMCTL;\r
- union { /* FLCTL_ERSVER_TIMCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_ERSVER_TIMCTL Bits */\r
- __IO uint32_t bSETUP : 8; /* */\r
- __IO uint32_t bHOLD : 4; /* */\r
- __I uint32_t bRESERVED0 : 4; /* Reserved */\r
- __I uint32_t bRESERVED1 : 16; /* Reserved */\r
- } b;\r
- } rERSVER_TIMCTL;\r
- union { /* FLCTL_LKGVER_TIMCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_LKGVER_TIMCTL Bits */\r
- __IO uint32_t bSETUP : 8; /* */\r
- __IO uint32_t bHOLD : 4; /* */\r
- __I uint32_t bRESERVED0 : 4; /* Reserved */\r
- __I uint32_t bRESERVED1 : 16; /* Reserved */\r
- } b;\r
- } rLKGVER_TIMCTL;\r
- union { /* FLCTL_PROGRAM_TIMCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_PROGRAM_TIMCTL Bits */\r
- __IO uint32_t bSETUP : 8; /* */\r
- __IO uint32_t bACTIVE : 20; /* */\r
- __IO uint32_t bHOLD : 4; /* */\r
- } b;\r
- } rPROGRAM_TIMCTL;\r
- union { /* FLCTL_ERASE_TIMCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_ERASE_TIMCTL Bits */\r
- __IO uint32_t bSETUP : 8; /* */\r
- __IO uint32_t bACTIVE : 20; /* */\r
- __IO uint32_t bHOLD : 4; /* */\r
- } b;\r
- } rERASE_TIMCTL;\r
- union { /* FLCTL_MASSERASE_TIMCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_MASSERASE_TIMCTL Bits */\r
- __IO uint32_t bBOOST_ACTIVE : 8; /* */\r
- __IO uint32_t bBOOST_HOLD : 8; /* */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMASSERASE_TIMCTL;\r
- union { /* FLCTL_BURSTPRG_TIMCTL Register */\r
- __IO uint32_t r;\r
- struct { /* FLCTL_BURSTPRG_TIMCTL Bits */\r
- __I uint32_t bRESERVED0 : 8; /* Reserved */\r
- __IO uint32_t bACTIVE : 20; /* */\r
- __I uint32_t bRESERVED1 : 4; /* Reserved */\r
- } b;\r
- } rBURSTPRG_TIMCTL;\r
+ __I uint32_t POWER_STAT; /**< Power Status Register */\r
+ uint32_t RESERVED0[3];\r
+ __IO uint32_t BANK0_RDCTL; /**< Bank0 Read Control Register */\r
+ __IO uint32_t BANK1_RDCTL; /**< Bank1 Read Control Register */\r
+ uint32_t RESERVED1[2];\r
+ __IO uint32_t RDBRST_CTLSTAT; /**< Read Burst/Compare Control and Status Register */\r
+ __IO uint32_t RDBRST_STARTADDR; /**< Read Burst/Compare Start Address Register */\r
+ __IO uint32_t RDBRST_LEN; /**< Read Burst/Compare Length Register */\r
+ uint32_t RESERVED2[4];\r
+ __IO uint32_t RDBRST_FAILADDR; /**< Read Burst/Compare Fail Address Register */\r
+ __IO uint32_t RDBRST_FAILCNT; /**< Read Burst/Compare Fail Count Register */\r
+ uint32_t RESERVED3[3];\r
+ __IO uint32_t PRG_CTLSTAT; /**< Program Control and Status Register */\r
+ __IO uint32_t PRGBRST_CTLSTAT; /**< Program Burst Control and Status Register */\r
+ __IO uint32_t PRGBRST_STARTADDR; /**< Program Burst Start Address Register */\r
+ uint32_t RESERVED4;\r
+ __IO uint32_t PRGBRST_DATA0_0; /**< Program Burst Data0 Register0 */\r
+ __IO uint32_t PRGBRST_DATA0_1; /**< Program Burst Data0 Register1 */\r
+ __IO uint32_t PRGBRST_DATA0_2; /**< Program Burst Data0 Register2 */\r
+ __IO uint32_t PRGBRST_DATA0_3; /**< Program Burst Data0 Register3 */\r
+ __IO uint32_t PRGBRST_DATA1_0; /**< Program Burst Data1 Register0 */\r
+ __IO uint32_t PRGBRST_DATA1_1; /**< Program Burst Data1 Register1 */\r
+ __IO uint32_t PRGBRST_DATA1_2; /**< Program Burst Data1 Register2 */\r
+ __IO uint32_t PRGBRST_DATA1_3; /**< Program Burst Data1 Register3 */\r
+ __IO uint32_t PRGBRST_DATA2_0; /**< Program Burst Data2 Register0 */\r
+ __IO uint32_t PRGBRST_DATA2_1; /**< Program Burst Data2 Register1 */\r
+ __IO uint32_t PRGBRST_DATA2_2; /**< Program Burst Data2 Register2 */\r
+ __IO uint32_t PRGBRST_DATA2_3; /**< Program Burst Data2 Register3 */\r
+ __IO uint32_t PRGBRST_DATA3_0; /**< Program Burst Data3 Register0 */\r
+ __IO uint32_t PRGBRST_DATA3_1; /**< Program Burst Data3 Register1 */\r
+ __IO uint32_t PRGBRST_DATA3_2; /**< Program Burst Data3 Register2 */\r
+ __IO uint32_t PRGBRST_DATA3_3; /**< Program Burst Data3 Register3 */\r
+ __IO uint32_t ERASE_CTLSTAT; /**< Erase Control and Status Register */\r
+ __IO uint32_t ERASE_SECTADDR; /**< Erase Sector Address Register */\r
+ uint32_t RESERVED5[2];\r
+ __IO uint32_t BANK0_INFO_WEPROT; /**< Information Memory Bank0 Write/Erase Protection Register */\r
+ __IO uint32_t BANK0_MAIN_WEPROT; /**< Main Memory Bank0 Write/Erase Protection Register */\r
+ uint32_t RESERVED6[2];\r
+ __IO uint32_t BANK1_INFO_WEPROT; /**< Information Memory Bank1 Write/Erase Protection Register */\r
+ __IO uint32_t BANK1_MAIN_WEPROT; /**< Main Memory Bank1 Write/Erase Protection Register */\r
+ uint32_t RESERVED7[2];\r
+ __IO uint32_t BMRK_CTLSTAT; /**< Benchmark Control and Status Register */\r
+ __IO uint32_t BMRK_IFETCH; /**< Benchmark Instruction Fetch Count Register */\r
+ __IO uint32_t BMRK_DREAD; /**< Benchmark Data Read Count Register */\r
+ __IO uint32_t BMRK_CMP; /**< Benchmark Count Compare Register */\r
+ uint32_t RESERVED8[4];\r
+ __IO uint32_t IFG; /**< Interrupt Flag Register */\r
+ __IO uint32_t IE; /**< Interrupt Enable Register */\r
+ __IO uint32_t CLRIFG; /**< Clear Interrupt Flag Register */\r
+ __IO uint32_t SETIFG; /**< Set Interrupt Flag Register */\r
+ __I uint32_t READ_TIMCTL; /**< Read Timing Control Register */\r
+ __I uint32_t READMARGIN_TIMCTL; /**< Read Margin Timing Control Register */\r
+ __I uint32_t PRGVER_TIMCTL; /**< Program Verify Timing Control Register */\r
+ __I uint32_t ERSVER_TIMCTL; /**< Erase Verify Timing Control Register */\r
+ __I uint32_t LKGVER_TIMCTL; /**< Leakage Verify Timing Control Register */\r
+ __I uint32_t PROGRAM_TIMCTL; /**< Program Timing Control Register */\r
+ __I uint32_t ERASE_TIMCTL; /**< Erase Timing Control Register */\r
+ __I uint32_t MASSERASE_TIMCTL; /**< Mass Erase Timing Control Register */\r
+ __I uint32_t BURSTPRG_TIMCTL; /**< Burst Program Timing Control Register */\r
} FLCTL_Type;\r
\r
+/*@}*/ /* end of group FLCTL */\r
+\r
\r
-//*****************************************************************************\r
-// PCM Registers\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* PCM Registers\r
+******************************************************************************/\r
+/** @addtogroup PCM MSP432P401R (PCM)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* PCMCTL0 Register */\r
- __IO uint32_t r;\r
- struct { /* PCMCTL0 Bits */\r
- __IO uint32_t bAMR : 4; /* Active Mode Request */\r
- __IO uint32_t bLPMR : 4; /* Low Power Mode Request */\r
- __I uint32_t bCPM : 6; /* Current Power Mode */\r
- __I uint32_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint32_t bKEY : 16; /* PCM key */\r
- } b;\r
- } rCTL0;\r
- union { /* PCMCTL1 Register */\r
- __IO uint32_t r;\r
- struct { /* PCMCTL1 Bits */\r
- __IO uint32_t bLOCKLPM5 : 1; /* Lock LPM5 */\r
- __IO uint32_t bLOCKBKUP : 1; /* Lock Backup */\r
- __IO uint32_t bFORCE_LPM_ENTRY : 1; /* Force LPM entry */\r
- __I uint32_t bRESERVED0 : 5; /* Reserved */\r
- __IO uint32_t bPMR_BUSY : 1; /* Power mode request busy flag */\r
- __I uint32_t bRESERVED1 : 7; /* Reserved */\r
- __IO uint32_t bKEY : 16; /* PCM key */\r
- } b;\r
- } rCTL1;\r
- union { /* PCMIE Register */\r
- __IO uint32_t r;\r
- struct { /* PCMIE Bits */\r
- __IO uint32_t bLPM_INVALID_TR_IE : 1; /* LPM invalid transition interrupt enable */\r
- __IO uint32_t bLPM_INVALID_CLK_IE : 1; /* LPM invalid clock interrupt enable */\r
- __IO uint32_t bAM_INVALID_TR_IE : 1; /* Active mode invalid transition interrupt enable */\r
- __I uint32_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint32_t bDCDC_ERROR_IE : 1; /* DC-DC error interrupt enable */\r
- __I uint32_t bRESERVED1 : 25; /* Reserved */\r
- } b;\r
- } rIE;\r
- union { /* PCMIFG Register */\r
- __I uint32_t r;\r
- struct { /* PCMIFG Bits */\r
- __I uint32_t bLPM_INVALID_TR_IFG : 1; /* LPM invalid transition flag */\r
- __I uint32_t bLPM_INVALID_CLK_IFG : 1; /* LPM invalid clock flag */\r
- __I uint32_t bAM_INVALID_TR_IFG : 1; /* Active mode invalid transition flag */\r
- __I uint32_t bRESERVED0 : 3; /* Reserved */\r
- __I uint32_t bDCDC_ERROR_IFG : 1; /* DC-DC error flag */\r
- __I uint32_t bRESERVED1 : 25; /* Reserved */\r
- } b;\r
- } rIFG;\r
- union { /* PCMCLRIFG Register */\r
- __O uint32_t r;\r
- struct { /* PCMCLRIFG Bits */\r
- __O uint32_t bCLR_LPM_INVALID_TR_IFG : 1; /* Clear LPM invalid transition flag */\r
- __O uint32_t bCLR_LPM_INVALID_CLK_IFG : 1; /* Clear LPM invalid clock flag */\r
- __O uint32_t bCLR_AM_INVALID_TR_IFG : 1; /* Clear active mode invalid transition flag */\r
- __O uint32_t bRESERVED0 : 3; /* Reserved */\r
- __O uint32_t bCLR_DCDC_ERROR_IFG : 1; /* Clear DC-DC error flag */\r
- __O uint32_t bRESERVED1 : 25; /* Reserved */\r
- } b;\r
- } rCLRIFG;\r
+ __IO uint32_t CTL0; /**< Control 0 Register */\r
+ __IO uint32_t CTL1; /**< Control 1 Register */\r
+ __IO uint32_t IE; /**< Interrupt Enable Register */\r
+ __I uint32_t IFG; /**< Interrupt Flag Register */\r
+ __O uint32_t CLRIFG; /**< Clear Interrupt Flag Register */\r
} PCM_Type;\r
\r
+/*@}*/ /* end of group PCM */\r
\r
-//*****************************************************************************\r
-// PMAP Registers\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* PMAP Registers\r
+******************************************************************************/\r
+/** @addtogroup PMAP MSP432P401R (PMAP)\r
+ @{\r
+*/\r
typedef struct {\r
- __IO uint16_t rKEYID; /* Port Mapping Key Register */\r
- union { /* PMAPCTL Register */\r
- __IO uint16_t r;\r
- struct { /* PMAPCTL Bits */\r
- __I uint16_t bLOCKED : 1; /* Port mapping lock bit */\r
- __IO uint16_t bPRECFG : 1; /* Port mapping reconfiguration control bit */\r
- __I uint16_t bRESERVED0 : 14; /* Reserved */\r
- } b;\r
- } rCTL;\r
- uint8_t RESERVED0[4];\r
- __IO uint16_t rP1MAP01; /* Port mapping register, P1.0 and P1.1 */\r
- __IO uint16_t rP1MAP23; /* Port mapping register, P1.2 and P1.3 */\r
- __IO uint16_t rP1MAP45; /* Port mapping register, P1.4 and P1.5 */\r
- __IO uint16_t rP1MAP67; /* Port mapping register, P1.6 and P1.7 */\r
- __IO uint16_t rP2MAP01; /* Port mapping register, P2.0 and P2.1 */\r
- __IO uint16_t rP2MAP23; /* Port mapping register, P2.2 and P2.3 */\r
- __IO uint16_t rP2MAP45; /* Port mapping register, P2.4 and P2.5 */\r
- __IO uint16_t rP2MAP67; /* Port mapping register, P2.6 and P2.7 */\r
- __IO uint16_t rP3MAP01; /* Port mapping register, P3.0 and P3.1 */\r
- __IO uint16_t rP3MAP23; /* Port mapping register, P3.2 and P3.3 */\r
- __IO uint16_t rP3MAP45; /* Port mapping register, P3.4 and P3.5 */\r
- __IO uint16_t rP3MAP67; /* Port mapping register, P3.6 and P3.7 */\r
- __IO uint16_t rP4MAP01; /* Port mapping register, P4.0 and P4.1 */\r
- __IO uint16_t rP4MAP23; /* Port mapping register, P4.2 and P4.3 */\r
- __IO uint16_t rP4MAP45; /* Port mapping register, P4.4 and P4.5 */\r
- __IO uint16_t rP4MAP67; /* Port mapping register, P4.6 and P4.7 */\r
- __IO uint16_t rP5MAP01; /* Port mapping register, P5.0 and P5.1 */\r
- __IO uint16_t rP5MAP23; /* Port mapping register, P5.2 and P5.3 */\r
- __IO uint16_t rP5MAP45; /* Port mapping register, P5.4 and P5.5 */\r
- __IO uint16_t rP5MAP67; /* Port mapping register, P5.6 and P5.7 */\r
- __IO uint16_t rP6MAP01; /* Port mapping register, P6.0 and P6.1 */\r
- __IO uint16_t rP6MAP23; /* Port mapping register, P6.2 and P6.3 */\r
- __IO uint16_t rP6MAP45; /* Port mapping register, P6.4 and P6.5 */\r
- __IO uint16_t rP6MAP67; /* Port mapping register, P6.6 and P6.7 */\r
- __IO uint16_t rP7MAP01; /* Port mapping register, P7.0 and P7.1 */\r
- __IO uint16_t rP7MAP23; /* Port mapping register, P7.2 and P7.3 */\r
- __IO uint16_t rP7MAP45; /* Port mapping register, P7.4 and P7.5 */\r
- __IO uint16_t rP7MAP67; /* Port mapping register, P7.6 and P7.7 */\r
-} PMAP_Type;\r
+ __IO uint16_t KEYID;\r
+ __IO uint16_t CTL;\r
+} PMAP_COMMON_Type;\r
\r
-\r
-//*****************************************************************************\r
-// PSS Registers\r
-//*****************************************************************************\r
typedef struct {\r
- union { /* PSSKEY Register */\r
- __IO uint32_t r;\r
- struct { /* PSSKEY Bits */\r
- __IO uint32_t bKEY : 16; /* PSS control key */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rKEY;\r
- union { /* PSSCTL0 Register */\r
- __IO uint32_t r;\r
- struct { /* PSSCTL0 Bits */\r
- __IO uint32_t bSVSMHOFF : 1; /* SVSM high-side off */\r
- __IO uint32_t bSVSMHLP : 1; /* SVSM high-side low power normal performance mode */\r
- __IO uint32_t bSVSMHS : 1; /* Supply supervisor or monitor selection for the high-side */\r
- __IO uint32_t bSVSMHTH : 3; /* SVSM high-side reset voltage level */\r
- __IO uint32_t bSVMHOE : 1; /* SVSM high-side output enable */\r
- __IO uint32_t bSVMHOUTPOLAL : 1; /* SVMHOUT pin polarity active low */\r
- __IO uint32_t bSVSLOFF : 1; /* SVS low-side off */\r
- __IO uint32_t bSVSLLP : 1; /* SVS low-side low power normal performance mode */\r
- __IO uint32_t bDCDC_FORCE : 1; /* Disables automatic supply voltage detection */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bVCORETRAN : 2; /* Controls VCORE Level Transition time */\r
- __I uint32_t bRESERVED1 : 18; /* Reserved */\r
- } b;\r
- } rCTL0;\r
- union { /* PSSCTL1 Register */\r
- __IO uint32_t r;\r
- struct { /* PSSCTL1 Bits */\r
- __IO uint32_t bDOCMON : 1; /* Turns the DOCM module on or off */\r
- __IO uint32_t bDOCMSAMP : 1; /* DOCM sample current */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bDOCMCM : 6; /* Controls current mirrors in DOCM for conversion */\r
- __I uint32_t bRESERVED1 : 23; /* Reserved */\r
- } b;\r
- } rCTL1;\r
- union { /* PSSCTL2 Register */\r
- __I uint32_t r;\r
- struct { /* PSSCTL2 Bits */\r
- __I uint32_t bDOCMOUT : 6; /* DOCM comparator output */\r
- __I uint32_t bRESERVED0 : 26; /* Reserved */\r
- } b;\r
- } rCTL2;\r
- uint8_t RESERVED0[36];\r
- union { /* PSSIE Register */\r
- __IO uint32_t r;\r
- struct { /* PSSIE Bits */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bSVSMHIE : 1; /* High-side SVSM interrupt enable */\r
- __I uint32_t bRESERVED1 : 30; /* Reserved */\r
- } b;\r
- } rIE;\r
- union { /* PSSIFG Register */\r
- __I uint32_t r;\r
- struct { /* PSSIFG Bits */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __I uint32_t bSVSMHIFG : 1; /* High-side SVSM interrupt flag */\r
- __I uint32_t bRESERVED1 : 30; /* Reserved */\r
- } b;\r
- } rIFG;\r
- union { /* PSSCLRIFG Register */\r
- __IO uint32_t r;\r
- struct { /* PSSCLRIFG Bits */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __O uint32_t bCLRSVSMHIFG : 1; /* SVSMH clear interrupt flag */\r
- __I uint32_t bRESERVED1 : 30; /* Reserved */\r
- } b;\r
- } rCLRIFG;\r
+ union {\r
+ __IO uint16_t PMAP_REGISTER[4];\r
+ struct {\r
+ __IO uint8_t PMAP_REGISTER0;\r
+ __IO uint8_t PMAP_REGISTER1;\r
+ __IO uint8_t PMAP_REGISTER2;\r
+ __IO uint8_t PMAP_REGISTER3;\r
+ __IO uint8_t PMAP_REGISTER4;\r
+ __IO uint8_t PMAP_REGISTER5;\r
+ __IO uint8_t PMAP_REGISTER6;\r
+ __IO uint8_t PMAP_REGISTER7;\r
+ };\r
+ };\r
+} PMAP_REGISTER_Type;\r
+\r
+/*@}*/ /* end of group PMAP */\r
+\r
+\r
+/******************************************************************************\r
+* PSS Registers\r
+******************************************************************************/\r
+/** @addtogroup PSS MSP432P401R (PSS)\r
+ @{\r
+*/\r
+typedef struct {\r
+ __IO uint32_t KEY; /**< Key Register */\r
+ __IO uint32_t CTL0; /**< Control 0 Register */\r
+ uint32_t RESERVED0[11];\r
+ __IO uint32_t IE; /**< Interrupt Enable Register */\r
+ __I uint32_t IFG; /**< Interrupt Flag Register */\r
+ __IO uint32_t CLRIFG; /**< Clear Interrupt Flag Register */\r
} PSS_Type;\r
\r
+/*@}*/ /* end of group PSS */\r
\r
-//*****************************************************************************\r
-// REF_A Registers\r
-//*****************************************************************************\r
+\r
+/******************************************************************************\r
+* REF_A Registers\r
+******************************************************************************/\r
+/** @addtogroup REF_A MSP432P401R (REF_A)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* REFCTL0 Register */\r
- __IO uint16_t r;\r
- struct { /* REFCTL0 Bits */\r
- __IO uint16_t bON : 1; /* Reference enable */\r
- __IO uint16_t bOUT : 1; /* Reference output buffer */\r
- __IO uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bTCOFF : 1; /* Temperature sensor disabled */\r
- __IO uint16_t bVSEL : 2; /* Reference voltage level select */\r
- __IO uint16_t bGENOT : 1; /* Reference generator one-time trigger */\r
- __IO uint16_t bBGOT : 1; /* Bandgap and bandgap buffer one-time trigger */\r
- __I uint16_t bGENACT : 1; /* Reference generator active */\r
- __I uint16_t bBGACT : 1; /* Reference bandgap active */\r
- __I uint16_t bGENBUSY : 1; /* Reference generator busy */\r
- __I uint16_t bBGMODE : 1; /* Bandgap mode */\r
- __I uint16_t bGENRDY : 1; /* Variable reference voltage ready status */\r
- __I uint16_t bBGRDY : 1; /* Buffered bandgap voltage ready status */\r
- __I uint16_t bRESERVED1 : 2; /* Reserved */\r
- } b;\r
- } rCTL0;\r
+ __IO uint16_t CTL0; /**< REF Control Register 0 */\r
} REF_A_Type;\r
\r
+/*@}*/ /* end of group REF_A */\r
+\r
\r
-//*****************************************************************************\r
-// RSTCTL Registers\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* RSTCTL Registers\r
+******************************************************************************/\r
+/** @addtogroup RSTCTL MSP432P401R (RSTCTL)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* RSTCTL_RESET_REQ Register */\r
- __IO uint32_t r;\r
- struct { /* RSTCTL_RESET_REQ Bits */\r
- __O uint32_t bSOFT_REQ : 1; /* Soft Reset request */\r
- __O uint32_t bHARD_REQ : 1; /* Hard Reset request */\r
- __I uint32_t bRESERVED0 : 6; /* Reserved */\r
- __O uint32_t bRSTKEY : 8; /* Write key to unlock reset request bits */\r
- __I uint32_t bRESERVED1 : 16; /* Reserved */\r
- } b;\r
- } rRESET_REQ;\r
- union { /* RSTCTL_HARDRESET_STAT Register */\r
- __I uint32_t r;\r
- struct { /* RSTCTL_HARDRESET_STAT Bits */\r
- __I uint32_t bSRC0 : 1; /* Indicates that SRC0 was the source of the Hard Reset */\r
- __I uint32_t bSRC1 : 1; /* Indicates that SRC1 was the source of the Hard Reset */\r
- __I uint32_t bSRC2 : 1; /* Indicates that SRC2 was the source of the Hard Reset */\r
- __I uint32_t bSRC3 : 1; /* Indicates that SRC3 was the source of the Hard Reset */\r
- __I uint32_t bSRC4 : 1; /* Indicates that SRC4 was the source of the Hard Reset */\r
- __I uint32_t bSRC5 : 1; /* Indicates that SRC5 was the source of the Hard Reset */\r
- __I uint32_t bSRC6 : 1; /* Indicates that SRC6 was the source of the Hard Reset */\r
- __I uint32_t bSRC7 : 1; /* Indicates that SRC7 was the source of the Hard Reset */\r
- __I uint32_t bSRC8 : 1; /* Indicates that SRC8 was the source of the Hard Reset */\r
- __I uint32_t bSRC9 : 1; /* Indicates that SRC9 was the source of the Hard Reset */\r
- __I uint32_t bSRC10 : 1; /* Indicates that SRC10 was the source of the Hard Reset */\r
- __I uint32_t bSRC11 : 1; /* Indicates that SRC11 was the source of the Hard Reset */\r
- __I uint32_t bSRC12 : 1; /* Indicates that SRC12 was the source of the Hard Reset */\r
- __I uint32_t bSRC13 : 1; /* Indicates that SRC13 was the source of the Hard Reset */\r
- __I uint32_t bSRC14 : 1; /* Indicates that SRC14 was the source of the Hard Reset */\r
- __I uint32_t bSRC15 : 1; /* Indicates that SRC15 was the source of the Hard Reset */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rHARDRESET_STAT;\r
- union { /* RSTCTL_HARDRESET_CLR Register */\r
- __IO uint32_t r;\r
- struct { /* RSTCTL_HARDRESET_CLR Bits */\r
- __O uint32_t bSRC0 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC1 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC2 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC3 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC4 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC5 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC6 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC7 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC8 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC9 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC10 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC11 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC12 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC13 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC14 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
- __O uint32_t bSRC15 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rHARDRESET_CLR;\r
- union { /* RSTCTL_HARDRESET_SET Register */\r
- __IO uint32_t r;\r
- struct { /* RSTCTL_HARDRESET_SET Bits */\r
- __O uint32_t bSRC0 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC1 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC2 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC3 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC4 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC5 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC6 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC7 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC8 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC9 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC10 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC11 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC12 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC13 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC14 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __O uint32_t bSRC15 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rHARDRESET_SET;\r
- union { /* RSTCTL_SOFTRESET_STAT Register */\r
- __I uint32_t r;\r
- struct { /* RSTCTL_SOFTRESET_STAT Bits */\r
- __I uint32_t bSRC0 : 1; /* If 1, indicates that SRC0 was the source of the Soft Reset */\r
- __I uint32_t bSRC1 : 1; /* If 1, indicates that SRC1 was the source of the Soft Reset */\r
- __I uint32_t bSRC2 : 1; /* If 1, indicates that SRC2 was the source of the Soft Reset */\r
- __I uint32_t bSRC3 : 1; /* If 1, indicates that SRC3 was the source of the Soft Reset */\r
- __I uint32_t bSRC4 : 1; /* If 1, indicates that SRC4 was the source of the Soft Reset */\r
- __I uint32_t bSRC5 : 1; /* If 1, indicates that SRC5 was the source of the Soft Reset */\r
- __I uint32_t bSRC6 : 1; /* If 1, indicates that SRC6 was the source of the Soft Reset */\r
- __I uint32_t bSRC7 : 1; /* If 1, indicates that SRC7 was the source of the Soft Reset */\r
- __I uint32_t bSRC8 : 1; /* If 1, indicates that SRC8 was the source of the Soft Reset */\r
- __I uint32_t bSRC9 : 1; /* If 1, indicates that SRC9 was the source of the Soft Reset */\r
- __I uint32_t bSRC10 : 1; /* If 1, indicates that SRC10 was the source of the Soft Reset */\r
- __I uint32_t bSRC11 : 1; /* If 1, indicates that SRC11 was the source of the Soft Reset */\r
- __I uint32_t bSRC12 : 1; /* If 1, indicates that SRC12 was the source of the Soft Reset */\r
- __I uint32_t bSRC13 : 1; /* If 1, indicates that SRC13 was the source of the Soft Reset */\r
- __I uint32_t bSRC14 : 1; /* If 1, indicates that SRC14 was the source of the Soft Reset */\r
- __I uint32_t bSRC15 : 1; /* If 1, indicates that SRC15 was the source of the Soft Reset */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rSOFTRESET_STAT;\r
- union { /* RSTCTL_SOFTRESET_CLR Register */\r
- __IO uint32_t r;\r
- struct { /* RSTCTL_SOFTRESET_CLR Bits */\r
- __O uint32_t bSRC0 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC1 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC2 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC3 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC4 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC5 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC6 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC7 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC8 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC9 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC10 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC11 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC12 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC13 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC14 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __O uint32_t bSRC15 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rSOFTRESET_CLR;\r
- union { /* RSTCTL_SOFTRESET_SET Register */\r
- __IO uint32_t r;\r
- struct { /* RSTCTL_SOFTRESET_SET Bits */\r
- __O uint32_t bSRC0 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC1 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC2 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC3 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC4 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC5 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC6 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC7 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC8 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC9 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC10 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC11 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC12 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC13 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC14 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __O uint32_t bSRC15 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rSOFTRESET_SET;\r
- uint8_t RESERVED0[228];\r
- union { /* RSTCTL_PSSRESET_STAT Register */\r
- __I uint32_t r;\r
- struct { /* RSTCTL_PSSRESET_STAT Bits */\r
- __I uint32_t bSVSL : 1; /* Indicates if POR was caused by an SVSL trip condition in the PSS */\r
- __I uint32_t bSVSMH : 1; /* Indicates if POR was caused by an SVSMH trip condition int the PSS */\r
- __I uint32_t bBGREF : 1; /* Indicates if POR was caused by a BGREF not okay condition in the PSS */\r
- __I uint32_t bVCCDET : 1; /* Indicates if POR was caused by a VCCDET trip condition in the PSS */\r
- __I uint32_t bRESERVED0 : 28; /* Reserved */\r
- } b;\r
- } rPSSRESET_STAT;\r
- union { /* RSTCTL_PSSRESET_CLR Register */\r
- __IO uint32_t r;\r
- struct { /* RSTCTL_PSSRESET_CLR Bits */\r
- __O uint32_t bCLR : 1; /* Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rPSSRESET_CLR;\r
- union { /* RSTCTL_PCMRESET_STAT Register */\r
- __I uint32_t r;\r
- struct { /* RSTCTL_PCMRESET_STAT Bits */\r
- __I uint32_t bLPM35 : 1; /* Indicates if POR was caused by PCM due to an exit from LPM3.5 */\r
- __I uint32_t bLPM45 : 1; /* Indicates if POR was caused by PCM due to an exit from LPM4.5 */\r
- __I uint32_t bRESERVED0 : 30; /* Reserved */\r
- } b;\r
- } rPCMRESET_STAT;\r
- union { /* RSTCTL_PCMRESET_CLR Register */\r
- __IO uint32_t r;\r
- struct { /* RSTCTL_PCMRESET_CLR Bits */\r
- __O uint32_t bCLR : 1; /* Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rPCMRESET_CLR;\r
- union { /* RSTCTL_PINRESET_STAT Register */\r
- __I uint32_t r;\r
- struct { /* RSTCTL_PINRESET_STAT Bits */\r
- __I uint32_t bRSTNMI : 1; /* POR was caused by RSTn/NMI pin based reset event */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rPINRESET_STAT;\r
- union { /* RSTCTL_PINRESET_CLR Register */\r
- __IO uint32_t r;\r
- struct { /* RSTCTL_PINRESET_CLR Bits */\r
- __O uint32_t bCLR : 1; /* Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rPINRESET_CLR;\r
- union { /* RSTCTL_REBOOTRESET_STAT Register */\r
- __I uint32_t r;\r
- struct { /* RSTCTL_REBOOTRESET_STAT Bits */\r
- __I uint32_t bREBOOT : 1; /* Indicates if Reboot reset was caused by the SYSCTL module. */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rREBOOTRESET_STAT;\r
- union { /* RSTCTL_REBOOTRESET_CLR Register */\r
- __IO uint32_t r;\r
- struct { /* RSTCTL_REBOOTRESET_CLR Bits */\r
- __O uint32_t bCLR : 1; /* Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rREBOOTRESET_CLR;\r
+ __IO uint32_t RESET_REQ; /**< Reset Request Register */\r
+ __I uint32_t HARDRESET_STAT; /**< Hard Reset Status Register */\r
+ __IO uint32_t HARDRESET_CLR; /**< Hard Reset Status Clear Register */\r
+ __IO uint32_t HARDRESET_SET; /**< Hard Reset Status Set Register */\r
+ __I uint32_t SOFTRESET_STAT; /**< Soft Reset Status Register */\r
+ __IO uint32_t SOFTRESET_CLR; /**< Soft Reset Status Clear Register */\r
+ __IO uint32_t SOFTRESET_SET; /**< Soft Reset Status Set Register */\r
+ uint32_t RESERVED0[57];\r
+ __I uint32_t PSSRESET_STAT; /**< PSS Reset Status Register */\r
+ __IO uint32_t PSSRESET_CLR; /**< PSS Reset Status Clear Register */\r
+ __I uint32_t PCMRESET_STAT; /**< PCM Reset Status Register */\r
+ __IO uint32_t PCMRESET_CLR; /**< PCM Reset Status Clear Register */\r
+ __I uint32_t PINRESET_STAT; /**< Pin Reset Status Register */\r
+ __IO uint32_t PINRESET_CLR; /**< Pin Reset Status Clear Register */\r
+ __I uint32_t REBOOTRESET_STAT; /**< Reboot Reset Status Register */\r
+ __IO uint32_t REBOOTRESET_CLR; /**< Reboot Reset Status Clear Register */\r
+ __I uint32_t CSRESET_STAT; /**< CS Reset Status Register */\r
+ __IO uint32_t CSRESET_CLR; /**< CS Reset Status Clear Register */\r
} RSTCTL_Type;\r
\r
-\r
-//*****************************************************************************\r
-// RTC_C Registers\r
-//*****************************************************************************\r
-typedef struct {\r
- union { /* RTCCTL0 Register */\r
- __IO uint16_t r;\r
- struct { /* RTCCTL0 Bits */\r
- __IO uint16_t bRDYIFG : 1; /* Real-time clock ready interrupt flag */\r
- __IO uint16_t bAIFG : 1; /* Real-time clock alarm interrupt flag */\r
- __IO uint16_t bTEVIFG : 1; /* Real-time clock time event interrupt flag */\r
- __IO uint16_t bOFIFG : 1; /* 32-kHz crystal oscillator fault interrupt flag */\r
- __IO uint16_t bRDYIE : 1; /* Real-time clock ready interrupt enable */\r
- __IO uint16_t bAIE : 1; /* Real-time clock alarm interrupt enable */\r
- __IO uint16_t bTEVIE : 1; /* Real-time clock time event interrupt enable */\r
- __IO uint16_t bOFIE : 1; /* 32-kHz crystal oscillator fault interrupt enable */\r
- __IO uint16_t bKEY : 8; /* Real-time clock key */\r
- } b;\r
- } rCTL0;\r
- union { /* RTCCTL13 Register */\r
- __IO uint16_t r;\r
- struct { /* RTCCTL13 Bits */\r
- __IO uint16_t bTEV : 2; /* Real-time clock time event */\r
- __IO uint16_t bSSEL : 2; /* Real-time clock source select */\r
- __I uint16_t bRDY : 1; /* Real-time clock ready */\r
- __I uint16_t bMODE : 1; /* */\r
- __IO uint16_t bHOLD : 1; /* Real-time clock hold */\r
- __IO uint16_t bBCD : 1; /* Real-time clock BCD select */\r
- __IO uint16_t bCALF : 2; /* Real-time clock calibration frequency */\r
- __I uint16_t bRESERVED0 : 6; /* Reserved */\r
- } b;\r
- } rCTL13;\r
- union { /* RTCOCAL Register */\r
- __IO uint16_t r;\r
- struct { /* RTCOCAL Bits */\r
- __IO uint16_t bOCAL : 8; /* Real-time clock offset error calibration */\r
- __I uint16_t bRESERVED0 : 7; /* Reserved */\r
- __IO uint16_t bOCALS : 1; /* Real-time clock offset error calibration sign */\r
- } b;\r
- } rOCAL;\r
- union { /* RTCTCMP Register */\r
- __IO uint16_t r;\r
- struct { /* RTCTCMP Bits */\r
- __IO uint16_t bTCMP : 8; /* Real-time clock temperature compensation */\r
- __I uint16_t bRESERVED0 : 5; /* Reserved */\r
- __I uint16_t bTCOK : 1; /* Real-time clock temperature compensation write OK */\r
- __I uint16_t bTCRDY : 1; /* Real-time clock temperature compensation ready */\r
- __IO uint16_t bTCMPS : 1; /* Real-time clock temperature compensation sign */\r
- } b;\r
- } rTCMP;\r
- union { /* RTCPS0CTL Register */\r
- __IO uint16_t r;\r
- struct { /* RTCPS0CTL Bits */\r
- __IO uint16_t bRT0PSIFG : 1; /* Prescale timer 0 interrupt flag */\r
- __IO uint16_t bRT0PSIE : 1; /* Prescale timer 0 interrupt enable */\r
- __IO uint16_t bRT0IP : 3; /* Prescale timer 0 interrupt interval */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rPS0CTL;\r
- union { /* RTCPS1CTL Register */\r
- __IO uint16_t r;\r
- struct { /* RTCPS1CTL Bits */\r
- __IO uint16_t bRT1PSIFG : 1; /* Prescale timer 1 interrupt flag */\r
- __IO uint16_t bRT1PSIE : 1; /* Prescale timer 1 interrupt enable */\r
- __IO uint16_t bRT1IP : 3; /* Prescale timer 1 interrupt interval */\r
- __I uint16_t bRESERVED0 : 11; /* Reserved */\r
- } b;\r
- } rPS1CTL;\r
- union { /* RTCPS Register */\r
- __IO uint16_t r;\r
- struct { /* RTCPS Bits */\r
- __IO uint16_t bRT0PS : 8; /* Prescale timer 0 counter value */\r
- __IO uint16_t bRT1PS : 8; /* Prescale timer 1 counter value */\r
- } b;\r
- } rPS;\r
- __I uint16_t rIV; /* Real-Time Clock Interrupt Vector Register */\r
- union { /* RTCTIM0 Register */\r
- __IO uint16_t r;\r
- struct { /* RTCTIM0 Bits */\r
- __IO uint16_t bSEC : 6; /* Seconds (0 to 59) */\r
- __I uint16_t bRESERVED0 : 2; /* Reserved */\r
- __IO uint16_t bMIN : 6; /* Minutes (0 to 59) */\r
- __I uint16_t bRESERVED1 : 2; /* Reserved */\r
- } b;\r
- struct { /* RTCTIM0_BCD Bits */\r
- __IO uint16_t bSEC_LD : 4; /* Seconds ? low digit (0 to 9) */\r
- __IO uint16_t bSEC_HD : 3; /* Seconds ? high digit (0 to 5) */\r
- __I uint16_t bRESERVED : 1; /* Reserved */\r
- __IO uint16_t bMIN_LD : 4; /* Minutes ? low digit (0 to 9) */\r
- __IO uint16_t bMIN_HD : 3; /* Minutes ? high digit (0 to 5) */\r
- } a;\r
- } rTIM0;\r
- union { /* RTCTIM1 Register */\r
- __IO uint16_t r;\r
- struct { /* RTCTIM1 Bits */\r
- __IO uint16_t bHOUR : 5; /* Hours (0 to 23) */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */\r
- __I uint16_t bRESERVED1 : 5; /* Reserved */\r
- } b;\r
- struct { /* RTCTIM1_BCD Bits */\r
- __IO uint16_t bHOUR_LD : 4; /* Hours ? low digit (0 to 9) */\r
- __IO uint16_t bHOUR_HD : 2; /* Hours ? high digit (0 to 2) */\r
- __I uint16_t bRESERVED : 2; /* Reserved */\r
- __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */\r
- } a;\r
- } rTIM1;\r
- union { /* RTCDATE Register */\r
- __IO uint16_t r;\r
- struct { /* RTCDATE Bits */\r
- __IO uint16_t bDAY : 5; /* Day of month (1 to 28, 29, 30, 31) */\r
- __I uint16_t bRESERVED0 : 3; /* Reserved */\r
- __IO uint16_t bMON : 4; /* Month (1 to 12) */\r
- __I uint16_t bRESERVED1 : 4; /* Reserved */\r
- } b;\r
- struct { /* RTCDATE_BCD Bits */\r
- __IO uint16_t bDAY_LD : 4; /* Day of month ? low digit (0 to 9) */\r
- __IO uint16_t bDAY_HD : 2; /* Day of month ? high digit (0 to 3) */\r
- __I uint16_t bRESERVED : 2; /* Reserved */\r
- __IO uint16_t bMON_LD : 4; /* Month ? low digit (0 to 9) */\r
- __IO uint16_t bMON_HD : 1; /* Month ? high digit (0 or 1) */\r
- } a;\r
- } rDATE;\r
- union { /* RTCYEAR Register */\r
- __IO uint16_t r;\r
- struct { /* RTCYEAR Bits */\r
- __IO uint16_t bYEAR_LB : 8; /* Year ? low byte. Valid values for Year are 0 to 4095. */\r
- __IO uint16_t bYEAR_HB : 4; /* Year ? high byte. Valid values for Year are 0 to 4095. */\r
- __I uint16_t bRESERVED0 : 4; /* Reserved */\r
- } b;\r
- struct { /* RTCYEAR_BCD Bits */\r
- __IO uint16_t bYEAR : 4; /* Year ? lowest digit (0 to 9) */\r
- __IO uint16_t bDEC : 4; /* Decade (0 to 9) */\r
- __IO uint16_t bCENT_LD : 4; /* Century ? low digit (0 to 9) */\r
- __IO uint16_t bCENT_HD : 3; /* Century ? high digit (0 to 4) */\r
- __I uint16_t bRESERVED : 1; /* Reserved */\r
- } a;\r
- } rYEAR;\r
- union { /* RTCAMINHR Register */\r
- __IO uint16_t r;\r
- struct { /* RTCAMINHR Bits */\r
- __IO uint16_t bMIN : 6; /* Minutes (0 to 59) */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bMINAE : 1; /* Alarm enable */\r
- __IO uint16_t bHOUR : 5; /* Hours (0 to 23) */\r
- __I uint16_t bRESERVED1 : 2; /* Reserved */\r
- __IO uint16_t bHOURAE : 1; /* Alarm enable */\r
- } b;\r
- struct { /* RTCAMINHR_BCD Bits */\r
- __IO uint16_t bMIN_LD : 4; /* Minutes ? low digit (0 to 9) */\r
- __IO uint16_t bMIN_HD : 3; /* Minutes ? high digit (0 to 5) */\r
- __IO uint16_t b : 1; /* Alarm enable */\r
- __IO uint16_t bHOUR_LD : 4; /* Hours ? low digit (0 to 9) */\r
- __IO uint16_t bHOUR_HD : 2; /* Hours ? high digit (0 to 2) */\r
- __I uint16_t bRESERVED : 1; /* Reserved */\r
- __IO uint16_t bHOURAE : 1; /* Alarm enable */\r
- } a;\r
- } rAMINHR;\r
- union { /* RTCADOWDAY Register */\r
- __IO uint16_t r;\r
- struct { /* RTCADOWDAY Bits */\r
- __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */\r
- __I uint16_t bRESERVED0 : 4; /* Reserved */\r
- __IO uint16_t bDOWAE : 1; /* Alarm enable */\r
- __IO uint16_t bDAY : 5; /* Day of month (1 to 28, 29, 30, 31) */\r
- __I uint16_t bRESERVED1 : 2; /* Reserved */\r
- __IO uint16_t bDAYAE : 1; /* Alarm enable */\r
- } b;\r
- struct { /* RTCADOWDAY_BCD Bits */\r
- __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */\r
- __I uint16_t bRESERVED : 4; /* Reserved */\r
- __IO uint16_t bDOWAE : 1; /* Alarm enable */\r
- __IO uint16_t bDAY_LD : 4; /* Day of month ? low digit (0 to 9) */\r
- __IO uint16_t bDAY_HD : 2; /* Day of month ? high digit (0 to 3) */\r
- __IO uint16_t bDAYAE : 1; /* Alarm enable */\r
- } a;\r
- } rADOWDAY;\r
- __IO uint16_t rBIN2BCD; /* Binary-to-BCD Conversion Register */\r
- __IO uint16_t rBCD2BIN; /* BCD-to-Binary Conversion Register */\r
-} RTC_C_Type;\r
+/*@}*/ /* end of group RSTCTL */\r
\r
\r
-//*****************************************************************************\r
-// SYSCTL Registers\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* RTC_C Registers\r
+******************************************************************************/\r
+/** @addtogroup RTC_C MSP432P401R (RTC_C)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* SYS_REBOOT_CTL Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_REBOOT_CTL Bits */\r
- __IO uint32_t bREBOOT : 1; /* Write 1 initiates a Reboot of the device */\r
- __I uint32_t bRESERVED0 : 7; /* Reserved */\r
- __O uint32_t bWKEY : 8; /* Key to enable writes to bit 0 */\r
- __I uint32_t bRESERVED1 : 16; /* Reserved */\r
- } b;\r
- } rREBOOT_CTL;\r
- union { /* SYS_NMI_CTLSTAT Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_NMI_CTLSTAT Bits */\r
- __IO uint32_t bCS_SRC : 1; /* CS interrupt as a source of NMI */\r
- __IO uint32_t bPSS_SRC : 1; /* PSS interrupt as a source of NMI */\r
- __IO uint32_t bPCM_SRC : 1; /* PCM interrupt as a source of NMI */\r
- __IO uint32_t bPIN_SRC : 1; /* */\r
- __I uint32_t bRESERVED0 : 12; /* Reserved */\r
- __I uint32_t bCS_FLG : 1; /* CS interrupt was the source of NMI */\r
- __I uint32_t bPSS_FLG : 1; /* PSS interrupt was the source of NMI */\r
- __I uint32_t bPCM_FLG : 1; /* PCM interrupt was the source of NMI */\r
- __IO uint32_t bPIN_FLG : 1; /* RSTn/NMI pin was the source of NMI */\r
- __I uint32_t bRESERVED1 : 12; /* Reserved */\r
- } b;\r
- } rNMI_CTLSTAT;\r
- union { /* SYS_WDTRESET_CTL Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_WDTRESET_CTL Bits */\r
- __IO uint32_t bTIMEOUT : 1; /* WDT timeout reset type */\r
- __IO uint32_t bVIOLATION : 1; /* WDT password violation reset type */\r
- __I uint32_t bRESERVED0 : 30; /* Reserved */\r
- } b;\r
- } rWDTRESET_CTL;\r
- union { /* SYS_PERIHALT_CTL Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_PERIHALT_CTL Bits */\r
- __IO uint32_t bT16_0 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bT16_1 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bT16_2 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bT16_3 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bT32_0 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bEUA0 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bEUA1 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bEUA2 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bEUA3 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bEUB0 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bEUB1 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bEUB2 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bEUB3 : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bADC : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bWDT : 1; /* Freezes IP operation when CPU is halted */\r
- __IO uint32_t bDMA : 1; /* Freezes IP operation when CPU is halted */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rPERIHALT_CTL;\r
- __I uint32_t rSRAM_SIZE; /* SRAM Size Register */\r
- union { /* SYS_SRAM_BANKEN Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_SRAM_BANKEN Bits */\r
- __I uint32_t bBNK0_EN : 1; /* SRAM Bank0 enable */\r
- __IO uint32_t bBNK1_EN : 1; /* SRAM Bank1 enable */\r
- __IO uint32_t bBNK2_EN : 1; /* SRAM Bank1 enable */\r
- __IO uint32_t bBNK3_EN : 1; /* SRAM Bank1 enable */\r
- __IO uint32_t bBNK4_EN : 1; /* SRAM Bank1 enable */\r
- __IO uint32_t bBNK5_EN : 1; /* SRAM Bank1 enable */\r
- __IO uint32_t bBNK6_EN : 1; /* SRAM Bank1 enable */\r
- __IO uint32_t bBNK7_EN : 1; /* SRAM Bank1 enable */\r
- __I uint32_t bRESERVED0 : 8; /* Reserved */\r
- __I uint32_t bSRAM_RDY : 1; /* SRAM ready */\r
- __I uint32_t bRESERVED1 : 15; /* Reserved */\r
- } b;\r
- } rSRAM_BANKEN;\r
- union { /* SYS_SRAM_BANKRET Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_SRAM_BANKRET Bits */\r
- __I uint32_t bBNK0_RET : 1; /* Bank0 retention */\r
- __IO uint32_t bBNK1_RET : 1; /* Bank1 retention */\r
- __IO uint32_t bBNK2_RET : 1; /* Bank2 retention */\r
- __IO uint32_t bBNK3_RET : 1; /* Bank3 retention */\r
- __IO uint32_t bBNK4_RET : 1; /* Bank4 retention */\r
- __IO uint32_t bBNK5_RET : 1; /* Bank5 retention */\r
- __IO uint32_t bBNK6_RET : 1; /* Bank6 retention */\r
- __IO uint32_t bBNK7_RET : 1; /* Bank7 retention */\r
- __I uint32_t bRESERVED0 : 8; /* Reserved */\r
- __I uint32_t bSRAM_RDY : 1; /* SRAM ready */\r
- __I uint32_t bRESERVED1 : 15; /* Reserved */\r
- } b;\r
- } rSRAM_BANKRET;\r
- uint8_t RESERVED0[4];\r
- __I uint32_t rFLASH_SIZE; /* Flash Size Register */\r
- uint8_t RESERVED1[12];\r
- union { /* SYS_DIO_GLTFLT_CTL Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_DIO_GLTFLT_CTL Bits */\r
- __IO uint32_t bGLTCH_EN : 1; /* Glitch filter enable */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rDIO_GLTFLT_CTL;\r
- uint8_t RESERVED2[12];\r
- union { /* SYS_SECDATA_UNLOCK Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_SECDATA_UNLOCK Bits */\r
- __IO uint32_t bUNLKEY : 16; /* Unlock key */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rSECDATA_UNLOCK;\r
- uint8_t RESERVED3[4028];\r
- union { /* SYS_MASTER_UNLOCK Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_MASTER_UNLOCK Bits */\r
- __IO uint32_t bUNLKEY : 16; /* Unlock Key */\r
- __I uint32_t bRESERVED0 : 16; /* Reserved */\r
- } b;\r
- } rMASTER_UNLOCK;\r
- __IO uint32_t rBOOTOVER_REQ0; /* Boot Override Request Register */\r
- __IO uint32_t rBOOTOVER_REQ1; /* Boot Override Request Register */\r
- __IO uint32_t rBOOTOVER_ACK; /* Boot Override Acknowledge Register */\r
- union { /* SYS_RESET_REQ Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_RESET_REQ Bits */\r
- __O uint32_t bPOR : 1; /* Generate POR */\r
- __O uint32_t bREBOOT : 1; /* Generate Reboot_Reset */\r
- __I uint32_t bRESERVED0 : 6; /* Reserved */\r
- __O uint32_t bWKEY : 8; /* Write key */\r
- __I uint32_t bRESERVED1 : 16; /* Reserved */\r
- } b;\r
- } rRESET_REQ;\r
- union { /* SYS_RESET_STATOVER Register */\r
- __IO uint32_t r;\r
- struct { /* SYS_RESET_STATOVER Bits */\r
- __I uint32_t bSOFT : 1; /* Indicates if SOFT Reset is active */\r
- __I uint32_t bHARD : 1; /* Indicates if HARD Reset is active */\r
- __I uint32_t bREBOOT : 1; /* Indicates if Reboot Reset is active */\r
- __I uint32_t bRESERVED0 : 5; /* Reserved */\r
- __IO uint32_t bSOFT_OVER : 1; /* SOFT_Reset overwrite request */\r
- __IO uint32_t bHARD_OVER : 1; /* HARD_Reset overwrite request */\r
- __IO uint32_t bRBT_OVER : 1; /* Reboot Reset overwrite request */\r
- __I uint32_t bRESERVED1 : 21; /* Reserved */\r
- } b;\r
- } rRESET_STATOVER;\r
- uint8_t RESERVED4[8];\r
- union { /* SYS_SYSTEM_STAT Register */\r
- __I uint32_t r;\r
- struct { /* SYS_SYSTEM_STAT Bits */\r
- __I uint32_t bRESERVED0 : 3; /* Reserved */\r
- __I uint32_t bDBG_SEC_ACT : 1; /* Debug Security active */\r
- __I uint32_t bJTAG_SWD_LOCK_ACT : 1; /* Indicates if JTAG and SWD Lock is active */\r
- __I uint32_t bIP_PROT_ACT : 1; /* Indicates if IP protection is active */\r
- __I uint32_t bRESERVED1 : 26; /* Reserved */\r
- } b;\r
- } rSYSTEM_STAT;\r
-} SYSCTL_Type;\r
+ __IO uint16_t CTL0; /**< RTCCTL0 Register */\r
+ __IO uint16_t CTL13; /**< RTCCTL13 Register */\r
+ __IO uint16_t OCAL; /**< RTCOCAL Register */\r
+ __IO uint16_t TCMP; /**< RTCTCMP Register */\r
+ __IO uint16_t PS0CTL; /**< Real-Time Clock Prescale Timer 0 Control Register */\r
+ __IO uint16_t PS1CTL; /**< Real-Time Clock Prescale Timer 1 Control Register */\r
+ __IO uint16_t PS; /**< Real-Time Clock Prescale Timer Counter Register */\r
+ __I uint16_t IV; /**< Real-Time Clock Interrupt Vector Register */\r
+ __IO uint16_t TIM0; /**< RTCTIM0 Register ? Hexadecimal Format */\r
+ __IO uint16_t TIM1; /**< Real-Time Clock Hour, Day of Week */\r
+ __IO uint16_t DATE; /**< RTCDATE - Hexadecimal Format */\r
+ __IO uint16_t YEAR; /**< RTCYEAR Register ? Hexadecimal Format */\r
+ __IO uint16_t AMINHR; /**< RTCMINHR - Hexadecimal Format */\r
+ __IO uint16_t ADOWDAY; /**< RTCADOWDAY - Hexadecimal Format */\r
+ __IO uint16_t BIN2BCD; /**< Binary-to-BCD Conversion Register */\r
+ __IO uint16_t BCD2BIN; /**< BCD-to-Binary Conversion Register */\r
+} RTC_C_Type;\r
\r
+/*@}*/ /* end of group RTC_C */\r
\r
-//*****************************************************************************\r
-// TIMER32 Registers\r
-//*****************************************************************************\r
+/** @addtogroup RTC_C_BCD MSP432P401R (RTC_C_BCD)\r
+ @{\r
+*/\r
typedef struct {\r
- __IO uint32_t rLOAD1; /* Timer 1 Load Register */\r
- __I uint32_t rVALUE1; /* Timer 1 Current Value Register */\r
- union { /* T32CONTROL1 Register */\r
- __IO uint32_t r;\r
- struct { /* T32CONTROL1 Bits */\r
- __IO uint32_t bONESHOT : 1; /* Selects one-shot or wrapping counter mode */\r
- __IO uint32_t bSIZE : 1; /* Selects 16 or 32 bit counter operation */\r
- __IO uint32_t bPRESCALE : 2; /* Prescale bits */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bIE : 1; /* Interrupt enable bit */\r
- __IO uint32_t bMODE : 1; /* Mode bit */\r
- __IO uint32_t bENABLE : 1; /* */\r
- __I uint32_t bRESERVED1 : 24; /* Reserved */\r
- } b;\r
- } rCONTROL1;\r
- __O uint32_t rINTCLR1; /* Timer 1 Interrupt Clear Register */\r
- union { /* T32RIS1 Register */\r
- __I uint32_t r;\r
- struct { /* T32RIS1 Bits */\r
- __I uint32_t bRAW_IFG : 1; /* Raw interrupt status */\r
- __I uint32_t b : 31; /* */\r
- } b;\r
- } rRIS1;\r
- union { /* T32MIS1 Register */\r
- __I uint32_t r;\r
- struct { /* T32MIS1 Bits */\r
- __I uint32_t b : 1; /* Enabled interrupt status */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rMIS1;\r
- __IO uint32_t rBGLOAD1; /* Timer 1 Background Load Register */\r
- uint8_t RESERVED0[4];\r
- __IO uint32_t rLOAD2; /* Timer 2 Load Register */\r
- __I uint32_t rVALUE2; /* Timer 2 Current Value Register */\r
- union { /* T32CONTROL2 Register */\r
- __IO uint32_t r;\r
- struct { /* T32CONTROL2 Bits */\r
- __IO uint32_t bONESHOT : 1; /* Selects one-shot or wrapping counter mode */\r
- __IO uint32_t bSIZE : 1; /* Selects 16 or 32 bit counter operation */\r
- __IO uint32_t bPRESCALE : 2; /* Prescale bits */\r
- __I uint32_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint32_t bIE : 1; /* Interrupt enable bit */\r
- __IO uint32_t bMODE : 1; /* Mode bit */\r
- __IO uint32_t bENABLE : 1; /* */\r
- __I uint32_t bRESERVED1 : 24; /* Reserved */\r
- } b;\r
- } rCONTROL2;\r
- __O uint32_t rINTCLR2; /* Timer 2 Interrupt Clear Register */\r
- union { /* T32RIS2 Register */\r
- __I uint32_t r;\r
- struct { /* T32RIS2 Bits */\r
- __I uint32_t bRAW_IFG : 1; /* Raw interrupt status */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rRIS2;\r
- union { /* T32MIS2 Register */\r
- __I uint32_t r;\r
- struct { /* T32MIS2 Bits */\r
- __I uint32_t bIFG : 1; /* Enabled interrupt status */\r
- __I uint32_t bRESERVED0 : 31; /* Reserved */\r
- } b;\r
- } rMIS2;\r
- __IO uint32_t rBGLOAD2; /* Timer 2 Background Load Register */\r
- uint8_t RESERVED1[3780];\r
- union { /* T32ITCR Register */\r
- __IO uint32_t r;\r
- struct { /* T32ITCR Bits */\r
- __IO uint32_t bTEST_EN : 1; /* Test mode */\r
- __I uint32_t b : 31; /* */\r
- } b;\r
- } rITCR;\r
- union { /* T32ITOP Register */\r
- __IO uint32_t r;\r
- struct { /* T32ITOP Bits */\r
- __O uint32_t bTIMINT1_VAL : 1; /* Value output on TIMINT1 */\r
- __O uint32_t bTIMINT2_VAL : 1; /* Value output on TIMINT2 */\r
- __I uint32_t bRESERVED0 : 30; /* Reserved */\r
- } b;\r
- } rITOP;\r
-} TIMER32_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A0 Registers\r
-//*****************************************************************************\r
+ uint16_t RESERVED0[8];\r
+ __IO uint16_t TIM0; /**< RTCTIM0 Register ? BCD Format */\r
+ __IO uint16_t TIM1; /**< RTCTIM1 Register ? BCD Format */\r
+ __IO uint16_t DATE; /**< Real-Time Clock Date - BCD Format */\r
+ __IO uint16_t YEAR; /**< RTCYEAR Register ? BCD Format */\r
+ __IO uint16_t AMINHR; /**< RTCMINHR - BCD Format */\r
+ __IO uint16_t ADOWDAY; /**< RTCADOWDAY - BCD Format */\r
+} RTC_C_BCD_Type;\r
+\r
+/*@}*/ /* end of group RTC_C_BCD */\r
+\r
+\r
+/******************************************************************************\r
+* SYSCTL Registers\r
+******************************************************************************/\r
+/** @addtogroup SYSCTL MSP432P401R (SYSCTL)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* TA0CTL Register */\r
- __IO uint16_t r;\r
- struct { /* TA0CTL Bits */\r
- __IO uint16_t bIFG : 1; /* TimerA interrupt flag */\r
- __IO uint16_t bIE : 1; /* TimerA interrupt enable */\r
- __IO uint16_t bCLR : 1; /* TimerA clear */\r
- __IO uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bMC : 2; /* Mode control */\r
- __IO uint16_t bID : 2; /* Input divider */\r
- __IO uint16_t bSSEL : 2; /* TimerA clock source select */\r
- __IO uint16_t bRESERVED1 : 6; /* Reserved */\r
- } b;\r
- } rCTL;\r
- union { /* TA0CCTL0 Register */\r
- __IO uint16_t r;\r
- struct { /* TA0CCTL0 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL0;\r
- union { /* TA0CCTL1 Register */\r
- __IO uint16_t r;\r
- struct { /* TA0CCTL1 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL1;\r
- union { /* TA0CCTL2 Register */\r
- __IO uint16_t r;\r
- struct { /* TA0CCTL2 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL2;\r
- union { /* TA0CCTL3 Register */\r
- __IO uint16_t r;\r
- struct { /* TA0CCTL3 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL3;\r
- union { /* TA0CCTL4 Register */\r
- __IO uint16_t r;\r
- struct { /* TA0CCTL4 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL4;\r
- union { /* TA0CCTL5 Register */\r
- __IO uint16_t r;\r
- struct { /* TA0CCTL5 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL5;\r
- union { /* TA0CCTL6 Register */\r
- __IO uint16_t r;\r
- struct { /* TA0CCTL6 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL6;\r
- __IO uint16_t rR; /* TimerA register */\r
- __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */\r
- union { /* TA0EX0 Register */\r
- __IO uint16_t r;\r
- struct { /* TA0EX0 Bits */\r
- __IO uint16_t bIDEX : 3; /* Input divider expansion */\r
- __I uint16_t bRESERVED0 : 13; /* Reserved */\r
- } b;\r
- } rEX0;\r
- uint8_t RESERVED0[12];\r
- __I uint16_t rIV; /* TimerAx Interrupt Vector Register */\r
-} TIMER_A0_Type;\r
-\r
+ __IO uint32_t REBOOT_CTL; /**< Reboot Control Register */\r
+ __IO uint32_t NMI_CTLSTAT; /**< NMI Control and Status Register */\r
+ __IO uint32_t WDTRESET_CTL; /**< Watchdog Reset Control Register */\r
+ __IO uint32_t PERIHALT_CTL; /**< Peripheral Halt Control Register */\r
+ __I uint32_t SRAM_SIZE; /**< SRAM Size Register */\r
+ __IO uint32_t SRAM_BANKEN; /**< SRAM Bank Enable Register */\r
+ __IO uint32_t SRAM_BANKRET; /**< SRAM Bank Retention Control Register */\r
+ uint32_t RESERVED0;\r
+ __I uint32_t FLASH_SIZE; /**< Flash Size Register */\r
+ uint32_t RESERVED1[3];\r
+ __IO uint32_t DIO_GLTFLT_CTL; /**< Digital I/O Glitch Filter Control Register */\r
+ uint32_t RESERVED2[3];\r
+ __IO uint32_t SECDATA_UNLOCK; /**< IP Protected Secure Zone Data Access Unlock Register */\r
+ uint32_t RESERVED3[175];\r
+ __IO uint32_t CSYS_MASTER_UNLOCK; /**< Master Unlock Register */\r
+ __IO uint32_t BOOT_CTL; /**< Boot Control Register */\r
+ uint32_t RESERVED4[2];\r
+ __IO uint32_t SEC_CTL; /**< Security Control Register */\r
+ uint32_t RESERVED5[3];\r
+ __IO uint32_t SEC_STARTADDR0; /**< Security Zone 0 Start Address Register */\r
+ __IO uint32_t SEC_STARTADDR1; /**< Security Zone 1 Start Address Register */\r
+ __IO uint32_t SEC_STARTADDR2; /**< Security Zone 2 Start Address Register */\r
+ __IO uint32_t SEC_STARTADDR3; /**< Security Zone 3 Start Address Register */\r
+ __IO uint32_t SEC_SIZE0; /**< Security Zone 0 Size Register */\r
+ __IO uint32_t SEC_SIZE1; /**< Security Zone 1 Size Register */\r
+ __IO uint32_t SEC_SIZE2; /**< Security Zone 2 Size Register */\r
+ __IO uint32_t SEC_SIZE3; /**< Security Zone 3 Size Register */\r
+ __IO uint32_t ETW_CTL; /**< ETW Control Register */\r
+ __IO uint32_t FLASH_SIZECFG; /**< Flash Size Configuration Register */\r
+ __IO uint32_t SRAM_SIZECFG; /**< SRAM Size Configuration Register */\r
+ __IO uint32_t SRAM_NUMBANK; /**< SRAM NUM BANK Configuration Register */\r
+ __IO uint32_t TIMER_CFG; /**< Timer Configuration Register */\r
+ __IO uint32_t EUSCI_CFG; /**< eUSCI Configuration Register */\r
+ __IO uint32_t ADC_CFG; /**< ADC Configuration Register */\r
+ __IO uint32_t XTAL_CFG; /**< Crystal Oscillator Configuration Register */\r
+ __IO uint32_t BOC_CFG; /**< Bond Out Configuration Register */\r
+} SYSCTL_Type;\r
\r
-//*****************************************************************************\r
-// TIMER_A1 Registers\r
-//*****************************************************************************\r
typedef struct {\r
- union { /* TA1CTL Register */\r
- __IO uint16_t r;\r
- struct { /* TA1CTL Bits */\r
- __IO uint16_t bIFG : 1; /* TimerA interrupt flag */\r
- __IO uint16_t bIE : 1; /* TimerA interrupt enable */\r
- __IO uint16_t bCLR : 1; /* TimerA clear */\r
- __IO uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bMC : 2; /* Mode control */\r
- __IO uint16_t bID : 2; /* Input divider */\r
- __IO uint16_t bSSEL : 2; /* TimerA clock source select */\r
- __IO uint16_t bRESERVED1 : 6; /* Reserved */\r
- } b;\r
- } rCTL;\r
- union { /* TA1CCTL0 Register */\r
- __IO uint16_t r;\r
- struct { /* TA1CCTL0 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL0;\r
- union { /* TA1CCTL1 Register */\r
- __IO uint16_t r;\r
- struct { /* TA1CCTL1 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL1;\r
- union { /* TA1CCTL2 Register */\r
- __IO uint16_t r;\r
- struct { /* TA1CCTL2 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL2;\r
- union { /* TA1CCTL3 Register */\r
- __IO uint16_t r;\r
- struct { /* TA1CCTL3 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL3;\r
- union { /* TA1CCTL4 Register */\r
- __IO uint16_t r;\r
- struct { /* TA1CCTL4 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL4;\r
- union { /* TA1CCTL5 Register */\r
- __IO uint16_t r;\r
- struct { /* TA1CCTL5 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL5;\r
- union { /* TA1CCTL6 Register */\r
- __IO uint16_t r;\r
- struct { /* TA1CCTL6 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL6;\r
- __IO uint16_t rR; /* TimerA register */\r
- __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */\r
- union { /* TA1EX0 Register */\r
- __IO uint16_t r;\r
- struct { /* TA1EX0 Bits */\r
- __IO uint16_t bIDEX : 3; /* Input divider expansion */\r
- __I uint16_t bRESERVED0 : 13; /* Reserved */\r
- } b;\r
- } rEX0;\r
- uint8_t RESERVED0[12];\r
- __I uint16_t rIV; /* TimerAx Interrupt Vector Register */\r
-} TIMER_A1_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A2 Registers\r
-//*****************************************************************************\r
+ __IO uint32_t MASTER_UNLOCK; /**< Master Unlock Register */\r
+ __IO uint32_t BOOTOVER_REQ[2]; /**< Boot Override Request Register */\r
+ __IO uint32_t BOOTOVER_ACK; /**< Boot Override Acknowledge Register */\r
+ __IO uint32_t RESET_REQ; /**< Reset Request Register */\r
+ __IO uint32_t RESET_STATOVER; /**< Reset Status and Override Register */\r
+ uint32_t RESERVED7[2];\r
+ __I uint32_t SYSTEM_STAT; /**< System Status Register */\r
+} SYSCTL_Boot_Type;\r
+\r
+/*@}*/ /* end of group SYSCTL */\r
+\r
+\r
+/******************************************************************************\r
+* Timer32 Registers\r
+******************************************************************************/\r
+/** @addtogroup Timer32 MSP432P401R (Timer32)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* TA2CTL Register */\r
- __IO uint16_t r;\r
- struct { /* TA2CTL Bits */\r
- __IO uint16_t bIFG : 1; /* TimerA interrupt flag */\r
- __IO uint16_t bIE : 1; /* TimerA interrupt enable */\r
- __IO uint16_t bCLR : 1; /* TimerA clear */\r
- __IO uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bMC : 2; /* Mode control */\r
- __IO uint16_t bID : 2; /* Input divider */\r
- __IO uint16_t bSSEL : 2; /* TimerA clock source select */\r
- __IO uint16_t bRESERVED1 : 6; /* Reserved */\r
- } b;\r
- } rCTL;\r
- union { /* TA2CCTL0 Register */\r
- __IO uint16_t r;\r
- struct { /* TA2CCTL0 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL0;\r
- union { /* TA2CCTL1 Register */\r
- __IO uint16_t r;\r
- struct { /* TA2CCTL1 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL1;\r
- union { /* TA2CCTL2 Register */\r
- __IO uint16_t r;\r
- struct { /* TA2CCTL2 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL2;\r
- union { /* TA2CCTL3 Register */\r
- __IO uint16_t r;\r
- struct { /* TA2CCTL3 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL3;\r
- union { /* TA2CCTL4 Register */\r
- __IO uint16_t r;\r
- struct { /* TA2CCTL4 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL4;\r
- union { /* TA2CCTL5 Register */\r
- __IO uint16_t r;\r
- struct { /* TA2CCTL5 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL5;\r
- union { /* TA2CCTL6 Register */\r
- __IO uint16_t r;\r
- struct { /* TA2CCTL6 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL6;\r
- __IO uint16_t rR; /* TimerA register */\r
- __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */\r
- union { /* TA2EX0 Register */\r
- __IO uint16_t r;\r
- struct { /* TA2EX0 Bits */\r
- __IO uint16_t bIDEX : 3; /* Input divider expansion */\r
- __I uint16_t bRESERVED0 : 13; /* Reserved */\r
- } b;\r
- } rEX0;\r
- uint8_t RESERVED0[12];\r
- __I uint16_t rIV; /* TimerAx Interrupt Vector Register */\r
-} TIMER_A2_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A3 Registers\r
-//*****************************************************************************\r
+ __IO uint32_t LOAD; /**< Timer 1 Load Register */\r
+ __I uint32_t VALUE; /**< Timer 1 Current Value Register */\r
+ __IO uint32_t CONTROL; /**< Timer 1 Timer Control Register */\r
+ __O uint32_t INTCLR; /**< Timer 1 Interrupt Clear Register */\r
+ __I uint32_t RIS; /**< Timer 1 Raw Interrupt Status Register */\r
+ __I uint32_t MIS; /**< Timer 1 Interrupt Status Register */\r
+ __IO uint32_t BGLOAD; /**< Timer 1 Background Load Register */\r
+} Timer32_Type;\r
+\r
+/*@}*/ /* end of group Timer32 */\r
+\r
+\r
+/******************************************************************************\r
+* Timer_A Registers\r
+******************************************************************************/\r
+/** @addtogroup Timer_A MSP432P401R (Timer_A)\r
+ @{\r
+*/\r
typedef struct {\r
- union { /* TA3CTL Register */\r
- __IO uint16_t r;\r
- struct { /* TA3CTL Bits */\r
- __IO uint16_t bIFG : 1; /* TimerA interrupt flag */\r
- __IO uint16_t bIE : 1; /* TimerA interrupt enable */\r
- __IO uint16_t bCLR : 1; /* TimerA clear */\r
- __IO uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bMC : 2; /* Mode control */\r
- __IO uint16_t bID : 2; /* Input divider */\r
- __IO uint16_t bSSEL : 2; /* TimerA clock source select */\r
- __IO uint16_t bRESERVED1 : 6; /* Reserved */\r
- } b;\r
- } rCTL;\r
- union { /* TA3CCTL0 Register */\r
- __IO uint16_t r;\r
- struct { /* TA3CCTL0 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL0;\r
- union { /* TA3CCTL1 Register */\r
- __IO uint16_t r;\r
- struct { /* TA3CCTL1 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL1;\r
- union { /* TA3CCTL2 Register */\r
- __IO uint16_t r;\r
- struct { /* TA3CCTL2 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL2;\r
- union { /* TA3CCTL3 Register */\r
- __IO uint16_t r;\r
- struct { /* TA3CCTL3 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL3;\r
- union { /* TA3CCTL4 Register */\r
- __IO uint16_t r;\r
- struct { /* TA3CCTL4 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL4;\r
- union { /* TA3CCTL5 Register */\r
- __IO uint16_t r;\r
- struct { /* TA3CCTL5 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL5;\r
- union { /* TA3CCTL6 Register */\r
- __IO uint16_t r;\r
- struct { /* TA3CCTL6 Bits */\r
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */\r
- __IO uint16_t bCOV : 1; /* Capture overflow */\r
- __IO uint16_t bOUT : 1; /* Output */\r
- __I uint16_t bCCI : 1; /* Capture/compare input */\r
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */\r
- __IO uint16_t bOUTMOD : 3; /* Output mode */\r
- __IO uint16_t bCAP : 1; /* Capture mode */\r
- __I uint16_t bRESERVED0 : 1; /* Reserved */\r
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */\r
- __IO uint16_t bSCS : 1; /* Synchronize capture source */\r
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */\r
- __IO uint16_t bCM : 2; /* Capture mode */\r
- } b;\r
- } rCCTL6;\r
- __IO uint16_t rR; /* TimerA register */\r
- __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */\r
- __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */\r
- union { /* TA3EX0 Register */\r
- __IO uint16_t r;\r
- struct { /* TA3EX0 Bits */\r
- __IO uint16_t bIDEX : 3; /* Input divider expansion */\r
- __I uint16_t bRESERVED0 : 13; /* Reserved */\r
- } b;\r
- } rEX0;\r
- uint8_t RESERVED0[12];\r
- __I uint16_t rIV; /* TimerAx Interrupt Vector Register */\r
-} TIMER_A3_Type;\r
-\r
-\r
-//*****************************************************************************\r
-// TLV Registers\r
-//*****************************************************************************\r
+ __IO uint16_t CTL; /**< TimerAx Control Register */\r
+ __IO uint16_t CCTL[7]; /**< Timer_A Capture/Compare Control Register */\r
+ __IO uint16_t R; /**< TimerA register */\r
+ __IO uint16_t CCR[7]; /**< Timer_A Capture/Compare Register */\r
+ __IO uint16_t EX0; /**< TimerAx Expansion 0 Register */\r
+ uint16_t RESERVED0[6];\r
+ __I uint16_t IV; /**< TimerAx Interrupt Vector Register */\r
+} Timer_A_Type;\r
+\r
+/*@}*/ /* end of group Timer_A */\r
+\r
+\r
+/******************************************************************************\r
+* TLV Registers\r
+******************************************************************************/\r
+/** @addtogroup TLV MSP432P401R (TLV)\r
+ @{\r
+*/\r
typedef struct {\r
- __IO uint32_t rTLV_CHECKSUM; /* TLV Checksum */\r
- __IO uint32_t rDEVICE_INFO_TAG; /* Device Info Tag */\r
- __IO uint32_t rDEVICE_INFO_LEN; /* Device Info Length */\r
- __IO uint32_t rDEVICE_ID; /* Device ID */\r
- __IO uint32_t rHWREV; /* HW Revision */\r
- __IO uint32_t rBCREV; /* Boot Code Revision */\r
- __IO uint32_t rROM_DRVLIB_REV; /* ROM Driver Library Revision */\r
- __IO uint32_t rDIE_REC_TAG; /* Die Record Tag */\r
- __IO uint32_t rDIE_REC_LEN; /* Die Record Length */\r
- __IO uint32_t rDIE_XPOS; /* Die X-Position */\r
- __IO uint32_t rDIE_YPOS; /* Die Y-Position */\r
- __IO uint32_t rWAFER_ID; /* Wafer ID */\r
- __IO uint32_t rLOT_ID; /* Lot ID */\r
- __IO uint32_t rRESERVED0; /* Reserved */\r
- __IO uint32_t rRESERVED1; /* Reserved */\r
- __IO uint32_t rRESERVED2; /* Reserved */\r
- __IO uint32_t rTEST_RESULTS; /* Test Results */\r
- __IO uint32_t rCS_CAL_TAG; /* Clock System Calibration Tag */\r
- __IO uint32_t rCS_CAL_LEN; /* Clock System Calibration Length */\r
- __IO uint32_t rDCOIR_FCAL_RSEL04; /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */\r
- __IO uint32_t rDCOIR_FCAL_RSEL5; /* DCO IR mode: Frequency calibration for DCORSEL 5 */\r
- __IO uint32_t rDCOIR_MAXPOSTUNE_RSEL04; /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */\r
- __IO uint32_t rDCOIR_MAXNEGTUNE_RSEL04; /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */\r
- __IO uint32_t rDCOIR_MAXPOSTUNE_RSEL5; /* DCO IR mode: Max Positive Tune for DCORSEL 5 */\r
- __IO uint32_t rDCOIR_MAXNEGTUNE_RSEL5; /* DCO IR mode: Max Negative Tune for DCORSEL 5 */\r
- __IO uint32_t rDCOIR_CONSTK_RSEL04; /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */\r
- __IO uint32_t rDCOIR_CONSTK_RSEL5; /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */\r
- __IO uint32_t rDCOER_FCAL_RSEL04; /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */\r
- __IO uint32_t rDCOER_FCAL_RSEL5; /* DCO ER mode: Frequency calibration for DCORSEL 5 */\r
- __IO uint32_t rDCOER_MAXPOSTUNE_RSEL04; /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */\r
- __IO uint32_t rDCOER_MAXNEGTUNE_RSEL04; /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */\r
- __IO uint32_t rDCOER_MAXPOSTUNE_RSEL5; /* DCO ER mode: Max Positive Tune for DCORSEL 5 */\r
- __IO uint32_t rDCOER_MAXNEGTUNE_RSEL5; /* DCO ER mode: Max Negative Tune for DCORSEL 5 */\r
- __IO uint32_t rDCOER_CONSTK_RSEL04; /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */\r
- __IO uint32_t rDCOER_CONSTK_RSEL5; /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */\r
- __IO uint32_t rADC14_CAL_TAG; /* ADC14 Calibration Tag */\r
- __IO uint32_t rADC14_CAL_LEN; /* ADC14 Calibration Length */\r
- __IO uint32_t rADC14_GF_EXTREF30C; /* ADC14 Gain Factor for External Reference 30°C */\r
- __IO uint32_t rADC14_GF_EXTREF85C; /* ADC14 Gain Factor for External Reference 85°C */\r
- __IO uint32_t rADC14_GF_BUF_EXTREF30C; /* ADC14 Gain Factor for Buffered External Reference 30°C */\r
- __IO uint32_t rADC14_GF_BUF_EXTREF85C; /* ADC14 Gain Factor for Buffered External Reference 85°C */\r
- __IO uint32_t rADC14_GF_BUF1P2V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */\r
- __IO uint32_t rADC14_GF_BUF1P2V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */\r
- __IO uint32_t rADC14_GF_BUF1P2V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */\r
- __IO uint32_t rADC14_GF_BUF1P2V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */\r
- __IO uint32_t rADC14_GF_BUF1P45V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */\r
- __IO uint32_t rADC14_GF_BUF1P45V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */\r
- __IO uint32_t rADC14_GF_BUF1P45V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */\r
- __IO uint32_t rADC14_GF_BUF1P45V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */\r
- __IO uint32_t rADC14_GF_BUF2P5V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */\r
- __IO uint32_t rADC14_GF_BUF2P5V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */\r
- __IO uint32_t rADC14_GF_BUF2P5V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */\r
- __IO uint32_t rADC14_GF_BUF2P5V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */\r
- __IO uint32_t rADC14_OFFSET_VRSEL_1; /* ADC14 Offset (ADC14VRSEL = 1h) */\r
- __IO uint32_t rADC14_OFFSET_VRSEL_E; /* ADC14 Offset (ADC14VRSEL = Eh) */\r
- __IO uint32_t rADC14_REF1P2V_TS30C; /* ADC14 1.2V Reference Temp. Sensor 30°C */\r
- __IO uint32_t rADC14_REF1P2V_TS85C; /* ADC14 1.2V Reference Temp. Sensor 85°C */\r
- __IO uint32_t rADC14_REF1P45V_TS30C; /* ADC14 1.45V Reference Temp. Sensor 30°C */\r
- __IO uint32_t rADC14_REF1P45V_TS85C; /* ADC14 1.45V Reference Temp. Sensor 85°C */\r
- __IO uint32_t rADC14_REF2P5V_TS30C; /* ADC14 2.5V Reference Temp. Sensor 30°C */\r
- __IO uint32_t rADC14_REF2P5V_TS85C; /* ADC14 2.5V Reference Temp. Sensor 85°C */\r
- __IO uint32_t rREF_CAL_TAG; /* REF Calibration Tag */\r
- __IO uint32_t rREF_CAL_LEN; /* REF Calibration Length */\r
- __IO uint32_t rREF_1P2V; /* REF 1.2V Reference */\r
- __IO uint32_t rREF_1P45V; /* REF 1.45V Reference */\r
- __IO uint32_t rREF_2P5V; /* REF 2.5V Reference */\r
- __IO uint32_t rRANDOM_NUM_TAG; /* 128-bit Random Number Tag */\r
- __IO uint32_t rRANDOM_NUM_LEN; /* 128-bit Random Number Length */\r
- __IO uint32_t rRANDOM_NUM_1; /* 32-bit Random Number 1 */\r
- __IO uint32_t rRANDOM_NUM_2; /* 32-bit Random Number 2 */\r
- __IO uint32_t rRANDOM_NUM_3; /* 32-bit Random Number 3 */\r
- __IO uint32_t rRANDOM_NUM_4; /* 32-bit Random Number 4 */\r
- __IO uint32_t rBSL_CFG_TAG; /* BSL Configuration Tag */\r
- __IO uint32_t rBSL_CFG_LEN; /* BSL Configuration Length */\r
- __IO uint32_t rBSL_PERIPHIF_SEL; /* BSL Peripheral Interface Selection */\r
- __IO uint32_t rBSL_PORTIF_CFG_UART; /* BSL Port Interface Configuration for UART */\r
- __IO uint32_t rBSL_PORTIF_CFG_SPI; /* BSL Port Interface Configuration for SPI */\r
- __IO uint32_t rBSL_PORTIF_CFG_I2C; /* BSL Port Interface Configuration for I2C */\r
- __IO uint32_t rTLV_END; /* TLV End Word */\r
+ __I uint32_t TLV_CHECKSUM; /**< TLV Checksum */\r
+ __I uint32_t DEVICE_INFO_TAG; /**< Device Info Tag */\r
+ __I uint32_t DEVICE_INFO_LEN; /**< Device Info Length */\r
+ __I uint32_t DEVICE_ID; /**< Device ID */\r
+ __I uint32_t HWREV; /**< HW Revision */\r
+ __I uint32_t BCREV; /**< Boot Code Revision */\r
+ __I uint32_t ROM_DRVLIB_REV; /**< ROM Driver Library Revision */\r
+ __I uint32_t DIE_REC_TAG; /**< Die Record Tag */\r
+ __I uint32_t DIE_REC_LEN; /**< Die Record Length */\r
+ __I uint32_t DIE_XPOS; /**< Die X-Position */\r
+ __I uint32_t DIE_YPOS; /**< Die Y-Position */\r
+ __I uint32_t WAFER_ID; /**< Wafer ID */\r
+ __I uint32_t LOT_ID; /**< Lot ID */\r
+ __I uint32_t RESERVED0; /**< Reserved */\r
+ __I uint32_t RESERVED1; /**< Reserved */\r
+ __I uint32_t RESERVED2; /**< Reserved */\r
+ __I uint32_t TEST_RESULTS; /**< Test Results */\r
+ __I uint32_t CS_CAL_TAG; /**< Clock System Calibration Tag */\r
+ __I uint32_t CS_CAL_LEN; /**< Clock System Calibration Length */\r
+ __I uint32_t DCOIR_FCAL_RSEL04; /**< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */\r
+ __I uint32_t DCOIR_FCAL_RSEL5; /**< DCO IR mode: Frequency calibration for DCORSEL 5 */\r
+ __I uint32_t DCOIR_MAXPOSTUNE_RSEL04; /**< DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */\r
+ __I uint32_t DCOIR_MAXNEGTUNE_RSEL04; /**< DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */\r
+ __I uint32_t DCOIR_MAXPOSTUNE_RSEL5; /**< DCO IR mode: Max Positive Tune for DCORSEL 5 */\r
+ __I uint32_t DCOIR_MAXNEGTUNE_RSEL5; /**< DCO IR mode: Max Negative Tune for DCORSEL 5 */\r
+ __I uint32_t DCOIR_CONSTK_RSEL04; /**< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */\r
+ __I uint32_t DCOIR_CONSTK_RSEL5; /**< DCO IR mode: DCO Constant (K) for DCORSEL 5 */\r
+ __I uint32_t DCOER_FCAL_RSEL04; /**< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */\r
+ __I uint32_t DCOER_FCAL_RSEL5; /**< DCO ER mode: Frequency calibration for DCORSEL 5 */\r
+ __I uint32_t DCOER_MAXPOSTUNE_RSEL04; /**< DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */\r
+ __I uint32_t DCOER_MAXNEGTUNE_RSEL04; /**< DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */\r
+ __I uint32_t DCOER_MAXPOSTUNE_RSEL5; /**< DCO ER mode: Max Positive Tune for DCORSEL 5 */\r
+ __I uint32_t DCOER_MAXNEGTUNE_RSEL5; /**< DCO ER mode: Max Negative Tune for DCORSEL 5 */\r
+ __I uint32_t DCOER_CONSTK_RSEL04; /**< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */\r
+ __I uint32_t DCOER_CONSTK_RSEL5; /**< DCO ER mode: DCO Constant (K) for DCORSEL 5 */\r
+ __I uint32_t ADC14_CAL_TAG; /**< ADC14 Calibration Tag */\r
+ __I uint32_t ADC14_CAL_LEN; /**< ADC14 Calibration Length */\r
+ __I uint32_t ADC14_GF_EXTREF30C; /**< ADC14 Gain Factor for External Reference 30°C */\r
+ __I uint32_t ADC14_GF_EXTREF85C; /**< ADC14 Gain Factor for External Reference 85°C */\r
+ __I uint32_t ADC14_GF_BUF_EXTREF30C; /**< ADC14 Gain Factor for Buffered External Reference 30°C */\r
+ __I uint32_t ADC14_GF_BUF_EXTREF85C; /**< ADC14 Gain Factor for Buffered External Reference 85°C */\r
+ __I uint32_t ADC14_GF_BUF1P2V_INTREF30C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */\r
+ __I uint32_t ADC14_GF_BUF1P2V_INTREF85C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */\r
+ __I uint32_t ADC14_GF_BUF1P2V_INTREF30C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */\r
+ __I uint32_t ADC14_GF_BUF1P2V_INTREF85C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */\r
+ __I uint32_t ADC14_GF_BUF1P45V_INTREF30C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */\r
+ __I uint32_t ADC14_GF_BUF1P45V_INTREF85C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */\r
+ __I uint32_t ADC14_GF_BUF1P45V_INTREF30C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */\r
+ __I uint32_t ADC14_GF_BUF1P45V_INTREF85C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */\r
+ __I uint32_t ADC14_GF_BUF2P5V_INTREF30C_REFOUT0; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */\r
+ __I uint32_t ADC14_GF_BUF2P5V_INTREF85C_REFOUT0; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */\r
+ __I uint32_t ADC14_GF_BUF2P5V_INTREF30C_REFOUT1; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */\r
+ __I uint32_t ADC14_GF_BUF2P5V_INTREF85C_REFOUT1; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */\r
+ __I uint32_t ADC14_OFFSET_VRSEL_1; /**< ADC14 Offset (ADC14VRSEL = 1h) */\r
+ __I uint32_t ADC14_OFFSET_VRSEL_E; /**< ADC14 Offset (ADC14VRSEL = Eh) */\r
+ __I uint32_t ADC14_REF1P2V_TS30C; /**< ADC14 1.2V Reference Temp. Sensor 30°C */\r
+ __I uint32_t ADC14_REF1P2V_TS85C; /**< ADC14 1.2V Reference Temp. Sensor 85°C */\r
+ __I uint32_t ADC14_REF1P45V_TS30C; /**< ADC14 1.45V Reference Temp. Sensor 30°C */\r
+ __I uint32_t ADC14_REF1P45V_TS85C; /**< ADC14 1.45V Reference Temp. Sensor 85°C */\r
+ __I uint32_t ADC14_REF2P5V_TS30C; /**< ADC14 2.5V Reference Temp. Sensor 30°C */\r
+ __I uint32_t ADC14_REF2P5V_TS85C; /**< ADC14 2.5V Reference Temp. Sensor 85°C */\r
+ __I uint32_t REF_CAL_TAG; /**< REF Calibration Tag */\r
+ __I uint32_t REF_CAL_LEN; /**< REF Calibration Length */\r
+ __I uint32_t REF_1P2V; /**< REF 1.2V Reference */\r
+ __I uint32_t REF_1P45V; /**< REF 1.45V Reference */\r
+ __I uint32_t REF_2P5V; /**< REF 2.5V Reference */\r
+ __I uint32_t FLASH_INFO_TAG; /**< Flash Info Tag */\r
+ __I uint32_t FLASH_INFO_LEN; /**< Flash Info Length */\r
+ __I uint32_t FLASH_MAX_PROG_PULSES; /**< Flash Maximum Programming Pulses */\r
+ __I uint32_t FLASH_MAX_ERASE_PULSES; /**< Flash Maximum Erase Pulses */\r
+ __I uint32_t RANDOM_NUM_TAG; /**< 128-bit Random Number Tag */\r
+ __I uint32_t RANDOM_NUM_LEN; /**< 128-bit Random Number Length */\r
+ __I uint32_t RANDOM_NUM_1; /**< 32-bit Random Number 1 */\r
+ __I uint32_t RANDOM_NUM_2; /**< 32-bit Random Number 2 */\r
+ __I uint32_t RANDOM_NUM_3; /**< 32-bit Random Number 3 */\r
+ __I uint32_t RANDOM_NUM_4; /**< 32-bit Random Number 4 */\r
+ __I uint32_t BSL_CFG_TAG; /**< BSL Configuration Tag */\r
+ __I uint32_t BSL_CFG_LEN; /**< BSL Configuration Length */\r
+ __I uint32_t BSL_PERIPHIF_SEL; /**< BSL Peripheral Interface Selection */\r
+ __I uint32_t BSL_PORTIF_CFG_UART; /**< BSL Port Interface Configuration for UART */\r
+ __I uint32_t BSL_PORTIF_CFG_SPI; /**< BSL Port Interface Configuration for SPI */\r
+ __I uint32_t BSL_PORTIF_CFG_I2C; /**< BSL Port Interface Configuration for I2C */\r
+ __I uint32_t TLV_END; /**< TLV End Word */\r
} TLV_Type;\r
\r
+/*@}*/ /* end of group TLV */\r
\r
-//*****************************************************************************\r
-// WDT_A Registers\r
-//*****************************************************************************\r
+\r
+/******************************************************************************\r
+* WDT_A Registers\r
+******************************************************************************/\r
+/** @addtogroup WDT_A MSP432P401R (WDT_A)\r
+ @{\r
+*/\r
typedef struct {\r
- uint8_t RESERVED0[12];\r
- union { /* WDTCTL Register */\r
- __IO uint16_t r;\r
- struct { /* WDTCTL Bits */\r
- __IO uint16_t bIS : 3; /* Watchdog timer interval select */\r
- __O uint16_t bCNTCL : 1; /* Watchdog timer counter clear */\r
- __IO uint16_t bTMSEL : 1; /* Watchdog timer mode select */\r
- __IO uint16_t bSSEL : 2; /* Watchdog timer clock source select */\r
- __IO uint16_t bHOLD : 1; /* Watchdog timer hold */\r
- __IO uint16_t bPW : 8; /* Watchdog timer password */\r
- } b;\r
- } rCTL;\r
+ uint16_t RESERVED0[6];\r
+ __IO uint16_t CTL; /**< Watchdog Timer Control Register */\r
} WDT_A_Type;\r
\r
-\r
-//*****************************************************************************\r
-// Peripheral register control bits\r
-//*****************************************************************************\r
-\r
-//*****************************************************************************\r
-// ADC14 Bits\r
-//*****************************************************************************\r
-/* ADC14CTL0[ADC14SC] Bits */\r
-#define ADC14SC_OFS ( 0) /* ADC14SC Offset */\r
-#define ADC14SC (0x00000001) /* ADC14 start conversion */\r
-/* ADC14CTL0[ADC14ENC] Bits */\r
-#define ADC14ENC_OFS ( 1) /* ADC14ENC Offset */\r
-#define ADC14ENC (0x00000002) /* ADC14 enable conversion */\r
-/* ADC14CTL0[ADC14ON] Bits */\r
-#define ADC14ON_OFS ( 4) /* ADC14ON Offset */\r
-#define ADC14ON (0x00000010) /* ADC14 on */\r
-/* ADC14CTL0[ADC14MSC] Bits */\r
-#define ADC14MSC_OFS ( 7) /* ADC14MSC Offset */\r
-#define ADC14MSC (0x00000080) /* ADC14 multiple sample and conversion */\r
-/* ADC14CTL0[ADC14SHT0] Bits */\r
-#define ADC14SHT0_OFS ( 8) /* ADC14SHT0 Offset */\r
-#define ADC14SHT0_M (0x00000f00) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT00 (0x00000100) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT01 (0x00000200) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT02 (0x00000400) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT03 (0x00000800) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT0_0 (0x00000000) /* 4 */\r
-#define ADC14SHT0_1 (0x00000100) /* 8 */\r
-#define ADC14SHT0_2 (0x00000200) /* 16 */\r
-#define ADC14SHT0_3 (0x00000300) /* 32 */\r
-#define ADC14SHT0_4 (0x00000400) /* 64 */\r
-#define ADC14SHT0_5 (0x00000500) /* 96 */\r
-#define ADC14SHT0_6 (0x00000600) /* 128 */\r
-#define ADC14SHT0_7 (0x00000700) /* 192 */\r
-#define ADC14SHT0__4 (0x00000000) /* 4 */\r
-#define ADC14SHT0__8 (0x00000100) /* 8 */\r
-#define ADC14SHT0__16 (0x00000200) /* 16 */\r
-#define ADC14SHT0__32 (0x00000300) /* 32 */\r
-#define ADC14SHT0__64 (0x00000400) /* 64 */\r
-#define ADC14SHT0__96 (0x00000500) /* 96 */\r
-#define ADC14SHT0__128 (0x00000600) /* 128 */\r
-#define ADC14SHT0__192 (0x00000700) /* 192 */\r
-/* ADC14CTL0[ADC14SHT1] Bits */\r
-#define ADC14SHT1_OFS (12) /* ADC14SHT1 Offset */\r
-#define ADC14SHT1_M (0x0000f000) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT10 (0x00001000) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT11 (0x00002000) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT12 (0x00004000) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT13 (0x00008000) /* ADC14 sample-and-hold time */\r
-#define ADC14SHT1_0 (0x00000000) /* 4 */\r
-#define ADC14SHT1_1 (0x00001000) /* 8 */\r
-#define ADC14SHT1_2 (0x00002000) /* 16 */\r
-#define ADC14SHT1_3 (0x00003000) /* 32 */\r
-#define ADC14SHT1_4 (0x00004000) /* 64 */\r
-#define ADC14SHT1_5 (0x00005000) /* 96 */\r
-#define ADC14SHT1_6 (0x00006000) /* 128 */\r
-#define ADC14SHT1_7 (0x00007000) /* 192 */\r
-#define ADC14SHT1__4 (0x00000000) /* 4 */\r
-#define ADC14SHT1__8 (0x00001000) /* 8 */\r
-#define ADC14SHT1__16 (0x00002000) /* 16 */\r
-#define ADC14SHT1__32 (0x00003000) /* 32 */\r
-#define ADC14SHT1__64 (0x00004000) /* 64 */\r
-#define ADC14SHT1__96 (0x00005000) /* 96 */\r
-#define ADC14SHT1__128 (0x00006000) /* 128 */\r
-#define ADC14SHT1__192 (0x00007000) /* 192 */\r
-/* ADC14CTL0[ADC14BUSY] Bits */\r
-#define ADC14BUSY_OFS (16) /* ADC14BUSY Offset */\r
-#define ADC14BUSY (0x00010000) /* ADC14 busy */\r
-/* ADC14CTL0[ADC14CONSEQ] Bits */\r
-#define ADC14CONSEQ_OFS (17) /* ADC14CONSEQ Offset */\r
-#define ADC14CONSEQ_M (0x00060000) /* ADC14 conversion sequence mode select */\r
-#define ADC14CONSEQ0 (0x00020000) /* ADC14 conversion sequence mode select */\r
-#define ADC14CONSEQ1 (0x00040000) /* ADC14 conversion sequence mode select */\r
-#define ADC14CONSEQ_0 (0x00000000) /* Single-channel, single-conversion */\r
-#define ADC14CONSEQ_1 (0x00020000) /* Sequence-of-channels */\r
-#define ADC14CONSEQ_2 (0x00040000) /* Repeat-single-channel */\r
-#define ADC14CONSEQ_3 (0x00060000) /* Repeat-sequence-of-channels */\r
-/* ADC14CTL0[ADC14SSEL] Bits */\r
-#define ADC14SSEL_OFS (19) /* ADC14SSEL Offset */\r
-#define ADC14SSEL_M (0x00380000) /* ADC14 clock source select */\r
-#define ADC14SSEL0 (0x00080000) /* ADC14 clock source select */\r
-#define ADC14SSEL1 (0x00100000) /* ADC14 clock source select */\r
-#define ADC14SSEL2 (0x00200000) /* ADC14 clock source select */\r
-#define ADC14SSEL_0 (0x00000000) /* MODCLK */\r
-#define ADC14SSEL_1 (0x00080000) /* SYSCLK */\r
-#define ADC14SSEL_2 (0x00100000) /* ACLK */\r
-#define ADC14SSEL_3 (0x00180000) /* MCLK */\r
-#define ADC14SSEL_4 (0x00200000) /* SMCLK */\r
-#define ADC14SSEL_5 (0x00280000) /* HSMCLK */\r
-#define ADC14SSEL__MODCLK (0x00000000) /* MODCLK */\r
-#define ADC14SSEL__SYSCLK (0x00080000) /* SYSCLK */\r
-#define ADC14SSEL__ACLK (0x00100000) /* ACLK */\r
-#define ADC14SSEL__MCLK (0x00180000) /* MCLK */\r
-#define ADC14SSEL__SMCLK (0x00200000) /* SMCLK */\r
-#define ADC14SSEL__HSMCLK (0x00280000) /* HSMCLK */\r
-/* ADC14CTL0[ADC14DIV] Bits */\r
-#define ADC14DIV_OFS (22) /* ADC14DIV Offset */\r
-#define ADC14DIV_M (0x01c00000) /* ADC14 clock divider */\r
-#define ADC14DIV0 (0x00400000) /* ADC14 clock divider */\r
-#define ADC14DIV1 (0x00800000) /* ADC14 clock divider */\r
-#define ADC14DIV2 (0x01000000) /* ADC14 clock divider */\r
-#define ADC14DIV_0 (0x00000000) /* /1 */\r
-#define ADC14DIV_1 (0x00400000) /* /2 */\r
-#define ADC14DIV_2 (0x00800000) /* /3 */\r
-#define ADC14DIV_3 (0x00c00000) /* /4 */\r
-#define ADC14DIV_4 (0x01000000) /* /5 */\r
-#define ADC14DIV_5 (0x01400000) /* /6 */\r
-#define ADC14DIV_6 (0x01800000) /* /7 */\r
-#define ADC14DIV_7 (0x01c00000) /* /8 */\r
-#define ADC14DIV__1 (0x00000000) /* /1 */\r
-#define ADC14DIV__2 (0x00400000) /* /2 */\r
-#define ADC14DIV__3 (0x00800000) /* /3 */\r
-#define ADC14DIV__4 (0x00c00000) /* /4 */\r
-#define ADC14DIV__5 (0x01000000) /* /5 */\r
-#define ADC14DIV__6 (0x01400000) /* /6 */\r
-#define ADC14DIV__7 (0x01800000) /* /7 */\r
-#define ADC14DIV__8 (0x01c00000) /* /8 */\r
-/* ADC14CTL0[ADC14ISSH] Bits */\r
-#define ADC14ISSH_OFS (25) /* ADC14ISSH Offset */\r
-#define ADC14ISSH (0x02000000) /* ADC14 invert signal sample-and-hold */\r
-/* ADC14CTL0[ADC14SHP] Bits */\r
-#define ADC14SHP_OFS (26) /* ADC14SHP Offset */\r
-#define ADC14SHP (0x04000000) /* ADC14 sample-and-hold pulse-mode select */\r
-/* ADC14CTL0[ADC14SHS] Bits */\r
-#define ADC14SHS_OFS (27) /* ADC14SHS Offset */\r
-#define ADC14SHS_M (0x38000000) /* ADC14 sample-and-hold source select */\r
-#define ADC14SHS0 (0x08000000) /* ADC14 sample-and-hold source select */\r
-#define ADC14SHS1 (0x10000000) /* ADC14 sample-and-hold source select */\r
-#define ADC14SHS2 (0x20000000) /* ADC14 sample-and-hold source select */\r
-#define ADC14SHS_0 (0x00000000) /* ADC14SC bit */\r
-#define ADC14SHS_1 (0x08000000) /* See device-specific data sheet for source */\r
-#define ADC14SHS_2 (0x10000000) /* See device-specific data sheet for source */\r
-#define ADC14SHS_3 (0x18000000) /* See device-specific data sheet for source */\r
-#define ADC14SHS_4 (0x20000000) /* See device-specific data sheet for source */\r
-#define ADC14SHS_5 (0x28000000) /* See device-specific data sheet for source */\r
-#define ADC14SHS_6 (0x30000000) /* See device-specific data sheet for source */\r
-#define ADC14SHS_7 (0x38000000) /* See device-specific data sheet for source */\r
-/* ADC14CTL0[ADC14PDIV] Bits */\r
-#define ADC14PDIV_OFS (30) /* ADC14PDIV Offset */\r
-#define ADC14PDIV_M (0xc0000000) /* ADC14 predivider */\r
-#define ADC14PDIV0 (0x40000000) /* ADC14 predivider */\r
-#define ADC14PDIV1 (0x80000000) /* ADC14 predivider */\r
-#define ADC14PDIV_0 (0x00000000) /* Predivide by 1 */\r
-#define ADC14PDIV_1 (0x40000000) /* Predivide by 4 */\r
-#define ADC14PDIV_2 (0x80000000) /* Predivide by 32 */\r
-#define ADC14PDIV_3 (0xc0000000) /* Predivide by 64 */\r
-#define ADC14PDIV__1 (0x00000000) /* Predivide by 1 */\r
-#define ADC14PDIV__4 (0x40000000) /* Predivide by 4 */\r
-#define ADC14PDIV__32 (0x80000000) /* Predivide by 32 */\r
-#define ADC14PDIV__64 (0xc0000000) /* Predivide by 64 */\r
-/* ADC14CTL1[ADC14PWRMD] Bits */\r
-#define ADC14PWRMD_OFS ( 0) /* ADC14PWRMD Offset */\r
-#define ADC14PWRMD_M (0x00000003) /* ADC14 power modes */\r
-#define ADC14PWRMD0 (0x00000001) /* ADC14 power modes */\r
-#define ADC14PWRMD1 (0x00000002) /* ADC14 power modes */\r
-#define ADC14PWRMD_0 (0x00000000) /* Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps. */\r
-#define ADC14PWRMD_2 (0x00000002) /* Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps. */\r
-/* ADC14CTL1[ADC14REFBURST] Bits */\r
-#define ADC14REFBURST_OFS ( 2) /* ADC14REFBURST Offset */\r
-#define ADC14REFBURST (0x00000004) /* ADC14 reference buffer burst */\r
-/* ADC14CTL1[ADC14DF] Bits */\r
-#define ADC14DF_OFS ( 3) /* ADC14DF Offset */\r
-#define ADC14DF (0x00000008) /* ADC14 data read-back format */\r
-/* ADC14CTL1[ADC14RES] Bits */\r
-#define ADC14RES_OFS ( 4) /* ADC14RES Offset */\r
-#define ADC14RES_M (0x00000030) /* ADC14 resolution */\r
-#define ADC14RES0 (0x00000010) /* ADC14 resolution */\r
-#define ADC14RES1 (0x00000020) /* ADC14 resolution */\r
-#define ADC14RES_0 (0x00000000) /* 8 bit (9 clock cycle conversion time) */\r
-#define ADC14RES_1 (0x00000010) /* 10 bit (11 clock cycle conversion time) */\r
-#define ADC14RES_2 (0x00000020) /* 12 bit (14 clock cycle conversion time) */\r
-#define ADC14RES_3 (0x00000030) /* 14 bit (16 clock cycle conversion time) */\r
-#define ADC14RES__8BIT (0x00000000) /* 8 bit (9 clock cycle conversion time) */\r
-#define ADC14RES__10BIT (0x00000010) /* 10 bit (11 clock cycle conversion time) */\r
-#define ADC14RES__12BIT (0x00000020) /* 12 bit (14 clock cycle conversion time) */\r
-#define ADC14RES__14BIT (0x00000030) /* 14 bit (16 clock cycle conversion time) */\r
-/* ADC14CTL1[ADC14CSTARTADD] Bits */\r
-#define ADC14CSTARTADD_OFS (16) /* ADC14CSTARTADD Offset */\r
-#define ADC14CSTARTADD_M (0x001f0000) /* ADC14 conversion start address */\r
-/* ADC14CTL1[ADC14BATMAP] Bits */\r
-#define ADC14BATMAP_OFS (22) /* ADC14BATMAP Offset */\r
-#define ADC14BATMAP (0x00400000) /* Controls 1/2 AVCC ADC input channel selection */\r
-/* ADC14CTL1[ADC14TCMAP] Bits */\r
-#define ADC14TCMAP_OFS (23) /* ADC14TCMAP Offset */\r
-#define ADC14TCMAP (0x00800000) /* Controls temperature sensor ADC input channel selection */\r
-/* ADC14CTL1[ADC14CH0MAP] Bits */\r
-#define ADC14CH0MAP_OFS (24) /* ADC14CH0MAP Offset */\r
-#define ADC14CH0MAP (0x01000000) /* Controls internal channel 0 selection to ADC input channel MAX-2 */\r
-/* ADC14CTL1[ADC14CH1MAP] Bits */\r
-#define ADC14CH1MAP_OFS (25) /* ADC14CH1MAP Offset */\r
-#define ADC14CH1MAP (0x02000000) /* Controls internal channel 1 selection to ADC input channel MAX-3 */\r
-/* ADC14CTL1[ADC14CH2MAP] Bits */\r
-#define ADC14CH2MAP_OFS (26) /* ADC14CH2MAP Offset */\r
-#define ADC14CH2MAP (0x04000000) /* Controls internal channel 2 selection to ADC input channel MAX-4 */\r
-/* ADC14CTL1[ADC14CH3MAP] Bits */\r
-#define ADC14CH3MAP_OFS (27) /* ADC14CH3MAP Offset */\r
-#define ADC14CH3MAP (0x08000000) /* Controls internal channel 3 selection to ADC input channel MAX-5 */\r
-/* ADC14LO0[ADC14LO0] Bits */\r
-#define ADC14LO0_OFS ( 0) /* ADC14LO0 Offset */\r
-#define ADC14LO0_M (0x0000ffff) /* Low threshold 0 */\r
-/* ADC14HI0[ADC14HI0] Bits */\r
-#define ADC14HI0_OFS ( 0) /* ADC14HI0 Offset */\r
-#define ADC14HI0_M (0x0000ffff) /* High threshold 0 */\r
-/* ADC14LO1[ADC14LO1] Bits */\r
-#define ADC14LO1_OFS ( 0) /* ADC14LO1 Offset */\r
-#define ADC14LO1_M (0x0000ffff) /* Low threshold 1 */\r
-/* ADC14HI1[ADC14HI1] Bits */\r
-#define ADC14HI1_OFS ( 0) /* ADC14HI1 Offset */\r
-#define ADC14HI1_M (0x0000ffff) /* High threshold 1 */\r
-/* ADC14MCTL[ADC14INCH] Bits */\r
-#define ADC14INCH_OFS ( 0) /* ADC14INCH Offset */\r
-#define ADC14INCH_M (0x0000001f) /* Input channel select */\r
-#define ADC14INCH0 (0x00000001) /* Input channel select */\r
-#define ADC14INCH1 (0x00000002) /* Input channel select */\r
-#define ADC14INCH2 (0x00000004) /* Input channel select */\r
-#define ADC14INCH3 (0x00000008) /* Input channel select */\r
-#define ADC14INCH4 (0x00000010) /* Input channel select */\r
-#define ADC14INCH_0 (0x00000000) /* If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */\r
-#define ADC14INCH_1 (0x00000001) /* If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */\r
-#define ADC14INCH_2 (0x00000002) /* If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */\r
-#define ADC14INCH_3 (0x00000003) /* If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */\r
-#define ADC14INCH_4 (0x00000004) /* If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */\r
-#define ADC14INCH_5 (0x00000005) /* If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */\r
-#define ADC14INCH_6 (0x00000006) /* If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */\r
-#define ADC14INCH_7 (0x00000007) /* If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */\r
-#define ADC14INCH_8 (0x00000008) /* If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */\r
-#define ADC14INCH_9 (0x00000009) /* If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */\r
-#define ADC14INCH_10 (0x0000000a) /* If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */\r
-#define ADC14INCH_11 (0x0000000b) /* If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */\r
-#define ADC14INCH_12 (0x0000000c) /* If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */\r
-#define ADC14INCH_13 (0x0000000d) /* If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */\r
-#define ADC14INCH_14 (0x0000000e) /* If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */\r
-#define ADC14INCH_15 (0x0000000f) /* If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */\r
-#define ADC14INCH_16 (0x00000010) /* If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */\r
-#define ADC14INCH_17 (0x00000011) /* If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */\r
-#define ADC14INCH_18 (0x00000012) /* If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */\r
-#define ADC14INCH_19 (0x00000013) /* If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */\r
-#define ADC14INCH_20 (0x00000014) /* If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */\r
-#define ADC14INCH_21 (0x00000015) /* If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */\r
-#define ADC14INCH_22 (0x00000016) /* If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */\r
-#define ADC14INCH_23 (0x00000017) /* If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */\r
-#define ADC14INCH_24 (0x00000018) /* If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */\r
-#define ADC14INCH_25 (0x00000019) /* If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */\r
-#define ADC14INCH_26 (0x0000001a) /* If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */\r
-#define ADC14INCH_27 (0x0000001b) /* If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */\r
-#define ADC14INCH_28 (0x0000001c) /* If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */\r
-#define ADC14INCH_29 (0x0000001d) /* If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */\r
-#define ADC14INCH_30 (0x0000001e) /* If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */\r
-#define ADC14INCH_31 (0x0000001f) /* If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */\r
-/* ADC14MCTL[ADC14EOS] Bits */\r
-#define ADC14EOS_OFS ( 7) /* ADC14EOS Offset */\r
-#define ADC14EOS (0x00000080) /* End of sequence */\r
-/* ADC14MCTL[ADC14VRSEL] Bits */\r
-#define ADC14VRSEL_OFS ( 8) /* ADC14VRSEL Offset */\r
-#define ADC14VRSEL_M (0x00000f00) /* Selects combinations of V(R+) and V(R-) sources */\r
-#define ADC14VRSEL0 (0x00000100) /* Selects combinations of V(R+) and V(R-) sources */\r
-#define ADC14VRSEL1 (0x00000200) /* Selects combinations of V(R+) and V(R-) sources */\r
-#define ADC14VRSEL2 (0x00000400) /* Selects combinations of V(R+) and V(R-) sources */\r
-#define ADC14VRSEL3 (0x00000800) /* Selects combinations of V(R+) and V(R-) sources */\r
-#define ADC14VRSEL_0 (0x00000000) /* V(R+) = AVCC, V(R-) = AVSS */\r
-#define ADC14VRSEL_1 (0x00000100) /* V(R+) = VREF buffered, V(R-) = AVSS */\r
-#define ADC14VRSEL_14 (0x00000e00) /* V(R+) = VeREF+, V(R-) = VeREF- */\r
-#define ADC14VRSEL_15 (0x00000f00) /* V(R+) = VeREF+ buffered, V(R-) = VeREF */\r
-/* ADC14MCTL[ADC14DIF] Bits */\r
-#define ADC14DIF_OFS (13) /* ADC14DIF Offset */\r
-#define ADC14DIF (0x00002000) /* Differential mode */\r
-/* ADC14MCTL[ADC14WINC] Bits */\r
-#define ADC14WINC_OFS (14) /* ADC14WINC Offset */\r
-#define ADC14WINC (0x00004000) /* Comparator window enable */\r
-/* ADC14MCTL[ADC14WINCTH] Bits */\r
-#define ADC14WINCTH_OFS (15) /* ADC14WINCTH Offset */\r
-#define ADC14WINCTH (0x00008000) /* Window comparator threshold register selection */\r
-/* ADC14MEM[CONVERSION_RESULTS] Bits */\r
-#define CONVERSION_RESULTS_OFS ( 0) /* Conversion_Results Offset */\r
-#define CONVERSION_RESULTS_M (0x0000ffff) /* Conversion Result */\r
-/* ADC14IER0[ADC14IE0] Bits */\r
-#define ADC14IE0_OFS ( 0) /* ADC14IE0 Offset */\r
-#define ADC14IE0 (0x00000001) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE1] Bits */\r
-#define ADC14IE1_OFS ( 1) /* ADC14IE1 Offset */\r
-#define ADC14IE1 (0x00000002) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE2] Bits */\r
-#define ADC14IE2_OFS ( 2) /* ADC14IE2 Offset */\r
-#define ADC14IE2 (0x00000004) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE3] Bits */\r
-#define ADC14IE3_OFS ( 3) /* ADC14IE3 Offset */\r
-#define ADC14IE3 (0x00000008) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE4] Bits */\r
-#define ADC14IE4_OFS ( 4) /* ADC14IE4 Offset */\r
-#define ADC14IE4 (0x00000010) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE5] Bits */\r
-#define ADC14IE5_OFS ( 5) /* ADC14IE5 Offset */\r
-#define ADC14IE5 (0x00000020) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE6] Bits */\r
-#define ADC14IE6_OFS ( 6) /* ADC14IE6 Offset */\r
-#define ADC14IE6 (0x00000040) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE7] Bits */\r
-#define ADC14IE7_OFS ( 7) /* ADC14IE7 Offset */\r
-#define ADC14IE7 (0x00000080) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE8] Bits */\r
-#define ADC14IE8_OFS ( 8) /* ADC14IE8 Offset */\r
-#define ADC14IE8 (0x00000100) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE9] Bits */\r
-#define ADC14IE9_OFS ( 9) /* ADC14IE9 Offset */\r
-#define ADC14IE9 (0x00000200) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE10] Bits */\r
-#define ADC14IE10_OFS (10) /* ADC14IE10 Offset */\r
-#define ADC14IE10 (0x00000400) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE11] Bits */\r
-#define ADC14IE11_OFS (11) /* ADC14IE11 Offset */\r
-#define ADC14IE11 (0x00000800) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE12] Bits */\r
-#define ADC14IE12_OFS (12) /* ADC14IE12 Offset */\r
-#define ADC14IE12 (0x00001000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE13] Bits */\r
-#define ADC14IE13_OFS (13) /* ADC14IE13 Offset */\r
-#define ADC14IE13 (0x00002000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE14] Bits */\r
-#define ADC14IE14_OFS (14) /* ADC14IE14 Offset */\r
-#define ADC14IE14 (0x00004000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE15] Bits */\r
-#define ADC14IE15_OFS (15) /* ADC14IE15 Offset */\r
-#define ADC14IE15 (0x00008000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE16] Bits */\r
-#define ADC14IE16_OFS (16) /* ADC14IE16 Offset */\r
-#define ADC14IE16 (0x00010000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE17] Bits */\r
-#define ADC14IE17_OFS (17) /* ADC14IE17 Offset */\r
-#define ADC14IE17 (0x00020000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE19] Bits */\r
-#define ADC14IE19_OFS (19) /* ADC14IE19 Offset */\r
-#define ADC14IE19 (0x00080000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE18] Bits */\r
-#define ADC14IE18_OFS (18) /* ADC14IE18 Offset */\r
-#define ADC14IE18 (0x00040000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE20] Bits */\r
-#define ADC14IE20_OFS (20) /* ADC14IE20 Offset */\r
-#define ADC14IE20 (0x00100000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE21] Bits */\r
-#define ADC14IE21_OFS (21) /* ADC14IE21 Offset */\r
-#define ADC14IE21 (0x00200000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE22] Bits */\r
-#define ADC14IE22_OFS (22) /* ADC14IE22 Offset */\r
-#define ADC14IE22 (0x00400000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE23] Bits */\r
-#define ADC14IE23_OFS (23) /* ADC14IE23 Offset */\r
-#define ADC14IE23 (0x00800000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE24] Bits */\r
-#define ADC14IE24_OFS (24) /* ADC14IE24 Offset */\r
-#define ADC14IE24 (0x01000000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE25] Bits */\r
-#define ADC14IE25_OFS (25) /* ADC14IE25 Offset */\r
-#define ADC14IE25 (0x02000000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE26] Bits */\r
-#define ADC14IE26_OFS (26) /* ADC14IE26 Offset */\r
-#define ADC14IE26 (0x04000000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE27] Bits */\r
-#define ADC14IE27_OFS (27) /* ADC14IE27 Offset */\r
-#define ADC14IE27 (0x08000000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE28] Bits */\r
-#define ADC14IE28_OFS (28) /* ADC14IE28 Offset */\r
-#define ADC14IE28 (0x10000000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE29] Bits */\r
-#define ADC14IE29_OFS (29) /* ADC14IE29 Offset */\r
-#define ADC14IE29 (0x20000000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE30] Bits */\r
-#define ADC14IE30_OFS (30) /* ADC14IE30 Offset */\r
-#define ADC14IE30 (0x40000000) /* Interrupt enable */\r
-/* ADC14IER0[ADC14IE31] Bits */\r
-#define ADC14IE31_OFS (31) /* ADC14IE31 Offset */\r
-#define ADC14IE31 (0x80000000) /* Interrupt enable */\r
-/* ADC14IER1[ADC14INIE] Bits */\r
-#define ADC14INIE_OFS ( 1) /* ADC14INIE Offset */\r
-#define ADC14INIE (0x00000002) /* Interrupt enable for ADC14MEMx within comparator window */\r
-/* ADC14IER1[ADC14LOIE] Bits */\r
-#define ADC14LOIE_OFS ( 2) /* ADC14LOIE Offset */\r
-#define ADC14LOIE (0x00000004) /* Interrupt enable for ADC14MEMx below comparator window */\r
-/* ADC14IER1[ADC14HIIE] Bits */\r
-#define ADC14HIIE_OFS ( 3) /* ADC14HIIE Offset */\r
-#define ADC14HIIE (0x00000008) /* Interrupt enable for ADC14MEMx above comparator window */\r
-/* ADC14IER1[ADC14OVIE] Bits */\r
-#define ADC14OVIE_OFS ( 4) /* ADC14OVIE Offset */\r
-#define ADC14OVIE (0x00000010) /* ADC14MEMx overflow-interrupt enable */\r
-/* ADC14IER1[ADC14TOVIE] Bits */\r
-#define ADC14TOVIE_OFS ( 5) /* ADC14TOVIE Offset */\r
-#define ADC14TOVIE (0x00000020) /* ADC14 conversion-time-overflow interrupt enable */\r
-/* ADC14IER1[ADC14RDYIE] Bits */\r
-#define ADC14RDYIE_OFS ( 6) /* ADC14RDYIE Offset */\r
-#define ADC14RDYIE (0x00000040) /* ADC14 local buffered reference ready interrupt enable */\r
-/* ADC14IFGR0[ADC14IFG0] Bits */\r
-#define ADC14IFG0_OFS ( 0) /* ADC14IFG0 Offset */\r
-#define ADC14IFG0 (0x00000001) /* ADC14MEM0 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG1] Bits */\r
-#define ADC14IFG1_OFS ( 1) /* ADC14IFG1 Offset */\r
-#define ADC14IFG1 (0x00000002) /* ADC14MEM1 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG2] Bits */\r
-#define ADC14IFG2_OFS ( 2) /* ADC14IFG2 Offset */\r
-#define ADC14IFG2 (0x00000004) /* ADC14MEM2 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG3] Bits */\r
-#define ADC14IFG3_OFS ( 3) /* ADC14IFG3 Offset */\r
-#define ADC14IFG3 (0x00000008) /* ADC14MEM3 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG4] Bits */\r
-#define ADC14IFG4_OFS ( 4) /* ADC14IFG4 Offset */\r
-#define ADC14IFG4 (0x00000010) /* ADC14MEM4 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG5] Bits */\r
-#define ADC14IFG5_OFS ( 5) /* ADC14IFG5 Offset */\r
-#define ADC14IFG5 (0x00000020) /* ADC14MEM5 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG6] Bits */\r
-#define ADC14IFG6_OFS ( 6) /* ADC14IFG6 Offset */\r
-#define ADC14IFG6 (0x00000040) /* ADC14MEM6 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG7] Bits */\r
-#define ADC14IFG7_OFS ( 7) /* ADC14IFG7 Offset */\r
-#define ADC14IFG7 (0x00000080) /* ADC14MEM7 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG8] Bits */\r
-#define ADC14IFG8_OFS ( 8) /* ADC14IFG8 Offset */\r
-#define ADC14IFG8 (0x00000100) /* ADC14MEM8 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG9] Bits */\r
-#define ADC14IFG9_OFS ( 9) /* ADC14IFG9 Offset */\r
-#define ADC14IFG9 (0x00000200) /* ADC14MEM9 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG10] Bits */\r
-#define ADC14IFG10_OFS (10) /* ADC14IFG10 Offset */\r
-#define ADC14IFG10 (0x00000400) /* ADC14MEM10 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG11] Bits */\r
-#define ADC14IFG11_OFS (11) /* ADC14IFG11 Offset */\r
-#define ADC14IFG11 (0x00000800) /* ADC14MEM11 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG12] Bits */\r
-#define ADC14IFG12_OFS (12) /* ADC14IFG12 Offset */\r
-#define ADC14IFG12 (0x00001000) /* ADC14MEM12 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG13] Bits */\r
-#define ADC14IFG13_OFS (13) /* ADC14IFG13 Offset */\r
-#define ADC14IFG13 (0x00002000) /* ADC14MEM13 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG14] Bits */\r
-#define ADC14IFG14_OFS (14) /* ADC14IFG14 Offset */\r
-#define ADC14IFG14 (0x00004000) /* ADC14MEM14 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG15] Bits */\r
-#define ADC14IFG15_OFS (15) /* ADC14IFG15 Offset */\r
-#define ADC14IFG15 (0x00008000) /* ADC14MEM15 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG16] Bits */\r
-#define ADC14IFG16_OFS (16) /* ADC14IFG16 Offset */\r
-#define ADC14IFG16 (0x00010000) /* ADC14MEM16 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG17] Bits */\r
-#define ADC14IFG17_OFS (17) /* ADC14IFG17 Offset */\r
-#define ADC14IFG17 (0x00020000) /* ADC14MEM17 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG18] Bits */\r
-#define ADC14IFG18_OFS (18) /* ADC14IFG18 Offset */\r
-#define ADC14IFG18 (0x00040000) /* ADC14MEM18 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG19] Bits */\r
-#define ADC14IFG19_OFS (19) /* ADC14IFG19 Offset */\r
-#define ADC14IFG19 (0x00080000) /* ADC14MEM19 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG20] Bits */\r
-#define ADC14IFG20_OFS (20) /* ADC14IFG20 Offset */\r
-#define ADC14IFG20 (0x00100000) /* ADC14MEM20 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG21] Bits */\r
-#define ADC14IFG21_OFS (21) /* ADC14IFG21 Offset */\r
-#define ADC14IFG21 (0x00200000) /* ADC14MEM21 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG22] Bits */\r
-#define ADC14IFG22_OFS (22) /* ADC14IFG22 Offset */\r
-#define ADC14IFG22 (0x00400000) /* ADC14MEM22 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG23] Bits */\r
-#define ADC14IFG23_OFS (23) /* ADC14IFG23 Offset */\r
-#define ADC14IFG23 (0x00800000) /* ADC14MEM23 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG24] Bits */\r
-#define ADC14IFG24_OFS (24) /* ADC14IFG24 Offset */\r
-#define ADC14IFG24 (0x01000000) /* ADC14MEM24 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG25] Bits */\r
-#define ADC14IFG25_OFS (25) /* ADC14IFG25 Offset */\r
-#define ADC14IFG25 (0x02000000) /* ADC14MEM25 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG26] Bits */\r
-#define ADC14IFG26_OFS (26) /* ADC14IFG26 Offset */\r
-#define ADC14IFG26 (0x04000000) /* ADC14MEM26 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG27] Bits */\r
-#define ADC14IFG27_OFS (27) /* ADC14IFG27 Offset */\r
-#define ADC14IFG27 (0x08000000) /* ADC14MEM27 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG28] Bits */\r
-#define ADC14IFG28_OFS (28) /* ADC14IFG28 Offset */\r
-#define ADC14IFG28 (0x10000000) /* ADC14MEM28 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG29] Bits */\r
-#define ADC14IFG29_OFS (29) /* ADC14IFG29 Offset */\r
-#define ADC14IFG29 (0x20000000) /* ADC14MEM29 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG30] Bits */\r
-#define ADC14IFG30_OFS (30) /* ADC14IFG30 Offset */\r
-#define ADC14IFG30 (0x40000000) /* ADC14MEM30 interrupt flag */\r
-/* ADC14IFGR0[ADC14IFG31] Bits */\r
-#define ADC14IFG31_OFS (31) /* ADC14IFG31 Offset */\r
-#define ADC14IFG31 (0x80000000) /* ADC14MEM31 interrupt flag */\r
-/* ADC14IFGR1[ADC14INIFG] Bits */\r
-#define ADC14INIFG_OFS ( 1) /* ADC14INIFG Offset */\r
-#define ADC14INIFG (0x00000002) /* Interrupt flag for ADC14MEMx within comparator window */\r
-/* ADC14IFGR1[ADC14LOIFG] Bits */\r
-#define ADC14LOIFG_OFS ( 2) /* ADC14LOIFG Offset */\r
-#define ADC14LOIFG (0x00000004) /* Interrupt flag for ADC14MEMx below comparator window */\r
-/* ADC14IFGR1[ADC14HIIFG] Bits */\r
-#define ADC14HIIFG_OFS ( 3) /* ADC14HIIFG Offset */\r
-#define ADC14HIIFG (0x00000008) /* Interrupt flag for ADC14MEMx above comparator window */\r
-/* ADC14IFGR1[ADC14OVIFG] Bits */\r
-#define ADC14OVIFG_OFS ( 4) /* ADC14OVIFG Offset */\r
-#define ADC14OVIFG (0x00000010) /* ADC14MEMx overflow interrupt flag */\r
-/* ADC14IFGR1[ADC14TOVIFG] Bits */\r
-#define ADC14TOVIFG_OFS ( 5) /* ADC14TOVIFG Offset */\r
-#define ADC14TOVIFG (0x00000020) /* ADC14 conversion time overflow interrupt flag */\r
-/* ADC14IFGR1[ADC14RDYIFG] Bits */\r
-#define ADC14RDYIFG_OFS ( 6) /* ADC14RDYIFG Offset */\r
-#define ADC14RDYIFG (0x00000040) /* ADC14 local buffered reference ready interrupt flag */\r
-/* ADC14CLRIFGR0[CLRADC14IFG0] Bits */\r
-#define CLRADC14IFG0_OFS ( 0) /* CLRADC14IFG0 Offset */\r
-#define CLRADC14IFG0 (0x00000001) /* clear ADC14IFG0 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG1] Bits */\r
-#define CLRADC14IFG1_OFS ( 1) /* CLRADC14IFG1 Offset */\r
-#define CLRADC14IFG1 (0x00000002) /* clear ADC14IFG1 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG2] Bits */\r
-#define CLRADC14IFG2_OFS ( 2) /* CLRADC14IFG2 Offset */\r
-#define CLRADC14IFG2 (0x00000004) /* clear ADC14IFG2 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG3] Bits */\r
-#define CLRADC14IFG3_OFS ( 3) /* CLRADC14IFG3 Offset */\r
-#define CLRADC14IFG3 (0x00000008) /* clear ADC14IFG3 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG4] Bits */\r
-#define CLRADC14IFG4_OFS ( 4) /* CLRADC14IFG4 Offset */\r
-#define CLRADC14IFG4 (0x00000010) /* clear ADC14IFG4 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG5] Bits */\r
-#define CLRADC14IFG5_OFS ( 5) /* CLRADC14IFG5 Offset */\r
-#define CLRADC14IFG5 (0x00000020) /* clear ADC14IFG5 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG6] Bits */\r
-#define CLRADC14IFG6_OFS ( 6) /* CLRADC14IFG6 Offset */\r
-#define CLRADC14IFG6 (0x00000040) /* clear ADC14IFG6 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG7] Bits */\r
-#define CLRADC14IFG7_OFS ( 7) /* CLRADC14IFG7 Offset */\r
-#define CLRADC14IFG7 (0x00000080) /* clear ADC14IFG7 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG8] Bits */\r
-#define CLRADC14IFG8_OFS ( 8) /* CLRADC14IFG8 Offset */\r
-#define CLRADC14IFG8 (0x00000100) /* clear ADC14IFG8 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG9] Bits */\r
-#define CLRADC14IFG9_OFS ( 9) /* CLRADC14IFG9 Offset */\r
-#define CLRADC14IFG9 (0x00000200) /* clear ADC14IFG9 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG10] Bits */\r
-#define CLRADC14IFG10_OFS (10) /* CLRADC14IFG10 Offset */\r
-#define CLRADC14IFG10 (0x00000400) /* clear ADC14IFG10 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG11] Bits */\r
-#define CLRADC14IFG11_OFS (11) /* CLRADC14IFG11 Offset */\r
-#define CLRADC14IFG11 (0x00000800) /* clear ADC14IFG11 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG12] Bits */\r
-#define CLRADC14IFG12_OFS (12) /* CLRADC14IFG12 Offset */\r
-#define CLRADC14IFG12 (0x00001000) /* clear ADC14IFG12 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG13] Bits */\r
-#define CLRADC14IFG13_OFS (13) /* CLRADC14IFG13 Offset */\r
-#define CLRADC14IFG13 (0x00002000) /* clear ADC14IFG13 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG14] Bits */\r
-#define CLRADC14IFG14_OFS (14) /* CLRADC14IFG14 Offset */\r
-#define CLRADC14IFG14 (0x00004000) /* clear ADC14IFG14 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG15] Bits */\r
-#define CLRADC14IFG15_OFS (15) /* CLRADC14IFG15 Offset */\r
-#define CLRADC14IFG15 (0x00008000) /* clear ADC14IFG15 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG16] Bits */\r
-#define CLRADC14IFG16_OFS (16) /* CLRADC14IFG16 Offset */\r
-#define CLRADC14IFG16 (0x00010000) /* clear ADC14IFG16 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG17] Bits */\r
-#define CLRADC14IFG17_OFS (17) /* CLRADC14IFG17 Offset */\r
-#define CLRADC14IFG17 (0x00020000) /* clear ADC14IFG17 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG18] Bits */\r
-#define CLRADC14IFG18_OFS (18) /* CLRADC14IFG18 Offset */\r
-#define CLRADC14IFG18 (0x00040000) /* clear ADC14IFG18 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG19] Bits */\r
-#define CLRADC14IFG19_OFS (19) /* CLRADC14IFG19 Offset */\r
-#define CLRADC14IFG19 (0x00080000) /* clear ADC14IFG19 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG20] Bits */\r
-#define CLRADC14IFG20_OFS (20) /* CLRADC14IFG20 Offset */\r
-#define CLRADC14IFG20 (0x00100000) /* clear ADC14IFG20 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG21] Bits */\r
-#define CLRADC14IFG21_OFS (21) /* CLRADC14IFG21 Offset */\r
-#define CLRADC14IFG21 (0x00200000) /* clear ADC14IFG21 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG22] Bits */\r
-#define CLRADC14IFG22_OFS (22) /* CLRADC14IFG22 Offset */\r
-#define CLRADC14IFG22 (0x00400000) /* clear ADC14IFG22 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG23] Bits */\r
-#define CLRADC14IFG23_OFS (23) /* CLRADC14IFG23 Offset */\r
-#define CLRADC14IFG23 (0x00800000) /* clear ADC14IFG23 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG24] Bits */\r
-#define CLRADC14IFG24_OFS (24) /* CLRADC14IFG24 Offset */\r
-#define CLRADC14IFG24 (0x01000000) /* clear ADC14IFG24 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG25] Bits */\r
-#define CLRADC14IFG25_OFS (25) /* CLRADC14IFG25 Offset */\r
-#define CLRADC14IFG25 (0x02000000) /* clear ADC14IFG25 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG26] Bits */\r
-#define CLRADC14IFG26_OFS (26) /* CLRADC14IFG26 Offset */\r
-#define CLRADC14IFG26 (0x04000000) /* clear ADC14IFG26 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG27] Bits */\r
-#define CLRADC14IFG27_OFS (27) /* CLRADC14IFG27 Offset */\r
-#define CLRADC14IFG27 (0x08000000) /* clear ADC14IFG27 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG28] Bits */\r
-#define CLRADC14IFG28_OFS (28) /* CLRADC14IFG28 Offset */\r
-#define CLRADC14IFG28 (0x10000000) /* clear ADC14IFG28 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG29] Bits */\r
-#define CLRADC14IFG29_OFS (29) /* CLRADC14IFG29 Offset */\r
-#define CLRADC14IFG29 (0x20000000) /* clear ADC14IFG29 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG30] Bits */\r
-#define CLRADC14IFG30_OFS (30) /* CLRADC14IFG30 Offset */\r
-#define CLRADC14IFG30 (0x40000000) /* clear ADC14IFG30 */\r
-/* ADC14CLRIFGR0[CLRADC14IFG31] Bits */\r
-#define CLRADC14IFG31_OFS (31) /* CLRADC14IFG31 Offset */\r
-#define CLRADC14IFG31 (0x80000000) /* clear ADC14IFG31 */\r
-/* ADC14CLRIFGR1[CLRADC14INIFG] Bits */\r
-#define CLRADC14INIFG_OFS ( 1) /* CLRADC14INIFG Offset */\r
-#define CLRADC14INIFG (0x00000002) /* clear ADC14INIFG */\r
-/* ADC14CLRIFGR1[CLRADC14LOIFG] Bits */\r
-#define CLRADC14LOIFG_OFS ( 2) /* CLRADC14LOIFG Offset */\r
-#define CLRADC14LOIFG (0x00000004) /* clear ADC14LOIFG */\r
-/* ADC14CLRIFGR1[CLRADC14HIIFG] Bits */\r
-#define CLRADC14HIIFG_OFS ( 3) /* CLRADC14HIIFG Offset */\r
-#define CLRADC14HIIFG (0x00000008) /* clear ADC14HIIFG */\r
-/* ADC14CLRIFGR1[CLRADC14OVIFG] Bits */\r
-#define CLRADC14OVIFG_OFS ( 4) /* CLRADC14OVIFG Offset */\r
-#define CLRADC14OVIFG (0x00000010) /* clear ADC14OVIFG */\r
-/* ADC14CLRIFGR1[CLRADC14TOVIFG] Bits */\r
-#define CLRADC14TOVIFG_OFS ( 5) /* CLRADC14TOVIFG Offset */\r
-#define CLRADC14TOVIFG (0x00000020) /* clear ADC14TOVIFG */\r
-/* ADC14CLRIFGR1[CLRADC14RDYIFG] Bits */\r
-#define CLRADC14RDYIFG_OFS ( 6) /* CLRADC14RDYIFG Offset */\r
-#define CLRADC14RDYIFG (0x00000040) /* clear ADC14RDYIFG */\r
-\r
-\r
-//*****************************************************************************\r
-// AES256 Bits\r
-//*****************************************************************************\r
-/* AESACTL0[AESOP] Bits */\r
-#define AESOP0 (0x0001) /* AESOP Bit 0 */\r
-#define AESOP1 (0x0002) /* AESOP Bit 1 */\r
-/* AESACTL0[AESOP] Bits */\r
-#define AESOP_OFS ( 0) /* AESOPx Offset */\r
-#define AESOP_M (0x0003) /* AES operation */\r
-//#define AESOP0 (0x0001) /* AES operation */\r
-//#define AESOP1 (0x0002) /* AES operation */\r
-#define AESOP_0 (0x0000) /* Encryption */\r
-#define AESOP_1 (0x0001) /* Decryption. The provided key is the same key used for encryption */\r
-#define AESOP_2 (0x0002) /* Generate first round key required for decryption */\r
-#define AESOP_3 (0x0003) /* Decryption. The provided key is the first round key required for decryption */\r
-/* AESACTL0[AESKL] Bits */\r
-#define AESKL0 (0x0004) /* AESKL Bit 0 */\r
-#define AESKL1 (0x0008) /* AESKL Bit 1 */\r
-/* AESACTL0[AESKL] Bits */\r
-#define AESKL_OFS ( 2) /* AESKLx Offset */\r
-#define AESKL_M (0x000c) /* AES key length */\r
-//#define AESKL0 (0x0004) /* AES key length */\r
-//#define AESKL1 (0x0008) /* AES key length */\r
-#define AESKL_0 (0x0000) /* AES128. The key size is 128 bit */\r
-#define AESKL_1 (0x0004) /* AES192. The key size is 192 bit. */\r
-#define AESKL_2 (0x0008) /* AES256. The key size is 256 bit */\r
-#define AESKL__128BIT (0x0000) /* AES128. The key size is 128 bit */\r
-#define AESKL__192BIT (0x0004) /* AES192. The key size is 192 bit. */\r
-#define AESKL__256BIT (0x0008) /* AES256. The key size is 256 bit */\r
-/* AESACTL0[AESCM] Bits */\r
-#define AESCM0 (0x0020) /* AESCM Bit 0 */\r
-#define AESCM1 (0x0040) /* AESCM Bit 1 */\r
-/* AESACTL0[AESCM] Bits */\r
-#define AESCM_OFS ( 5) /* AESCMx Offset */\r
-#define AESCM_M (0x0060) /* AES cipher mode select */\r
-//#define AESCM0 (0x0020) /* AES cipher mode select */\r
-//#define AESCM1 (0x0040) /* AES cipher mode select */\r
-#define AESCM_0 (0x0000) /* ECB */\r
-#define AESCM_1 (0x0020) /* CBC */\r
-#define AESCM_2 (0x0040) /* OFB */\r
-#define AESCM_3 (0x0060) /* CFB */\r
-#define AESCM__ECB (0x0000) /* ECB */\r
-#define AESCM__CBC (0x0020) /* CBC */\r
-#define AESCM__OFB (0x0040) /* OFB */\r
-#define AESCM__CFB (0x0060) /* CFB */\r
-/* AESACTL0[AESSWRST] Bits */\r
-#define AESSWRST_OFS ( 7) /* AESSWRST Offset */\r
-#define AESSWRST (0x0080) /* AES software reset */\r
-/* AESACTL0[AESRDYIFG] Bits */\r
-#define AESRDYIFG_OFS ( 8) /* AESRDYIFG Offset */\r
-#define AESRDYIFG (0x0100) /* AES ready interrupt flag */\r
-/* AESACTL0[AESERRFG] Bits */\r
-#define AESERRFG_OFS (11) /* AESERRFG Offset */\r
-#define AESERRFG (0x0800) /* AES error flag */\r
-/* AESACTL0[AESRDYIE] Bits */\r
-#define AESRDYIE_OFS (12) /* AESRDYIE Offset */\r
-#define AESRDYIE (0x1000) /* AES ready interrupt enable */\r
-/* AESACTL0[AESCMEN] Bits */\r
-#define AESCMEN_OFS (15) /* AESCMEN Offset */\r
-#define AESCMEN (0x8000) /* AES cipher mode enable */\r
-/* AESACTL1[AESBLKCNT] Bits */\r
-#define AESBLKCNT0 (0x0001) /* AESBLKCNT Bit 0 */\r
-#define AESBLKCNT1 (0x0002) /* AESBLKCNT Bit 1 */\r
-#define AESBLKCNT2 (0x0004) /* AESBLKCNT Bit 2 */\r
-#define AESBLKCNT3 (0x0008) /* AESBLKCNT Bit 3 */\r
-#define AESBLKCNT4 (0x0010) /* AESBLKCNT Bit 4 */\r
-#define AESBLKCNT5 (0x0020) /* AESBLKCNT Bit 5 */\r
-#define AESBLKCNT6 (0x0040) /* AESBLKCNT Bit 6 */\r
-#define AESBLKCNT7 (0x0080) /* AESBLKCNT Bit 7 */\r
-/* AESACTL1[AESBLKCNT] Bits */\r
-#define AESBLKCNT_OFS ( 0) /* AESBLKCNTx Offset */\r
-#define AESBLKCNT_M (0x00ff) /* Cipher Block Counter */\r
-/* AESASTAT[AESBUSY] Bits */\r
-#define AESBUSY_OFS ( 0) /* AESBUSY Offset */\r
-#define AESBUSY (0x0001) /* AES accelerator module busy */\r
-/* AESASTAT[AESKEYWR] Bits */\r
-#define AESKEYWR_OFS ( 1) /* AESKEYWR Offset */\r
-#define AESKEYWR (0x0002) /* All 16 bytes written to AESAKEY */\r
-/* AESASTAT[AESDINWR] Bits */\r
-#define AESDINWR_OFS ( 2) /* AESDINWR Offset */\r
-#define AESDINWR (0x0004) /* All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */\r
-/* AESASTAT[AESDOUTRD] Bits */\r
-#define AESDOUTRD_OFS ( 3) /* AESDOUTRD Offset */\r
-#define AESDOUTRD (0x0008) /* All 16 bytes read from AESADOUT */\r
-/* AESASTAT[AESKEYCNT] Bits */\r
-#define AESKEYCNT0 (0x0010) /* AESKEYCNT Bit 0 */\r
-#define AESKEYCNT1 (0x0020) /* AESKEYCNT Bit 1 */\r
-#define AESKEYCNT2 (0x0040) /* AESKEYCNT Bit 2 */\r
-#define AESKEYCNT3 (0x0080) /* AESKEYCNT Bit 3 */\r
-/* AESASTAT[AESKEYCNT] Bits */\r
-#define AESKEYCNT_OFS ( 4) /* AESKEYCNTx Offset */\r
-#define AESKEYCNT_M (0x00f0) /* Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */\r
-/* AESASTAT[AESDINCNT] Bits */\r
-#define AESDINCNT0 (0x0100) /* AESDINCNT Bit 0 */\r
-#define AESDINCNT1 (0x0200) /* AESDINCNT Bit 1 */\r
-#define AESDINCNT2 (0x0400) /* AESDINCNT Bit 2 */\r
-#define AESDINCNT3 (0x0800) /* AESDINCNT Bit 3 */\r
-/* AESASTAT[AESDINCNT] Bits */\r
-#define AESDINCNT_OFS ( 8) /* AESDINCNTx Offset */\r
-#define AESDINCNT_M (0x0f00) /* Bytes written via AESADIN, AESAXDIN or AESAXIN */\r
-/* AESASTAT[AESDOUTCNT] Bits */\r
-#define AESDOUTCNT0 (0x1000) /* AESDOUTCNT Bit 0 */\r
-#define AESDOUTCNT1 (0x2000) /* AESDOUTCNT Bit 1 */\r
-#define AESDOUTCNT2 (0x4000) /* AESDOUTCNT Bit 2 */\r
-#define AESDOUTCNT3 (0x8000) /* AESDOUTCNT Bit 3 */\r
-/* AESASTAT[AESDOUTCNT] Bits */\r
-#define AESDOUTCNT_OFS (12) /* AESDOUTCNTx Offset */\r
-#define AESDOUTCNT_M (0xf000) /* Bytes read via AESADOUT */\r
-/* AESAKEY[AESKEY0] Bits */\r
-#define AESKEY00 (0x0001) /* AESKEY0 Bit 0 */\r
-#define AESKEY01 (0x0002) /* AESKEY0 Bit 1 */\r
-#define AESKEY02 (0x0004) /* AESKEY0 Bit 2 */\r
-#define AESKEY03 (0x0008) /* AESKEY0 Bit 3 */\r
-#define AESKEY04 (0x0010) /* AESKEY0 Bit 4 */\r
-#define AESKEY05 (0x0020) /* AESKEY0 Bit 5 */\r
-#define AESKEY06 (0x0040) /* AESKEY0 Bit 6 */\r
-#define AESKEY07 (0x0080) /* AESKEY0 Bit 7 */\r
-/* AESAKEY[AESKEY0] Bits */\r
-#define AESKEY0_OFS ( 0) /* AESKEY0x Offset */\r
-#define AESKEY0_M (0x00ff) /* AES key byte n when AESAKEY is written as half-word */\r
-/* AESAKEY[AESKEY1] Bits */\r
-#define AESKEY10 (0x0100) /* AESKEY1 Bit 0 */\r
-#define AESKEY11 (0x0200) /* AESKEY1 Bit 1 */\r
-#define AESKEY12 (0x0400) /* AESKEY1 Bit 2 */\r
-#define AESKEY13 (0x0800) /* AESKEY1 Bit 3 */\r
-#define AESKEY14 (0x1000) /* AESKEY1 Bit 4 */\r
-#define AESKEY15 (0x2000) /* AESKEY1 Bit 5 */\r
-#define AESKEY16 (0x4000) /* AESKEY1 Bit 6 */\r
-#define AESKEY17 (0x8000) /* AESKEY1 Bit 7 */\r
-/* AESAKEY[AESKEY1] Bits */\r
-#define AESKEY1_OFS ( 8) /* AESKEY1x Offset */\r
-#define AESKEY1_M (0xff00) /* AES key byte n+1 when AESAKEY is written as half-word */\r
-/* AESADIN[AESDIN0] Bits */\r
-#define AESDIN00 (0x0001) /* AESDIN0 Bit 0 */\r
-#define AESDIN01 (0x0002) /* AESDIN0 Bit 1 */\r
-#define AESDIN02 (0x0004) /* AESDIN0 Bit 2 */\r
-#define AESDIN03 (0x0008) /* AESDIN0 Bit 3 */\r
-#define AESDIN04 (0x0010) /* AESDIN0 Bit 4 */\r
-#define AESDIN05 (0x0020) /* AESDIN0 Bit 5 */\r
-#define AESDIN06 (0x0040) /* AESDIN0 Bit 6 */\r
-#define AESDIN07 (0x0080) /* AESDIN0 Bit 7 */\r
-/* AESADIN[AESDIN0] Bits */\r
-#define AESDIN0_OFS ( 0) /* AESDIN0x Offset */\r
-#define AESDIN0_M (0x00ff) /* AES data in byte n when AESADIN is written as half-word */\r
-/* AESADIN[AESDIN1] Bits */\r
-#define AESDIN10 (0x0100) /* AESDIN1 Bit 0 */\r
-#define AESDIN11 (0x0200) /* AESDIN1 Bit 1 */\r
-#define AESDIN12 (0x0400) /* AESDIN1 Bit 2 */\r
-#define AESDIN13 (0x0800) /* AESDIN1 Bit 3 */\r
-#define AESDIN14 (0x1000) /* AESDIN1 Bit 4 */\r
-#define AESDIN15 (0x2000) /* AESDIN1 Bit 5 */\r
-#define AESDIN16 (0x4000) /* AESDIN1 Bit 6 */\r
-#define AESDIN17 (0x8000) /* AESDIN1 Bit 7 */\r
-/* AESADIN[AESDIN1] Bits */\r
-#define AESDIN1_OFS ( 8) /* AESDIN1x Offset */\r
-#define AESDIN1_M (0xff00) /* AES data in byte n+1 when AESADIN is written as half-word */\r
-/* AESADOUT[AESDOUT0] Bits */\r
-#define AESDOUT00 (0x0001) /* AESDOUT0 Bit 0 */\r
-#define AESDOUT01 (0x0002) /* AESDOUT0 Bit 1 */\r
-#define AESDOUT02 (0x0004) /* AESDOUT0 Bit 2 */\r
-#define AESDOUT03 (0x0008) /* AESDOUT0 Bit 3 */\r
-#define AESDOUT04 (0x0010) /* AESDOUT0 Bit 4 */\r
-#define AESDOUT05 (0x0020) /* AESDOUT0 Bit 5 */\r
-#define AESDOUT06 (0x0040) /* AESDOUT0 Bit 6 */\r
-#define AESDOUT07 (0x0080) /* AESDOUT0 Bit 7 */\r
-/* AESADOUT[AESDOUT0] Bits */\r
-#define AESDOUT0_OFS ( 0) /* AESDOUT0x Offset */\r
-#define AESDOUT0_M (0x00ff) /* AES data out byte n when AESADOUT is read as half-word */\r
-/* AESADOUT[AESDOUT1] Bits */\r
-#define AESDOUT10 (0x0100) /* AESDOUT1 Bit 0 */\r
-#define AESDOUT11 (0x0200) /* AESDOUT1 Bit 1 */\r
-#define AESDOUT12 (0x0400) /* AESDOUT1 Bit 2 */\r
-#define AESDOUT13 (0x0800) /* AESDOUT1 Bit 3 */\r
-#define AESDOUT14 (0x1000) /* AESDOUT1 Bit 4 */\r
-#define AESDOUT15 (0x2000) /* AESDOUT1 Bit 5 */\r
-#define AESDOUT16 (0x4000) /* AESDOUT1 Bit 6 */\r
-#define AESDOUT17 (0x8000) /* AESDOUT1 Bit 7 */\r
-/* AESADOUT[AESDOUT1] Bits */\r
-#define AESDOUT1_OFS ( 8) /* AESDOUT1x Offset */\r
-#define AESDOUT1_M (0xff00) /* AES data out byte n+1 when AESADOUT is read as half-word */\r
-/* AESAXDIN[AESXDIN0] Bits */\r
-#define AESXDIN00 (0x0001) /* AESXDIN0 Bit 0 */\r
-#define AESXDIN01 (0x0002) /* AESXDIN0 Bit 1 */\r
-#define AESXDIN02 (0x0004) /* AESXDIN0 Bit 2 */\r
-#define AESXDIN03 (0x0008) /* AESXDIN0 Bit 3 */\r
-#define AESXDIN04 (0x0010) /* AESXDIN0 Bit 4 */\r
-#define AESXDIN05 (0x0020) /* AESXDIN0 Bit 5 */\r
-#define AESXDIN06 (0x0040) /* AESXDIN0 Bit 6 */\r
-#define AESXDIN07 (0x0080) /* AESXDIN0 Bit 7 */\r
-/* AESAXDIN[AESXDIN0] Bits */\r
-#define AESXDIN0_OFS ( 0) /* AESXDIN0x Offset */\r
-#define AESXDIN0_M (0x00ff) /* AES data in byte n when AESAXDIN is written as half-word */\r
-/* AESAXDIN[AESXDIN1] Bits */\r
-#define AESXDIN10 (0x0100) /* AESXDIN1 Bit 0 */\r
-#define AESXDIN11 (0x0200) /* AESXDIN1 Bit 1 */\r
-#define AESXDIN12 (0x0400) /* AESXDIN1 Bit 2 */\r
-#define AESXDIN13 (0x0800) /* AESXDIN1 Bit 3 */\r
-#define AESXDIN14 (0x1000) /* AESXDIN1 Bit 4 */\r
-#define AESXDIN15 (0x2000) /* AESXDIN1 Bit 5 */\r
-#define AESXDIN16 (0x4000) /* AESXDIN1 Bit 6 */\r
-#define AESXDIN17 (0x8000) /* AESXDIN1 Bit 7 */\r
-/* AESAXDIN[AESXDIN1] Bits */\r
-#define AESXDIN1_OFS ( 8) /* AESXDIN1x Offset */\r
-#define AESXDIN1_M (0xff00) /* AES data in byte n+1 when AESAXDIN is written as half-word */\r
-/* AESAXIN[AESXIN0] Bits */\r
-#define AESXIN00 (0x0001) /* AESXIN0 Bit 0 */\r
-#define AESXIN01 (0x0002) /* AESXIN0 Bit 1 */\r
-#define AESXIN02 (0x0004) /* AESXIN0 Bit 2 */\r
-#define AESXIN03 (0x0008) /* AESXIN0 Bit 3 */\r
-#define AESXIN04 (0x0010) /* AESXIN0 Bit 4 */\r
-#define AESXIN05 (0x0020) /* AESXIN0 Bit 5 */\r
-#define AESXIN06 (0x0040) /* AESXIN0 Bit 6 */\r
-#define AESXIN07 (0x0080) /* AESXIN0 Bit 7 */\r
-/* AESAXIN[AESXIN0] Bits */\r
-#define AESXIN0_OFS ( 0) /* AESXIN0x Offset */\r
-#define AESXIN0_M (0x00ff) /* AES data in byte n when AESAXIN is written as half-word */\r
-/* AESAXIN[AESXIN1] Bits */\r
-#define AESXIN10 (0x0100) /* AESXIN1 Bit 0 */\r
-#define AESXIN11 (0x0200) /* AESXIN1 Bit 1 */\r
-#define AESXIN12 (0x0400) /* AESXIN1 Bit 2 */\r
-#define AESXIN13 (0x0800) /* AESXIN1 Bit 3 */\r
-#define AESXIN14 (0x1000) /* AESXIN1 Bit 4 */\r
-#define AESXIN15 (0x2000) /* AESXIN1 Bit 5 */\r
-#define AESXIN16 (0x4000) /* AESXIN1 Bit 6 */\r
-#define AESXIN17 (0x8000) /* AESXIN1 Bit 7 */\r
-/* AESAXIN[AESXIN1] Bits */\r
-#define AESXIN1_OFS ( 8) /* AESXIN1x Offset */\r
-#define AESXIN1_M (0xff00) /* AES data in byte n+1 when AESAXIN is written as half-word */\r
-\r
-\r
-//*****************************************************************************\r
-// CAPTIO0 Bits\r
-//*****************************************************************************\r
-/* CAPTIO0CTL[CAPTIOPISEL] Bits */\r
-#define CAPTIOPISEL0 (0x0002) /* CAPTIOPISEL Bit 0 */\r
-#define CAPTIOPISEL1 (0x0004) /* CAPTIOPISEL Bit 1 */\r
-#define CAPTIOPISEL2 (0x0008) /* CAPTIOPISEL Bit 2 */\r
-/* CAPTIO0CTL[CAPTIOPISEL] Bits */\r
-#define CAPTIOPISEL_OFS ( 1) /* CAPTIOPISELx Offset */\r
-#define CAPTIOPISEL_M (0x000e) /* Capacitive Touch IO pin select */\r
-//#define CAPTIOPISEL0 (0x0002) /* Capacitive Touch IO pin select */\r
-//#define CAPTIOPISEL1 (0x0004) /* Capacitive Touch IO pin select */\r
-//#define CAPTIOPISEL2 (0x0008) /* Capacitive Touch IO pin select */\r
-#define CAPTIOPISEL_0 (0x0000) /* Px.0 */\r
-#define CAPTIOPISEL_1 (0x0002) /* Px.1 */\r
-#define CAPTIOPISEL_2 (0x0004) /* Px.2 */\r
-#define CAPTIOPISEL_3 (0x0006) /* Px.3 */\r
-#define CAPTIOPISEL_4 (0x0008) /* Px.4 */\r
-#define CAPTIOPISEL_5 (0x000a) /* Px.5 */\r
-#define CAPTIOPISEL_6 (0x000c) /* Px.6 */\r
-#define CAPTIOPISEL_7 (0x000e) /* Px.7 */\r
-/* CAPTIO0CTL[CAPTIOPOSEL] Bits */\r
-#define CAPTIOPOSEL0 (0x0010) /* CAPTIOPOSEL Bit 0 */\r
-#define CAPTIOPOSEL1 (0x0020) /* CAPTIOPOSEL Bit 1 */\r
-#define CAPTIOPOSEL2 (0x0040) /* CAPTIOPOSEL Bit 2 */\r
-#define CAPTIOPOSEL3 (0x0080) /* CAPTIOPOSEL Bit 3 */\r
-/* CAPTIO0CTL[CAPTIOPOSEL] Bits */\r
-#define CAPTIOPOSEL_OFS ( 4) /* CAPTIOPOSELx Offset */\r
-#define CAPTIOPOSEL_M (0x00f0) /* Capacitive Touch IO port select */\r
-//#define CAPTIOPOSEL0 (0x0010) /* Capacitive Touch IO port select */\r
-//#define CAPTIOPOSEL1 (0x0020) /* Capacitive Touch IO port select */\r
-//#define CAPTIOPOSEL2 (0x0040) /* Capacitive Touch IO port select */\r
-//#define CAPTIOPOSEL3 (0x0080) /* Capacitive Touch IO port select */\r
-#define CAPTIOPOSEL_0 (0x0000) /* Px = PJ */\r
-#define CAPTIOPOSEL_1 (0x0010) /* Px = P1 */\r
-#define CAPTIOPOSEL_2 (0x0020) /* Px = P2 */\r
-#define CAPTIOPOSEL_3 (0x0030) /* Px = P3 */\r
-#define CAPTIOPOSEL_4 (0x0040) /* Px = P4 */\r
-#define CAPTIOPOSEL_5 (0x0050) /* Px = P5 */\r
-#define CAPTIOPOSEL_6 (0x0060) /* Px = P6 */\r
-#define CAPTIOPOSEL_7 (0x0070) /* Px = P7 */\r
-#define CAPTIOPOSEL_8 (0x0080) /* Px = P8 */\r
-#define CAPTIOPOSEL_9 (0x0090) /* Px = P9 */\r
-#define CAPTIOPOSEL_10 (0x00a0) /* Px = P10 */\r
-#define CAPTIOPOSEL_11 (0x00b0) /* Px = P11 */\r
-#define CAPTIOPOSEL_12 (0x00c0) /* Px = P12 */\r
-#define CAPTIOPOSEL_13 (0x00d0) /* Px = P13 */\r
-#define CAPTIOPOSEL_14 (0x00e0) /* Px = P14 */\r
-#define CAPTIOPOSEL_15 (0x00f0) /* Px = P15 */\r
-#define CAPTIOPOSEL__PJ (0x0000) /* Px = PJ */\r
-#define CAPTIOPOSEL__P1 (0x0010) /* Px = P1 */\r
-#define CAPTIOPOSEL__P2 (0x0020) /* Px = P2 */\r
-#define CAPTIOPOSEL__P3 (0x0030) /* Px = P3 */\r
-#define CAPTIOPOSEL__P4 (0x0040) /* Px = P4 */\r
-#define CAPTIOPOSEL__P5 (0x0050) /* Px = P5 */\r
-#define CAPTIOPOSEL__P6 (0x0060) /* Px = P6 */\r
-#define CAPTIOPOSEL__P7 (0x0070) /* Px = P7 */\r
-#define CAPTIOPOSEL__P8 (0x0080) /* Px = P8 */\r
-#define CAPTIOPOSEL__P9 (0x0090) /* Px = P9 */\r
-#define CAPTIOPOSEL__P10 (0x00a0) /* Px = P10 */\r
-#define CAPTIOPOSEL__P11 (0x00b0) /* Px = P11 */\r
-#define CAPTIOPOSEL__P12 (0x00c0) /* Px = P12 */\r
-#define CAPTIOPOSEL__P13 (0x00d0) /* Px = P13 */\r
-#define CAPTIOPOSEL__P14 (0x00e0) /* Px = P14 */\r
-#define CAPTIOPOSEL__P15 (0x00f0) /* Px = P15 */\r
-/* CAPTIO0CTL[CAPTIOEN] Bits */\r
-#define CAPTIOEN_OFS ( 8) /* CAPTIOEN Offset */\r
-#define CAPTIOEN (0x0100) /* Capacitive Touch IO enable */\r
-/* CAPTIO0CTL[CAPTIOSTATE] Bits */\r
-#define CAPTIOSTATE_OFS ( 9) /* CAPTIOSTATE Offset */\r
-#define CAPTIOSTATE (0x0200) /* Capacitive Touch IO state */\r
-\r
-\r
-//*****************************************************************************\r
-// CAPTIO1 Bits\r
-//*****************************************************************************\r
-/* CAPTIO1CTL[CAPTIOPISEL] Bits */\r
-//#define CAPTIOPISEL0 (0x0002) /* CAPTIOPISEL Bit 0 */\r
-//#define CAPTIOPISEL1 (0x0004) /* CAPTIOPISEL Bit 1 */\r
-//#define CAPTIOPISEL2 (0x0008) /* CAPTIOPISEL Bit 2 */\r
-/* CAPTIO1CTL[CAPTIOPISEL] Bits */\r
-//#define CAPTIOPISEL_OFS ( 1) /* CAPTIOPISELx Offset */\r
-//#define CAPTIOPISEL_M (0x000e) /* Capacitive Touch IO pin select */\r
-//#define CAPTIOPISEL0 (0x0002) /* Capacitive Touch IO pin select */\r
-//#define CAPTIOPISEL1 (0x0004) /* Capacitive Touch IO pin select */\r
-//#define CAPTIOPISEL2 (0x0008) /* Capacitive Touch IO pin select */\r
-//#define CAPTIOPISEL_0 (0x0000) /* Px.0 */\r
-//#define CAPTIOPISEL_1 (0x0002) /* Px.1 */\r
-//#define CAPTIOPISEL_2 (0x0004) /* Px.2 */\r
-//#define CAPTIOPISEL_3 (0x0006) /* Px.3 */\r
-//#define CAPTIOPISEL_4 (0x0008) /* Px.4 */\r
-//#define CAPTIOPISEL_5 (0x000a) /* Px.5 */\r
-//#define CAPTIOPISEL_6 (0x000c) /* Px.6 */\r
-//#define CAPTIOPISEL_7 (0x000e) /* Px.7 */\r
-/* CAPTIO1CTL[CAPTIOPOSEL] Bits */\r
-//#define CAPTIOPOSEL0 (0x0010) /* CAPTIOPOSEL Bit 0 */\r
-//#define CAPTIOPOSEL1 (0x0020) /* CAPTIOPOSEL Bit 1 */\r
-//#define CAPTIOPOSEL2 (0x0040) /* CAPTIOPOSEL Bit 2 */\r
-//#define CAPTIOPOSEL3 (0x0080) /* CAPTIOPOSEL Bit 3 */\r
-/* CAPTIO1CTL[CAPTIOPOSEL] Bits */\r
-//#define CAPTIOPOSEL_OFS ( 4) /* CAPTIOPOSELx Offset */\r
-//#define CAPTIOPOSEL_M (0x00f0) /* Capacitive Touch IO port select */\r
-//#define CAPTIOPOSEL0 (0x0010) /* Capacitive Touch IO port select */\r
-//#define CAPTIOPOSEL1 (0x0020) /* Capacitive Touch IO port select */\r
-//#define CAPTIOPOSEL2 (0x0040) /* Capacitive Touch IO port select */\r
-//#define CAPTIOPOSEL3 (0x0080) /* Capacitive Touch IO port select */\r
-//#define CAPTIOPOSEL_0 (0x0000) /* Px = PJ */\r
-//#define CAPTIOPOSEL_1 (0x0010) /* Px = P1 */\r
-//#define CAPTIOPOSEL_2 (0x0020) /* Px = P2 */\r
-//#define CAPTIOPOSEL_3 (0x0030) /* Px = P3 */\r
-//#define CAPTIOPOSEL_4 (0x0040) /* Px = P4 */\r
-//#define CAPTIOPOSEL_5 (0x0050) /* Px = P5 */\r
-//#define CAPTIOPOSEL_6 (0x0060) /* Px = P6 */\r
-//#define CAPTIOPOSEL_7 (0x0070) /* Px = P7 */\r
-//#define CAPTIOPOSEL_8 (0x0080) /* Px = P8 */\r
-//#define CAPTIOPOSEL_9 (0x0090) /* Px = P9 */\r
-//#define CAPTIOPOSEL_10 (0x00a0) /* Px = P10 */\r
-//#define CAPTIOPOSEL_11 (0x00b0) /* Px = P11 */\r
-//#define CAPTIOPOSEL_12 (0x00c0) /* Px = P12 */\r
-//#define CAPTIOPOSEL_13 (0x00d0) /* Px = P13 */\r
-//#define CAPTIOPOSEL_14 (0x00e0) /* Px = P14 */\r
-//#define CAPTIOPOSEL_15 (0x00f0) /* Px = P15 */\r
-//#define CAPTIOPOSEL__PJ (0x0000) /* Px = PJ */\r
-//#define CAPTIOPOSEL__P1 (0x0010) /* Px = P1 */\r
-//#define CAPTIOPOSEL__P2 (0x0020) /* Px = P2 */\r
-//#define CAPTIOPOSEL__P3 (0x0030) /* Px = P3 */\r
-//#define CAPTIOPOSEL__P4 (0x0040) /* Px = P4 */\r
-//#define CAPTIOPOSEL__P5 (0x0050) /* Px = P5 */\r
-//#define CAPTIOPOSEL__P6 (0x0060) /* Px = P6 */\r
-//#define CAPTIOPOSEL__P7 (0x0070) /* Px = P7 */\r
-//#define CAPTIOPOSEL__P8 (0x0080) /* Px = P8 */\r
-//#define CAPTIOPOSEL__P9 (0x0090) /* Px = P9 */\r
-//#define CAPTIOPOSEL__P10 (0x00a0) /* Px = P10 */\r
-//#define CAPTIOPOSEL__P11 (0x00b0) /* Px = P11 */\r
-//#define CAPTIOPOSEL__P12 (0x00c0) /* Px = P12 */\r
-//#define CAPTIOPOSEL__P13 (0x00d0) /* Px = P13 */\r
-//#define CAPTIOPOSEL__P14 (0x00e0) /* Px = P14 */\r
-//#define CAPTIOPOSEL__P15 (0x00f0) /* Px = P15 */\r
-/* CAPTIO1CTL[CAPTIOEN] Bits */\r
-//#define CAPTIOEN_OFS ( 8) /* CAPTIOEN Offset */\r
-//#define CAPTIOEN (0x0100) /* Capacitive Touch IO enable */\r
-/* CAPTIO1CTL[CAPTIOSTATE] Bits */\r
-//#define CAPTIOSTATE_OFS ( 9) /* CAPTIOSTATE Offset */\r
-//#define CAPTIOSTATE (0x0200) /* Capacitive Touch IO state */\r
+/*@}*/ /* end of group WDT_A */\r
\r
\r
-//*****************************************************************************\r
-// COMP_E0 Bits\r
-//*****************************************************************************\r
-/* CE0CTL0[CEIPSEL] Bits */\r
-#define CEIPSEL_OFS ( 0) /* CEIPSEL Offset */\r
-#define CEIPSEL_M (0x000f) /* Channel input selected for the V+ terminal */\r
-#define CEIPSEL0 (0x0001) /* Channel input selected for the V+ terminal */\r
-#define CEIPSEL1 (0x0002) /* Channel input selected for the V+ terminal */\r
-#define CEIPSEL2 (0x0004) /* Channel input selected for the V+ terminal */\r
-#define CEIPSEL3 (0x0008) /* Channel input selected for the V+ terminal */\r
-#define CEIPSEL_0 (0x0000) /* Channel 0 selected */\r
-#define CEIPSEL_1 (0x0001) /* Channel 1 selected */\r
-#define CEIPSEL_2 (0x0002) /* Channel 2 selected */\r
-#define CEIPSEL_3 (0x0003) /* Channel 3 selected */\r
-#define CEIPSEL_4 (0x0004) /* Channel 4 selected */\r
-#define CEIPSEL_5 (0x0005) /* Channel 5 selected */\r
-#define CEIPSEL_6 (0x0006) /* Channel 6 selected */\r
-#define CEIPSEL_7 (0x0007) /* Channel 7 selected */\r
-#define CEIPSEL_8 (0x0008) /* Channel 8 selected */\r
-#define CEIPSEL_9 (0x0009) /* Channel 9 selected */\r
-#define CEIPSEL_10 (0x000a) /* Channel 10 selected */\r
-#define CEIPSEL_11 (0x000b) /* Channel 11 selected */\r
-#define CEIPSEL_12 (0x000c) /* Channel 12 selected */\r
-#define CEIPSEL_13 (0x000d) /* Channel 13 selected */\r
-#define CEIPSEL_14 (0x000e) /* Channel 14 selected */\r
-#define CEIPSEL_15 (0x000f) /* Channel 15 selected */\r
-/* CE0CTL0[CEIPEN] Bits */\r
-#define CEIPEN_OFS ( 7) /* CEIPEN Offset */\r
-#define CEIPEN (0x0080) /* Channel input enable for the V+ terminal */\r
-/* CE0CTL0[CEIMSEL] Bits */\r
-#define CEIMSEL_OFS ( 8) /* CEIMSEL Offset */\r
-#define CEIMSEL_M (0x0f00) /* Channel input selected for the - terminal */\r
-#define CEIMSEL0 (0x0100) /* Channel input selected for the - terminal */\r
-#define CEIMSEL1 (0x0200) /* Channel input selected for the - terminal */\r
-#define CEIMSEL2 (0x0400) /* Channel input selected for the - terminal */\r
-#define CEIMSEL3 (0x0800) /* Channel input selected for the - terminal */\r
-#define CEIMSEL_0 (0x0000) /* Channel 0 selected */\r
-#define CEIMSEL_1 (0x0100) /* Channel 1 selected */\r
-#define CEIMSEL_2 (0x0200) /* Channel 2 selected */\r
-#define CEIMSEL_3 (0x0300) /* Channel 3 selected */\r
-#define CEIMSEL_4 (0x0400) /* Channel 4 selected */\r
-#define CEIMSEL_5 (0x0500) /* Channel 5 selected */\r
-#define CEIMSEL_6 (0x0600) /* Channel 6 selected */\r
-#define CEIMSEL_7 (0x0700) /* Channel 7 selected */\r
-#define CEIMSEL_8 (0x0800) /* Channel 8 selected */\r
-#define CEIMSEL_9 (0x0900) /* Channel 9 selected */\r
-#define CEIMSEL_10 (0x0a00) /* Channel 10 selected */\r
-#define CEIMSEL_11 (0x0b00) /* Channel 11 selected */\r
-#define CEIMSEL_12 (0x0c00) /* Channel 12 selected */\r
-#define CEIMSEL_13 (0x0d00) /* Channel 13 selected */\r
-#define CEIMSEL_14 (0x0e00) /* Channel 14 selected */\r
-#define CEIMSEL_15 (0x0f00) /* Channel 15 selected */\r
-/* CE0CTL0[CEIMEN] Bits */\r
-#define CEIMEN_OFS (15) /* CEIMEN Offset */\r
-#define CEIMEN (0x8000) /* Channel input enable for the - terminal */\r
-/* CE0CTL1[CEOUT] Bits */\r
-#define CEOUT_OFS ( 0) /* CEOUT Offset */\r
-#define CEOUT (0x0001) /* Comparator output value */\r
-/* CE0CTL1[CEOUTPOL] Bits */\r
-#define CEOUTPOL_OFS ( 1) /* CEOUTPOL Offset */\r
-#define CEOUTPOL (0x0002) /* Comparator output polarity */\r
-/* CE0CTL1[CEF] Bits */\r
-#define CEF_OFS ( 2) /* CEF Offset */\r
-#define CEF (0x0004) /* Comparator output filter */\r
-/* CE0CTL1[CEIES] Bits */\r
-#define CEIES_OFS ( 3) /* CEIES Offset */\r
-#define CEIES (0x0008) /* Interrupt edge select for CEIIFG and CEIFG */\r
-/* CE0CTL1[CESHORT] Bits */\r
-#define CESHORT_OFS ( 4) /* CESHORT Offset */\r
-#define CESHORT (0x0010) /* Input short */\r
-/* CE0CTL1[CEEX] Bits */\r
-#define CEEX_OFS ( 5) /* CEEX Offset */\r
-#define CEEX (0x0020) /* Exchange */\r
-/* CE0CTL1[CEFDLY] Bits */\r
-#define CEFDLY_OFS ( 6) /* CEFDLY Offset */\r
-#define CEFDLY_M (0x00c0) /* Filter delay */\r
-#define CEFDLY0 (0x0040) /* Filter delay */\r
-#define CEFDLY1 (0x0080) /* Filter delay */\r
-#define CEFDLY_0 (0x0000) /* Typical filter delay of TBD (450) ns */\r
-#define CEFDLY_1 (0x0040) /* Typical filter delay of TBD (900) ns */\r
-#define CEFDLY_2 (0x0080) /* Typical filter delay of TBD (1800) ns */\r
-#define CEFDLY_3 (0x00c0) /* Typical filter delay of TBD (3600) ns */\r
-/* CE0CTL1[CEPWRMD] Bits */\r
-#define CEPWRMD_OFS ( 8) /* CEPWRMD Offset */\r
-#define CEPWRMD_M (0x0300) /* Power Mode */\r
-#define CEPWRMD0 (0x0100) /* Power Mode */\r
-#define CEPWRMD1 (0x0200) /* Power Mode */\r
-#define CEPWRMD_0 (0x0000) /* High-speed mode */\r
-#define CEPWRMD_1 (0x0100) /* Normal mode */\r
-#define CEPWRMD_2 (0x0200) /* Ultra-low power mode */\r
-/* CE0CTL1[CEON] Bits */\r
-#define CEON_OFS (10) /* CEON Offset */\r
-#define CEON (0x0400) /* Comparator On */\r
-/* CE0CTL1[CEMRVL] Bits */\r
-#define CEMRVL_OFS (11) /* CEMRVL Offset */\r
-#define CEMRVL (0x0800) /* This bit is valid of CEMRVS is set to 1 */\r
-/* CE0CTL1[CEMRVS] Bits */\r
-#define CEMRVS_OFS (12) /* CEMRVS Offset */\r
-#define CEMRVS (0x1000) /* */\r
-/* CE0CTL2[CEREF0] Bits */\r
-#define CEREF0_OFS ( 0) /* CEREF0 Offset */\r
-#define CEREF0_M (0x001f) /* Reference resistor tap 0 */\r
-/* CE0CTL2[CERSEL] Bits */\r
-#define CERSEL_OFS ( 5) /* CERSEL Offset */\r
-#define CERSEL (0x0020) /* Reference select */\r
-/* CE0CTL2[CERS] Bits */\r
-#define CERS_OFS ( 6) /* CERS Offset */\r
-#define CERS_M (0x00c0) /* Reference source */\r
-#define CERS0 (0x0040) /* Reference source */\r
-#define CERS1 (0x0080) /* Reference source */\r
-#define CERS_0 (0x0000) /* No current is drawn by the reference circuitry */\r
-#define CERS_1 (0x0040) /* VCC applied to the resistor ladder */\r
-#define CERS_2 (0x0080) /* Shared reference voltage applied to the resistor ladder */\r
-#define CERS_3 (0x00c0) /* Shared reference voltage supplied to V(CREF). Resistor ladder is off */\r
-/* CE0CTL2[CEREF1] Bits */\r
-#define CEREF1_OFS ( 8) /* CEREF1 Offset */\r
-#define CEREF1_M (0x1f00) /* Reference resistor tap 1 */\r
-/* CE0CTL2[CEREFL] Bits */\r
-#define CEREFL_OFS (13) /* CEREFL Offset */\r
-#define CEREFL_M (0x6000) /* Reference voltage level */\r
-#define CEREFL0 (0x2000) /* Reference voltage level */\r
-#define CEREFL1 (0x4000) /* Reference voltage level */\r
-#define CEREFL_0 (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */\r
-#define CEREFL_1 (0x2000) /* 1.2 V is selected as shared reference voltage input */\r
-#define CEREFL_2 (0x4000) /* 2.0 V is selected as shared reference voltage input */\r
-#define CEREFL_3 (0x6000) /* 2.5 V is selected as shared reference voltage input */\r
-#define CEREFL__OFF (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */\r
-#define CEREFL__1P2V (0x2000) /* 1.2 V is selected as shared reference voltage input */\r
-#define CEREFL__2P0V (0x4000) /* 2.0 V is selected as shared reference voltage input */\r
-#define CEREFL__2P5V (0x6000) /* 2.5 V is selected as shared reference voltage input */\r
-/* CE0CTL2[CEREFACC] Bits */\r
-#define CEREFACC_OFS (15) /* CEREFACC Offset */\r
-#define CEREFACC (0x8000) /* Reference accuracy */\r
-/* CE0CTL3[CEPD0] Bits */\r
-#define CEPD0_OFS ( 0) /* CEPD0 Offset */\r
-#define CEPD0 (0x0001) /* Port disable */\r
-/* CE0CTL3[CEPD1] Bits */\r
-#define CEPD1_OFS ( 1) /* CEPD1 Offset */\r
-#define CEPD1 (0x0002) /* Port disable */\r
-/* CE0CTL3[CEPD2] Bits */\r
-#define CEPD2_OFS ( 2) /* CEPD2 Offset */\r
-#define CEPD2 (0x0004) /* Port disable */\r
-/* CE0CTL3[CEPD3] Bits */\r
-#define CEPD3_OFS ( 3) /* CEPD3 Offset */\r
-#define CEPD3 (0x0008) /* Port disable */\r
-/* CE0CTL3[CEPD4] Bits */\r
-#define CEPD4_OFS ( 4) /* CEPD4 Offset */\r
-#define CEPD4 (0x0010) /* Port disable */\r
-/* CE0CTL3[CEPD5] Bits */\r
-#define CEPD5_OFS ( 5) /* CEPD5 Offset */\r
-#define CEPD5 (0x0020) /* Port disable */\r
-/* CE0CTL3[CEPD6] Bits */\r
-#define CEPD6_OFS ( 6) /* CEPD6 Offset */\r
-#define CEPD6 (0x0040) /* Port disable */\r
-/* CE0CTL3[CEPD7] Bits */\r
-#define CEPD7_OFS ( 7) /* CEPD7 Offset */\r
-#define CEPD7 (0x0080) /* Port disable */\r
-/* CE0CTL3[CEPD8] Bits */\r
-#define CEPD8_OFS ( 8) /* CEPD8 Offset */\r
-#define CEPD8 (0x0100) /* Port disable */\r
-/* CE0CTL3[CEPD9] Bits */\r
-#define CEPD9_OFS ( 9) /* CEPD9 Offset */\r
-#define CEPD9 (0x0200) /* Port disable */\r
-/* CE0CTL3[CEPD10] Bits */\r
-#define CEPD10_OFS (10) /* CEPD10 Offset */\r
-#define CEPD10 (0x0400) /* Port disable */\r
-/* CE0CTL3[CEPD11] Bits */\r
-#define CEPD11_OFS (11) /* CEPD11 Offset */\r
-#define CEPD11 (0x0800) /* Port disable */\r
-/* CE0CTL3[CEPD12] Bits */\r
-#define CEPD12_OFS (12) /* CEPD12 Offset */\r
-#define CEPD12 (0x1000) /* Port disable */\r
-/* CE0CTL3[CEPD13] Bits */\r
-#define CEPD13_OFS (13) /* CEPD13 Offset */\r
-#define CEPD13 (0x2000) /* Port disable */\r
-/* CE0CTL3[CEPD14] Bits */\r
-#define CEPD14_OFS (14) /* CEPD14 Offset */\r
-#define CEPD14 (0x4000) /* Port disable */\r
-/* CE0CTL3[CEPD15] Bits */\r
-#define CEPD15_OFS (15) /* CEPD15 Offset */\r
-#define CEPD15 (0x8000) /* Port disable */\r
-/* CE0INT[CEIFG] Bits */\r
-#define CEIFG_OFS ( 0) /* CEIFG Offset */\r
-#define CEIFG (0x0001) /* Comparator output interrupt flag */\r
-/* CE0INT[CEIIFG] Bits */\r
-#define CEIIFG_OFS ( 1) /* CEIIFG Offset */\r
-#define CEIIFG (0x0002) /* Comparator output inverted interrupt flag */\r
-/* CE0INT[CERDYIFG] Bits */\r
-#define CERDYIFG_OFS ( 4) /* CERDYIFG Offset */\r
-#define CERDYIFG (0x0010) /* Comparator ready interrupt flag */\r
-/* CE0INT[CEIE] Bits */\r
-#define CEIE_OFS ( 8) /* CEIE Offset */\r
-#define CEIE (0x0100) /* Comparator output interrupt enable */\r
-/* CE0INT[CEIIE] Bits */\r
-#define CEIIE_OFS ( 9) /* CEIIE Offset */\r
-#define CEIIE (0x0200) /* Comparator output interrupt enable inverted polarity */\r
-/* CE0INT[CERDYIE] Bits */\r
-#define CERDYIE_OFS (12) /* CERDYIE Offset */\r
-#define CERDYIE (0x1000) /* Comparator ready interrupt enable */\r
-\r
-\r
-//*****************************************************************************\r
-// COMP_E1 Bits\r
-//*****************************************************************************\r
-/* CE1CTL0[CEIPSEL] Bits */\r
-//#define CEIPSEL_OFS ( 0) /* CEIPSEL Offset */\r
-//#define CEIPSEL_M (0x000f) /* Channel input selected for the V+ terminal */\r
-//#define CEIPSEL0 (0x0001) /* Channel input selected for the V+ terminal */\r
-//#define CEIPSEL1 (0x0002) /* Channel input selected for the V+ terminal */\r
-//#define CEIPSEL2 (0x0004) /* Channel input selected for the V+ terminal */\r
-//#define CEIPSEL3 (0x0008) /* Channel input selected for the V+ terminal */\r
-//#define CEIPSEL_0 (0x0000) /* Channel 0 selected */\r
-//#define CEIPSEL_1 (0x0001) /* Channel 1 selected */\r
-//#define CEIPSEL_2 (0x0002) /* Channel 2 selected */\r
-//#define CEIPSEL_3 (0x0003) /* Channel 3 selected */\r
-//#define CEIPSEL_4 (0x0004) /* Channel 4 selected */\r
-//#define CEIPSEL_5 (0x0005) /* Channel 5 selected */\r
-//#define CEIPSEL_6 (0x0006) /* Channel 6 selected */\r
-//#define CEIPSEL_7 (0x0007) /* Channel 7 selected */\r
-//#define CEIPSEL_8 (0x0008) /* Channel 8 selected */\r
-//#define CEIPSEL_9 (0x0009) /* Channel 9 selected */\r
-//#define CEIPSEL_10 (0x000a) /* Channel 10 selected */\r
-//#define CEIPSEL_11 (0x000b) /* Channel 11 selected */\r
-//#define CEIPSEL_12 (0x000c) /* Channel 12 selected */\r
-//#define CEIPSEL_13 (0x000d) /* Channel 13 selected */\r
-//#define CEIPSEL_14 (0x000e) /* Channel 14 selected */\r
-//#define CEIPSEL_15 (0x000f) /* Channel 15 selected */\r
-/* CE1CTL0[CEIPEN] Bits */\r
-//#define CEIPEN_OFS ( 7) /* CEIPEN Offset */\r
-//#define CEIPEN (0x0080) /* Channel input enable for the V+ terminal */\r
-/* CE1CTL0[CEIMSEL] Bits */\r
-//#define CEIMSEL_OFS ( 8) /* CEIMSEL Offset */\r
-//#define CEIMSEL_M (0x0f00) /* Channel input selected for the - terminal */\r
-//#define CEIMSEL0 (0x0100) /* Channel input selected for the - terminal */\r
-//#define CEIMSEL1 (0x0200) /* Channel input selected for the - terminal */\r
-//#define CEIMSEL2 (0x0400) /* Channel input selected for the - terminal */\r
-//#define CEIMSEL3 (0x0800) /* Channel input selected for the - terminal */\r
-//#define CEIMSEL_0 (0x0000) /* Channel 0 selected */\r
-//#define CEIMSEL_1 (0x0100) /* Channel 1 selected */\r
-//#define CEIMSEL_2 (0x0200) /* Channel 2 selected */\r
-//#define CEIMSEL_3 (0x0300) /* Channel 3 selected */\r
-//#define CEIMSEL_4 (0x0400) /* Channel 4 selected */\r
-//#define CEIMSEL_5 (0x0500) /* Channel 5 selected */\r
-//#define CEIMSEL_6 (0x0600) /* Channel 6 selected */\r
-//#define CEIMSEL_7 (0x0700) /* Channel 7 selected */\r
-//#define CEIMSEL_8 (0x0800) /* Channel 8 selected */\r
-//#define CEIMSEL_9 (0x0900) /* Channel 9 selected */\r
-//#define CEIMSEL_10 (0x0a00) /* Channel 10 selected */\r
-//#define CEIMSEL_11 (0x0b00) /* Channel 11 selected */\r
-//#define CEIMSEL_12 (0x0c00) /* Channel 12 selected */\r
-//#define CEIMSEL_13 (0x0d00) /* Channel 13 selected */\r
-//#define CEIMSEL_14 (0x0e00) /* Channel 14 selected */\r
-//#define CEIMSEL_15 (0x0f00) /* Channel 15 selected */\r
-/* CE1CTL0[CEIMEN] Bits */\r
-//#define CEIMEN_OFS (15) /* CEIMEN Offset */\r
-//#define CEIMEN (0x8000) /* Channel input enable for the - terminal */\r
-/* CE1CTL1[CEOUT] Bits */\r
-//#define CEOUT_OFS ( 0) /* CEOUT Offset */\r
-//#define CEOUT (0x0001) /* Comparator output value */\r
-/* CE1CTL1[CEOUTPOL] Bits */\r
-//#define CEOUTPOL_OFS ( 1) /* CEOUTPOL Offset */\r
-//#define CEOUTPOL (0x0002) /* Comparator output polarity */\r
-/* CE1CTL1[CEF] Bits */\r
-//#define CEF_OFS ( 2) /* CEF Offset */\r
-//#define CEF (0x0004) /* Comparator output filter */\r
-/* CE1CTL1[CEIES] Bits */\r
-//#define CEIES_OFS ( 3) /* CEIES Offset */\r
-//#define CEIES (0x0008) /* Interrupt edge select for CEIIFG and CEIFG */\r
-/* CE1CTL1[CESHORT] Bits */\r
-//#define CESHORT_OFS ( 4) /* CESHORT Offset */\r
-//#define CESHORT (0x0010) /* Input short */\r
-/* CE1CTL1[CEEX] Bits */\r
-//#define CEEX_OFS ( 5) /* CEEX Offset */\r
-//#define CEEX (0x0020) /* Exchange */\r
-/* CE1CTL1[CEFDLY] Bits */\r
-//#define CEFDLY_OFS ( 6) /* CEFDLY Offset */\r
-//#define CEFDLY_M (0x00c0) /* Filter delay */\r
-//#define CEFDLY0 (0x0040) /* Filter delay */\r
-//#define CEFDLY1 (0x0080) /* Filter delay */\r
-//#define CEFDLY_0 (0x0000) /* Typical filter delay of TBD (450) ns */\r
-//#define CEFDLY_1 (0x0040) /* Typical filter delay of TBD (900) ns */\r
-//#define CEFDLY_2 (0x0080) /* Typical filter delay of TBD (1800) ns */\r
-//#define CEFDLY_3 (0x00c0) /* Typical filter delay of TBD (3600) ns */\r
-/* CE1CTL1[CEPWRMD] Bits */\r
-//#define CEPWRMD_OFS ( 8) /* CEPWRMD Offset */\r
-//#define CEPWRMD_M (0x0300) /* Power Mode */\r
-//#define CEPWRMD0 (0x0100) /* Power Mode */\r
-//#define CEPWRMD1 (0x0200) /* Power Mode */\r
-//#define CEPWRMD_0 (0x0000) /* High-speed mode */\r
-//#define CEPWRMD_1 (0x0100) /* Normal mode */\r
-//#define CEPWRMD_2 (0x0200) /* Ultra-low power mode */\r
-/* CE1CTL1[CEON] Bits */\r
-//#define CEON_OFS (10) /* CEON Offset */\r
-//#define CEON (0x0400) /* Comparator On */\r
-/* CE1CTL1[CEMRVL] Bits */\r
-//#define CEMRVL_OFS (11) /* CEMRVL Offset */\r
-//#define CEMRVL (0x0800) /* This bit is valid of CEMRVS is set to 1 */\r
-/* CE1CTL1[CEMRVS] Bits */\r
-//#define CEMRVS_OFS (12) /* CEMRVS Offset */\r
-//#define CEMRVS (0x1000) /* */\r
-/* CE1CTL2[CEREF0] Bits */\r
-//#define CEREF0_OFS ( 0) /* CEREF0 Offset */\r
-//#define CEREF0_M (0x001f) /* Reference resistor tap 0 */\r
-/* CE1CTL2[CERSEL] Bits */\r
-//#define CERSEL_OFS ( 5) /* CERSEL Offset */\r
-//#define CERSEL (0x0020) /* Reference select */\r
-/* CE1CTL2[CERS] Bits */\r
-//#define CERS_OFS ( 6) /* CERS Offset */\r
-//#define CERS_M (0x00c0) /* Reference source */\r
-//#define CERS0 (0x0040) /* Reference source */\r
-//#define CERS1 (0x0080) /* Reference source */\r
-//#define CERS_0 (0x0000) /* No current is drawn by the reference circuitry */\r
-//#define CERS_1 (0x0040) /* VCC applied to the resistor ladder */\r
-//#define CERS_2 (0x0080) /* Shared reference voltage applied to the resistor ladder */\r
-//#define CERS_3 (0x00c0) /* Shared reference voltage supplied to V(CREF). Resistor ladder is off */\r
-/* CE1CTL2[CEREF1] Bits */\r
-//#define CEREF1_OFS ( 8) /* CEREF1 Offset */\r
-//#define CEREF1_M (0x1f00) /* Reference resistor tap 1 */\r
-/* CE1CTL2[CEREFL] Bits */\r
-//#define CEREFL_OFS (13) /* CEREFL Offset */\r
-//#define CEREFL_M (0x6000) /* Reference voltage level */\r
-//#define CEREFL0 (0x2000) /* Reference voltage level */\r
-//#define CEREFL1 (0x4000) /* Reference voltage level */\r
-//#define CEREFL_0 (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */\r
-//#define CEREFL_1 (0x2000) /* 1.2 V is selected as shared reference voltage input */\r
-//#define CEREFL_2 (0x4000) /* 2.0 V is selected as shared reference voltage input */\r
-//#define CEREFL_3 (0x6000) /* 2.5 V is selected as shared reference voltage input */\r
-//#define CEREFL__OFF (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */\r
-//#define CEREFL__1P2V (0x2000) /* 1.2 V is selected as shared reference voltage input */\r
-//#define CEREFL__2P0V (0x4000) /* 2.0 V is selected as shared reference voltage input */\r
-//#define CEREFL__2P5V (0x6000) /* 2.5 V is selected as shared reference voltage input */\r
-/* CE1CTL2[CEREFACC] Bits */\r
-//#define CEREFACC_OFS (15) /* CEREFACC Offset */\r
-//#define CEREFACC (0x8000) /* Reference accuracy */\r
-/* CE1CTL3[CEPD0] Bits */\r
-//#define CEPD0_OFS ( 0) /* CEPD0 Offset */\r
-//#define CEPD0 (0x0001) /* Port disable */\r
-/* CE1CTL3[CEPD1] Bits */\r
-//#define CEPD1_OFS ( 1) /* CEPD1 Offset */\r
-//#define CEPD1 (0x0002) /* Port disable */\r
-/* CE1CTL3[CEPD2] Bits */\r
-//#define CEPD2_OFS ( 2) /* CEPD2 Offset */\r
-//#define CEPD2 (0x0004) /* Port disable */\r
-/* CE1CTL3[CEPD3] Bits */\r
-//#define CEPD3_OFS ( 3) /* CEPD3 Offset */\r
-//#define CEPD3 (0x0008) /* Port disable */\r
-/* CE1CTL3[CEPD4] Bits */\r
-//#define CEPD4_OFS ( 4) /* CEPD4 Offset */\r
-//#define CEPD4 (0x0010) /* Port disable */\r
-/* CE1CTL3[CEPD5] Bits */\r
-//#define CEPD5_OFS ( 5) /* CEPD5 Offset */\r
-//#define CEPD5 (0x0020) /* Port disable */\r
-/* CE1CTL3[CEPD6] Bits */\r
-//#define CEPD6_OFS ( 6) /* CEPD6 Offset */\r
-//#define CEPD6 (0x0040) /* Port disable */\r
-/* CE1CTL3[CEPD7] Bits */\r
-//#define CEPD7_OFS ( 7) /* CEPD7 Offset */\r
-//#define CEPD7 (0x0080) /* Port disable */\r
-/* CE1CTL3[CEPD8] Bits */\r
-//#define CEPD8_OFS ( 8) /* CEPD8 Offset */\r
-//#define CEPD8 (0x0100) /* Port disable */\r
-/* CE1CTL3[CEPD9] Bits */\r
-//#define CEPD9_OFS ( 9) /* CEPD9 Offset */\r
-//#define CEPD9 (0x0200) /* Port disable */\r
-/* CE1CTL3[CEPD10] Bits */\r
-//#define CEPD10_OFS (10) /* CEPD10 Offset */\r
-//#define CEPD10 (0x0400) /* Port disable */\r
-/* CE1CTL3[CEPD11] Bits */\r
-//#define CEPD11_OFS (11) /* CEPD11 Offset */\r
-//#define CEPD11 (0x0800) /* Port disable */\r
-/* CE1CTL3[CEPD12] Bits */\r
-//#define CEPD12_OFS (12) /* CEPD12 Offset */\r
-//#define CEPD12 (0x1000) /* Port disable */\r
-/* CE1CTL3[CEPD13] Bits */\r
-//#define CEPD13_OFS (13) /* CEPD13 Offset */\r
-//#define CEPD13 (0x2000) /* Port disable */\r
-/* CE1CTL3[CEPD14] Bits */\r
-//#define CEPD14_OFS (14) /* CEPD14 Offset */\r
-//#define CEPD14 (0x4000) /* Port disable */\r
-/* CE1CTL3[CEPD15] Bits */\r
-//#define CEPD15_OFS (15) /* CEPD15 Offset */\r
-//#define CEPD15 (0x8000) /* Port disable */\r
-/* CE1INT[CEIFG] Bits */\r
-//#define CEIFG_OFS ( 0) /* CEIFG Offset */\r
-//#define CEIFG (0x0001) /* Comparator output interrupt flag */\r
-/* CE1INT[CEIIFG] Bits */\r
-//#define CEIIFG_OFS ( 1) /* CEIIFG Offset */\r
-//#define CEIIFG (0x0002) /* Comparator output inverted interrupt flag */\r
-/* CE1INT[CERDYIFG] Bits */\r
-//#define CERDYIFG_OFS ( 4) /* CERDYIFG Offset */\r
-//#define CERDYIFG (0x0010) /* Comparator ready interrupt flag */\r
-/* CE1INT[CEIE] Bits */\r
-//#define CEIE_OFS ( 8) /* CEIE Offset */\r
-//#define CEIE (0x0100) /* Comparator output interrupt enable */\r
-/* CE1INT[CEIIE] Bits */\r
-//#define CEIIE_OFS ( 9) /* CEIIE Offset */\r
-//#define CEIIE (0x0200) /* Comparator output interrupt enable inverted polarity */\r
-/* CE1INT[CERDYIE] Bits */\r
-//#define CERDYIE_OFS (12) /* CERDYIE Offset */\r
-//#define CERDYIE (0x1000) /* Comparator ready interrupt enable */\r
-\r
-\r
-//*****************************************************************************\r
-// COREDEBUG Bits\r
-//*****************************************************************************\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_DEBUGEN] Bits */\r
-#define COREDEBUG_DHCSR_C_DEBUGEN_OFS ( 0) /* C_DEBUGEN Offset */\r
-#define COREDEBUG_DHCSR_C_DEBUGEN (0x00000001) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_HALT] Bits */\r
-#define COREDEBUG_DHCSR_C_HALT_OFS ( 1) /* C_HALT Offset */\r
-#define COREDEBUG_DHCSR_C_HALT (0x00000002) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_STEP] Bits */\r
-#define COREDEBUG_DHCSR_C_STEP_OFS ( 2) /* C_STEP Offset */\r
-#define COREDEBUG_DHCSR_C_STEP (0x00000004) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_MASKINTS] Bits */\r
-#define COREDEBUG_DHCSR_C_MASKINTS_OFS ( 3) /* C_MASKINTS Offset */\r
-#define COREDEBUG_DHCSR_C_MASKINTS (0x00000008) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_SNAPSTALL] Bits */\r
-#define COREDEBUG_DHCSR_C_SNAPSTALL_OFS ( 5) /* C_SNAPSTALL Offset */\r
-#define COREDEBUG_DHCSR_C_SNAPSTALL (0x00000020) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_REGRDY] Bits */\r
-#define COREDEBUG_DHCSR_S_REGRDY_OFS (16) /* S_REGRDY Offset */\r
-#define COREDEBUG_DHCSR_S_REGRDY (0x00010000) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_HALT] Bits */\r
-#define COREDEBUG_DHCSR_S_HALT_OFS (17) /* S_HALT Offset */\r
-#define COREDEBUG_DHCSR_S_HALT (0x00020000) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_SLEEP] Bits */\r
-#define COREDEBUG_DHCSR_S_SLEEP_OFS (18) /* S_SLEEP Offset */\r
-#define COREDEBUG_DHCSR_S_SLEEP (0x00040000) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_LOCKUP] Bits */\r
-#define COREDEBUG_DHCSR_S_LOCKUP_OFS (19) /* S_LOCKUP Offset */\r
-#define COREDEBUG_DHCSR_S_LOCKUP (0x00080000) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_RETIRE_ST] Bits */\r
-#define COREDEBUG_DHCSR_S_RETIRE_ST_OFS (24) /* S_RETIRE_ST Offset */\r
-#define COREDEBUG_DHCSR_S_RETIRE_ST (0x01000000) /* */\r
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_RESET_ST] Bits */\r
-#define COREDEBUG_DHCSR_S_RESET_ST_OFS (25) /* S_RESET_ST Offset */\r
-#define COREDEBUG_DHCSR_S_RESET_ST (0x02000000) /* */\r
-/* COREDEBUG_DCRSR[COREDEBUG_DCRSR_REGSEL] Bits */\r
-#define COREDEBUG_DCRSR_REGSEL_OFS ( 0) /* REGSEL Offset */\r
-#define COREDEBUG_DCRSR_REGSEL_M (0x0000001f) /* */\r
-#define COREDEBUG_DCRSR_REGSEL0 (0x00000001) /* */\r
-#define COREDEBUG_DCRSR_REGSEL1 (0x00000002) /* */\r
-#define COREDEBUG_DCRSR_REGSEL2 (0x00000004) /* */\r
-#define COREDEBUG_DCRSR_REGSEL3 (0x00000008) /* */\r
-#define COREDEBUG_DCRSR_REGSEL4 (0x00000010) /* */\r
-#define COREDEBUG_DCRSR_REGSEL_0 (0x00000000) /* R11 */\r
-//#define COREDEBUG_DCRSR_REGSEL_0 (0x00000000) /* R0 */\r
-#define COREDEBUG_DCRSR_REGSEL_1 (0x00000001) /* R1 */\r
-#define COREDEBUG_DCRSR_REGSEL_2 (0x00000002) /* R2 */\r
-#define COREDEBUG_DCRSR_REGSEL_3 (0x00000003) /* R3 */\r
-#define COREDEBUG_DCRSR_REGSEL_4 (0x00000004) /* R4 */\r
-#define COREDEBUG_DCRSR_REGSEL_5 (0x00000005) /* R5 */\r
-#define COREDEBUG_DCRSR_REGSEL_6 (0x00000006) /* R6 */\r
-#define COREDEBUG_DCRSR_REGSEL_7 (0x00000007) /* R7 */\r
-#define COREDEBUG_DCRSR_REGSEL_8 (0x00000008) /* R8 */\r
-#define COREDEBUG_DCRSR_REGSEL_9 (0x00000009) /* R9 */\r
-#define COREDEBUG_DCRSR_REGSEL_10 (0x0000000a) /* R10 */\r
-#define COREDEBUG_DCRSR_REGSEL_12 (0x0000000c) /* R12 */\r
-#define COREDEBUG_DCRSR_REGSEL_13 (0x0000000d) /* Current SP */\r
-#define COREDEBUG_DCRSR_REGSEL_14 (0x0000000e) /* LR */\r
-#define COREDEBUG_DCRSR_REGSEL_15 (0x0000000f) /* DebugReturnAddress */\r
-#define COREDEBUG_DCRSR_REGSEL_16 (0x00000010) /* xPSR/flags, execution state information, and exception number */\r
-#define COREDEBUG_DCRSR_REGSEL_17 (0x00000011) /* MSP (Main SP) */\r
-#define COREDEBUG_DCRSR_REGSEL_18 (0x00000012) /* PSP (Process SP) */\r
-#define COREDEBUG_DCRSR_REGSEL_20 (0x00000014) /* CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0] */\r
-/* COREDEBUG_DCRSR[COREDEBUG_DCRSR_REGWNR] Bits */\r
-#define COREDEBUG_DCRSR_REGWNR_OFS (16) /* REGWNR Offset */\r
-#define COREDEBUG_DCRSR_REGWNR (0x00010000) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_CORERESET] Bits */\r
-#define COREDEBUG_DEMCR_VC_CORERESET_OFS ( 0) /* VC_CORERESET Offset */\r
-#define COREDEBUG_DEMCR_VC_CORERESET (0x00000001) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_MMERR] Bits */\r
-#define COREDEBUG_DEMCR_VC_MMERR_OFS ( 4) /* VC_MMERR Offset */\r
-#define COREDEBUG_DEMCR_VC_MMERR (0x00000010) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_NOCPERR] Bits */\r
-#define COREDEBUG_DEMCR_VC_NOCPERR_OFS ( 5) /* VC_NOCPERR Offset */\r
-#define COREDEBUG_DEMCR_VC_NOCPERR (0x00000020) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_CHKERR] Bits */\r
-#define COREDEBUG_DEMCR_VC_CHKERR_OFS ( 6) /* VC_CHKERR Offset */\r
-#define COREDEBUG_DEMCR_VC_CHKERR (0x00000040) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_STATERR] Bits */\r
-#define COREDEBUG_DEMCR_VC_STATERR_OFS ( 7) /* VC_STATERR Offset */\r
-#define COREDEBUG_DEMCR_VC_STATERR (0x00000080) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_BUSERR] Bits */\r
-#define COREDEBUG_DEMCR_VC_BUSERR_OFS ( 8) /* VC_BUSERR Offset */\r
-#define COREDEBUG_DEMCR_VC_BUSERR (0x00000100) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_INTERR] Bits */\r
-#define COREDEBUG_DEMCR_VC_INTERR_OFS ( 9) /* VC_INTERR Offset */\r
-#define COREDEBUG_DEMCR_VC_INTERR (0x00000200) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_HARDERR] Bits */\r
-#define COREDEBUG_DEMCR_VC_HARDERR_OFS (10) /* VC_HARDERR Offset */\r
-#define COREDEBUG_DEMCR_VC_HARDERR (0x00000400) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_EN] Bits */\r
-#define COREDEBUG_DEMCR_MON_EN_OFS (16) /* MON_EN Offset */\r
-#define COREDEBUG_DEMCR_MON_EN (0x00010000) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_PEND] Bits */\r
-#define COREDEBUG_DEMCR_MON_PEND_OFS (17) /* MON_PEND Offset */\r
-#define COREDEBUG_DEMCR_MON_PEND (0x00020000) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_STEP] Bits */\r
-#define COREDEBUG_DEMCR_MON_STEP_OFS (18) /* MON_STEP Offset */\r
-#define COREDEBUG_DEMCR_MON_STEP (0x00040000) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_REQ] Bits */\r
-#define COREDEBUG_DEMCR_MON_REQ_OFS (19) /* MON_REQ Offset */\r
-#define COREDEBUG_DEMCR_MON_REQ (0x00080000) /* */\r
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_TRCENA] Bits */\r
-#define COREDEBUG_DEMCR_TRCENA_OFS (24) /* TRCENA Offset */\r
-#define COREDEBUG_DEMCR_TRCENA (0x01000000) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// CRC32 Bits\r
-//*****************************************************************************\r
-\r
+#if defined ( __CC_ARM )\r
+#pragma no_anon_unions\r
+#endif\r
\r
-//*****************************************************************************\r
-// CS Bits\r
-//*****************************************************************************\r
-/* CSKEY[CSKEY] Bits */\r
-#define CSKEY_OFS ( 0) /* CSKEY Offset */\r
-#define CSKEY_M (0x0000ffff) /* Write xxxx_695Ah to unlock */\r
-/* CSCTL0[DCOTUNE] Bits */\r
-#define DCOTUNE_OFS ( 0) /* DCOTUNE Offset */\r
-#define DCOTUNE_M (0x00001fff) /* DCO frequency tuning select */\r
-/* CSCTL0[DCORSEL] Bits */\r
-#define DCORSEL_OFS (16) /* DCORSEL Offset */\r
-#define DCORSEL_M (0x00070000) /* DCO frequency range select */\r
-#define DCORSEL0 (0x00010000) /* DCO frequency range select */\r
-#define DCORSEL1 (0x00020000) /* DCO frequency range select */\r
-#define DCORSEL2 (0x00040000) /* DCO frequency range select */\r
-#define DCORSEL_0 (0x00000000) /* Nominal DCO Frequency Range (MHz): 1 to 2 */\r
-#define DCORSEL_1 (0x00010000) /* Nominal DCO Frequency Range (MHz): 2 to 4 */\r
-#define DCORSEL_2 (0x00020000) /* Nominal DCO Frequency Range (MHz): 4 to 8 */\r
-#define DCORSEL_3 (0x00030000) /* Nominal DCO Frequency Range (MHz): 8 to 16 */\r
-#define DCORSEL_4 (0x00040000) /* Nominal DCO Frequency Range (MHz): 16 to 32 */\r
-#define DCORSEL_5 (0x00050000) /* Nominal DCO Frequency Range (MHz): 32 to 64 */\r
-/* CSCTL0[DCORES] Bits */\r
-#define DCORES_OFS (22) /* DCORES Offset */\r
-#define DCORES (0x00400000) /* Enables the DCO external resistor mode */\r
-/* CSCTL0[DCOEN] Bits */\r
-#define DCOEN_OFS (23) /* DCOEN Offset */\r
-#define DCOEN (0x00800000) /* Enables the DCO oscillator */\r
-/* CSCTL0[DIS_DCO_DELAY_CNT] Bits */\r
-#define DIS_DCO_DELAY_CNT_OFS (24) /* DIS_DCO_DELAY_CNT Offset */\r
-#define DIS_DCO_DELAY_CNT (0x01000000) /* */\r
-/* CSCTL1[SELM] Bits */\r
-#define SELM_OFS ( 0) /* SELM Offset */\r
-#define SELM_M (0x00000007) /* Selects the MCLK source */\r
-#define SELM0 (0x00000001) /* Selects the MCLK source */\r
-#define SELM1 (0x00000002) /* Selects the MCLK source */\r
-#define SELM2 (0x00000004) /* Selects the MCLK source */\r
-#define SELM_0 (0x00000000) /* when LFXT available, otherwise REFOCLK */\r
-#define SELM_1 (0x00000001) /* */\r
-#define SELM_2 (0x00000002) /* */\r
-#define SELM_3 (0x00000003) /* */\r
-#define SELM_4 (0x00000004) /* */\r
-#define SELM_5 (0x00000005) /* when HFXT available, otherwise DCOCLK */\r
-#define SELM_6 (0x00000006) /* when HFXT2 available, otherwise DCOCLK */\r
-#define SELM__LFXTCLK (0x00000000) /* when LFXT available, otherwise REFOCLK */\r
-#define SELM__VLOCLK (0x00000001) /* */\r
-#define SELM__REFOCLK (0x00000002) /* */\r
-#define SELM__DCOCLK (0x00000003) /* */\r
-#define SELM__MODOSC (0x00000004) /* */\r
-#define SELM__HFXTCLK (0x00000005) /* when HFXT available, otherwise DCOCLK */\r
-#define SELM__HFXT2CLK (0x00000006) /* when HFXT2 available, otherwise DCOCLK */\r
-#define SELM_7 (0x00000007) /* for future use. Defaults to DCOCLK. Not recommended for use to ensure future compatibilities. */\r
-/* CSCTL1[SELS] Bits */\r
-#define SELS_OFS ( 4) /* SELS Offset */\r
-#define SELS_M (0x00000070) /* Selects the SMCLK and HSMCLK source */\r
-#define SELS0 (0x00000010) /* Selects the SMCLK and HSMCLK source */\r
-#define SELS1 (0x00000020) /* Selects the SMCLK and HSMCLK source */\r
-#define SELS2 (0x00000040) /* Selects the SMCLK and HSMCLK source */\r
-#define SELS_0 (0x00000000) /* when LFXT available, otherwise REFOCLK */\r
-#define SELS_1 (0x00000010) /* */\r
-#define SELS_2 (0x00000020) /* */\r
-#define SELS_3 (0x00000030) /* */\r
-#define SELS_4 (0x00000040) /* */\r
-#define SELS_5 (0x00000050) /* when HFXT available, otherwise DCOCLK */\r
-#define SELS_6 (0x00000060) /* when HFXT2 available, otherwise DCOCLK */\r
-#define SELS__LFXTCLK (0x00000000) /* when LFXT available, otherwise REFOCLK */\r
-#define SELS__VLOCLK (0x00000010) /* */\r
-#define SELS__REFOCLK (0x00000020) /* */\r
-#define SELS__DCOCLK (0x00000030) /* */\r
-#define SELS__MODOSC (0x00000040) /* */\r
-#define SELS__HFXTCLK (0x00000050) /* when HFXT available, otherwise DCOCLK */\r
-#define SELS__HFXT2CLK (0x00000060) /* when HFXT2 available, otherwise DCOCLK */\r
-#define SELS_7 (0x00000070) /* for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities. */\r
-/* CSCTL1[SELA] Bits */\r
-#define SELA_OFS ( 8) /* SELA Offset */\r
-#define SELA_M (0x00000700) /* Selects the ACLK source */\r
-#define SELA0 (0x00000100) /* Selects the ACLK source */\r
-#define SELA1 (0x00000200) /* Selects the ACLK source */\r
-#define SELA2 (0x00000400) /* Selects the ACLK source */\r
-#define SELA_0 (0x00000000) /* when LFXT available, otherwise REFOCLK */\r
-#define SELA_1 (0x00000100) /* */\r
-#define SELA_2 (0x00000200) /* */\r
-#define SELA__LFXTCLK (0x00000000) /* when LFXT available, otherwise REFOCLK */\r
-#define SELA__VLOCLK (0x00000100) /* */\r
-#define SELA__REFOCLK (0x00000200) /* */\r
-#define SELA_3 (0x00000300) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */\r
-#define SELA_4 (0x00000400) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */\r
-#define SELA_5 (0x00000500) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */\r
-#define SELA_6 (0x00000600) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */\r
-#define SELA_7 (0x00000700) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */\r
-/* CSCTL1[SELB] Bits */\r
-#define SELB_OFS (12) /* SELB Offset */\r
-#define SELB (0x00001000) /* Selects the BCLK source */\r
-/* CSCTL1[DIVM] Bits */\r
-#define DIVM_OFS (16) /* DIVM Offset */\r
-#define DIVM_M (0x00070000) /* MCLK source divider */\r
-#define DIVM0 (0x00010000) /* MCLK source divider */\r
-#define DIVM1 (0x00020000) /* MCLK source divider */\r
-#define DIVM2 (0x00040000) /* MCLK source divider */\r
-#define DIVM_0 (0x00000000) /* f(MCLK)/1 */\r
-#define DIVM_1 (0x00010000) /* f(MCLK)/2 */\r
-#define DIVM_2 (0x00020000) /* f(MCLK)/4 */\r
-#define DIVM_3 (0x00030000) /* f(MCLK)/8 */\r
-#define DIVM_4 (0x00040000) /* f(MCLK)/16 */\r
-#define DIVM_5 (0x00050000) /* f(MCLK)/32 */\r
-#define DIVM_6 (0x00060000) /* f(MCLK)/64 */\r
-#define DIVM_7 (0x00070000) /* f(MCLK)/128 */\r
-#define DIVM__1 (0x00000000) /* f(MCLK)/1 */\r
-#define DIVM__2 (0x00010000) /* f(MCLK)/2 */\r
-#define DIVM__4 (0x00020000) /* f(MCLK)/4 */\r
-#define DIVM__8 (0x00030000) /* f(MCLK)/8 */\r
-#define DIVM__16 (0x00040000) /* f(MCLK)/16 */\r
-#define DIVM__32 (0x00050000) /* f(MCLK)/32 */\r
-#define DIVM__64 (0x00060000) /* f(MCLK)/64 */\r
-#define DIVM__128 (0x00070000) /* f(MCLK)/128 */\r
-/* CSCTL1[DIVHS] Bits */\r
-#define DIVHS_OFS (20) /* DIVHS Offset */\r
-#define DIVHS_M (0x00700000) /* HSMCLK source divider */\r
-#define DIVHS0 (0x00100000) /* HSMCLK source divider */\r
-#define DIVHS1 (0x00200000) /* HSMCLK source divider */\r
-#define DIVHS2 (0x00400000) /* HSMCLK source divider */\r
-#define DIVHS_0 (0x00000000) /* f(HSMCLK)/1 */\r
-#define DIVHS_1 (0x00100000) /* f(HSMCLK)/2 */\r
-#define DIVHS_2 (0x00200000) /* f(HSMCLK)/4 */\r
-#define DIVHS_3 (0x00300000) /* f(HSMCLK)/8 */\r
-#define DIVHS_4 (0x00400000) /* f(HSMCLK)/16 */\r
-#define DIVHS_5 (0x00500000) /* f(HSMCLK)/32 */\r
-#define DIVHS_6 (0x00600000) /* f(HSMCLK)/64 */\r
-#define DIVHS_7 (0x00700000) /* f(HSMCLK)/128 */\r
-#define DIVHS__1 (0x00000000) /* f(HSMCLK)/1 */\r
-#define DIVHS__2 (0x00100000) /* f(HSMCLK)/2 */\r
-#define DIVHS__4 (0x00200000) /* f(HSMCLK)/4 */\r
-#define DIVHS__8 (0x00300000) /* f(HSMCLK)/8 */\r
-#define DIVHS__16 (0x00400000) /* f(HSMCLK)/16 */\r
-#define DIVHS__32 (0x00500000) /* f(HSMCLK)/32 */\r
-#define DIVHS__64 (0x00600000) /* f(HSMCLK)/64 */\r
-#define DIVHS__128 (0x00700000) /* f(HSMCLK)/128 */\r
-/* CSCTL1[DIVA] Bits */\r
-#define DIVA_OFS (24) /* DIVA Offset */\r
-#define DIVA_M (0x07000000) /* ACLK source divider */\r
-#define DIVA0 (0x01000000) /* ACLK source divider */\r
-#define DIVA1 (0x02000000) /* ACLK source divider */\r
-#define DIVA2 (0x04000000) /* ACLK source divider */\r
-#define DIVA_0 (0x00000000) /* f(ACLK)/1 */\r
-#define DIVA_1 (0x01000000) /* f(ACLK)/2 */\r
-#define DIVA_2 (0x02000000) /* f(ACLK)/4 */\r
-#define DIVA_3 (0x03000000) /* f(ACLK)/8 */\r
-#define DIVA_4 (0x04000000) /* f(ACLK)/16 */\r
-#define DIVA_5 (0x05000000) /* f(ACLK)/32 */\r
-#define DIVA_6 (0x06000000) /* f(ACLK)/64 */\r
-#define DIVA_7 (0x07000000) /* f(ACLK)/128 */\r
-#define DIVA__1 (0x00000000) /* f(ACLK)/1 */\r
-#define DIVA__2 (0x01000000) /* f(ACLK)/2 */\r
-#define DIVA__4 (0x02000000) /* f(ACLK)/4 */\r
-#define DIVA__8 (0x03000000) /* f(ACLK)/8 */\r
-#define DIVA__16 (0x04000000) /* f(ACLK)/16 */\r
-#define DIVA__32 (0x05000000) /* f(ACLK)/32 */\r
-#define DIVA__64 (0x06000000) /* f(ACLK)/64 */\r
-#define DIVA__128 (0x07000000) /* f(ACLK)/128 */\r
-/* CSCTL1[DIVS] Bits */\r
-#define DIVS_OFS (28) /* DIVS Offset */\r
-#define DIVS_M (0x70000000) /* SMCLK source divider */\r
-#define DIVS0 (0x10000000) /* SMCLK source divider */\r
-#define DIVS1 (0x20000000) /* SMCLK source divider */\r
-#define DIVS2 (0x40000000) /* SMCLK source divider */\r
-#define DIVS_0 (0x00000000) /* f(SMCLK)/1 */\r
-#define DIVS_1 (0x10000000) /* f(SMCLK)/2 */\r
-#define DIVS_2 (0x20000000) /* f(SMCLK)/4 */\r
-#define DIVS_3 (0x30000000) /* f(SMCLK)/8 */\r
-#define DIVS_4 (0x40000000) /* f(SMCLK)/16 */\r
-#define DIVS_5 (0x50000000) /* f(SMCLK)/32 */\r
-#define DIVS_6 (0x60000000) /* f(SMCLK)/64 */\r
-#define DIVS_7 (0x70000000) /* f(SMCLK)/128 */\r
-#define DIVS__1 (0x00000000) /* f(SMCLK)/1 */\r
-#define DIVS__2 (0x10000000) /* f(SMCLK)/2 */\r
-#define DIVS__4 (0x20000000) /* f(SMCLK)/4 */\r
-#define DIVS__8 (0x30000000) /* f(SMCLK)/8 */\r
-#define DIVS__16 (0x40000000) /* f(SMCLK)/16 */\r
-#define DIVS__32 (0x50000000) /* f(SMCLK)/32 */\r
-#define DIVS__64 (0x60000000) /* f(SMCLK)/64 */\r
-#define DIVS__128 (0x70000000) /* f(SMCLK)/128 */\r
-/* CSCTL2[LFXTDRIVE] Bits */\r
-#define LFXTDRIVE_OFS ( 0) /* LFXTDRIVE Offset */\r
-#define LFXTDRIVE_M (0x00000007) /* LFXT oscillator current can be adjusted to its drive needs */\r
-#define LFXTDRIVE0 (0x00000001) /* LFXT oscillator current can be adjusted to its drive needs */\r
-#define LFXTDRIVE1 (0x00000002) /* LFXT oscillator current can be adjusted to its drive needs */\r
-#define LFXTDRIVE2 (0x00000004) /* LFXT oscillator current can be adjusted to its drive needs */\r
-#define LFXTDRIVE_0 (0x00000000) /* Lowest current consumption. */\r
-#define LFXTDRIVE_1 (0x00000001) /* Increased drive strength LFXT oscillator. */\r
-#define LFXTDRIVE_2 (0x00000002) /* Increased drive strength LFXT oscillator. */\r
-#define LFXTDRIVE_3 (0x00000003) /* Increased drive strength LFXT oscillator. */\r
-#define LFXTDRIVE_4 (0x00000004) /* Increased drive strength LFXT oscillator. */\r
-#define LFXTDRIVE_5 (0x00000005) /* Increased drive strength LFXT oscillator. */\r
-#define LFXTDRIVE_6 (0x00000006) /* Increased drive strength LFXT oscillator. */\r
-#define LFXTDRIVE_7 (0x00000007) /* Maximum drive strength LFXT oscillator. */\r
-/* CSCTL2[LFXTAGCOFF] Bits */\r
-#define LFXTAGCOFF_OFS ( 7) /* LFXTAGCOFF Offset */\r
-#define LFXTAGCOFF (0x00000080) /* Disables the automatic gain control of the LFXT crystal */\r
-/* CSCTL2[LFXT_EN] Bits */\r
-#define LFXT_EN_OFS ( 8) /* LFXT_EN Offset */\r
-#define LFXT_EN (0x00000100) /* Turns on the LFXT oscillator regardless if used as a clock resource */\r
-/* CSCTL2[LFXTBYPASS] Bits */\r
-#define LFXTBYPASS_OFS ( 9) /* LFXTBYPASS Offset */\r
-#define LFXTBYPASS (0x00000200) /* LFXT bypass select */\r
-/* CSCTL2[HFXTDRIVE] Bits */\r
-#define HFXTDRIVE_OFS (16) /* HFXTDRIVE Offset */\r
-#define HFXTDRIVE (0x00010000) /* HFXT oscillator drive selection */\r
-/* CSCTL2[HFXTFREQ] Bits */\r
-#define HFXTFREQ_OFS (20) /* HFXTFREQ Offset */\r
-#define HFXTFREQ_M (0x00700000) /* HFXT frequency selection */\r
-#define HFXTFREQ0 (0x00100000) /* HFXT frequency selection */\r
-#define HFXTFREQ1 (0x00200000) /* HFXT frequency selection */\r
-#define HFXTFREQ2 (0x00400000) /* HFXT frequency selection */\r
-#define HFXTFREQ_0 (0x00000000) /* 1 MHz to 4 MHz */\r
-#define HFXTFREQ_1 (0x00100000) /* >4 MHz to 8 MHz */\r
-#define HFXTFREQ_2 (0x00200000) /* >8 MHz to 16 MHz */\r
-#define HFXTFREQ_3 (0x00300000) /* >16 MHz to 24 MHz */\r
-#define HFXTFREQ_4 (0x00400000) /* >24 MHz to 32 MHz */\r
-#define HFXTFREQ_5 (0x00500000) /* >32 MHz to 40 MHz */\r
-#define HFXTFREQ_6 (0x00600000) /* >40 MHz to 48 MHz */\r
-/* CSCTL2[HFXT_EN] Bits */\r
-#define HFXT_EN_OFS (24) /* HFXT_EN Offset */\r
-#define HFXT_EN (0x01000000) /* Turns on the HFXT oscillator regardless if used as a clock resource */\r
-/* CSCTL2[HFXTBYPASS] Bits */\r
-#define HFXTBYPASS_OFS (25) /* HFXTBYPASS Offset */\r
-#define HFXTBYPASS (0x02000000) /* HFXT bypass select */\r
-/* CSCTL3[FCNTLF] Bits */\r
-#define FCNTLF_OFS ( 0) /* FCNTLF Offset */\r
-#define FCNTLF_M (0x00000003) /* Start flag counter for LFXT */\r
-#define FCNTLF0 (0x00000001) /* Start flag counter for LFXT */\r
-#define FCNTLF1 (0x00000002) /* Start flag counter for LFXT */\r
-#define FCNTLF_0 (0x00000000) /* 4096 cycles */\r
-#define FCNTLF_1 (0x00000001) /* 8192 cycles */\r
-#define FCNTLF_2 (0x00000002) /* 16384 cycles */\r
-#define FCNTLF_3 (0x00000003) /* 32768 cycles */\r
-#define FCNTLF__4096 (0x00000000) /* 4096 cycles */\r
-#define FCNTLF__8192 (0x00000001) /* 8192 cycles */\r
-#define FCNTLF__16384 (0x00000002) /* 16384 cycles */\r
-#define FCNTLF__32768 (0x00000003) /* 32768 cycles */\r
-/* CSCTL3[RFCNTLF] Bits */\r
-#define RFCNTLF_OFS ( 2) /* RFCNTLF Offset */\r
-#define RFCNTLF (0x00000004) /* Reset start fault counter for LFXT */\r
-/* CSCTL3[FCNTLF_EN] Bits */\r
-#define FCNTLF_EN_OFS ( 3) /* FCNTLF_EN Offset */\r
-#define FCNTLF_EN (0x00000008) /* Enable start fault counter for LFXT */\r
-/* CSCTL3[FCNTHF] Bits */\r
-#define FCNTHF_OFS ( 4) /* FCNTHF Offset */\r
-#define FCNTHF_M (0x00000030) /* Start flag counter for HFXT */\r
-#define FCNTHF0 (0x00000010) /* Start flag counter for HFXT */\r
-#define FCNTHF1 (0x00000020) /* Start flag counter for HFXT */\r
-#define FCNTHF_0 (0x00000000) /* 2048 cycles */\r
-#define FCNTHF_1 (0x00000010) /* 4096 cycles */\r
-#define FCNTHF_2 (0x00000020) /* 8192 cycles */\r
-#define FCNTHF_3 (0x00000030) /* 16384 cycles */\r
-#define FCNTHF__2048 (0x00000000) /* 2048 cycles */\r
-#define FCNTHF__4096 (0x00000010) /* 4096 cycles */\r
-#define FCNTHF__8192 (0x00000020) /* 8192 cycles */\r
-#define FCNTHF__16384 (0x00000030) /* 16384 cycles */\r
-/* CSCTL3[RFCNTHF] Bits */\r
-#define RFCNTHF_OFS ( 6) /* RFCNTHF Offset */\r
-#define RFCNTHF (0x00000040) /* Reset start fault counter for HFXT */\r
-/* CSCTL3[FCNTHF_EN] Bits */\r
-#define FCNTHF_EN_OFS ( 7) /* FCNTHF_EN Offset */\r
-#define FCNTHF_EN (0x00000080) /* Enable start fault counter for HFXT */\r
-/* CSCTL3[FCNTHF2] Bits */\r
-#define FCNTHF2_OFS ( 8) /* FCNTHF2 Offset */\r
-#define FCNTHF2_M (0x00000300) /* Start flag counter for HFXT2 */\r
-#define FCNTHF20 (0x00000100) /* Start flag counter for HFXT2 */\r
-#define FCNTHF21 (0x00000200) /* Start flag counter for HFXT2 */\r
-#define FCNTHF2_0 (0x00000000) /* 2048 cycles */\r
-#define FCNTHF2_1 (0x00000100) /* 4096 cycles */\r
-#define FCNTHF2_2 (0x00000200) /* 8192 cycles */\r
-#define FCNTHF2_3 (0x00000300) /* 16384 cycles */\r
-#define FCNTHF2__2048 (0x00000000) /* 2048 cycles */\r
-#define FCNTHF2__4096 (0x00000100) /* 4096 cycles */\r
-#define FCNTHF2__8192 (0x00000200) /* 8192 cycles */\r
-#define FCNTHF2__16384 (0x00000300) /* 16384 cycles */\r
-/* CSCTL3[RFCNTHF2] Bits */\r
-#define RFCNTHF2_OFS (10) /* RFCNTHF2 Offset */\r
-#define RFCNTHF2 (0x00000400) /* Reset start fault counter for HFXT2 */\r
-/* CSCTL3[FCNTHF2_EN] Bits */\r
-#define FCNTHF2_EN_OFS (11) /* FCNTHF2_EN Offset */\r
-#define FCNTHF2_EN (0x00000800) /* Enable start fault counter for HFXT2 */\r
-/* CSCTL4[HFXT2DRIVE] Bits */\r
-#define HFXT2DRIVE_OFS ( 0) /* HFXT2DRIVE Offset */\r
-#define HFXT2DRIVE_M (0x00000007) /* HFXT2 oscillator current can be adjusted to its drive needs */\r
-#define HFXT2DRIVE0 (0x00000001) /* HFXT2 oscillator current can be adjusted to its drive needs */\r
-#define HFXT2DRIVE1 (0x00000002) /* HFXT2 oscillator current can be adjusted to its drive needs */\r
-#define HFXT2DRIVE2 (0x00000004) /* HFXT2 oscillator current can be adjusted to its drive needs */\r
-#define HFXT2DRIVE_0 (0x00000000) /* Lowest current consumption */\r
-#define HFXT2DRIVE_1 (0x00000001) /* Increased drive strength HFXT2 oscillator */\r
-#define HFXT2DRIVE_2 (0x00000002) /* Increased drive strength HFXT2 oscillator */\r
-#define HFXT2DRIVE_3 (0x00000003) /* Increased drive strength HFXT2 oscillator */\r
-#define HFXT2DRIVE_4 (0x00000004) /* Increased drive strength HFXT2 oscillator */\r
-#define HFXT2DRIVE_5 (0x00000005) /* Increased drive strength HFXT2 oscillator */\r
-#define HFXT2DRIVE_6 (0x00000006) /* Increased drive strength HFXT2 oscillator */\r
-#define HFXT2DRIVE_7 (0x00000007) /* Maximum drive strength HFXT2 oscillator */\r
-/* CSCTL4[HFXT2FREQ] Bits */\r
-#define HFXT2FREQ_OFS ( 4) /* HFXT2FREQ Offset */\r
-#define HFXT2FREQ_M (0x00000070) /* HFXT2 frequency selection */\r
-/* CSCTL4[HFXT2_EN] Bits */\r
-#define HFXT2_EN_OFS ( 8) /* HFXT2_EN Offset */\r
-#define HFXT2_EN (0x00000100) /* Turns on the HFXT2 oscillator */\r
-/* CSCTL4[HFXT2BYPASS] Bits */\r
-#define HFXT2BYPASS_OFS ( 9) /* HFXT2BYPASS Offset */\r
-#define HFXT2BYPASS (0x00000200) /* HFXT2 bypass select */\r
-/* CSCTL5[REFCNTSEL] Bits */\r
-#define REFCNTSEL_OFS ( 0) /* REFCNTSEL Offset */\r
-#define REFCNTSEL_M (0x00000007) /* Reference counter source select */\r
-/* CSCTL5[REFCNTPS] Bits */\r
-#define REFCNTPS_OFS ( 3) /* REFCNTPS Offset */\r
-#define REFCNTPS_M (0x00000038) /* Reference clock prescaler */\r
-/* CSCTL5[CALSTART] Bits */\r
-#define CALSTART_OFS ( 7) /* CALSTART Offset */\r
-#define CALSTART (0x00000080) /* Start clock calibration counters */\r
-/* CSCTL5[PERCNTSEL] Bits */\r
-#define PERCNTSEL_OFS ( 8) /* PERCNTSEL Offset */\r
-#define PERCNTSEL_M (0x00000700) /* Period counter source select */\r
-/* CSCTL6[PERCNT] Bits */\r
-#define PERCNT_OFS ( 0) /* PERCNT Offset */\r
-#define PERCNT_M (0x0000ffff) /* Calibration period counter */\r
-/* CSCTL7[REFCNT] Bits */\r
-#define REFCNT_OFS ( 0) /* REFCNT Offset */\r
-#define REFCNT_M (0x0000ffff) /* Calibration reference period counter */\r
-/* CSCLKEN[ACLK_EN] Bits */\r
-#define ACLK_EN_OFS ( 0) /* ACLK_EN Offset */\r
-#define ACLK_EN (0x00000001) /* ACLK system clock conditional request enable */\r
-/* CSCLKEN[MCLK_EN] Bits */\r
-#define MCLK_EN_OFS ( 1) /* MCLK_EN Offset */\r
-#define MCLK_EN (0x00000002) /* MCLK system clock conditional request enable */\r
-/* CSCLKEN[HSMCLK_EN] Bits */\r
-#define HSMCLK_EN_OFS ( 2) /* HSMCLK_EN Offset */\r
-#define HSMCLK_EN (0x00000004) /* HSMCLK system clock conditional request enable */\r
-/* CSCLKEN[SMCLK_EN] Bits */\r
-#define SMCLK_EN_OFS ( 3) /* SMCLK_EN Offset */\r
-#define SMCLK_EN (0x00000008) /* SMCLK system clock conditional request enable */\r
-/* CSCLKEN[VLO_EN] Bits */\r
-#define VLO_EN_OFS ( 8) /* VLO_EN Offset */\r
-#define VLO_EN (0x00000100) /* Turns on the VLO oscillator */\r
-/* CSCLKEN[REFO_EN] Bits */\r
-#define REFO_EN_OFS ( 9) /* REFO_EN Offset */\r
-#define REFO_EN (0x00000200) /* Turns on the REFO oscillator */\r
-/* CSCLKEN[MODOSC_EN] Bits */\r
-#define MODOSC_EN_OFS (10) /* MODOSC_EN Offset */\r
-#define MODOSC_EN (0x00000400) /* Turns on the MODOSC oscillator */\r
-/* CSCLKEN[REFOFSEL] Bits */\r
-#define REFOFSEL_OFS (15) /* REFOFSEL Offset */\r
-#define REFOFSEL (0x00008000) /* Selects REFO nominal frequency */\r
-/* CSSTAT[DCO_ON] Bits */\r
-#define DCO_ON_OFS ( 0) /* DCO_ON Offset */\r
-#define DCO_ON (0x00000001) /* DCO status */\r
-/* CSSTAT[DCOBIAS_ON] Bits */\r
-#define DCOBIAS_ON_OFS ( 1) /* DCOBIAS_ON Offset */\r
-#define DCOBIAS_ON (0x00000002) /* DCO bias status */\r
-/* CSSTAT[HFXT_ON] Bits */\r
-#define HFXT_ON_OFS ( 2) /* HFXT_ON Offset */\r
-#define HFXT_ON (0x00000004) /* HFXT status */\r
-/* CSSTAT[HFXT2_ON] Bits */\r
-#define HFXT2_ON_OFS ( 3) /* HFXT2_ON Offset */\r
-#define HFXT2_ON (0x00000008) /* HFXT2 status */\r
-/* CSSTAT[MODOSC_ON] Bits */\r
-#define MODOSC_ON_OFS ( 4) /* MODOSC_ON Offset */\r
-#define MODOSC_ON (0x00000010) /* MODOSC status */\r
-/* CSSTAT[VLO_ON] Bits */\r
-#define VLO_ON_OFS ( 5) /* VLO_ON Offset */\r
-#define VLO_ON (0x00000020) /* VLO status */\r
-/* CSSTAT[LFXT_ON] Bits */\r
-#define LFXT_ON_OFS ( 6) /* LFXT_ON Offset */\r
-#define LFXT_ON (0x00000040) /* LFXT status */\r
-/* CSSTAT[REFO_ON] Bits */\r
-#define REFO_ON_OFS ( 7) /* REFO_ON Offset */\r
-#define REFO_ON (0x00000080) /* REFO status */\r
-/* CSSTAT[ACLK_ON] Bits */\r
-#define ACLK_ON_OFS (16) /* ACLK_ON Offset */\r
-#define ACLK_ON (0x00010000) /* ACLK system clock status */\r
-/* CSSTAT[MCLK_ON] Bits */\r
-#define MCLK_ON_OFS (17) /* MCLK_ON Offset */\r
-#define MCLK_ON (0x00020000) /* MCLK system clock status */\r
-/* CSSTAT[HSMCLK_ON] Bits */\r
-#define HSMCLK_ON_OFS (18) /* HSMCLK_ON Offset */\r
-#define HSMCLK_ON (0x00040000) /* HSMCLK system clock status */\r
-/* CSSTAT[SMCLK_ON] Bits */\r
-#define SMCLK_ON_OFS (19) /* SMCLK_ON Offset */\r
-#define SMCLK_ON (0x00080000) /* SMCLK system clock status */\r
-/* CSSTAT[MODCLK_ON] Bits */\r
-#define MODCLK_ON_OFS (20) /* MODCLK_ON Offset */\r
-#define MODCLK_ON (0x00100000) /* MODCLK system clock status */\r
-/* CSSTAT[VLOCLK_ON] Bits */\r
-#define VLOCLK_ON_OFS (21) /* VLOCLK_ON Offset */\r
-#define VLOCLK_ON (0x00200000) /* VLOCLK system clock status */\r
-/* CSSTAT[LFXTCLK_ON] Bits */\r
-#define LFXTCLK_ON_OFS (22) /* LFXTCLK_ON Offset */\r
-#define LFXTCLK_ON (0x00400000) /* LFXTCLK system clock status */\r
-/* CSSTAT[REFOCLK_ON] Bits */\r
-#define REFOCLK_ON_OFS (23) /* REFOCLK_ON Offset */\r
-#define REFOCLK_ON (0x00800000) /* REFOCLK system clock status */\r
-/* CSSTAT[ACLK_READY] Bits */\r
-#define ACLK_READY_OFS (24) /* ACLK_READY Offset */\r
-#define ACLK_READY (0x01000000) /* ACLK Ready status */\r
-/* CSSTAT[MCLK_READY] Bits */\r
-#define MCLK_READY_OFS (25) /* MCLK_READY Offset */\r
-#define MCLK_READY (0x02000000) /* MCLK Ready status */\r
-/* CSSTAT[HSMCLK_READY] Bits */\r
-#define HSMCLK_READY_OFS (26) /* HSMCLK_READY Offset */\r
-#define HSMCLK_READY (0x04000000) /* HSMCLK Ready status */\r
-/* CSSTAT[SMCLK_READY] Bits */\r
-#define SMCLK_READY_OFS (27) /* SMCLK_READY Offset */\r
-#define SMCLK_READY (0x08000000) /* SMCLK Ready status */\r
-/* CSSTAT[BCLK_READY] Bits */\r
-#define BCLK_READY_OFS (28) /* BCLK_READY Offset */\r
-#define BCLK_READY (0x10000000) /* BCLK Ready status */\r
-/* CSIE[LFXTIE] Bits */\r
-#define LFXTIE_OFS ( 0) /* LFXTIE Offset */\r
-#define LFXTIE (0x00000001) /* LFXT oscillator fault flag interrupt enable */\r
-/* CSIE[HFXTIE] Bits */\r
-#define HFXTIE_OFS ( 1) /* HFXTIE Offset */\r
-#define HFXTIE (0x00000002) /* HFXT oscillator fault flag interrupt enable */\r
-/* CSIE[HFXT2IE] Bits */\r
-#define HFXT2IE_OFS ( 2) /* HFXT2IE Offset */\r
-#define HFXT2IE (0x00000004) /* HFXT2 oscillator fault flag interrupt enable */\r
-/* CSIE[DCOMINIE] Bits */\r
-#define DCOMINIE_OFS ( 4) /* DCOMINIE Offset */\r
-#define DCOMINIE (0x00000010) /* DCO minimum fault flag interrupt enable */\r
-/* CSIE[DCOMAXIE] Bits */\r
-#define DCOMAXIE_OFS ( 5) /* DCOMAXIE Offset */\r
-#define DCOMAXIE (0x00000020) /* DCO maximum fault flag interrupt enable */\r
-/* CSIE[DCORIE] Bits */\r
-#define DCORIE_OFS ( 6) /* DCORIE Offset */\r
-#define DCORIE (0x00000040) /* DCO external resistor fault flag interrupt enable */\r
-/* CSIE[FCNTLFIE] Bits */\r
-#define FCNTLFIE_OFS ( 8) /* FCNTLFIE Offset */\r
-#define FCNTLFIE (0x00000100) /* Start fault counter interrupt enable LFXT */\r
-/* CSIE[FCNTHFIE] Bits */\r
-#define FCNTHFIE_OFS ( 9) /* FCNTHFIE Offset */\r
-#define FCNTHFIE (0x00000200) /* Start fault counter interrupt enable HFXT */\r
-/* CSIE[FCNTHF2IE] Bits */\r
-#define FCNTHF2IE_OFS (10) /* FCNTHF2IE Offset */\r
-#define FCNTHF2IE (0x00000400) /* Start fault counter interrupt enable HFXT2 */\r
-/* CSIE[PLLOOLIE] Bits */\r
-#define PLLOOLIE_OFS (12) /* PLLOOLIE Offset */\r
-#define PLLOOLIE (0x00001000) /* PLL out-of-lock interrupt enable */\r
-/* CSIE[PLLLOSIE] Bits */\r
-#define PLLLOSIE_OFS (13) /* PLLLOSIE Offset */\r
-#define PLLLOSIE (0x00002000) /* PLL loss-of-signal interrupt enable */\r
-/* CSIE[PLLOORIE] Bits */\r
-#define PLLOORIE_OFS (14) /* PLLOORIE Offset */\r
-#define PLLOORIE (0x00004000) /* PLL out-of-range interrupt enable */\r
-/* CSIE[CALIE] Bits */\r
-#define CALIE_OFS (15) /* CALIE Offset */\r
-#define CALIE (0x00008000) /* REFCNT period counter interrupt enable */\r
-/* CSIFG[LFXTIFG] Bits */\r
-#define LFXTIFG_OFS ( 0) /* LFXTIFG Offset */\r
-#define LFXTIFG (0x00000001) /* LFXT oscillator fault flag */\r
-/* CSIFG[HFXTIFG] Bits */\r
-#define HFXTIFG_OFS ( 1) /* HFXTIFG Offset */\r
-#define HFXTIFG (0x00000002) /* HFXT oscillator fault flag */\r
-/* CSIFG[HFXT2IFG] Bits */\r
-#define HFXT2IFG_OFS ( 2) /* HFXT2IFG Offset */\r
-#define HFXT2IFG (0x00000004) /* HFXT2 oscillator fault flag */\r
-/* CSIFG[DCOMINIFG] Bits */\r
-#define DCOMINIFG_OFS ( 4) /* DCOMINIFG Offset */\r
-#define DCOMINIFG (0x00000010) /* DCO minimum fault flag */\r
-/* CSIFG[DCOMAXIFG] Bits */\r
-#define DCOMAXIFG_OFS ( 5) /* DCOMAXIFG Offset */\r
-#define DCOMAXIFG (0x00000020) /* DCO maximum fault flag */\r
-/* CSIFG[DCORIFG] Bits */\r
-#define DCORIFG_OFS ( 6) /* DCORIFG Offset */\r
-#define DCORIFG (0x00000040) /* DCO external resistor fault flag */\r
-/* CSIFG[FCNTLFIFG] Bits */\r
-#define FCNTLFIFG_OFS ( 8) /* FCNTLFIFG Offset */\r
-#define FCNTLFIFG (0x00000100) /* Start fault counter interrupt flag LFXT */\r
-/* CSIFG[FCNTHFIFG] Bits */\r
-#define FCNTHFIFG_OFS ( 9) /* FCNTHFIFG Offset */\r
-#define FCNTHFIFG (0x00000200) /* Start fault counter interrupt flag HFXT */\r
-/* CSIFG[FCNTHF2IFG] Bits */\r
-#define FCNTHF2IFG_OFS (11) /* FCNTHF2IFG Offset */\r
-#define FCNTHF2IFG (0x00000800) /* Start fault counter interrupt flag HFXT2 */\r
-/* CSIFG[PLLOOLIFG] Bits */\r
-#define PLLOOLIFG_OFS (12) /* PLLOOLIFG Offset */\r
-#define PLLOOLIFG (0x00001000) /* PLL out-of-lock interrupt flag */\r
-/* CSIFG[PLLLOSIFG] Bits */\r
-#define PLLLOSIFG_OFS (13) /* PLLLOSIFG Offset */\r
-#define PLLLOSIFG (0x00002000) /* PLL loss-of-signal interrupt flag */\r
-/* CSIFG[PLLOORIFG] Bits */\r
-#define PLLOORIFG_OFS (14) /* PLLOORIFG Offset */\r
-#define PLLOORIFG (0x00004000) /* PLL out-of-range interrupt flag */\r
-/* CSIFG[CALIFG] Bits */\r
-#define CALIFG_OFS (15) /* CALIFG Offset */\r
-#define CALIFG (0x00008000) /* REFCNT period counter expired */\r
-/* CSCLRIFG[CLR_LFXTIFG] Bits */\r
-#define CLR_LFXTIFG_OFS ( 0) /* CLR_LFXTIFG Offset */\r
-#define CLR_LFXTIFG (0x00000001) /* Clear LFXT oscillator fault interrupt flag */\r
-/* CSCLRIFG[CLR_HFXTIFG] Bits */\r
-#define CLR_HFXTIFG_OFS ( 1) /* CLR_HFXTIFG Offset */\r
-#define CLR_HFXTIFG (0x00000002) /* Clear HFXT oscillator fault interrupt flag */\r
-/* CSCLRIFG[CLR_HFXT2IFG] Bits */\r
-#define CLR_HFXT2IFG_OFS ( 2) /* CLR_HFXT2IFG Offset */\r
-#define CLR_HFXT2IFG (0x00000004) /* Clear HFXT2 oscillator fault interrupt flag */\r
-/* CSCLRIFG[CLR_DCOMAXIFG] Bits */\r
-#define CLR_DCOMAXIFG_OFS ( 5) /* CLR_DCOMAXIFG Offset */\r
-#define CLR_DCOMAXIFG (0x00000020) /* Clear DCO maximum fault interrupt flag */\r
-/* CSCLRIFG[CLR_DCORIFG] Bits */\r
-#define CLR_DCORIFG_OFS ( 6) /* CLR_DCORIFG Offset */\r
-#define CLR_DCORIFG (0x00000040) /* Clear DCO external resistor fault interrupt flag */\r
-/* CSCLRIFG[CLR_CALIFG] Bits */\r
-#define CLR_CALIFG_OFS ( 7) /* CLR_CALIFG Offset */\r
-#define CLR_CALIFG (0x00000080) /* REFCNT period counter clear interrupt flag */\r
-/* CSCLRIFG[CLR_DCOMINIFG] Bits */\r
-#define CLR_DCOMINIFG_OFS ( 4) /* CLR_DCOMINIFG Offset */\r
-#define CLR_DCOMINIFG (0x00000010) /* Clear DCO minimum fault interrupt flag */\r
-/* CSCLRIFG[CLR_FCNTLFIFG] Bits */\r
-#define CLR_FCNTLFIFG_OFS ( 8) /* CLR_FCNTLFIFG Offset */\r
-#define CLR_FCNTLFIFG (0x00000100) /* Start fault counter clear interrupt flag LFXT */\r
-/* CSCLRIFG[CLR_FCNTHFIFG] Bits */\r
-#define CLR_FCNTHFIFG_OFS ( 9) /* CLR_FCNTHFIFG Offset */\r
-#define CLR_FCNTHFIFG (0x00000200) /* Start fault counter clear interrupt flag HFXT */\r
-/* CSCLRIFG[CLR_FCNTHF2IFG] Bits */\r
-#define CLR_FCNTHF2IFG_OFS (10) /* CLR_FCNTHF2IFG Offset */\r
-#define CLR_FCNTHF2IFG (0x00000400) /* Start fault counter clear interrupt flag HFXT2 */\r
-/* CSCLRIFG[CLR_PLLOOLIFG] Bits */\r
-#define CLR_PLLOOLIFG_OFS (12) /* CLR_PLLOOLIFG Offset */\r
-#define CLR_PLLOOLIFG (0x00001000) /* PLL out-of-lock clear interrupt flag */\r
-/* CSCLRIFG[CLR_PLLLOSIFG] Bits */\r
-#define CLR_PLLLOSIFG_OFS (13) /* CLR_PLLLOSIFG Offset */\r
-#define CLR_PLLLOSIFG (0x00002000) /* PLL loss-of-signal clear interrupt flag */\r
-/* CSCLRIFG[CLR_PLLOORIFG] Bits */\r
-#define CLR_PLLOORIFG_OFS (14) /* CLR_PLLOORIFG Offset */\r
-#define CLR_PLLOORIFG (0x00004000) /* PLL out-of-range clear interrupt flag */\r
-/* CSSETIFG[SET_LFXTIFG] Bits */\r
-#define SET_LFXTIFG_OFS ( 0) /* SET_LFXTIFG Offset */\r
-#define SET_LFXTIFG (0x00000001) /* Set LFXT oscillator fault interrupt flag */\r
-/* CSSETIFG[SET_HFXTIFG] Bits */\r
-#define SET_HFXTIFG_OFS ( 1) /* SET_HFXTIFG Offset */\r
-#define SET_HFXTIFG (0x00000002) /* Set HFXT oscillator fault interrupt flag */\r
-/* CSSETIFG[SET_HFXT2IFG] Bits */\r
-#define SET_HFXT2IFG_OFS ( 2) /* SET_HFXT2IFG Offset */\r
-#define SET_HFXT2IFG (0x00000004) /* Set HFXT2 oscillator fault interrupt flag */\r
-/* CSSETIFG[SET_DCOMINIFG] Bits */\r
-#define SET_DCOMINIFG_OFS ( 4) /* SET_DCOMINIFG Offset */\r
-#define SET_DCOMINIFG (0x00000010) /* Set DCO minimum fault interrupt flag */\r
-/* CSSETIFG[SET_DCOMAXIFG] Bits */\r
-#define SET_DCOMAXIFG_OFS ( 5) /* SET_DCOMAXIFG Offset */\r
-#define SET_DCOMAXIFG (0x00000020) /* Set DCO maximum fault interrupt flag */\r
-/* CSSETIFG[SET_DCORIFG] Bits */\r
-#define SET_DCORIFG_OFS ( 6) /* SET_DCORIFG Offset */\r
-#define SET_DCORIFG (0x00000040) /* Set DCO external resistor fault interrupt flag */\r
-/* CSSETIFG[SET_CALIFG] Bits */\r
-#define SET_CALIFG_OFS ( 7) /* SET_CALIFG Offset */\r
-#define SET_CALIFG (0x00000080) /* REFCNT period counter set interrupt flag */\r
-/* CSSETIFG[SET_FCNTHFIFG] Bits */\r
-#define SET_FCNTHFIFG_OFS ( 9) /* SET_FCNTHFIFG Offset */\r
-#define SET_FCNTHFIFG (0x00000200) /* Start fault counter set interrupt flag HFXT */\r
-/* CSSETIFG[SET_FCNTHF2IFG] Bits */\r
-#define SET_FCNTHF2IFG_OFS (10) /* SET_FCNTHF2IFG Offset */\r
-#define SET_FCNTHF2IFG (0x00000400) /* Start fault counter set interrupt flag HFXT2 */\r
-/* CSSETIFG[SET_FCNTLFIFG] Bits */\r
-#define SET_FCNTLFIFG_OFS ( 8) /* SET_FCNTLFIFG Offset */\r
-#define SET_FCNTLFIFG (0x00000100) /* Start fault counter set interrupt flag LFXT */\r
-/* CSSETIFG[SET_PLLOOLIFG] Bits */\r
-#define SET_PLLOOLIFG_OFS (12) /* SET_PLLOOLIFG Offset */\r
-#define SET_PLLOOLIFG (0x00001000) /* PLL out-of-lock set interrupt flag */\r
-/* CSSETIFG[SET_PLLLOSIFG] Bits */\r
-#define SET_PLLLOSIFG_OFS (13) /* SET_PLLLOSIFG Offset */\r
-#define SET_PLLLOSIFG (0x00002000) /* PLL loss-of-signal set interrupt flag */\r
-/* CSSETIFG[SET_PLLOORIFG] Bits */\r
-#define SET_PLLOORIFG_OFS (14) /* SET_PLLOORIFG Offset */\r
-#define SET_PLLOORIFG (0x00004000) /* PLL out-of-range set interrupt flag */\r
-/* CSDCOERCAL[DCO_TCTRIM] Bits */\r
-#define DCO_TCTRIM_OFS ( 0) /* DCO_TCTRIM Offset */\r
-#define DCO_TCTRIM_M (0x00000003) /* DCO Temperature compensation Trim */\r
-/* CSDCOERCAL[DCO_FTRIM] Bits */\r
-#define DCO_FTRIM_OFS (16) /* DCO_FTRIM Offset */\r
-#define DCO_FTRIM_M (0x07ff0000) /* DCO frequency trim */\r
+/*@}*/ /* end of group MSP432P401R_Peripherals */\r
+\r
+/******************************************************************************\r
+* Peripheral declaration *\r
+******************************************************************************/\r
+/** @addtogroup MSP432P401R_PeripheralDecl MSP432P401R Peripheral Declaration\r
+ @{\r
+*/\r
+\r
+#define ADC14 ((ADC14_Type *) ADC14_BASE) \r
+#define AES256 ((AES256_Type *) AES256_BASE) \r
+#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE)\r
+#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE)\r
+#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE)\r
+#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE)\r
+#define CRC32 ((CRC32_Type *) CRC32_BASE) \r
+#define CS ((CS_Type *) CS_BASE) \r
+#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000))\r
+#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020))\r
+#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040))\r
+#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060))\r
+#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080))\r
+#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120))\r
+#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000))\r
+#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000))\r
+#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020))\r
+#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020))\r
+#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040))\r
+#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040))\r
+#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060))\r
+#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060))\r
+#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080))\r
+#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080))\r
+#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE)\r
+#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000))\r
+#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE)\r
+#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE)\r
+#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE)\r
+#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE)\r
+#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE)\r
+#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE)\r
+#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE)\r
+#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE)\r
+#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE)\r
+#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE)\r
+#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE)\r
+#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE)\r
+#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE)\r
+#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE)\r
+#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE)\r
+#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE)\r
+#define FLCTL ((FLCTL_Type *) FLCTL_BASE) \r
+#define PCM ((PCM_Type *) PCM_BASE) \r
+#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE)\r
+#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008))\r
+#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010))\r
+#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018))\r
+#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020))\r
+#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028))\r
+#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030))\r
+#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038))\r
+#define PSS ((PSS_Type *) PSS_BASE) \r
+#define REF_A ((REF_A_Type *) REF_A_BASE) \r
+#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) \r
+#define RTC_C ((RTC_C_Type *) RTC_C_BASE) \r
+#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE)\r
+#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE)\r
+#define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000))\r
+#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE)\r
+#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020))\r
+#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE)\r
+#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE)\r
+#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE)\r
+#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE)\r
+#define TLV ((TLV_Type *) TLV_BASE) \r
+#define WDT_A ((WDT_A_Type *) WDT_A_BASE) \r
+\r
+\r
+/*@}*/ /* end of group MSP432P401R_PeripheralDecl */\r
+\r
+/*@}*/ /* end of group MSP432P401R_Definitions */\r
+\r
+#endif /* __CMSIS_CONFIG__ */\r
+\r
+/******************************************************************************\r
+* Peripheral register control bits *\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+* ADC14 Bits\r
+******************************************************************************/\r
+/* ADC14_CTL0[SC] Bits */\r
+#define ADC14_CTL0_SC_OFS ( 0) /**< ADC14SC Bit Offset */\r
+#define ADC14_CTL0_SC ((uint32_t)0x00000001) /**< ADC14 start conversion */\r
+/* ADC14_CTL0[ENC] Bits */\r
+#define ADC14_CTL0_ENC_OFS ( 1) /**< ADC14ENC Bit Offset */\r
+#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /**< ADC14 enable conversion */\r
+/* ADC14_CTL0[ON] Bits */\r
+#define ADC14_CTL0_ON_OFS ( 4) /**< ADC14ON Bit Offset */\r
+#define ADC14_CTL0_ON ((uint32_t)0x00000010) /**< ADC14 on */\r
+/* ADC14_CTL0[MSC] Bits */\r
+#define ADC14_CTL0_MSC_OFS ( 7) /**< ADC14MSC Bit Offset */\r
+#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /**< ADC14 multiple sample and conversion */\r
+/* ADC14_CTL0[SHT0] Bits */\r
+#define ADC14_CTL0_SHT0_OFS ( 8) /**< ADC14SHT0 Bit Offset */\r
+#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /**< ADC14SHT0 Bit Mask */\r
+#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /**< SHT0 Bit 0 */\r
+#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /**< SHT0 Bit 1 */\r
+#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /**< SHT0 Bit 2 */\r
+#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /**< SHT0 Bit 3 */\r
+#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /**< 4 */\r
+#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /**< 8 */\r
+#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /**< 16 */\r
+#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /**< 32 */\r
+#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /**< 64 */\r
+#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /**< 96 */\r
+#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /**< 128 */\r
+#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /**< 192 */\r
+#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /**< 4 */\r
+#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /**< 8 */\r
+#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /**< 16 */\r
+#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /**< 32 */\r
+#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /**< 64 */\r
+#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /**< 96 */\r
+#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /**< 128 */\r
+#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /**< 192 */\r
+/* ADC14_CTL0[SHT1] Bits */\r
+#define ADC14_CTL0_SHT1_OFS (12) /**< ADC14SHT1 Bit Offset */\r
+#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /**< ADC14SHT1 Bit Mask */\r
+#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /**< SHT1 Bit 0 */\r
+#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /**< SHT1 Bit 1 */\r
+#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /**< SHT1 Bit 2 */\r
+#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /**< SHT1 Bit 3 */\r
+#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /**< 4 */\r
+#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /**< 8 */\r
+#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /**< 16 */\r
+#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /**< 32 */\r
+#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /**< 64 */\r
+#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /**< 96 */\r
+#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /**< 128 */\r
+#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /**< 192 */\r
+#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /**< 4 */\r
+#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /**< 8 */\r
+#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /**< 16 */\r
+#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /**< 32 */\r
+#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /**< 64 */\r
+#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /**< 96 */\r
+#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /**< 128 */\r
+#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /**< 192 */\r
+/* ADC14_CTL0[BUSY] Bits */\r
+#define ADC14_CTL0_BUSY_OFS (16) /**< ADC14BUSY Bit Offset */\r
+#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /**< ADC14 busy */\r
+/* ADC14_CTL0[CONSEQ] Bits */\r
+#define ADC14_CTL0_CONSEQ_OFS (17) /**< ADC14CONSEQ Bit Offset */\r
+#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /**< ADC14CONSEQ Bit Mask */\r
+#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /**< CONSEQ Bit 0 */\r
+#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /**< CONSEQ Bit 1 */\r
+#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /**< Single-channel, single-conversion */\r
+#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /**< Sequence-of-channels */\r
+#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /**< Repeat-single-channel */\r
+#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /**< Repeat-sequence-of-channels */\r
+/* ADC14_CTL0[SSEL] Bits */\r
+#define ADC14_CTL0_SSEL_OFS (19) /**< ADC14SSEL Bit Offset */\r
+#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /**< ADC14SSEL Bit Mask */\r
+#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /**< SSEL Bit 0 */\r
+#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /**< SSEL Bit 1 */\r
+#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /**< SSEL Bit 2 */\r
+#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /**< MODCLK */\r
+#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /**< SYSCLK */\r
+#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /**< ACLK */\r
+#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /**< MCLK */\r
+#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /**< SMCLK */\r
+#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /**< HSMCLK */\r
+#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /**< MODCLK */\r
+#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /**< SYSCLK */\r
+#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /**< ACLK */\r
+#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /**< MCLK */\r
+#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /**< SMCLK */\r
+#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /**< HSMCLK */\r
+/* ADC14_CTL0[DIV] Bits */\r
+#define ADC14_CTL0_DIV_OFS (22) /**< ADC14DIV Bit Offset */\r
+#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /**< ADC14DIV Bit Mask */\r
+#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /**< DIV Bit 0 */\r
+#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /**< DIV Bit 1 */\r
+#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /**< DIV Bit 2 */\r
+#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /**< /1 */\r
+#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /**< /2 */\r
+#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /**< /3 */\r
+#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /**< /4 */\r
+#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /**< /5 */\r
+#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /**< /6 */\r
+#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /**< /7 */\r
+#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /**< /8 */\r
+#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /**< /1 */\r
+#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /**< /2 */\r
+#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /**< /3 */\r
+#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /**< /4 */\r
+#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /**< /5 */\r
+#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /**< /6 */\r
+#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /**< /7 */\r
+#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /**< /8 */\r
+/* ADC14_CTL0[ISSH] Bits */\r
+#define ADC14_CTL0_ISSH_OFS (25) /**< ADC14ISSH Bit Offset */\r
+#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /**< ADC14 invert signal sample-and-hold */\r
+/* ADC14_CTL0[SHP] Bits */\r
+#define ADC14_CTL0_SHP_OFS (26) /**< ADC14SHP Bit Offset */\r
+#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /**< ADC14 sample-and-hold pulse-mode select */\r
+/* ADC14_CTL0[SHS] Bits */\r
+#define ADC14_CTL0_SHS_OFS (27) /**< ADC14SHS Bit Offset */\r
+#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /**< ADC14SHS Bit Mask */\r
+#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /**< SHS Bit 0 */\r
+#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /**< SHS Bit 1 */\r
+#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /**< SHS Bit 2 */\r
+#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /**< ADC14SC bit */\r
+#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /**< See device-specific data sheet for source */\r
+#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /**< See device-specific data sheet for source */\r
+#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /**< See device-specific data sheet for source */\r
+#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /**< See device-specific data sheet for source */\r
+#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /**< See device-specific data sheet for source */\r
+#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /**< See device-specific data sheet for source */\r
+#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /**< See device-specific data sheet for source */\r
+/* ADC14_CTL0[PDIV] Bits */\r
+#define ADC14_CTL0_PDIV_OFS (30) /**< ADC14PDIV Bit Offset */\r
+#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /**< ADC14PDIV Bit Mask */\r
+#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /**< PDIV Bit 0 */\r
+#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /**< PDIV Bit 1 */\r
+#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /**< Predivide by 1 */\r
+#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /**< Predivide by 4 */\r
+#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /**< Predivide by 32 */\r
+#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /**< Predivide by 64 */\r
+#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /**< Predivide by 1 */\r
+#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /**< Predivide by 4 */\r
+#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /**< Predivide by 32 */\r
+#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /**< Predivide by 64 */\r
+/* ADC14_CTL1[PWRMD] Bits */\r
+#define ADC14_CTL1_PWRMD_OFS ( 0) /**< ADC14PWRMD Bit Offset */\r
+#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /**< ADC14PWRMD Bit Mask */\r
+#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /**< PWRMD Bit 0 */\r
+#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /**< PWRMD Bit 1 */\r
+#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /**< Regular power mode for use with any resolution setting. Sample rate can be up */\r
+ /* to 1 Msps. */\r
+#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /**< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate */\r
+ /* must not exceed 200 ksps. */\r
+/* ADC14_CTL1[REFBURST] Bits */\r
+#define ADC14_CTL1_REFBURST_OFS ( 2) /**< ADC14REFBURST Bit Offset */\r
+#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /**< ADC14 reference buffer burst */\r
+/* ADC14_CTL1[DF] Bits */\r
+#define ADC14_CTL1_DF_OFS ( 3) /**< ADC14DF Bit Offset */\r
+#define ADC14_CTL1_DF ((uint32_t)0x00000008) /**< ADC14 data read-back format */\r
+/* ADC14_CTL1[RES] Bits */\r
+#define ADC14_CTL1_RES_OFS ( 4) /**< ADC14RES Bit Offset */\r
+#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /**< ADC14RES Bit Mask */\r
+#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /**< RES Bit 0 */\r
+#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /**< RES Bit 1 */\r
+#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /**< 8 bit (9 clock cycle conversion time) */\r
+#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /**< 10 bit (11 clock cycle conversion time) */\r
+#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /**< 12 bit (14 clock cycle conversion time) */\r
+#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /**< 14 bit (16 clock cycle conversion time) */\r
+#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /**< 8 bit (9 clock cycle conversion time) */\r
+#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /**< 10 bit (11 clock cycle conversion time) */\r
+#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /**< 12 bit (14 clock cycle conversion time) */\r
+#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /**< 14 bit (16 clock cycle conversion time) */\r
+/* ADC14_CTL1[CSTARTADD] Bits */\r
+#define ADC14_CTL1_CSTARTADD_OFS (16) /**< ADC14CSTARTADD Bit Offset */\r
+#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /**< ADC14CSTARTADD Bit Mask */\r
+/* ADC14_CTL1[BATMAP] Bits */\r
+#define ADC14_CTL1_BATMAP_OFS (22) /**< ADC14BATMAP Bit Offset */\r
+#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /**< Controls 1/2 AVCC ADC input channel selection */\r
+/* ADC14_CTL1[TCMAP] Bits */\r
+#define ADC14_CTL1_TCMAP_OFS (23) /**< ADC14TCMAP Bit Offset */\r
+#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /**< Controls temperature sensor ADC input channel selection */\r
+/* ADC14_CTL1[CH0MAP] Bits */\r
+#define ADC14_CTL1_CH0MAP_OFS (24) /**< ADC14CH0MAP Bit Offset */\r
+#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /**< Controls internal channel 0 selection to ADC input channel MAX-2 */\r
+/* ADC14_CTL1[CH1MAP] Bits */\r
+#define ADC14_CTL1_CH1MAP_OFS (25) /**< ADC14CH1MAP Bit Offset */\r
+#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /**< Controls internal channel 1 selection to ADC input channel MAX-3 */\r
+/* ADC14_CTL1[CH2MAP] Bits */\r
+#define ADC14_CTL1_CH2MAP_OFS (26) /**< ADC14CH2MAP Bit Offset */\r
+#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /**< Controls internal channel 2 selection to ADC input channel MAX-4 */\r
+/* ADC14_CTL1[CH3MAP] Bits */\r
+#define ADC14_CTL1_CH3MAP_OFS (27) /**< ADC14CH3MAP Bit Offset */\r
+#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /**< Controls internal channel 3 selection to ADC input channel MAX-5 */\r
+/* ADC14_LO0[LO0] Bits */\r
+#define ADC14_LO0_LO0_OFS ( 0) /**< ADC14LO0 Bit Offset */\r
+#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /**< ADC14LO0 Bit Mask */\r
+/* ADC14_HI0[HI0] Bits */\r
+#define ADC14_HI0_HI0_OFS ( 0) /**< ADC14HI0 Bit Offset */\r
+#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /**< ADC14HI0 Bit Mask */\r
+/* ADC14_LO1[LO1] Bits */\r
+#define ADC14_LO1_LO1_OFS ( 0) /**< ADC14LO1 Bit Offset */\r
+#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /**< ADC14LO1 Bit Mask */\r
+/* ADC14_HI1[HI1] Bits */\r
+#define ADC14_HI1_HI1_OFS ( 0) /**< ADC14HI1 Bit Offset */\r
+#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /**< ADC14HI1 Bit Mask */\r
+/* ADC14_MCTLN[INCH] Bits */\r
+#define ADC14_MCTLN_INCH_OFS ( 0) /**< ADC14INCH Bit Offset */\r
+#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /**< ADC14INCH Bit Mask */\r
+#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /**< INCH Bit 0 */\r
+#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /**< INCH Bit 1 */\r
+#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /**< INCH Bit 2 */\r
+#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /**< INCH Bit 3 */\r
+#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /**< INCH Bit 4 */\r
+#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /**< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */\r
+#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /**< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */\r
+#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /**< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */\r
+#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /**< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */\r
+#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /**< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */\r
+#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /**< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */\r
+#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /**< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */\r
+#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /**< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */\r
+#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /**< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */\r
+#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /**< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */\r
+#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /**< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */\r
+#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /**< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */\r
+#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /**< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */\r
+#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /**< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */\r
+#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /**< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */\r
+#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /**< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */\r
+#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /**< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */\r
+#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /**< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */\r
+#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /**< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */\r
+#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /**< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */\r
+#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /**< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */\r
+#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /**< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */\r
+#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /**< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */\r
+#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /**< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */\r
+#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /**< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */\r
+#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /**< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */\r
+#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /**< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */\r
+#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /**< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */\r
+#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /**< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */\r
+#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /**< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */\r
+#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /**< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */\r
+#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /**< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */\r
+/* ADC14_MCTLN[EOS] Bits */\r
+#define ADC14_MCTLN_EOS_OFS ( 7) /**< ADC14EOS Bit Offset */\r
+#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /**< End of sequence */\r
+/* ADC14_MCTLN[VRSEL] Bits */\r
+#define ADC14_MCTLN_VRSEL_OFS ( 8) /**< ADC14VRSEL Bit Offset */\r
+#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /**< ADC14VRSEL Bit Mask */\r
+#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /**< VRSEL Bit 0 */\r
+#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /**< VRSEL Bit 1 */\r
+#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /**< VRSEL Bit 2 */\r
+#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /**< VRSEL Bit 3 */\r
+#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /**< V(R+) = AVCC, V(R-) = AVSS */\r
+#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /**< V(R+) = VREF buffered, V(R-) = AVSS */\r
+#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /**< V(R+) = VeREF+, V(R-) = VeREF- */\r
+#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /**< V(R+) = VeREF+ buffered, V(R-) = VeREF */\r
+/* ADC14_MCTLN[DIF] Bits */\r
+#define ADC14_MCTLN_DIF_OFS (13) /**< ADC14DIF Bit Offset */\r
+#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /**< Differential mode */\r
+/* ADC14_MCTLN[WINC] Bits */\r
+#define ADC14_MCTLN_WINC_OFS (14) /**< ADC14WINC Bit Offset */\r
+#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /**< Comparator window enable */\r
+/* ADC14_MCTLN[WINCTH] Bits */\r
+#define ADC14_MCTLN_WINCTH_OFS (15) /**< ADC14WINCTH Bit Offset */\r
+#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /**< Window comparator threshold register selection */\r
+/* ADC14_MEMN[CONVRES] Bits */\r
+#define ADC14_MEMN_CONVRES_OFS ( 0) /**< Conversion_Results Bit Offset */\r
+#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /**< Conversion_Results Bit Mask */\r
+/* ADC14_IER0[IE0] Bits */\r
+#define ADC14_IER0_IE0_OFS ( 0) /**< ADC14IE0 Bit Offset */\r
+#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /**< Interrupt enable */\r
+/* ADC14_IER0[IE1] Bits */\r
+#define ADC14_IER0_IE1_OFS ( 1) /**< ADC14IE1 Bit Offset */\r
+#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /**< Interrupt enable */\r
+/* ADC14_IER0[IE2] Bits */\r
+#define ADC14_IER0_IE2_OFS ( 2) /**< ADC14IE2 Bit Offset */\r
+#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /**< Interrupt enable */\r
+/* ADC14_IER0[IE3] Bits */\r
+#define ADC14_IER0_IE3_OFS ( 3) /**< ADC14IE3 Bit Offset */\r
+#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /**< Interrupt enable */\r
+/* ADC14_IER0[IE4] Bits */\r
+#define ADC14_IER0_IE4_OFS ( 4) /**< ADC14IE4 Bit Offset */\r
+#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /**< Interrupt enable */\r
+/* ADC14_IER0[IE5] Bits */\r
+#define ADC14_IER0_IE5_OFS ( 5) /**< ADC14IE5 Bit Offset */\r
+#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /**< Interrupt enable */\r
+/* ADC14_IER0[IE6] Bits */\r
+#define ADC14_IER0_IE6_OFS ( 6) /**< ADC14IE6 Bit Offset */\r
+#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /**< Interrupt enable */\r
+/* ADC14_IER0[IE7] Bits */\r
+#define ADC14_IER0_IE7_OFS ( 7) /**< ADC14IE7 Bit Offset */\r
+#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /**< Interrupt enable */\r
+/* ADC14_IER0[IE8] Bits */\r
+#define ADC14_IER0_IE8_OFS ( 8) /**< ADC14IE8 Bit Offset */\r
+#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /**< Interrupt enable */\r
+/* ADC14_IER0[IE9] Bits */\r
+#define ADC14_IER0_IE9_OFS ( 9) /**< ADC14IE9 Bit Offset */\r
+#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /**< Interrupt enable */\r
+/* ADC14_IER0[IE10] Bits */\r
+#define ADC14_IER0_IE10_OFS (10) /**< ADC14IE10 Bit Offset */\r
+#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /**< Interrupt enable */\r
+/* ADC14_IER0[IE11] Bits */\r
+#define ADC14_IER0_IE11_OFS (11) /**< ADC14IE11 Bit Offset */\r
+#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /**< Interrupt enable */\r
+/* ADC14_IER0[IE12] Bits */\r
+#define ADC14_IER0_IE12_OFS (12) /**< ADC14IE12 Bit Offset */\r
+#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE13] Bits */\r
+#define ADC14_IER0_IE13_OFS (13) /**< ADC14IE13 Bit Offset */\r
+#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE14] Bits */\r
+#define ADC14_IER0_IE14_OFS (14) /**< ADC14IE14 Bit Offset */\r
+#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE15] Bits */\r
+#define ADC14_IER0_IE15_OFS (15) /**< ADC14IE15 Bit Offset */\r
+#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE16] Bits */\r
+#define ADC14_IER0_IE16_OFS (16) /**< ADC14IE16 Bit Offset */\r
+#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE17] Bits */\r
+#define ADC14_IER0_IE17_OFS (17) /**< ADC14IE17 Bit Offset */\r
+#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE19] Bits */\r
+#define ADC14_IER0_IE19_OFS (19) /**< ADC14IE19 Bit Offset */\r
+#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE18] Bits */\r
+#define ADC14_IER0_IE18_OFS (18) /**< ADC14IE18 Bit Offset */\r
+#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE20] Bits */\r
+#define ADC14_IER0_IE20_OFS (20) /**< ADC14IE20 Bit Offset */\r
+#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE21] Bits */\r
+#define ADC14_IER0_IE21_OFS (21) /**< ADC14IE21 Bit Offset */\r
+#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE22] Bits */\r
+#define ADC14_IER0_IE22_OFS (22) /**< ADC14IE22 Bit Offset */\r
+#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE23] Bits */\r
+#define ADC14_IER0_IE23_OFS (23) /**< ADC14IE23 Bit Offset */\r
+#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE24] Bits */\r
+#define ADC14_IER0_IE24_OFS (24) /**< ADC14IE24 Bit Offset */\r
+#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE25] Bits */\r
+#define ADC14_IER0_IE25_OFS (25) /**< ADC14IE25 Bit Offset */\r
+#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE26] Bits */\r
+#define ADC14_IER0_IE26_OFS (26) /**< ADC14IE26 Bit Offset */\r
+#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE27] Bits */\r
+#define ADC14_IER0_IE27_OFS (27) /**< ADC14IE27 Bit Offset */\r
+#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE28] Bits */\r
+#define ADC14_IER0_IE28_OFS (28) /**< ADC14IE28 Bit Offset */\r
+#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE29] Bits */\r
+#define ADC14_IER0_IE29_OFS (29) /**< ADC14IE29 Bit Offset */\r
+#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE30] Bits */\r
+#define ADC14_IER0_IE30_OFS (30) /**< ADC14IE30 Bit Offset */\r
+#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /**< Interrupt enable */\r
+/* ADC14_IER0[IE31] Bits */\r
+#define ADC14_IER0_IE31_OFS (31) /**< ADC14IE31 Bit Offset */\r
+#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /**< Interrupt enable */\r
+/* ADC14_IER1[INIE] Bits */\r
+#define ADC14_IER1_INIE_OFS ( 1) /**< ADC14INIE Bit Offset */\r
+#define ADC14_IER1_INIE ((uint32_t)0x00000002) /**< Interrupt enable for ADC14MEMx within comparator window */\r
+/* ADC14_IER1[LOIE] Bits */\r
+#define ADC14_IER1_LOIE_OFS ( 2) /**< ADC14LOIE Bit Offset */\r
+#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /**< Interrupt enable for ADC14MEMx below comparator window */\r
+/* ADC14_IER1[HIIE] Bits */\r
+#define ADC14_IER1_HIIE_OFS ( 3) /**< ADC14HIIE Bit Offset */\r
+#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /**< Interrupt enable for ADC14MEMx above comparator window */\r
+/* ADC14_IER1[OVIE] Bits */\r
+#define ADC14_IER1_OVIE_OFS ( 4) /**< ADC14OVIE Bit Offset */\r
+#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /**< ADC14MEMx overflow-interrupt enable */\r
+/* ADC14_IER1[TOVIE] Bits */\r
+#define ADC14_IER1_TOVIE_OFS ( 5) /**< ADC14TOVIE Bit Offset */\r
+#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /**< ADC14 conversion-time-overflow interrupt enable */\r
+/* ADC14_IER1[RDYIE] Bits */\r
+#define ADC14_IER1_RDYIE_OFS ( 6) /**< ADC14RDYIE Bit Offset */\r
+#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /**< ADC14 local buffered reference ready interrupt enable */\r
+/* ADC14_IFGR0[IFG0] Bits */\r
+#define ADC14_IFGR0_IFG0_OFS ( 0) /**< ADC14IFG0 Bit Offset */\r
+#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /**< ADC14MEM0 interrupt flag */\r
+/* ADC14_IFGR0[IFG1] Bits */\r
+#define ADC14_IFGR0_IFG1_OFS ( 1) /**< ADC14IFG1 Bit Offset */\r
+#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /**< ADC14MEM1 interrupt flag */\r
+/* ADC14_IFGR0[IFG2] Bits */\r
+#define ADC14_IFGR0_IFG2_OFS ( 2) /**< ADC14IFG2 Bit Offset */\r
+#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /**< ADC14MEM2 interrupt flag */\r
+/* ADC14_IFGR0[IFG3] Bits */\r
+#define ADC14_IFGR0_IFG3_OFS ( 3) /**< ADC14IFG3 Bit Offset */\r
+#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /**< ADC14MEM3 interrupt flag */\r
+/* ADC14_IFGR0[IFG4] Bits */\r
+#define ADC14_IFGR0_IFG4_OFS ( 4) /**< ADC14IFG4 Bit Offset */\r
+#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /**< ADC14MEM4 interrupt flag */\r
+/* ADC14_IFGR0[IFG5] Bits */\r
+#define ADC14_IFGR0_IFG5_OFS ( 5) /**< ADC14IFG5 Bit Offset */\r
+#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /**< ADC14MEM5 interrupt flag */\r
+/* ADC14_IFGR0[IFG6] Bits */\r
+#define ADC14_IFGR0_IFG6_OFS ( 6) /**< ADC14IFG6 Bit Offset */\r
+#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /**< ADC14MEM6 interrupt flag */\r
+/* ADC14_IFGR0[IFG7] Bits */\r
+#define ADC14_IFGR0_IFG7_OFS ( 7) /**< ADC14IFG7 Bit Offset */\r
+#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /**< ADC14MEM7 interrupt flag */\r
+/* ADC14_IFGR0[IFG8] Bits */\r
+#define ADC14_IFGR0_IFG8_OFS ( 8) /**< ADC14IFG8 Bit Offset */\r
+#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /**< ADC14MEM8 interrupt flag */\r
+/* ADC14_IFGR0[IFG9] Bits */\r
+#define ADC14_IFGR0_IFG9_OFS ( 9) /**< ADC14IFG9 Bit Offset */\r
+#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /**< ADC14MEM9 interrupt flag */\r
+/* ADC14_IFGR0[IFG10] Bits */\r
+#define ADC14_IFGR0_IFG10_OFS (10) /**< ADC14IFG10 Bit Offset */\r
+#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /**< ADC14MEM10 interrupt flag */\r
+/* ADC14_IFGR0[IFG11] Bits */\r
+#define ADC14_IFGR0_IFG11_OFS (11) /**< ADC14IFG11 Bit Offset */\r
+#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /**< ADC14MEM11 interrupt flag */\r
+/* ADC14_IFGR0[IFG12] Bits */\r
+#define ADC14_IFGR0_IFG12_OFS (12) /**< ADC14IFG12 Bit Offset */\r
+#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /**< ADC14MEM12 interrupt flag */\r
+/* ADC14_IFGR0[IFG13] Bits */\r
+#define ADC14_IFGR0_IFG13_OFS (13) /**< ADC14IFG13 Bit Offset */\r
+#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /**< ADC14MEM13 interrupt flag */\r
+/* ADC14_IFGR0[IFG14] Bits */\r
+#define ADC14_IFGR0_IFG14_OFS (14) /**< ADC14IFG14 Bit Offset */\r
+#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /**< ADC14MEM14 interrupt flag */\r
+/* ADC14_IFGR0[IFG15] Bits */\r
+#define ADC14_IFGR0_IFG15_OFS (15) /**< ADC14IFG15 Bit Offset */\r
+#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /**< ADC14MEM15 interrupt flag */\r
+/* ADC14_IFGR0[IFG16] Bits */\r
+#define ADC14_IFGR0_IFG16_OFS (16) /**< ADC14IFG16 Bit Offset */\r
+#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /**< ADC14MEM16 interrupt flag */\r
+/* ADC14_IFGR0[IFG17] Bits */\r
+#define ADC14_IFGR0_IFG17_OFS (17) /**< ADC14IFG17 Bit Offset */\r
+#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /**< ADC14MEM17 interrupt flag */\r
+/* ADC14_IFGR0[IFG18] Bits */\r
+#define ADC14_IFGR0_IFG18_OFS (18) /**< ADC14IFG18 Bit Offset */\r
+#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /**< ADC14MEM18 interrupt flag */\r
+/* ADC14_IFGR0[IFG19] Bits */\r
+#define ADC14_IFGR0_IFG19_OFS (19) /**< ADC14IFG19 Bit Offset */\r
+#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /**< ADC14MEM19 interrupt flag */\r
+/* ADC14_IFGR0[IFG20] Bits */\r
+#define ADC14_IFGR0_IFG20_OFS (20) /**< ADC14IFG20 Bit Offset */\r
+#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /**< ADC14MEM20 interrupt flag */\r
+/* ADC14_IFGR0[IFG21] Bits */\r
+#define ADC14_IFGR0_IFG21_OFS (21) /**< ADC14IFG21 Bit Offset */\r
+#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /**< ADC14MEM21 interrupt flag */\r
+/* ADC14_IFGR0[IFG22] Bits */\r
+#define ADC14_IFGR0_IFG22_OFS (22) /**< ADC14IFG22 Bit Offset */\r
+#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /**< ADC14MEM22 interrupt flag */\r
+/* ADC14_IFGR0[IFG23] Bits */\r
+#define ADC14_IFGR0_IFG23_OFS (23) /**< ADC14IFG23 Bit Offset */\r
+#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /**< ADC14MEM23 interrupt flag */\r
+/* ADC14_IFGR0[IFG24] Bits */\r
+#define ADC14_IFGR0_IFG24_OFS (24) /**< ADC14IFG24 Bit Offset */\r
+#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /**< ADC14MEM24 interrupt flag */\r
+/* ADC14_IFGR0[IFG25] Bits */\r
+#define ADC14_IFGR0_IFG25_OFS (25) /**< ADC14IFG25 Bit Offset */\r
+#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /**< ADC14MEM25 interrupt flag */\r
+/* ADC14_IFGR0[IFG26] Bits */\r
+#define ADC14_IFGR0_IFG26_OFS (26) /**< ADC14IFG26 Bit Offset */\r
+#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /**< ADC14MEM26 interrupt flag */\r
+/* ADC14_IFGR0[IFG27] Bits */\r
+#define ADC14_IFGR0_IFG27_OFS (27) /**< ADC14IFG27 Bit Offset */\r
+#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /**< ADC14MEM27 interrupt flag */\r
+/* ADC14_IFGR0[IFG28] Bits */\r
+#define ADC14_IFGR0_IFG28_OFS (28) /**< ADC14IFG28 Bit Offset */\r
+#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /**< ADC14MEM28 interrupt flag */\r
+/* ADC14_IFGR0[IFG29] Bits */\r
+#define ADC14_IFGR0_IFG29_OFS (29) /**< ADC14IFG29 Bit Offset */\r
+#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /**< ADC14MEM29 interrupt flag */\r
+/* ADC14_IFGR0[IFG30] Bits */\r
+#define ADC14_IFGR0_IFG30_OFS (30) /**< ADC14IFG30 Bit Offset */\r
+#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /**< ADC14MEM30 interrupt flag */\r
+/* ADC14_IFGR0[IFG31] Bits */\r
+#define ADC14_IFGR0_IFG31_OFS (31) /**< ADC14IFG31 Bit Offset */\r
+#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /**< ADC14MEM31 interrupt flag */\r
+/* ADC14_IFGR1[INIFG] Bits */\r
+#define ADC14_IFGR1_INIFG_OFS ( 1) /**< ADC14INIFG Bit Offset */\r
+#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /**< Interrupt flag for ADC14MEMx within comparator window */\r
+/* ADC14_IFGR1[LOIFG] Bits */\r
+#define ADC14_IFGR1_LOIFG_OFS ( 2) /**< ADC14LOIFG Bit Offset */\r
+#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /**< Interrupt flag for ADC14MEMx below comparator window */\r
+/* ADC14_IFGR1[HIIFG] Bits */\r
+#define ADC14_IFGR1_HIIFG_OFS ( 3) /**< ADC14HIIFG Bit Offset */\r
+#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /**< Interrupt flag for ADC14MEMx above comparator window */\r
+/* ADC14_IFGR1[OVIFG] Bits */\r
+#define ADC14_IFGR1_OVIFG_OFS ( 4) /**< ADC14OVIFG Bit Offset */\r
+#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /**< ADC14MEMx overflow interrupt flag */\r
+/* ADC14_IFGR1[TOVIFG] Bits */\r
+#define ADC14_IFGR1_TOVIFG_OFS ( 5) /**< ADC14TOVIFG Bit Offset */\r
+#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /**< ADC14 conversion time overflow interrupt flag */\r
+/* ADC14_IFGR1[RDYIFG] Bits */\r
+#define ADC14_IFGR1_RDYIFG_OFS ( 6) /**< ADC14RDYIFG Bit Offset */\r
+#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /**< ADC14 local buffered reference ready interrupt flag */\r
+/* ADC14_CLRIFGR0[CLRIFG0] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /**< CLRADC14IFG0 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /**< clear ADC14IFG0 */\r
+/* ADC14_CLRIFGR0[CLRIFG1] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /**< CLRADC14IFG1 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /**< clear ADC14IFG1 */\r
+/* ADC14_CLRIFGR0[CLRIFG2] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /**< CLRADC14IFG2 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /**< clear ADC14IFG2 */\r
+/* ADC14_CLRIFGR0[CLRIFG3] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /**< CLRADC14IFG3 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /**< clear ADC14IFG3 */\r
+/* ADC14_CLRIFGR0[CLRIFG4] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /**< CLRADC14IFG4 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /**< clear ADC14IFG4 */\r
+/* ADC14_CLRIFGR0[CLRIFG5] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /**< CLRADC14IFG5 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /**< clear ADC14IFG5 */\r
+/* ADC14_CLRIFGR0[CLRIFG6] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /**< CLRADC14IFG6 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /**< clear ADC14IFG6 */\r
+/* ADC14_CLRIFGR0[CLRIFG7] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /**< CLRADC14IFG7 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /**< clear ADC14IFG7 */\r
+/* ADC14_CLRIFGR0[CLRIFG8] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /**< CLRADC14IFG8 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /**< clear ADC14IFG8 */\r
+/* ADC14_CLRIFGR0[CLRIFG9] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /**< CLRADC14IFG9 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /**< clear ADC14IFG9 */\r
+/* ADC14_CLRIFGR0[CLRIFG10] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /**< CLRADC14IFG10 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /**< clear ADC14IFG10 */\r
+/* ADC14_CLRIFGR0[CLRIFG11] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /**< CLRADC14IFG11 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /**< clear ADC14IFG11 */\r
+/* ADC14_CLRIFGR0[CLRIFG12] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /**< CLRADC14IFG12 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /**< clear ADC14IFG12 */\r
+/* ADC14_CLRIFGR0[CLRIFG13] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /**< CLRADC14IFG13 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /**< clear ADC14IFG13 */\r
+/* ADC14_CLRIFGR0[CLRIFG14] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /**< CLRADC14IFG14 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /**< clear ADC14IFG14 */\r
+/* ADC14_CLRIFGR0[CLRIFG15] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /**< CLRADC14IFG15 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /**< clear ADC14IFG15 */\r
+/* ADC14_CLRIFGR0[CLRIFG16] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /**< CLRADC14IFG16 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /**< clear ADC14IFG16 */\r
+/* ADC14_CLRIFGR0[CLRIFG17] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /**< CLRADC14IFG17 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /**< clear ADC14IFG17 */\r
+/* ADC14_CLRIFGR0[CLRIFG18] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /**< CLRADC14IFG18 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /**< clear ADC14IFG18 */\r
+/* ADC14_CLRIFGR0[CLRIFG19] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /**< CLRADC14IFG19 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /**< clear ADC14IFG19 */\r
+/* ADC14_CLRIFGR0[CLRIFG20] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /**< CLRADC14IFG20 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /**< clear ADC14IFG20 */\r
+/* ADC14_CLRIFGR0[CLRIFG21] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /**< CLRADC14IFG21 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /**< clear ADC14IFG21 */\r
+/* ADC14_CLRIFGR0[CLRIFG22] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /**< CLRADC14IFG22 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /**< clear ADC14IFG22 */\r
+/* ADC14_CLRIFGR0[CLRIFG23] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /**< CLRADC14IFG23 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /**< clear ADC14IFG23 */\r
+/* ADC14_CLRIFGR0[CLRIFG24] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /**< CLRADC14IFG24 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /**< clear ADC14IFG24 */\r
+/* ADC14_CLRIFGR0[CLRIFG25] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /**< CLRADC14IFG25 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /**< clear ADC14IFG25 */\r
+/* ADC14_CLRIFGR0[CLRIFG26] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /**< CLRADC14IFG26 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /**< clear ADC14IFG26 */\r
+/* ADC14_CLRIFGR0[CLRIFG27] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /**< CLRADC14IFG27 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /**< clear ADC14IFG27 */\r
+/* ADC14_CLRIFGR0[CLRIFG28] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /**< CLRADC14IFG28 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /**< clear ADC14IFG28 */\r
+/* ADC14_CLRIFGR0[CLRIFG29] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /**< CLRADC14IFG29 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /**< clear ADC14IFG29 */\r
+/* ADC14_CLRIFGR0[CLRIFG30] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /**< CLRADC14IFG30 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /**< clear ADC14IFG30 */\r
+/* ADC14_CLRIFGR0[CLRIFG31] Bits */\r
+#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /**< CLRADC14IFG31 Bit Offset */\r
+#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /**< clear ADC14IFG31 */\r
+/* ADC14_CLRIFGR1[CLRINIFG] Bits */\r
+#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /**< CLRADC14INIFG Bit Offset */\r
+#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /**< clear ADC14INIFG */\r
+/* ADC14_CLRIFGR1[CLRLOIFG] Bits */\r
+#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /**< CLRADC14LOIFG Bit Offset */\r
+#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /**< clear ADC14LOIFG */\r
+/* ADC14_CLRIFGR1[CLRHIIFG] Bits */\r
+#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /**< CLRADC14HIIFG Bit Offset */\r
+#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /**< clear ADC14HIIFG */\r
+/* ADC14_CLRIFGR1[CLROVIFG] Bits */\r
+#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /**< CLRADC14OVIFG Bit Offset */\r
+#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /**< clear ADC14OVIFG */\r
+/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */\r
+#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /**< CLRADC14TOVIFG Bit Offset */\r
+#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /**< clear ADC14TOVIFG */\r
+/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */\r
+#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /**< CLRADC14RDYIFG Bit Offset */\r
+#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /**< clear ADC14RDYIFG */\r
+\r
+\r
+/******************************************************************************\r
+* AES256 Bits\r
+******************************************************************************/\r
+/* AES256_CTL0[OP] Bits */\r
+#define AES256_CTL0_OP_OFS ( 0) /**< AESOPx Bit Offset */\r
+#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /**< AESOPx Bit Mask */\r
+#define AES256_CTL0_OP0 ((uint16_t)0x0001) /**< OP Bit 0 */\r
+#define AES256_CTL0_OP1 ((uint16_t)0x0002) /**< OP Bit 1 */\r
+#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /**< Encryption */\r
+#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /**< Decryption. The provided key is the same key used for encryption */\r
+#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /**< Generate first round key required for decryption */\r
+#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /**< Decryption. The provided key is the first round key required for decryption */\r
+/* AES256_CTL0[KL] Bits */\r
+#define AES256_CTL0_KL_OFS ( 2) /**< AESKLx Bit Offset */\r
+#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /**< AESKLx Bit Mask */\r
+#define AES256_CTL0_KL0 ((uint16_t)0x0004) /**< KL Bit 0 */\r
+#define AES256_CTL0_KL1 ((uint16_t)0x0008) /**< KL Bit 1 */\r
+#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /**< AES128. The key size is 128 bit */\r
+#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /**< AES192. The key size is 192 bit. */\r
+#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /**< AES256. The key size is 256 bit */\r
+#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /**< AES128. The key size is 128 bit */\r
+#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /**< AES192. The key size is 192 bit. */\r
+#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /**< AES256. The key size is 256 bit */\r
+/* AES256_CTL0[CM] Bits */\r
+#define AES256_CTL0_CM_OFS ( 5) /**< AESCMx Bit Offset */\r
+#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /**< AESCMx Bit Mask */\r
+#define AES256_CTL0_CM0 ((uint16_t)0x0020) /**< CM Bit 0 */\r
+#define AES256_CTL0_CM1 ((uint16_t)0x0040) /**< CM Bit 1 */\r
+#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /**< ECB */\r
+#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /**< CBC */\r
+#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /**< OFB */\r
+#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /**< CFB */\r
+#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /**< ECB */\r
+#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /**< CBC */\r
+#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /**< OFB */\r
+#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /**< CFB */\r
+/* AES256_CTL0[SWRST] Bits */\r
+#define AES256_CTL0_SWRST_OFS ( 7) /**< AESSWRST Bit Offset */\r
+#define AES256_CTL0_SWRST ((uint16_t)0x0080) /**< AES software reset */\r
+/* AES256_CTL0[RDYIFG] Bits */\r
+#define AES256_CTL0_RDYIFG_OFS ( 8) /**< AESRDYIFG Bit Offset */\r
+#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /**< AES ready interrupt flag */\r
+/* AES256_CTL0[ERRFG] Bits */\r
+#define AES256_CTL0_ERRFG_OFS (11) /**< AESERRFG Bit Offset */\r
+#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /**< AES error flag */\r
+/* AES256_CTL0[RDYIE] Bits */\r
+#define AES256_CTL0_RDYIE_OFS (12) /**< AESRDYIE Bit Offset */\r
+#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /**< AES ready interrupt enable */\r
+/* AES256_CTL0[CMEN] Bits */\r
+#define AES256_CTL0_CMEN_OFS (15) /**< AESCMEN Bit Offset */\r
+#define AES256_CTL0_CMEN ((uint16_t)0x8000) /**< AES cipher mode enable */\r
+/* AES256_CTL1[BLKCNT] Bits */\r
+#define AES256_CTL1_BLKCNT_OFS ( 0) /**< AESBLKCNTx Bit Offset */\r
+#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /**< AESBLKCNTx Bit Mask */\r
+#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /**< BLKCNT Bit 0 */\r
+#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /**< BLKCNT Bit 1 */\r
+#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /**< BLKCNT Bit 2 */\r
+#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /**< BLKCNT Bit 3 */\r
+#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /**< BLKCNT Bit 4 */\r
+#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /**< BLKCNT Bit 5 */\r
+#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /**< BLKCNT Bit 6 */\r
+#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /**< BLKCNT Bit 7 */\r
+/* AES256_STAT[BUSY] Bits */\r
+#define AES256_STAT_BUSY_OFS ( 0) /**< AESBUSY Bit Offset */\r
+#define AES256_STAT_BUSY ((uint16_t)0x0001) /**< AES accelerator module busy */\r
+/* AES256_STAT[KEYWR] Bits */\r
+#define AES256_STAT_KEYWR_OFS ( 1) /**< AESKEYWR Bit Offset */\r
+#define AES256_STAT_KEYWR ((uint16_t)0x0002) /**< All 16 bytes written to AESAKEY */\r
+/* AES256_STAT[DINWR] Bits */\r
+#define AES256_STAT_DINWR_OFS ( 2) /**< AESDINWR Bit Offset */\r
+#define AES256_STAT_DINWR ((uint16_t)0x0004) /**< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */\r
+/* AES256_STAT[DOUTRD] Bits */\r
+#define AES256_STAT_DOUTRD_OFS ( 3) /**< AESDOUTRD Bit Offset */\r
+#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /**< All 16 bytes read from AESADOUT */\r
+/* AES256_STAT[KEYCNT] Bits */\r
+#define AES256_STAT_KEYCNT_OFS ( 4) /**< AESKEYCNTx Bit Offset */\r
+#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /**< AESKEYCNTx Bit Mask */\r
+#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /**< KEYCNT Bit 0 */\r
+#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /**< KEYCNT Bit 1 */\r
+#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /**< KEYCNT Bit 2 */\r
+#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /**< KEYCNT Bit 3 */\r
+/* AES256_STAT[DINCNT] Bits */\r
+#define AES256_STAT_DINCNT_OFS ( 8) /**< AESDINCNTx Bit Offset */\r
+#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /**< AESDINCNTx Bit Mask */\r
+#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /**< DINCNT Bit 0 */\r
+#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /**< DINCNT Bit 1 */\r
+#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /**< DINCNT Bit 2 */\r
+#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /**< DINCNT Bit 3 */\r
+/* AES256_STAT[DOUTCNT] Bits */\r
+#define AES256_STAT_DOUTCNT_OFS (12) /**< AESDOUTCNTx Bit Offset */\r
+#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /**< AESDOUTCNTx Bit Mask */\r
+#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /**< DOUTCNT Bit 0 */\r
+#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /**< DOUTCNT Bit 1 */\r
+#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /**< DOUTCNT Bit 2 */\r
+#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /**< DOUTCNT Bit 3 */\r
+/* AES256_KEY[KEY0] Bits */\r
+#define AES256_KEY_KEY0_OFS ( 0) /**< AESKEY0x Bit Offset */\r
+#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /**< AESKEY0x Bit Mask */\r
+#define AES256_KEY_KEY00 ((uint16_t)0x0001) /**< KEY0 Bit 0 */\r
+#define AES256_KEY_KEY01 ((uint16_t)0x0002) /**< KEY0 Bit 1 */\r
+#define AES256_KEY_KEY02 ((uint16_t)0x0004) /**< KEY0 Bit 2 */\r
+#define AES256_KEY_KEY03 ((uint16_t)0x0008) /**< KEY0 Bit 3 */\r
+#define AES256_KEY_KEY04 ((uint16_t)0x0010) /**< KEY0 Bit 4 */\r
+#define AES256_KEY_KEY05 ((uint16_t)0x0020) /**< KEY0 Bit 5 */\r
+#define AES256_KEY_KEY06 ((uint16_t)0x0040) /**< KEY0 Bit 6 */\r
+#define AES256_KEY_KEY07 ((uint16_t)0x0080) /**< KEY0 Bit 7 */\r
+/* AES256_KEY[KEY1] Bits */\r
+#define AES256_KEY_KEY1_OFS ( 8) /**< AESKEY1x Bit Offset */\r
+#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /**< AESKEY1x Bit Mask */\r
+#define AES256_KEY_KEY10 ((uint16_t)0x0100) /**< KEY1 Bit 0 */\r
+#define AES256_KEY_KEY11 ((uint16_t)0x0200) /**< KEY1 Bit 1 */\r
+#define AES256_KEY_KEY12 ((uint16_t)0x0400) /**< KEY1 Bit 2 */\r
+#define AES256_KEY_KEY13 ((uint16_t)0x0800) /**< KEY1 Bit 3 */\r
+#define AES256_KEY_KEY14 ((uint16_t)0x1000) /**< KEY1 Bit 4 */\r
+#define AES256_KEY_KEY15 ((uint16_t)0x2000) /**< KEY1 Bit 5 */\r
+#define AES256_KEY_KEY16 ((uint16_t)0x4000) /**< KEY1 Bit 6 */\r
+#define AES256_KEY_KEY17 ((uint16_t)0x8000) /**< KEY1 Bit 7 */\r
+/* AES256_DIN[DIN0] Bits */\r
+#define AES256_DIN_DIN0_OFS ( 0) /**< AESDIN0x Bit Offset */\r
+#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /**< AESDIN0x Bit Mask */\r
+#define AES256_DIN_DIN00 ((uint16_t)0x0001) /**< DIN0 Bit 0 */\r
+#define AES256_DIN_DIN01 ((uint16_t)0x0002) /**< DIN0 Bit 1 */\r
+#define AES256_DIN_DIN02 ((uint16_t)0x0004) /**< DIN0 Bit 2 */\r
+#define AES256_DIN_DIN03 ((uint16_t)0x0008) /**< DIN0 Bit 3 */\r
+#define AES256_DIN_DIN04 ((uint16_t)0x0010) /**< DIN0 Bit 4 */\r
+#define AES256_DIN_DIN05 ((uint16_t)0x0020) /**< DIN0 Bit 5 */\r
+#define AES256_DIN_DIN06 ((uint16_t)0x0040) /**< DIN0 Bit 6 */\r
+#define AES256_DIN_DIN07 ((uint16_t)0x0080) /**< DIN0 Bit 7 */\r
+/* AES256_DIN[DIN1] Bits */\r
+#define AES256_DIN_DIN1_OFS ( 8) /**< AESDIN1x Bit Offset */\r
+#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /**< AESDIN1x Bit Mask */\r
+#define AES256_DIN_DIN10 ((uint16_t)0x0100) /**< DIN1 Bit 0 */\r
+#define AES256_DIN_DIN11 ((uint16_t)0x0200) /**< DIN1 Bit 1 */\r
+#define AES256_DIN_DIN12 ((uint16_t)0x0400) /**< DIN1 Bit 2 */\r
+#define AES256_DIN_DIN13 ((uint16_t)0x0800) /**< DIN1 Bit 3 */\r
+#define AES256_DIN_DIN14 ((uint16_t)0x1000) /**< DIN1 Bit 4 */\r
+#define AES256_DIN_DIN15 ((uint16_t)0x2000) /**< DIN1 Bit 5 */\r
+#define AES256_DIN_DIN16 ((uint16_t)0x4000) /**< DIN1 Bit 6 */\r
+#define AES256_DIN_DIN17 ((uint16_t)0x8000) /**< DIN1 Bit 7 */\r
+/* AES256_DOUT[DOUT0] Bits */\r
+#define AES256_DOUT_DOUT0_OFS ( 0) /**< AESDOUT0x Bit Offset */\r
+#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /**< AESDOUT0x Bit Mask */\r
+#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /**< DOUT0 Bit 0 */\r
+#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /**< DOUT0 Bit 1 */\r
+#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /**< DOUT0 Bit 2 */\r
+#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /**< DOUT0 Bit 3 */\r
+#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /**< DOUT0 Bit 4 */\r
+#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /**< DOUT0 Bit 5 */\r
+#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /**< DOUT0 Bit 6 */\r
+#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /**< DOUT0 Bit 7 */\r
+/* AES256_DOUT[DOUT1] Bits */\r
+#define AES256_DOUT_DOUT1_OFS ( 8) /**< AESDOUT1x Bit Offset */\r
+#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /**< AESDOUT1x Bit Mask */\r
+#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /**< DOUT1 Bit 0 */\r
+#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /**< DOUT1 Bit 1 */\r
+#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /**< DOUT1 Bit 2 */\r
+#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /**< DOUT1 Bit 3 */\r
+#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /**< DOUT1 Bit 4 */\r
+#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /**< DOUT1 Bit 5 */\r
+#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /**< DOUT1 Bit 6 */\r
+#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /**< DOUT1 Bit 7 */\r
+/* AES256_XDIN[XDIN0] Bits */\r
+#define AES256_XDIN_XDIN0_OFS ( 0) /**< AESXDIN0x Bit Offset */\r
+#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /**< AESXDIN0x Bit Mask */\r
+#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /**< XDIN0 Bit 0 */\r
+#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /**< XDIN0 Bit 1 */\r
+#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /**< XDIN0 Bit 2 */\r
+#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /**< XDIN0 Bit 3 */\r
+#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /**< XDIN0 Bit 4 */\r
+#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /**< XDIN0 Bit 5 */\r
+#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /**< XDIN0 Bit 6 */\r
+#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /**< XDIN0 Bit 7 */\r
+/* AES256_XDIN[XDIN1] Bits */\r
+#define AES256_XDIN_XDIN1_OFS ( 8) /**< AESXDIN1x Bit Offset */\r
+#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /**< AESXDIN1x Bit Mask */\r
+#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /**< XDIN1 Bit 0 */\r
+#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /**< XDIN1 Bit 1 */\r
+#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /**< XDIN1 Bit 2 */\r
+#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /**< XDIN1 Bit 3 */\r
+#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /**< XDIN1 Bit 4 */\r
+#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /**< XDIN1 Bit 5 */\r
+#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /**< XDIN1 Bit 6 */\r
+#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /**< XDIN1 Bit 7 */\r
+/* AES256_XIN[XIN0] Bits */\r
+#define AES256_XIN_XIN0_OFS ( 0) /**< AESXIN0x Bit Offset */\r
+#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /**< AESXIN0x Bit Mask */\r
+#define AES256_XIN_XIN00 ((uint16_t)0x0001) /**< XIN0 Bit 0 */\r
+#define AES256_XIN_XIN01 ((uint16_t)0x0002) /**< XIN0 Bit 1 */\r
+#define AES256_XIN_XIN02 ((uint16_t)0x0004) /**< XIN0 Bit 2 */\r
+#define AES256_XIN_XIN03 ((uint16_t)0x0008) /**< XIN0 Bit 3 */\r
+#define AES256_XIN_XIN04 ((uint16_t)0x0010) /**< XIN0 Bit 4 */\r
+#define AES256_XIN_XIN05 ((uint16_t)0x0020) /**< XIN0 Bit 5 */\r
+#define AES256_XIN_XIN06 ((uint16_t)0x0040) /**< XIN0 Bit 6 */\r
+#define AES256_XIN_XIN07 ((uint16_t)0x0080) /**< XIN0 Bit 7 */\r
+/* AES256_XIN[XIN1] Bits */\r
+#define AES256_XIN_XIN1_OFS ( 8) /**< AESXIN1x Bit Offset */\r
+#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /**< AESXIN1x Bit Mask */\r
+#define AES256_XIN_XIN10 ((uint16_t)0x0100) /**< XIN1 Bit 0 */\r
+#define AES256_XIN_XIN11 ((uint16_t)0x0200) /**< XIN1 Bit 1 */\r
+#define AES256_XIN_XIN12 ((uint16_t)0x0400) /**< XIN1 Bit 2 */\r
+#define AES256_XIN_XIN13 ((uint16_t)0x0800) /**< XIN1 Bit 3 */\r
+#define AES256_XIN_XIN14 ((uint16_t)0x1000) /**< XIN1 Bit 4 */\r
+#define AES256_XIN_XIN15 ((uint16_t)0x2000) /**< XIN1 Bit 5 */\r
+#define AES256_XIN_XIN16 ((uint16_t)0x4000) /**< XIN1 Bit 6 */\r
+#define AES256_XIN_XIN17 ((uint16_t)0x8000) /**< XIN1 Bit 7 */\r
+\r
+\r
+/******************************************************************************\r
+* CAPTIO Bits\r
+******************************************************************************/\r
+/* CAPTIO_CTL[PISEL] Bits */\r
+#define CAPTIO_CTL_PISEL_OFS ( 1) /**< CAPTIOPISELx Bit Offset */\r
+#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /**< CAPTIOPISELx Bit Mask */\r
+#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /**< PISEL Bit 0 */\r
+#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /**< PISEL Bit 1 */\r
+#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /**< PISEL Bit 2 */\r
+#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /**< Px.0 */\r
+#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /**< Px.1 */\r
+#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /**< Px.2 */\r
+#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /**< Px.3 */\r
+#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /**< Px.4 */\r
+#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /**< Px.5 */\r
+#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /**< Px.6 */\r
+#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /**< Px.7 */\r
+/* CAPTIO_CTL[POSEL] Bits */\r
+#define CAPTIO_CTL_POSEL_OFS ( 4) /**< CAPTIOPOSELx Bit Offset */\r
+#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /**< CAPTIOPOSELx Bit Mask */\r
+#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /**< POSEL Bit 0 */\r
+#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /**< POSEL Bit 1 */\r
+#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /**< POSEL Bit 2 */\r
+#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /**< POSEL Bit 3 */\r
+#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /**< Px = PJ */\r
+#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /**< Px = P1 */\r
+#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /**< Px = P2 */\r
+#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /**< Px = P3 */\r
+#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /**< Px = P4 */\r
+#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /**< Px = P5 */\r
+#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /**< Px = P6 */\r
+#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /**< Px = P7 */\r
+#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /**< Px = P8 */\r
+#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /**< Px = P9 */\r
+#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /**< Px = P10 */\r
+#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /**< Px = P11 */\r
+#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /**< Px = P12 */\r
+#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /**< Px = P13 */\r
+#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /**< Px = P14 */\r
+#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /**< Px = P15 */\r
+#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /**< Px = PJ */\r
+#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /**< Px = P1 */\r
+#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /**< Px = P2 */\r
+#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /**< Px = P3 */\r
+#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /**< Px = P4 */\r
+#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /**< Px = P5 */\r
+#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /**< Px = P6 */\r
+#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /**< Px = P7 */\r
+#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /**< Px = P8 */\r
+#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /**< Px = P9 */\r
+#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /**< Px = P10 */\r
+#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /**< Px = P11 */\r
+#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /**< Px = P12 */\r
+#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /**< Px = P13 */\r
+#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /**< Px = P14 */\r
+#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /**< Px = P15 */\r
+/* CAPTIO_CTL[EN] Bits */\r
+#define CAPTIO_CTL_EN_OFS ( 8) /**< CAPTIOEN Bit Offset */\r
+#define CAPTIO_CTL_EN ((uint16_t)0x0100) /**< Capacitive Touch IO enable */\r
+/* CAPTIO_CTL[STATE] Bits */\r
+#define CAPTIO_CTL_STATE_OFS ( 9) /**< CAPTIOSTATE Bit Offset */\r
+#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /**< Capacitive Touch IO state */\r
+\r
+\r
+/******************************************************************************\r
+* COMP_E Bits\r
+******************************************************************************/\r
+/* COMP_E_CTL0[IPSEL] Bits */\r
+#define COMP_E_CTL0_IPSEL_OFS ( 0) /**< CEIPSEL Bit Offset */\r
+#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /**< CEIPSEL Bit Mask */\r
+#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /**< IPSEL Bit 0 */\r
+#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /**< IPSEL Bit 1 */\r
+#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /**< IPSEL Bit 2 */\r
+#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /**< IPSEL Bit 3 */\r
+#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /**< Channel 0 selected */\r
+#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /**< Channel 1 selected */\r
+#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /**< Channel 2 selected */\r
+#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /**< Channel 3 selected */\r
+#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /**< Channel 4 selected */\r
+#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /**< Channel 5 selected */\r
+#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /**< Channel 6 selected */\r
+#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /**< Channel 7 selected */\r
+#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /**< Channel 8 selected */\r
+#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /**< Channel 9 selected */\r
+#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /**< Channel 10 selected */\r
+#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /**< Channel 11 selected */\r
+#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /**< Channel 12 selected */\r
+#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /**< Channel 13 selected */\r
+#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /**< Channel 14 selected */\r
+#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /**< Channel 15 selected */\r
+/* COMP_E_CTL0[IPEN] Bits */\r
+#define COMP_E_CTL0_IPEN_OFS ( 7) /**< CEIPEN Bit Offset */\r
+#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /**< Channel input enable for the V+ terminal */\r
+/* COMP_E_CTL0[IMSEL] Bits */\r
+#define COMP_E_CTL0_IMSEL_OFS ( 8) /**< CEIMSEL Bit Offset */\r
+#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /**< CEIMSEL Bit Mask */\r
+#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /**< IMSEL Bit 0 */\r
+#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /**< IMSEL Bit 1 */\r
+#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /**< IMSEL Bit 2 */\r
+#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /**< IMSEL Bit 3 */\r
+#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /**< Channel 0 selected */\r
+#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /**< Channel 1 selected */\r
+#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /**< Channel 2 selected */\r
+#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /**< Channel 3 selected */\r
+#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /**< Channel 4 selected */\r
+#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /**< Channel 5 selected */\r
+#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /**< Channel 6 selected */\r
+#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /**< Channel 7 selected */\r
+#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /**< Channel 8 selected */\r
+#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /**< Channel 9 selected */\r
+#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /**< Channel 10 selected */\r
+#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /**< Channel 11 selected */\r
+#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /**< Channel 12 selected */\r
+#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /**< Channel 13 selected */\r
+#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /**< Channel 14 selected */\r
+#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /**< Channel 15 selected */\r
+/* COMP_E_CTL0[IMEN] Bits */\r
+#define COMP_E_CTL0_IMEN_OFS (15) /**< CEIMEN Bit Offset */\r
+#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /**< Channel input enable for the - terminal */\r
+/* COMP_E_CTL1[OUT] Bits */\r
+#define COMP_E_CTL1_OUT_OFS ( 0) /**< CEOUT Bit Offset */\r
+#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /**< Comparator output value */\r
+/* COMP_E_CTL1[OUTPOL] Bits */\r
+#define COMP_E_CTL1_OUTPOL_OFS ( 1) /**< CEOUTPOL Bit Offset */\r
+#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /**< Comparator output polarity */\r
+/* COMP_E_CTL1[F] Bits */\r
+#define COMP_E_CTL1_F_OFS ( 2) /**< CEF Bit Offset */\r
+#define COMP_E_CTL1_F ((uint16_t)0x0004) /**< Comparator output filter */\r
+/* COMP_E_CTL1[IES] Bits */\r
+#define COMP_E_CTL1_IES_OFS ( 3) /**< CEIES Bit Offset */\r
+#define COMP_E_CTL1_IES ((uint16_t)0x0008) /**< Interrupt edge select for CEIIFG and CEIFG */\r
+/* COMP_E_CTL1[SHORT] Bits */\r
+#define COMP_E_CTL1_SHORT_OFS ( 4) /**< CESHORT Bit Offset */\r
+#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /**< Input short */\r
+/* COMP_E_CTL1[EX] Bits */\r
+#define COMP_E_CTL1_EX_OFS ( 5) /**< CEEX Bit Offset */\r
+#define COMP_E_CTL1_EX ((uint16_t)0x0020) /**< Exchange */\r
+/* COMP_E_CTL1[FDLY] Bits */\r
+#define COMP_E_CTL1_FDLY_OFS ( 6) /**< CEFDLY Bit Offset */\r
+#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /**< CEFDLY Bit Mask */\r
+#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /**< FDLY Bit 0 */\r
+#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /**< FDLY Bit 1 */\r
+#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /**< Typical filter delay of TBD (450) ns */\r
+#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /**< Typical filter delay of TBD (900) ns */\r
+#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /**< Typical filter delay of TBD (1800) ns */\r
+#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /**< Typical filter delay of TBD (3600) ns */\r
+/* COMP_E_CTL1[PWRMD] Bits */\r
+#define COMP_E_CTL1_PWRMD_OFS ( 8) /**< CEPWRMD Bit Offset */\r
+#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /**< CEPWRMD Bit Mask */\r
+#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /**< PWRMD Bit 0 */\r
+#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /**< PWRMD Bit 1 */\r
+#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /**< High-speed mode */\r
+#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /**< Normal mode */\r
+#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /**< Ultra-low power mode */\r
+/* COMP_E_CTL1[ON] Bits */\r
+#define COMP_E_CTL1_ON_OFS (10) /**< CEON Bit Offset */\r
+#define COMP_E_CTL1_ON ((uint16_t)0x0400) /**< Comparator On */\r
+/* COMP_E_CTL1[MRVL] Bits */\r
+#define COMP_E_CTL1_MRVL_OFS (11) /**< CEMRVL Bit Offset */\r
+#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /**< This bit is valid of CEMRVS is set to 1 */\r
+/* COMP_E_CTL1[MRVS] Bits */\r
+#define COMP_E_CTL1_MRVS_OFS (12) /**< CEMRVS Bit Offset */\r
+#define COMP_E_CTL1_MRVS ((uint16_t)0x1000)\r
+/* COMP_E_CTL2[REF0] Bits */\r
+#define COMP_E_CTL2_REF0_OFS ( 0) /**< CEREF0 Bit Offset */\r
+#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /**< CEREF0 Bit Mask */\r
+/* COMP_E_CTL2[RSEL] Bits */\r
+#define COMP_E_CTL2_RSEL_OFS ( 5) /**< CERSEL Bit Offset */\r
+#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /**< Reference select */\r
+/* COMP_E_CTL2[RS] Bits */\r
+#define COMP_E_CTL2_RS_OFS ( 6) /**< CERS Bit Offset */\r
+#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /**< CERS Bit Mask */\r
+#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /**< RS Bit 0 */\r
+#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /**< RS Bit 1 */\r
+#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /**< No current is drawn by the reference circuitry */\r
+#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /**< VCC applied to the resistor ladder */\r
+#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /**< Shared reference voltage applied to the resistor ladder */\r
+#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /**< Shared reference voltage supplied to V(CREF). Resistor ladder is off */\r
+/* COMP_E_CTL2[REF1] Bits */\r
+#define COMP_E_CTL2_REF1_OFS ( 8) /**< CEREF1 Bit Offset */\r
+#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /**< CEREF1 Bit Mask */\r
+/* COMP_E_CTL2[REFL] Bits */\r
+#define COMP_E_CTL2_REFL_OFS (13) /**< CEREFL Bit Offset */\r
+#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /**< CEREFL Bit Mask */\r
+#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /**< REFL Bit 0 */\r
+#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /**< REFL Bit 1 */\r
+#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /**< Reference amplifier is disabled. No reference voltage is requested */\r
+#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /**< 1.2 V is selected as shared reference voltage input */\r
+#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /**< 2.0 V is selected as shared reference voltage input */\r
+#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /**< 2.5 V is selected as shared reference voltage input */\r
+#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /**< Reference amplifier is disabled. No reference voltage is requested */\r
+#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /**< 1.2 V is selected as shared reference voltage input */\r
+#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /**< 2.0 V is selected as shared reference voltage input */\r
+#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /**< 2.5 V is selected as shared reference voltage input */\r
+/* COMP_E_CTL2[REFACC] Bits */\r
+#define COMP_E_CTL2_REFACC_OFS (15) /**< CEREFACC Bit Offset */\r
+#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /**< Reference accuracy */\r
+/* COMP_E_CTL3[PD0] Bits */\r
+#define COMP_E_CTL3_PD0_OFS ( 0) /**< CEPD0 Bit Offset */\r
+#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /**< Port disable */\r
+/* COMP_E_CTL3[PD1] Bits */\r
+#define COMP_E_CTL3_PD1_OFS ( 1) /**< CEPD1 Bit Offset */\r
+#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /**< Port disable */\r
+/* COMP_E_CTL3[PD2] Bits */\r
+#define COMP_E_CTL3_PD2_OFS ( 2) /**< CEPD2 Bit Offset */\r
+#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /**< Port disable */\r
+/* COMP_E_CTL3[PD3] Bits */\r
+#define COMP_E_CTL3_PD3_OFS ( 3) /**< CEPD3 Bit Offset */\r
+#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /**< Port disable */\r
+/* COMP_E_CTL3[PD4] Bits */\r
+#define COMP_E_CTL3_PD4_OFS ( 4) /**< CEPD4 Bit Offset */\r
+#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /**< Port disable */\r
+/* COMP_E_CTL3[PD5] Bits */\r
+#define COMP_E_CTL3_PD5_OFS ( 5) /**< CEPD5 Bit Offset */\r
+#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /**< Port disable */\r
+/* COMP_E_CTL3[PD6] Bits */\r
+#define COMP_E_CTL3_PD6_OFS ( 6) /**< CEPD6 Bit Offset */\r
+#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /**< Port disable */\r
+/* COMP_E_CTL3[PD7] Bits */\r
+#define COMP_E_CTL3_PD7_OFS ( 7) /**< CEPD7 Bit Offset */\r
+#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /**< Port disable */\r
+/* COMP_E_CTL3[PD8] Bits */\r
+#define COMP_E_CTL3_PD8_OFS ( 8) /**< CEPD8 Bit Offset */\r
+#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /**< Port disable */\r
+/* COMP_E_CTL3[PD9] Bits */\r
+#define COMP_E_CTL3_PD9_OFS ( 9) /**< CEPD9 Bit Offset */\r
+#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /**< Port disable */\r
+/* COMP_E_CTL3[PD10] Bits */\r
+#define COMP_E_CTL3_PD10_OFS (10) /**< CEPD10 Bit Offset */\r
+#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /**< Port disable */\r
+/* COMP_E_CTL3[PD11] Bits */\r
+#define COMP_E_CTL3_PD11_OFS (11) /**< CEPD11 Bit Offset */\r
+#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /**< Port disable */\r
+/* COMP_E_CTL3[PD12] Bits */\r
+#define COMP_E_CTL3_PD12_OFS (12) /**< CEPD12 Bit Offset */\r
+#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /**< Port disable */\r
+/* COMP_E_CTL3[PD13] Bits */\r
+#define COMP_E_CTL3_PD13_OFS (13) /**< CEPD13 Bit Offset */\r
+#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /**< Port disable */\r
+/* COMP_E_CTL3[PD14] Bits */\r
+#define COMP_E_CTL3_PD14_OFS (14) /**< CEPD14 Bit Offset */\r
+#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /**< Port disable */\r
+/* COMP_E_CTL3[PD15] Bits */\r
+#define COMP_E_CTL3_PD15_OFS (15) /**< CEPD15 Bit Offset */\r
+#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /**< Port disable */\r
+/* COMP_E_INT[IFG] Bits */\r
+#define COMP_E_INT_IFG_OFS ( 0) /**< CEIFG Bit Offset */\r
+#define COMP_E_INT_IFG ((uint16_t)0x0001) /**< Comparator output interrupt flag */\r
+/* COMP_E_INT[IIFG] Bits */\r
+#define COMP_E_INT_IIFG_OFS ( 1) /**< CEIIFG Bit Offset */\r
+#define COMP_E_INT_IIFG ((uint16_t)0x0002) /**< Comparator output inverted interrupt flag */\r
+/* COMP_E_INT[RDYIFG] Bits */\r
+#define COMP_E_INT_RDYIFG_OFS ( 4) /**< CERDYIFG Bit Offset */\r
+#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /**< Comparator ready interrupt flag */\r
+/* COMP_E_INT[IE] Bits */\r
+#define COMP_E_INT_IE_OFS ( 8) /**< CEIE Bit Offset */\r
+#define COMP_E_INT_IE ((uint16_t)0x0100) /**< Comparator output interrupt enable */\r
+/* COMP_E_INT[IIE] Bits */\r
+#define COMP_E_INT_IIE_OFS ( 9) /**< CEIIE Bit Offset */\r
+#define COMP_E_INT_IIE ((uint16_t)0x0200) /**< Comparator output interrupt enable inverted polarity */\r
+/* COMP_E_INT[RDYIE] Bits */\r
+#define COMP_E_INT_RDYIE_OFS (12) /**< CERDYIE Bit Offset */\r
+#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /**< Comparator ready interrupt enable */\r
+\r
+\r
+/******************************************************************************\r
+* COREDEBUG Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* CRC32 Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* CS Bits\r
+******************************************************************************/\r
+/* CS_KEY[KEY] Bits */\r
+#define CS_KEY_KEY_OFS ( 0) /**< CSKEY Bit Offset */\r
+#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /**< CSKEY Bit Mask */\r
+/* CS_CTL0[DCOTUNE] Bits */\r
+#define CS_CTL0_DCOTUNE_OFS ( 0) /**< DCOTUNE Bit Offset */\r
+#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /**< DCOTUNE Bit Mask */\r
+/* CS_CTL0[DCORSEL] Bits */\r
+#define CS_CTL0_DCORSEL_OFS (16) /**< DCORSEL Bit Offset */\r
+#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /**< DCORSEL Bit Mask */\r
+#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /**< DCORSEL Bit 0 */\r
+#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /**< DCORSEL Bit 1 */\r
+#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /**< DCORSEL Bit 2 */\r
+#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /**< Nominal DCO Frequency Range (MHz): 1 to 2 */\r
+#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /**< Nominal DCO Frequency Range (MHz): 2 to 4 */\r
+#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /**< Nominal DCO Frequency Range (MHz): 4 to 8 */\r
+#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /**< Nominal DCO Frequency Range (MHz): 8 to 16 */\r
+#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /**< Nominal DCO Frequency Range (MHz): 16 to 32 */\r
+#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /**< Nominal DCO Frequency Range (MHz): 32 to 64 */\r
+/* CS_CTL0[DCORES] Bits */\r
+#define CS_CTL0_DCORES_OFS (22) /**< DCORES Bit Offset */\r
+#define CS_CTL0_DCORES ((uint32_t)0x00400000) /**< Enables the DCO external resistor mode */\r
+/* CS_CTL0[DCOEN] Bits */\r
+#define CS_CTL0_DCOEN_OFS (23) /**< DCOEN Bit Offset */\r
+#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /**< Enables the DCO oscillator */\r
+/* CS_CTL1[SELM] Bits */\r
+#define CS_CTL1_SELM_OFS ( 0) /**< SELM Bit Offset */\r
+#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /**< SELM Bit Mask */\r
+#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /**< SELM Bit 0 */\r
+#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /**< SELM Bit 1 */\r
+#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /**< SELM Bit 2 */\r
+#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */\r
+#define CS_CTL1_SELM_1 ((uint32_t)0x00000001)\r
+#define CS_CTL1_SELM_2 ((uint32_t)0x00000002)\r
+#define CS_CTL1_SELM_3 ((uint32_t)0x00000003)\r
+#define CS_CTL1_SELM_4 ((uint32_t)0x00000004)\r
+#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /**< when HFXT available, otherwise DCOCLK */\r
+#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /**< when HFXT2 available, otherwise DCOCLK */\r
+#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */\r
+#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001)\r
+#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002)\r
+#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003)\r
+#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004)\r
+#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /**< when HFXT available, otherwise DCOCLK */\r
+#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /**< when HFXT2 available, otherwise DCOCLK */\r
+#define CS_CTL1_SELM_7 ((uint32_t)0x00000007) /**< for future use. Defaults to DCOCLK. Not recommended for use to ensure future */\r
+ /* compatibilities. */\r
+/* CS_CTL1[SELS] Bits */\r
+#define CS_CTL1_SELS_OFS ( 4) /**< SELS Bit Offset */\r
+#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /**< SELS Bit Mask */\r
+#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /**< SELS Bit 0 */\r
+#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /**< SELS Bit 1 */\r
+#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /**< SELS Bit 2 */\r
+#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */\r
+#define CS_CTL1_SELS_1 ((uint32_t)0x00000010)\r
+#define CS_CTL1_SELS_2 ((uint32_t)0x00000020)\r
+#define CS_CTL1_SELS_3 ((uint32_t)0x00000030)\r
+#define CS_CTL1_SELS_4 ((uint32_t)0x00000040)\r
+#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /**< when HFXT available, otherwise DCOCLK */\r
+#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /**< when HFXT2 available, otherwise DCOCLK */\r
+#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */\r
+#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010)\r
+#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020)\r
+#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030)\r
+#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040)\r
+#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /**< when HFXT available, otherwise DCOCLK */\r
+#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /**< when HFXT2 available, otherwise DCOCLK */\r
+#define CS_CTL1_SELS_7 ((uint32_t)0x00000070) /**< for furture use. Defaults to DCOCLK. Do not use to ensure future */\r
+ /* compatibilities. */\r
+/* CS_CTL1[SELA] Bits */\r
+#define CS_CTL1_SELA_OFS ( 8) /**< SELA Bit Offset */\r
+#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /**< SELA Bit Mask */\r
+#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /**< SELA Bit 0 */\r
+#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /**< SELA Bit 1 */\r
+#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /**< SELA Bit 2 */\r
+#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */\r
+#define CS_CTL1_SELA_1 ((uint32_t)0x00000100)\r
+#define CS_CTL1_SELA_2 ((uint32_t)0x00000200)\r
+#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */\r
+#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100)\r
+#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200)\r
+#define CS_CTL1_SELA_3 ((uint32_t)0x00000300) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */\r
+ /* compatibilities. */\r
+#define CS_CTL1_SELA_4 ((uint32_t)0x00000400) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */\r
+ /* compatibilities. */\r
+#define CS_CTL1_SELA_5 ((uint32_t)0x00000500) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */\r
+ /* compatibilities. */\r
+#define CS_CTL1_SELA_6 ((uint32_t)0x00000600) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */\r
+ /* compatibilities. */\r
+#define CS_CTL1_SELA_7 ((uint32_t)0x00000700) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */\r
+ /* compatibilities. */\r
+/* CS_CTL1[SELB] Bits */\r
+#define CS_CTL1_SELB_OFS (12) /**< SELB Bit Offset */\r
+#define CS_CTL1_SELB ((uint32_t)0x00001000) /**< Selects the BCLK source */\r
+/* CS_CTL1[DIVM] Bits */\r
+#define CS_CTL1_DIVM_OFS (16) /**< DIVM Bit Offset */\r
+#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /**< DIVM Bit Mask */\r
+#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /**< DIVM Bit 0 */\r
+#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /**< DIVM Bit 1 */\r
+#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /**< DIVM Bit 2 */\r
+#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /**< f(MCLK)/1 */\r
+#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /**< f(MCLK)/2 */\r
+#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /**< f(MCLK)/4 */\r
+#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /**< f(MCLK)/8 */\r
+#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /**< f(MCLK)/16 */\r
+#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /**< f(MCLK)/32 */\r
+#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /**< f(MCLK)/64 */\r
+#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /**< f(MCLK)/128 */\r
+#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /**< f(MCLK)/1 */\r
+#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /**< f(MCLK)/2 */\r
+#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /**< f(MCLK)/4 */\r
+#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /**< f(MCLK)/8 */\r
+#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /**< f(MCLK)/16 */\r
+#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /**< f(MCLK)/32 */\r
+#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /**< f(MCLK)/64 */\r
+#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /**< f(MCLK)/128 */\r
+/* CS_CTL1[DIVHS] Bits */\r
+#define CS_CTL1_DIVHS_OFS (20) /**< DIVHS Bit Offset */\r
+#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /**< DIVHS Bit Mask */\r
+#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /**< DIVHS Bit 0 */\r
+#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /**< DIVHS Bit 1 */\r
+#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /**< DIVHS Bit 2 */\r
+#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /**< f(HSMCLK)/1 */\r
+#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /**< f(HSMCLK)/2 */\r
+#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /**< f(HSMCLK)/4 */\r
+#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /**< f(HSMCLK)/8 */\r
+#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /**< f(HSMCLK)/16 */\r
+#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /**< f(HSMCLK)/32 */\r
+#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /**< f(HSMCLK)/64 */\r
+#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /**< f(HSMCLK)/128 */\r
+#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /**< f(HSMCLK)/1 */\r
+#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /**< f(HSMCLK)/2 */\r
+#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /**< f(HSMCLK)/4 */\r
+#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /**< f(HSMCLK)/8 */\r
+#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /**< f(HSMCLK)/16 */\r
+#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /**< f(HSMCLK)/32 */\r
+#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /**< f(HSMCLK)/64 */\r
+#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /**< f(HSMCLK)/128 */\r
+/* CS_CTL1[DIVA] Bits */\r
+#define CS_CTL1_DIVA_OFS (24) /**< DIVA Bit Offset */\r
+#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /**< DIVA Bit Mask */\r
+#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /**< DIVA Bit 0 */\r
+#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /**< DIVA Bit 1 */\r
+#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /**< DIVA Bit 2 */\r
+#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /**< f(ACLK)/1 */\r
+#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /**< f(ACLK)/2 */\r
+#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /**< f(ACLK)/4 */\r
+#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /**< f(ACLK)/8 */\r
+#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /**< f(ACLK)/16 */\r
+#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /**< f(ACLK)/32 */\r
+#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /**< f(ACLK)/64 */\r
+#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /**< f(ACLK)/128 */\r
+#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /**< f(ACLK)/1 */\r
+#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /**< f(ACLK)/2 */\r
+#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /**< f(ACLK)/4 */\r
+#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /**< f(ACLK)/8 */\r
+#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /**< f(ACLK)/16 */\r
+#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /**< f(ACLK)/32 */\r
+#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /**< f(ACLK)/64 */\r
+#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /**< f(ACLK)/128 */\r
+/* CS_CTL1[DIVS] Bits */\r
+#define CS_CTL1_DIVS_OFS (28) /**< DIVS Bit Offset */\r
+#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /**< DIVS Bit Mask */\r
+#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /**< DIVS Bit 0 */\r
+#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /**< DIVS Bit 1 */\r
+#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /**< DIVS Bit 2 */\r
+#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /**< f(SMCLK)/1 */\r
+#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /**< f(SMCLK)/2 */\r
+#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /**< f(SMCLK)/4 */\r
+#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /**< f(SMCLK)/8 */\r
+#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /**< f(SMCLK)/16 */\r
+#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /**< f(SMCLK)/32 */\r
+#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /**< f(SMCLK)/64 */\r
+#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /**< f(SMCLK)/128 */\r
+#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /**< f(SMCLK)/1 */\r
+#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /**< f(SMCLK)/2 */\r
+#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /**< f(SMCLK)/4 */\r
+#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /**< f(SMCLK)/8 */\r
+#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /**< f(SMCLK)/16 */\r
+#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /**< f(SMCLK)/32 */\r
+#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /**< f(SMCLK)/64 */\r
+#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /**< f(SMCLK)/128 */\r
+/* CS_CTL2[LFXTDRIVE] Bits */\r
+#define CS_CTL2_LFXTDRIVE_OFS ( 0) /**< LFXTDRIVE Bit Offset */\r
+#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /**< LFXTDRIVE Bit Mask */\r
+#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /**< LFXTDRIVE Bit 0 */\r
+#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /**< LFXTDRIVE Bit 1 */\r
+#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /**< Lowest drive strength and current consumption LFXT oscillator. */\r
+#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /**< Increased drive strength LFXT oscillator. */\r
+#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /**< Increased drive strength LFXT oscillator. */\r
+#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /**< Maximum drive strength and maximum current consumption LFXT oscillator. */\r
+/* CS_CTL2[LFXTAGCOFF] Bits */\r
+#define CS_CTL2_LFXTAGCOFF_OFS ( 7) /**< LFXTAGCOFF Bit Offset */\r
+#define CS_CTL2_LFXTAGCOFF ((uint32_t)0x00000080) /**< Disables the automatic gain control of the LFXT crystal */\r
+/* CS_CTL2[LFXT_EN] Bits */\r
+#define CS_CTL2_LFXT_EN_OFS ( 8) /**< LFXT_EN Bit Offset */\r
+#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /**< Turns on the LFXT oscillator regardless if used as a clock resource */\r
+/* CS_CTL2[LFXTBYPASS] Bits */\r
+#define CS_CTL2_LFXTBYPASS_OFS ( 9) /**< LFXTBYPASS Bit Offset */\r
+#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /**< LFXT bypass select */\r
+/* CS_CTL2[HFXTDRIVE] Bits */\r
+#define CS_CTL2_HFXTDRIVE_OFS (16) /**< HFXTDRIVE Bit Offset */\r
+#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /**< HFXT oscillator drive selection */\r
+/* CS_CTL2[HFXTFREQ] Bits */\r
+#define CS_CTL2_HFXTFREQ_OFS (20) /**< HFXTFREQ Bit Offset */\r
+#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /**< HFXTFREQ Bit Mask */\r
+#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /**< HFXTFREQ Bit 0 */\r
+#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /**< HFXTFREQ Bit 1 */\r
+#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /**< HFXTFREQ Bit 2 */\r
+#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /**< 1 MHz to 4 MHz */\r
+#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /**< >4 MHz to 8 MHz */\r
+#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /**< >8 MHz to 16 MHz */\r
+#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /**< >16 MHz to 24 MHz */\r
+#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /**< >24 MHz to 32 MHz */\r
+#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /**< >32 MHz to 40 MHz */\r
+#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /**< >40 MHz to 48 MHz */\r
+#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /**< Reserved for future use. */\r
+/* CS_CTL2[HFXT_EN] Bits */\r
+#define CS_CTL2_HFXT_EN_OFS (24) /**< HFXT_EN Bit Offset */\r
+#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /**< Turns on the HFXT oscillator regardless if used as a clock resource */\r
+/* CS_CTL2[HFXTBYPASS] Bits */\r
+#define CS_CTL2_HFXTBYPASS_OFS (25) /**< HFXTBYPASS Bit Offset */\r
+#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /**< HFXT bypass select */\r
+/* CS_CTL3[FCNTLF] Bits */\r
+#define CS_CTL3_FCNTLF_OFS ( 0) /**< FCNTLF Bit Offset */\r
+#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /**< FCNTLF Bit Mask */\r
+#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /**< FCNTLF Bit 0 */\r
+#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /**< FCNTLF Bit 1 */\r
+#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /**< 4096 cycles */\r
+#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /**< 8192 cycles */\r
+#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /**< 16384 cycles */\r
+#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /**< 32768 cycles */\r
+#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /**< 4096 cycles */\r
+#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /**< 8192 cycles */\r
+#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /**< 16384 cycles */\r
+#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /**< 32768 cycles */\r
+/* CS_CTL3[RFCNTLF] Bits */\r
+#define CS_CTL3_RFCNTLF_OFS ( 2) /**< RFCNTLF Bit Offset */\r
+#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /**< Reset start fault counter for LFXT */\r
+/* CS_CTL3[FCNTLF_EN] Bits */\r
+#define CS_CTL3_FCNTLF_EN_OFS ( 3) /**< FCNTLF_EN Bit Offset */\r
+#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /**< Enable start fault counter for LFXT */\r
+/* CS_CTL3[FCNTHF] Bits */\r
+#define CS_CTL3_FCNTHF_OFS ( 4) /**< FCNTHF Bit Offset */\r
+#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /**< FCNTHF Bit Mask */\r
+#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /**< FCNTHF Bit 0 */\r
+#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /**< FCNTHF Bit 1 */\r
+#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /**< 2048 cycles */\r
+#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /**< 4096 cycles */\r
+#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /**< 8192 cycles */\r
+#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /**< 16384 cycles */\r
+#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /**< 2048 cycles */\r
+#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /**< 4096 cycles */\r
+#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /**< 8192 cycles */\r
+#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /**< 16384 cycles */\r
+/* CS_CTL3[RFCNTHF] Bits */\r
+#define CS_CTL3_RFCNTHF_OFS ( 6) /**< RFCNTHF Bit Offset */\r
+#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /**< Reset start fault counter for HFXT */\r
+/* CS_CTL3[FCNTHF_EN] Bits */\r
+#define CS_CTL3_FCNTHF_EN_OFS ( 7) /**< FCNTHF_EN Bit Offset */\r
+#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /**< Enable start fault counter for HFXT */\r
+/* CS_CTL3[FCNTHF2] Bits */\r
+#define CS_CTL3_FCNTHF2_OFS ( 8) /**< FCNTHF2 Bit Offset */\r
+#define CS_CTL3_FCNTHF2_MASK ((uint32_t)0x00000300) /**< FCNTHF2 Bit Mask */\r
+#define CS_CTL3_FCNTHF20 ((uint32_t)0x00000100) /**< FCNTHF2 Bit 0 */\r
+#define CS_CTL3_FCNTHF21 ((uint32_t)0x00000200) /**< FCNTHF2 Bit 1 */\r
+#define CS_CTL3_FCNTHF2_0 ((uint32_t)0x00000000) /**< 2048 cycles */\r
+#define CS_CTL3_FCNTHF2_1 ((uint32_t)0x00000100) /**< 4096 cycles */\r
+#define CS_CTL3_FCNTHF2_2 ((uint32_t)0x00000200) /**< 8192 cycles */\r
+#define CS_CTL3_FCNTHF2_3 ((uint32_t)0x00000300) /**< 16384 cycles */\r
+#define CS_CTL3_FCNTHF2__2048 ((uint32_t)0x00000000) /**< 2048 cycles */\r
+#define CS_CTL3_FCNTHF2__4096 ((uint32_t)0x00000100) /**< 4096 cycles */\r
+#define CS_CTL3_FCNTHF2__8192 ((uint32_t)0x00000200) /**< 8192 cycles */\r
+#define CS_CTL3_FCNTHF2__16384 ((uint32_t)0x00000300) /**< 16384 cycles */\r
+/* CS_CTL3[RFCNTHF2] Bits */\r
+#define CS_CTL3_RFCNTHF2_OFS (10) /**< RFCNTHF2 Bit Offset */\r
+#define CS_CTL3_RFCNTHF2 ((uint32_t)0x00000400) /**< Reset start fault counter for HFXT2 */\r
+/* CS_CTL3[FCNTHF2_EN] Bits */\r
+#define CS_CTL3_FCNTHF2_EN_OFS (11) /**< FCNTHF2_EN Bit Offset */\r
+#define CS_CTL3_FCNTHF2_EN ((uint32_t)0x00000800) /**< Enable start fault counter for HFXT2 */\r
+/* CS_CTL4[HFXT2DRIVE] Bits */\r
+#define CS_CTL4_HFXT2DRIVE_OFS ( 0) /**< HFXT2DRIVE Bit Offset */\r
+#define CS_CTL4_HFXT2DRIVE ((uint32_t)0x00000001) /**< HFXT2 oscillator current can be adjusted to its drive needs */\r
+/* CS_CTL4[HFXT2FREQ] Bits */\r
+#define CS_CTL4_HFXT2FREQ_OFS ( 4) /**< HFXT2FREQ Bit Offset */\r
+#define CS_CTL4_HFXT2FREQ_MASK ((uint32_t)0x00000070) /**< HFXT2FREQ Bit Mask */\r
+#define CS_CTL4_HFXT2FREQ0 ((uint32_t)0x00000010) /**< HFXT2FREQ Bit 0 */\r
+#define CS_CTL4_HFXT2FREQ1 ((uint32_t)0x00000020) /**< HFXT2FREQ Bit 1 */\r
+#define CS_CTL4_HFXT2FREQ2 ((uint32_t)0x00000040) /**< HFXT2FREQ Bit 2 */\r
+#define CS_CTL4_HFXT2FREQ_0 ((uint32_t)0x00000000) /**< 1 MHz to 4 MHz */\r
+#define CS_CTL4_HFXT2FREQ_1 ((uint32_t)0x00000010) /**< >4 MHz to 8 MHz */\r
+#define CS_CTL4_HFXT2FREQ_2 ((uint32_t)0x00000020) /**< >8 MHz to 16 MHz */\r
+#define CS_CTL4_HFXT2FREQ_3 ((uint32_t)0x00000030) /**< >16 MHz to 24 MHz */\r
+#define CS_CTL4_HFXT2FREQ_4 ((uint32_t)0x00000040) /**< >24 MHz to 32 MHz */\r
+#define CS_CTL4_HFXT2FREQ_5 ((uint32_t)0x00000050) /**< >32 MHz to 40 MHz */\r
+#define CS_CTL4_HFXT2FREQ_6 ((uint32_t)0x00000060) /**< >40 MHz to 48 MHz */\r
+#define CS_CTL4_HFXT2FREQ_7 ((uint32_t)0x00000070) /**< Reserved for future use. */\r
+/* CS_CTL4[HFXT2_EN] Bits */\r
+#define CS_CTL4_HFXT2_EN_OFS ( 8) /**< HFXT2_EN Bit Offset */\r
+#define CS_CTL4_HFXT2_EN ((uint32_t)0x00000100) /**< Turns on the HFXT2 oscillator */\r
+/* CS_CTL4[HFXT2BYPASS] Bits */\r
+#define CS_CTL4_HFXT2BYPASS_OFS ( 9) /**< HFXT2BYPASS Bit Offset */\r
+#define CS_CTL4_HFXT2BYPASS ((uint32_t)0x00000200) /**< HFXT2 bypass select */\r
+/* CS_CTL5[REFCNTSEL] Bits */\r
+#define CS_CTL5_REFCNTSEL_OFS ( 0) /**< REFCNTSEL Bit Offset */\r
+#define CS_CTL5_REFCNTSEL_MASK ((uint32_t)0x00000007) /**< REFCNTSEL Bit Mask */\r
+/* CS_CTL5[REFCNTPS] Bits */\r
+#define CS_CTL5_REFCNTPS_OFS ( 3) /**< REFCNTPS Bit Offset */\r
+#define CS_CTL5_REFCNTPS_MASK ((uint32_t)0x00000038) /**< REFCNTPS Bit Mask */\r
+/* CS_CTL5[CALSTART] Bits */\r
+#define CS_CTL5_CALSTART_OFS ( 7) /**< CALSTART Bit Offset */\r
+#define CS_CTL5_CALSTART ((uint32_t)0x00000080) /**< Start clock calibration counters */\r
+/* CS_CTL5[PERCNTSEL] Bits */\r
+#define CS_CTL5_PERCNTSEL_OFS ( 8) /**< PERCNTSEL Bit Offset */\r
+#define CS_CTL5_PERCNTSEL_MASK ((uint32_t)0x00000700) /**< PERCNTSEL Bit Mask */\r
+/* CS_CTL6[PERCNT] Bits */\r
+#define CS_CTL6_PERCNT_OFS ( 0) /**< PERCNT Bit Offset */\r
+#define CS_CTL6_PERCNT_MASK ((uint32_t)0x0000FFFF) /**< PERCNT Bit Mask */\r
+/* CS_CTL7[REFCNT] Bits */\r
+#define CS_CTL7_REFCNT_OFS ( 0) /**< REFCNT Bit Offset */\r
+#define CS_CTL7_REFCNT_MASK ((uint32_t)0x0000FFFF) /**< REFCNT Bit Mask */\r
+/* CS_CLKEN[ACLK_EN] Bits */\r
+#define CS_CLKEN_ACLK_EN_OFS ( 0) /**< ACLK_EN Bit Offset */\r
+#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /**< ACLK system clock conditional request enable */\r
+/* CS_CLKEN[MCLK_EN] Bits */\r
+#define CS_CLKEN_MCLK_EN_OFS ( 1) /**< MCLK_EN Bit Offset */\r
+#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /**< MCLK system clock conditional request enable */\r
+/* CS_CLKEN[HSMCLK_EN] Bits */\r
+#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /**< HSMCLK_EN Bit Offset */\r
+#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /**< HSMCLK system clock conditional request enable */\r
+/* CS_CLKEN[SMCLK_EN] Bits */\r
+#define CS_CLKEN_SMCLK_EN_OFS ( 3) /**< SMCLK_EN Bit Offset */\r
+#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /**< SMCLK system clock conditional request enable */\r
+/* CS_CLKEN[VLO_EN] Bits */\r
+#define CS_CLKEN_VLO_EN_OFS ( 8) /**< VLO_EN Bit Offset */\r
+#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /**< Turns on the VLO oscillator */\r
+/* CS_CLKEN[REFO_EN] Bits */\r
+#define CS_CLKEN_REFO_EN_OFS ( 9) /**< REFO_EN Bit Offset */\r
+#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /**< Turns on the REFO oscillator */\r
+/* CS_CLKEN[MODOSC_EN] Bits */\r
+#define CS_CLKEN_MODOSC_EN_OFS (10) /**< MODOSC_EN Bit Offset */\r
+#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /**< Turns on the MODOSC oscillator */\r
+/* CS_CLKEN[REFOFSEL] Bits */\r
+#define CS_CLKEN_REFOFSEL_OFS (15) /**< REFOFSEL Bit Offset */\r
+#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /**< Selects REFO nominal frequency */\r
+/* CS_STAT[DCO_ON] Bits */\r
+#define CS_STAT_DCO_ON_OFS ( 0) /**< DCO_ON Bit Offset */\r
+#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /**< DCO status */\r
+/* CS_STAT[DCOBIAS_ON] Bits */\r
+#define CS_STAT_DCOBIAS_ON_OFS ( 1) /**< DCOBIAS_ON Bit Offset */\r
+#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /**< DCO bias status */\r
+/* CS_STAT[HFXT_ON] Bits */\r
+#define CS_STAT_HFXT_ON_OFS ( 2) /**< HFXT_ON Bit Offset */\r
+#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /**< HFXT status */\r
+/* CS_STAT[HFXT2_ON] Bits */\r
+#define CS_STAT_HFXT2_ON_OFS ( 3) /**< HFXT2_ON Bit Offset */\r
+#define CS_STAT_HFXT2_ON ((uint32_t)0x00000008) /**< HFXT2 status */\r
+/* CS_STAT[MODOSC_ON] Bits */\r
+#define CS_STAT_MODOSC_ON_OFS ( 4) /**< MODOSC_ON Bit Offset */\r
+#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /**< MODOSC status */\r
+/* CS_STAT[VLO_ON] Bits */\r
+#define CS_STAT_VLO_ON_OFS ( 5) /**< VLO_ON Bit Offset */\r
+#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /**< VLO status */\r
+/* CS_STAT[LFXT_ON] Bits */\r
+#define CS_STAT_LFXT_ON_OFS ( 6) /**< LFXT_ON Bit Offset */\r
+#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /**< LFXT status */\r
+/* CS_STAT[REFO_ON] Bits */\r
+#define CS_STAT_REFO_ON_OFS ( 7) /**< REFO_ON Bit Offset */\r
+#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /**< REFO status */\r
+/* CS_STAT[ACLK_ON] Bits */\r
+#define CS_STAT_ACLK_ON_OFS (16) /**< ACLK_ON Bit Offset */\r
+#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /**< ACLK system clock status */\r
+/* CS_STAT[MCLK_ON] Bits */\r
+#define CS_STAT_MCLK_ON_OFS (17) /**< MCLK_ON Bit Offset */\r
+#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /**< MCLK system clock status */\r
+/* CS_STAT[HSMCLK_ON] Bits */\r
+#define CS_STAT_HSMCLK_ON_OFS (18) /**< HSMCLK_ON Bit Offset */\r
+#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /**< HSMCLK system clock status */\r
+/* CS_STAT[SMCLK_ON] Bits */\r
+#define CS_STAT_SMCLK_ON_OFS (19) /**< SMCLK_ON Bit Offset */\r
+#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /**< SMCLK system clock status */\r
+/* CS_STAT[MODCLK_ON] Bits */\r
+#define CS_STAT_MODCLK_ON_OFS (20) /**< MODCLK_ON Bit Offset */\r
+#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /**< MODCLK system clock status */\r
+/* CS_STAT[VLOCLK_ON] Bits */\r
+#define CS_STAT_VLOCLK_ON_OFS (21) /**< VLOCLK_ON Bit Offset */\r
+#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /**< VLOCLK system clock status */\r
+/* CS_STAT[LFXTCLK_ON] Bits */\r
+#define CS_STAT_LFXTCLK_ON_OFS (22) /**< LFXTCLK_ON Bit Offset */\r
+#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /**< LFXTCLK system clock status */\r
+/* CS_STAT[REFOCLK_ON] Bits */\r
+#define CS_STAT_REFOCLK_ON_OFS (23) /**< REFOCLK_ON Bit Offset */\r
+#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /**< REFOCLK system clock status */\r
+/* CS_STAT[ACLK_READY] Bits */\r
+#define CS_STAT_ACLK_READY_OFS (24) /**< ACLK_READY Bit Offset */\r
+#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /**< ACLK Ready status */\r
+/* CS_STAT[MCLK_READY] Bits */\r
+#define CS_STAT_MCLK_READY_OFS (25) /**< MCLK_READY Bit Offset */\r
+#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /**< MCLK Ready status */\r
+/* CS_STAT[HSMCLK_READY] Bits */\r
+#define CS_STAT_HSMCLK_READY_OFS (26) /**< HSMCLK_READY Bit Offset */\r
+#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /**< HSMCLK Ready status */\r
+/* CS_STAT[SMCLK_READY] Bits */\r
+#define CS_STAT_SMCLK_READY_OFS (27) /**< SMCLK_READY Bit Offset */\r
+#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /**< SMCLK Ready status */\r
+/* CS_STAT[BCLK_READY] Bits */\r
+#define CS_STAT_BCLK_READY_OFS (28) /**< BCLK_READY Bit Offset */\r
+#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /**< BCLK Ready status */\r
+/* CS_IE[LFXTIE] Bits */\r
+#define CS_IE_LFXTIE_OFS ( 0) /**< LFXTIE Bit Offset */\r
+#define CS_IE_LFXTIE ((uint32_t)0x00000001) /**< LFXT oscillator fault flag interrupt enable */\r
+/* CS_IE[HFXTIE] Bits */\r
+#define CS_IE_HFXTIE_OFS ( 1) /**< HFXTIE Bit Offset */\r
+#define CS_IE_HFXTIE ((uint32_t)0x00000002) /**< HFXT oscillator fault flag interrupt enable */\r
+/* CS_IE[HFXT2IE] Bits */\r
+#define CS_IE_HFXT2IE_OFS ( 2) /**< HFXT2IE Bit Offset */\r
+#define CS_IE_HFXT2IE ((uint32_t)0x00000004) /**< HFXT2 oscillator fault flag interrupt enable */\r
+/* CS_IE[DCOR_OPNIE] Bits */\r
+#define CS_IE_DCOR_OPNIE_OFS ( 6) /**< DCOR_OPNIE Bit Offset */\r
+#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /**< DCO external resistor open circuit fault flag interrupt enable. */\r
+/* CS_IE[FCNTLFIE] Bits */\r
+#define CS_IE_FCNTLFIE_OFS ( 8) /**< FCNTLFIE Bit Offset */\r
+#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /**< Start fault counter interrupt enable LFXT */\r
+/* CS_IE[FCNTHFIE] Bits */\r
+#define CS_IE_FCNTHFIE_OFS ( 9) /**< FCNTHFIE Bit Offset */\r
+#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /**< Start fault counter interrupt enable HFXT */\r
+/* CS_IE[FCNTHF2IE] Bits */\r
+#define CS_IE_FCNTHF2IE_OFS (10) /**< FCNTHF2IE Bit Offset */\r
+#define CS_IE_FCNTHF2IE ((uint32_t)0x00000400) /**< Start fault counter interrupt enable HFXT2 */\r
+/* CS_IE[PLLOOLIE] Bits */\r
+#define CS_IE_PLLOOLIE_OFS (12) /**< PLLOOLIE Bit Offset */\r
+#define CS_IE_PLLOOLIE ((uint32_t)0x00001000) /**< PLL out-of-lock interrupt enable */\r
+/* CS_IE[PLLLOSIE] Bits */\r
+#define CS_IE_PLLLOSIE_OFS (13) /**< PLLLOSIE Bit Offset */\r
+#define CS_IE_PLLLOSIE ((uint32_t)0x00002000) /**< PLL loss-of-signal interrupt enable */\r
+/* CS_IE[PLLOORIE] Bits */\r
+#define CS_IE_PLLOORIE_OFS (14) /**< PLLOORIE Bit Offset */\r
+#define CS_IE_PLLOORIE ((uint32_t)0x00004000) /**< PLL out-of-range interrupt enable */\r
+/* CS_IE[CALIE] Bits */\r
+#define CS_IE_CALIE_OFS (15) /**< CALIE Bit Offset */\r
+#define CS_IE_CALIE ((uint32_t)0x00008000) /**< REFCNT period counter interrupt enable */\r
+/* CS_IFG[LFXTIFG] Bits */\r
+#define CS_IFG_LFXTIFG_OFS ( 0) /**< LFXTIFG Bit Offset */\r
+#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /**< LFXT oscillator fault flag */\r
+/* CS_IFG[HFXTIFG] Bits */\r
+#define CS_IFG_HFXTIFG_OFS ( 1) /**< HFXTIFG Bit Offset */\r
+#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /**< HFXT oscillator fault flag */\r
+/* CS_IFG[HFXT2IFG] Bits */\r
+#define CS_IFG_HFXT2IFG_OFS ( 2) /**< HFXT2IFG Bit Offset */\r
+#define CS_IFG_HFXT2IFG ((uint32_t)0x00000004) /**< HFXT2 oscillator fault flag */\r
+/* CS_IFG[DCOR_SHTIFG] Bits */\r
+#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /**< DCOR_SHTIFG Bit Offset */\r
+#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /**< DCO external resistor short circuit fault flag. */\r
+/* CS_IFG[DCOR_OPNIFG] Bits */\r
+#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /**< DCOR_OPNIFG Bit Offset */\r
+#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /**< DCO external resistor open circuit fault flag. */\r
+/* CS_IFG[FCNTLFIFG] Bits */\r
+#define CS_IFG_FCNTLFIFG_OFS ( 8) /**< FCNTLFIFG Bit Offset */\r
+#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /**< Start fault counter interrupt flag LFXT */\r
+/* CS_IFG[FCNTHFIFG] Bits */\r
+#define CS_IFG_FCNTHFIFG_OFS ( 9) /**< FCNTHFIFG Bit Offset */\r
+#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /**< Start fault counter interrupt flag HFXT */\r
+/* CS_IFG[FCNTHF2IFG] Bits */\r
+#define CS_IFG_FCNTHF2IFG_OFS (11) /**< FCNTHF2IFG Bit Offset */\r
+#define CS_IFG_FCNTHF2IFG ((uint32_t)0x00000800) /**< Start fault counter interrupt flag HFXT2 */\r
+/* CS_IFG[PLLOOLIFG] Bits */\r
+#define CS_IFG_PLLOOLIFG_OFS (12) /**< PLLOOLIFG Bit Offset */\r
+#define CS_IFG_PLLOOLIFG ((uint32_t)0x00001000) /**< PLL out-of-lock interrupt flag */\r
+/* CS_IFG[PLLLOSIFG] Bits */\r
+#define CS_IFG_PLLLOSIFG_OFS (13) /**< PLLLOSIFG Bit Offset */\r
+#define CS_IFG_PLLLOSIFG ((uint32_t)0x00002000) /**< PLL loss-of-signal interrupt flag */\r
+/* CS_IFG[PLLOORIFG] Bits */\r
+#define CS_IFG_PLLOORIFG_OFS (14) /**< PLLOORIFG Bit Offset */\r
+#define CS_IFG_PLLOORIFG ((uint32_t)0x00004000) /**< PLL out-of-range interrupt flag */\r
+/* CS_IFG[CALIFG] Bits */\r
+#define CS_IFG_CALIFG_OFS (15) /**< CALIFG Bit Offset */\r
+#define CS_IFG_CALIFG ((uint32_t)0x00008000) /**< REFCNT period counter expired */\r
+/* CS_CLRIFG[CLR_LFXTIFG] Bits */\r
+#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /**< CLR_LFXTIFG Bit Offset */\r
+#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /**< Clear LFXT oscillator fault interrupt flag */\r
+/* CS_CLRIFG[CLR_HFXTIFG] Bits */\r
+#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /**< CLR_HFXTIFG Bit Offset */\r
+#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /**< Clear HFXT oscillator fault interrupt flag */\r
+/* CS_CLRIFG[CLR_HFXT2IFG] Bits */\r
+#define CS_CLRIFG_CLR_HFXT2IFG_OFS ( 2) /**< CLR_HFXT2IFG Bit Offset */\r
+#define CS_CLRIFG_CLR_HFXT2IFG ((uint32_t)0x00000004) /**< Clear HFXT2 oscillator fault interrupt flag */\r
+/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */\r
+#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /**< CLR_DCOR_OPNIFG Bit Offset */\r
+#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /**< Clear DCO external resistor open circuit fault interrupt flag. */\r
+/* CS_CLRIFG[CLR_CALIFG] Bits */\r
+#define CS_CLRIFG_CLR_CALIFG_OFS (15) /**< CLR_CALIFG Bit Offset */\r
+#define CS_CLRIFG_CLR_CALIFG ((uint32_t)0x00008000) /**< REFCNT period counter clear interrupt flag */\r
+/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */\r
+#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /**< CLR_FCNTLFIFG Bit Offset */\r
+#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /**< Start fault counter clear interrupt flag LFXT */\r
+/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */\r
+#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /**< CLR_FCNTHFIFG Bit Offset */\r
+#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /**< Start fault counter clear interrupt flag HFXT */\r
+/* CS_CLRIFG[CLR_FCNTHF2IFG] Bits */\r
+#define CS_CLRIFG_CLR_FCNTHF2IFG_OFS (10) /**< CLR_FCNTHF2IFG Bit Offset */\r
+#define CS_CLRIFG_CLR_FCNTHF2IFG ((uint32_t)0x00000400) /**< Start fault counter clear interrupt flag HFXT2 */\r
+/* CS_CLRIFG[CLR_PLLOOLIFG] Bits */\r
+#define CS_CLRIFG_CLR_PLLOOLIFG_OFS (12) /**< CLR_PLLOOLIFG Bit Offset */\r
+#define CS_CLRIFG_CLR_PLLOOLIFG ((uint32_t)0x00001000) /**< PLL out-of-lock clear interrupt flag */\r
+/* CS_CLRIFG[CLR_PLLLOSIFG] Bits */\r
+#define CS_CLRIFG_CLR_PLLLOSIFG_OFS (13) /**< CLR_PLLLOSIFG Bit Offset */\r
+#define CS_CLRIFG_CLR_PLLLOSIFG ((uint32_t)0x00002000) /**< PLL loss-of-signal clear interrupt flag */\r
+/* CS_CLRIFG[CLR_PLLOORIFG] Bits */\r
+#define CS_CLRIFG_CLR_PLLOORIFG_OFS (14) /**< CLR_PLLOORIFG Bit Offset */\r
+#define CS_CLRIFG_CLR_PLLOORIFG ((uint32_t)0x00004000) /**< PLL out-of-range clear interrupt flag */\r
+/* CS_SETIFG[SET_LFXTIFG] Bits */\r
+#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /**< SET_LFXTIFG Bit Offset */\r
+#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /**< Set LFXT oscillator fault interrupt flag */\r
+/* CS_SETIFG[SET_HFXTIFG] Bits */\r
+#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /**< SET_HFXTIFG Bit Offset */\r
+#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /**< Set HFXT oscillator fault interrupt flag */\r
+/* CS_SETIFG[SET_HFXT2IFG] Bits */\r
+#define CS_SETIFG_SET_HFXT2IFG_OFS ( 2) /**< SET_HFXT2IFG Bit Offset */\r
+#define CS_SETIFG_SET_HFXT2IFG ((uint32_t)0x00000004) /**< Set HFXT2 oscillator fault interrupt flag */\r
+/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */\r
+#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /**< SET_DCOR_OPNIFG Bit Offset */\r
+#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /**< Set DCO external resistor open circuit fault interrupt flag. */\r
+/* CS_SETIFG[SET_CALIFG] Bits */\r
+#define CS_SETIFG_SET_CALIFG_OFS (15) /**< SET_CALIFG Bit Offset */\r
+#define CS_SETIFG_SET_CALIFG ((uint32_t)0x00008000) /**< REFCNT period counter set interrupt flag */\r
+/* CS_SETIFG[SET_FCNTHFIFG] Bits */\r
+#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /**< SET_FCNTHFIFG Bit Offset */\r
+#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /**< Start fault counter set interrupt flag HFXT */\r
+/* CS_SETIFG[SET_FCNTHF2IFG] Bits */\r
+#define CS_SETIFG_SET_FCNTHF2IFG_OFS (10) /**< SET_FCNTHF2IFG Bit Offset */\r
+#define CS_SETIFG_SET_FCNTHF2IFG ((uint32_t)0x00000400) /**< Start fault counter set interrupt flag HFXT2 */\r
+/* CS_SETIFG[SET_FCNTLFIFG] Bits */\r
+#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /**< SET_FCNTLFIFG Bit Offset */\r
+#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /**< Start fault counter set interrupt flag LFXT */\r
+/* CS_SETIFG[SET_PLLOOLIFG] Bits */\r
+#define CS_SETIFG_SET_PLLOOLIFG_OFS (12) /**< SET_PLLOOLIFG Bit Offset */\r
+#define CS_SETIFG_SET_PLLOOLIFG ((uint32_t)0x00001000) /**< PLL out-of-lock set interrupt flag */\r
+/* CS_SETIFG[SET_PLLLOSIFG] Bits */\r
+#define CS_SETIFG_SET_PLLLOSIFG_OFS (13) /**< SET_PLLLOSIFG Bit Offset */\r
+#define CS_SETIFG_SET_PLLLOSIFG ((uint32_t)0x00002000) /**< PLL loss-of-signal set interrupt flag */\r
+/* CS_SETIFG[SET_PLLOORIFG] Bits */\r
+#define CS_SETIFG_SET_PLLOORIFG_OFS (14) /**< SET_PLLOORIFG Bit Offset */\r
+#define CS_SETIFG_SET_PLLOORIFG ((uint32_t)0x00004000) /**< PLL out-of-range set interrupt flag */\r
+/* CS_DCOERCAL0[DCO_TCCAL] Bits */\r
+#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /**< DCO_TCCAL Bit Offset */\r
+#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /**< DCO_TCCAL Bit Mask */\r
+/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */\r
+#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /**< DCO_FCAL_RSEL04 Bit Offset */\r
+#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /**< DCO_FCAL_RSEL04 Bit Mask */\r
+/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */\r
+#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /**< DCO_FCAL_RSEL5 Bit Offset */\r
+#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /**< DCO_FCAL_RSEL5 Bit Mask */\r
\r
/* Pre-defined bitfield values */\r
-#define CSKEY_VAL (0x0000695A) /* CS control key value */\r
-\r
-\r
-//*****************************************************************************\r
-// DIO Bits\r
-//*****************************************************************************\r
-/* PAIN[P1IN] Bits */\r
-#define P1IN_OFS ( 0) /* P1IN Offset */\r
-#define P1IN_M (0x00ff) /* Port 1 Input */\r
-/* PAIN[P2IN] Bits */\r
-#define P2IN_OFS ( 8) /* P2IN Offset */\r
-#define P2IN_M (0xff00) /* Port 2 Input */\r
-/* PAOUT[P2OUT] Bits */\r
-#define P2OUT_OFS ( 8) /* P2OUT Offset */\r
-#define P2OUT_M (0xff00) /* Port 2 Output */\r
-/* PAOUT[P1OUT] Bits */\r
-#define P1OUT_OFS ( 0) /* P1OUT Offset */\r
-#define P1OUT_M (0x00ff) /* Port 1 Output */\r
-/* PADIR[P1DIR] Bits */\r
-#define P1DIR_OFS ( 0) /* P1DIR Offset */\r
-#define P1DIR_M (0x00ff) /* Port 1 Direction */\r
-/* PADIR[P2DIR] Bits */\r
-#define P2DIR_OFS ( 8) /* P2DIR Offset */\r
-#define P2DIR_M (0xff00) /* Port 2 Direction */\r
-/* PAREN[P1REN] Bits */\r
-#define P1REN_OFS ( 0) /* P1REN Offset */\r
-#define P1REN_M (0x00ff) /* Port 1 Resistor Enable */\r
-/* PAREN[P2REN] Bits */\r
-#define P2REN_OFS ( 8) /* P2REN Offset */\r
-#define P2REN_M (0xff00) /* Port 2 Resistor Enable */\r
-/* PADS[P1DS] Bits */\r
-#define P1DS_OFS ( 0) /* P1DS Offset */\r
-#define P1DS_M (0x00ff) /* Port 1 Drive Strength */\r
-/* PADS[P2DS] Bits */\r
-#define P2DS_OFS ( 8) /* P2DS Offset */\r
-#define P2DS_M (0xff00) /* Port 2 Drive Strength */\r
-/* PASEL0[P1SEL0] Bits */\r
-#define P1SEL0_OFS ( 0) /* P1SEL0 Offset */\r
-#define P1SEL0_M (0x00ff) /* Port 1 Select 0 */\r
-/* PASEL0[P2SEL0] Bits */\r
-#define P2SEL0_OFS ( 8) /* P2SEL0 Offset */\r
-#define P2SEL0_M (0xff00) /* Port 2 Select 0 */\r
-/* PASEL1[P1SEL1] Bits */\r
-#define P1SEL1_OFS ( 0) /* P1SEL1 Offset */\r
-#define P1SEL1_M (0x00ff) /* Port 1 Select 1 */\r
-/* PASEL1[P2SEL1] Bits */\r
-#define P2SEL1_OFS ( 8) /* P2SEL1 Offset */\r
-#define P2SEL1_M (0xff00) /* Port 2 Select 1 */\r
-/* P1IV[P1IV] Bits */\r
-#define P1IV_OFS ( 0) /* P1IV Offset */\r
-#define P1IV_M (0x001f) /* Port 1 interrupt vector value */\r
-#define P1IV0 (0x0001) /* Port 1 interrupt vector value */\r
-#define P1IV1 (0x0002) /* Port 1 interrupt vector value */\r
-#define P1IV2 (0x0004) /* Port 1 interrupt vector value */\r
-#define P1IV3 (0x0008) /* Port 1 interrupt vector value */\r
-#define P1IV4 (0x0010) /* Port 1 interrupt vector value */\r
-#define P1IV_0 (0x0000) /* No interrupt pending */\r
-#define P1IV_2 (0x0002) /* Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */\r
-#define P1IV_4 (0x0004) /* Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */\r
-#define P1IV_6 (0x0006) /* Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */\r
-#define P1IV_8 (0x0008) /* Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */\r
-#define P1IV_10 (0x000a) /* Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */\r
-#define P1IV_12 (0x000c) /* Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */\r
-#define P1IV_14 (0x000e) /* Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */\r
-#define P1IV_16 (0x0010) /* Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */\r
-#define P1IV__NONE (0x0000) /* No interrupt pending */\r
-#define P1IV__P1IFG0 (0x0002) /* Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */\r
-#define P1IV__P1IFG1 (0x0004) /* Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */\r
-#define P1IV__P1IFG2 (0x0006) /* Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */\r
-#define P1IV__P1IFG3 (0x0008) /* Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */\r
-#define P1IV__P1IFG4 (0x000a) /* Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */\r
-#define P1IV__P1IFG5 (0x000c) /* Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */\r
-#define P1IV__P1IFG6 (0x000e) /* Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */\r
-#define P1IV__P1IFG7 (0x0010) /* Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */\r
-/* PASELC[P1SELC] Bits */\r
-#define P1SELC_OFS ( 0) /* P1SELC Offset */\r
-#define P1SELC_M (0x00ff) /* Port 1 Complement Select */\r
-/* PASELC[P2SELC] Bits */\r
-#define P2SELC_OFS ( 8) /* P2SELC Offset */\r
-#define P2SELC_M (0xff00) /* Port 2 Complement Select */\r
-/* PAIES[P1IES] Bits */\r
-#define P1IES_OFS ( 0) /* P1IES Offset */\r
-#define P1IES_M (0x00ff) /* Port 1 Interrupt Edge Select */\r
-/* PAIES[P2IES] Bits */\r
-#define P2IES_OFS ( 8) /* P2IES Offset */\r
-#define P2IES_M (0xff00) /* Port 2 Interrupt Edge Select */\r
-/* PAIE[P1IE] Bits */\r
-#define P1IE_OFS ( 0) /* P1IE Offset */\r
-#define P1IE_M (0x00ff) /* Port 1 Interrupt Enable */\r
-/* PAIE[P2IE] Bits */\r
-#define P2IE_OFS ( 8) /* P2IE Offset */\r
-#define P2IE_M (0xff00) /* Port 2 Interrupt Enable */\r
-/* PAIFG[P1IFG] Bits */\r
-#define P1IFG_OFS ( 0) /* P1IFG Offset */\r
-#define P1IFG_M (0x00ff) /* Port 1 Interrupt Flag */\r
-/* PAIFG[P2IFG] Bits */\r
-#define P2IFG_OFS ( 8) /* P2IFG Offset */\r
-#define P2IFG_M (0xff00) /* Port 2 Interrupt Flag */\r
-/* P2IV[P2IV] Bits */\r
-#define P2IV_OFS ( 0) /* P2IV Offset */\r
-#define P2IV_M (0x001f) /* Port 2 interrupt vector value */\r
-#define P2IV0 (0x0001) /* Port 2 interrupt vector value */\r
-#define P2IV1 (0x0002) /* Port 2 interrupt vector value */\r
-#define P2IV2 (0x0004) /* Port 2 interrupt vector value */\r
-#define P2IV3 (0x0008) /* Port 2 interrupt vector value */\r
-#define P2IV4 (0x0010) /* Port 2 interrupt vector value */\r
-#define P2IV_0 (0x0000) /* No interrupt pending */\r
-#define P2IV_2 (0x0002) /* Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */\r
-#define P2IV_4 (0x0004) /* Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */\r
-#define P2IV_6 (0x0006) /* Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */\r
-#define P2IV_8 (0x0008) /* Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */\r
-#define P2IV_10 (0x000a) /* Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */\r
-#define P2IV_12 (0x000c) /* Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */\r
-#define P2IV_14 (0x000e) /* Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */\r
-#define P2IV_16 (0x0010) /* Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */\r
-#define P2IV__NONE (0x0000) /* No interrupt pending */\r
-#define P2IV__P2IFG0 (0x0002) /* Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */\r
-#define P2IV__P2IFG1 (0x0004) /* Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */\r
-#define P2IV__P2IFG2 (0x0006) /* Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */\r
-#define P2IV__P2IFG3 (0x0008) /* Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */\r
-#define P2IV__P2IFG4 (0x000a) /* Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */\r
-#define P2IV__P2IFG5 (0x000c) /* Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */\r
-#define P2IV__P2IFG6 (0x000e) /* Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */\r
-#define P2IV__P2IFG7 (0x0010) /* Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */\r
-/* PBIN[P3IN] Bits */\r
-#define P3IN_OFS ( 0) /* P3IN Offset */\r
-#define P3IN_M (0x00ff) /* Port 3 Input */\r
-/* PBIN[P4IN] Bits */\r
-#define P4IN_OFS ( 8) /* P4IN Offset */\r
-#define P4IN_M (0xff00) /* Port 4 Input */\r
-/* PBOUT[P3OUT] Bits */\r
-#define P3OUT_OFS ( 0) /* P3OUT Offset */\r
-#define P3OUT_M (0x00ff) /* Port 3 Output */\r
-/* PBOUT[P4OUT] Bits */\r
-#define P4OUT_OFS ( 8) /* P4OUT Offset */\r
-#define P4OUT_M (0xff00) /* Port 4 Output */\r
-/* PBDIR[P3DIR] Bits */\r
-#define P3DIR_OFS ( 0) /* P3DIR Offset */\r
-#define P3DIR_M (0x00ff) /* Port 3 Direction */\r
-/* PBDIR[P4DIR] Bits */\r
-#define P4DIR_OFS ( 8) /* P4DIR Offset */\r
-#define P4DIR_M (0xff00) /* Port 4 Direction */\r
-/* PBREN[P3REN] Bits */\r
-#define P3REN_OFS ( 0) /* P3REN Offset */\r
-#define P3REN_M (0x00ff) /* Port 3 Resistor Enable */\r
-/* PBREN[P4REN] Bits */\r
-#define P4REN_OFS ( 8) /* P4REN Offset */\r
-#define P4REN_M (0xff00) /* Port 4 Resistor Enable */\r
-/* PBDS[P3DS] Bits */\r
-#define P3DS_OFS ( 0) /* P3DS Offset */\r
-#define P3DS_M (0x00ff) /* Port 3 Drive Strength */\r
-/* PBDS[P4DS] Bits */\r
-#define P4DS_OFS ( 8) /* P4DS Offset */\r
-#define P4DS_M (0xff00) /* Port 4 Drive Strength */\r
-/* PBSEL0[P4SEL0] Bits */\r
-#define P4SEL0_OFS ( 8) /* P4SEL0 Offset */\r
-#define P4SEL0_M (0xff00) /* Port 4 Select 0 */\r
-/* PBSEL0[P3SEL0] Bits */\r
-#define P3SEL0_OFS ( 0) /* P3SEL0 Offset */\r
-#define P3SEL0_M (0x00ff) /* Port 3 Select 0 */\r
-/* PBSEL1[P3SEL1] Bits */\r
-#define P3SEL1_OFS ( 0) /* P3SEL1 Offset */\r
-#define P3SEL1_M (0x00ff) /* Port 3 Select 1 */\r
-/* PBSEL1[P4SEL1] Bits */\r
-#define P4SEL1_OFS ( 8) /* P4SEL1 Offset */\r
-#define P4SEL1_M (0xff00) /* Port 4 Select 1 */\r
-/* P3IV[P3IV] Bits */\r
-#define P3IV_OFS ( 0) /* P3IV Offset */\r
-#define P3IV_M (0x001f) /* Port 3 interrupt vector value */\r
-#define P3IV0 (0x0001) /* Port 3 interrupt vector value */\r
-#define P3IV1 (0x0002) /* Port 3 interrupt vector value */\r
-#define P3IV2 (0x0004) /* Port 3 interrupt vector value */\r
-#define P3IV3 (0x0008) /* Port 3 interrupt vector value */\r
-#define P3IV4 (0x0010) /* Port 3 interrupt vector value */\r
-#define P3IV_0 (0x0000) /* No interrupt pending */\r
-#define P3IV_2 (0x0002) /* Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */\r
-#define P3IV_4 (0x0004) /* Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */\r
-#define P3IV_6 (0x0006) /* Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */\r
-#define P3IV_8 (0x0008) /* Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */\r
-#define P3IV_10 (0x000a) /* Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */\r
-#define P3IV_12 (0x000c) /* Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */\r
-#define P3IV_14 (0x000e) /* Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */\r
-#define P3IV_16 (0x0010) /* Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */\r
-#define P3IV__NONE (0x0000) /* No interrupt pending */\r
-#define P3IV__P3IFG0 (0x0002) /* Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */\r
-#define P3IV__P3IFG1 (0x0004) /* Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */\r
-#define P3IV__P3IFG2 (0x0006) /* Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */\r
-#define P3IV__P3IFG3 (0x0008) /* Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */\r
-#define P3IV__P3IFG4 (0x000a) /* Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */\r
-#define P3IV__P3IFG5 (0x000c) /* Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */\r
-#define P3IV__P3IFG6 (0x000e) /* Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */\r
-#define P3IV__P3IFG7 (0x0010) /* Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */\r
-/* PBSELC[P3SELC] Bits */\r
-#define P3SELC_OFS ( 0) /* P3SELC Offset */\r
-#define P3SELC_M (0x00ff) /* Port 3 Complement Select */\r
-/* PBSELC[P4SELC] Bits */\r
-#define P4SELC_OFS ( 8) /* P4SELC Offset */\r
-#define P4SELC_M (0xff00) /* Port 4 Complement Select */\r
-/* PBIES[P3IES] Bits */\r
-#define P3IES_OFS ( 0) /* P3IES Offset */\r
-#define P3IES_M (0x00ff) /* Port 3 Interrupt Edge Select */\r
-/* PBIES[P4IES] Bits */\r
-#define P4IES_OFS ( 8) /* P4IES Offset */\r
-#define P4IES_M (0xff00) /* Port 4 Interrupt Edge Select */\r
-/* PBIE[P3IE] Bits */\r
-#define P3IE_OFS ( 0) /* P3IE Offset */\r
-#define P3IE_M (0x00ff) /* Port 3 Interrupt Enable */\r
-/* PBIE[P4IE] Bits */\r
-#define P4IE_OFS ( 8) /* P4IE Offset */\r
-#define P4IE_M (0xff00) /* Port 4 Interrupt Enable */\r
-/* PBIFG[P3IFG] Bits */\r
-#define P3IFG_OFS ( 0) /* P3IFG Offset */\r
-#define P3IFG_M (0x00ff) /* Port 3 Interrupt Flag */\r
-/* PBIFG[P4IFG] Bits */\r
-#define P4IFG_OFS ( 8) /* P4IFG Offset */\r
-#define P4IFG_M (0xff00) /* Port 4 Interrupt Flag */\r
-/* P4IV[P4IV] Bits */\r
-#define P4IV_OFS ( 0) /* P4IV Offset */\r
-#define P4IV_M (0x001f) /* Port 4 interrupt vector value */\r
-#define P4IV0 (0x0001) /* Port 4 interrupt vector value */\r
-#define P4IV1 (0x0002) /* Port 4 interrupt vector value */\r
-#define P4IV2 (0x0004) /* Port 4 interrupt vector value */\r
-#define P4IV3 (0x0008) /* Port 4 interrupt vector value */\r
-#define P4IV4 (0x0010) /* Port 4 interrupt vector value */\r
-#define P4IV_0 (0x0000) /* No interrupt pending */\r
-#define P4IV_2 (0x0002) /* Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */\r
-#define P4IV_4 (0x0004) /* Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */\r
-#define P4IV_6 (0x0006) /* Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */\r
-#define P4IV_8 (0x0008) /* Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */\r
-#define P4IV_10 (0x000a) /* Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */\r
-#define P4IV_12 (0x000c) /* Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */\r
-#define P4IV_14 (0x000e) /* Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */\r
-#define P4IV_16 (0x0010) /* Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */\r
-#define P4IV__NONE (0x0000) /* No interrupt pending */\r
-#define P4IV__P4IFG0 (0x0002) /* Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */\r
-#define P4IV__P4IFG1 (0x0004) /* Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */\r
-#define P4IV__P4IFG2 (0x0006) /* Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */\r
-#define P4IV__P4IFG3 (0x0008) /* Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */\r
-#define P4IV__P4IFG4 (0x000a) /* Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */\r
-#define P4IV__P4IFG5 (0x000c) /* Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */\r
-#define P4IV__P4IFG6 (0x000e) /* Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */\r
-#define P4IV__P4IFG7 (0x0010) /* Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */\r
-/* PCIN[P5IN] Bits */\r
-#define P5IN_OFS ( 0) /* P5IN Offset */\r
-#define P5IN_M (0x00ff) /* Port 5 Input */\r
-/* PCIN[P6IN] Bits */\r
-#define P6IN_OFS ( 8) /* P6IN Offset */\r
-#define P6IN_M (0xff00) /* Port 6 Input */\r
-/* PCOUT[P5OUT] Bits */\r
-#define P5OUT_OFS ( 0) /* P5OUT Offset */\r
-#define P5OUT_M (0x00ff) /* Port 5 Output */\r
-/* PCOUT[P6OUT] Bits */\r
-#define P6OUT_OFS ( 8) /* P6OUT Offset */\r
-#define P6OUT_M (0xff00) /* Port 6 Output */\r
-/* PCDIR[P5DIR] Bits */\r
-#define P5DIR_OFS ( 0) /* P5DIR Offset */\r
-#define P5DIR_M (0x00ff) /* Port 5 Direction */\r
-/* PCDIR[P6DIR] Bits */\r
-#define P6DIR_OFS ( 8) /* P6DIR Offset */\r
-#define P6DIR_M (0xff00) /* Port 6 Direction */\r
-/* PCREN[P5REN] Bits */\r
-#define P5REN_OFS ( 0) /* P5REN Offset */\r
-#define P5REN_M (0x00ff) /* Port 5 Resistor Enable */\r
-/* PCREN[P6REN] Bits */\r
-#define P6REN_OFS ( 8) /* P6REN Offset */\r
-#define P6REN_M (0xff00) /* Port 6 Resistor Enable */\r
-/* PCDS[P5DS] Bits */\r
-#define P5DS_OFS ( 0) /* P5DS Offset */\r
-#define P5DS_M (0x00ff) /* Port 5 Drive Strength */\r
-/* PCDS[P6DS] Bits */\r
-#define P6DS_OFS ( 8) /* P6DS Offset */\r
-#define P6DS_M (0xff00) /* Port 6 Drive Strength */\r
-/* PCSEL0[P5SEL0] Bits */\r
-#define P5SEL0_OFS ( 0) /* P5SEL0 Offset */\r
-#define P5SEL0_M (0x00ff) /* Port 5 Select 0 */\r
-/* PCSEL0[P6SEL0] Bits */\r
-#define P6SEL0_OFS ( 8) /* P6SEL0 Offset */\r
-#define P6SEL0_M (0xff00) /* Port 6 Select 0 */\r
-/* PCSEL1[P5SEL1] Bits */\r
-#define P5SEL1_OFS ( 0) /* P5SEL1 Offset */\r
-#define P5SEL1_M (0x00ff) /* Port 5 Select 1 */\r
-/* PCSEL1[P6SEL1] Bits */\r
-#define P6SEL1_OFS ( 8) /* P6SEL1 Offset */\r
-#define P6SEL1_M (0xff00) /* Port 6 Select 1 */\r
-/* P5IV[P5IV] Bits */\r
-#define P5IV_OFS ( 0) /* P5IV Offset */\r
-#define P5IV_M (0x001f) /* Port 5 interrupt vector value */\r
-#define P5IV0 (0x0001) /* Port 5 interrupt vector value */\r
-#define P5IV1 (0x0002) /* Port 5 interrupt vector value */\r
-#define P5IV2 (0x0004) /* Port 5 interrupt vector value */\r
-#define P5IV3 (0x0008) /* Port 5 interrupt vector value */\r
-#define P5IV4 (0x0010) /* Port 5 interrupt vector value */\r
-#define P5IV_0 (0x0000) /* No interrupt pending */\r
-#define P5IV_2 (0x0002) /* Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */\r
-#define P5IV_4 (0x0004) /* Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */\r
-#define P5IV_6 (0x0006) /* Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */\r
-#define P5IV_8 (0x0008) /* Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */\r
-#define P5IV_10 (0x000a) /* Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */\r
-#define P5IV_12 (0x000c) /* Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */\r
-#define P5IV_14 (0x000e) /* Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */\r
-#define P5IV_16 (0x0010) /* Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */\r
-#define P5IV__NONE (0x0000) /* No interrupt pending */\r
-#define P5IV__P5IFG0 (0x0002) /* Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */\r
-#define P5IV__P5IFG1 (0x0004) /* Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */\r
-#define P5IV__P5IFG2 (0x0006) /* Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */\r
-#define P5IV__P5IFG3 (0x0008) /* Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */\r
-#define P5IV__P5IFG4 (0x000a) /* Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */\r
-#define P5IV__P5IFG5 (0x000c) /* Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */\r
-#define P5IV__P5IFG6 (0x000e) /* Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */\r
-#define P5IV__P5IFG7 (0x0010) /* Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */\r
-/* PCSELC[P5SELC] Bits */\r
-#define P5SELC_OFS ( 0) /* P5SELC Offset */\r
-#define P5SELC_M (0x00ff) /* Port 5 Complement Select */\r
-/* PCSELC[P6SELC] Bits */\r
-#define P6SELC_OFS ( 8) /* P6SELC Offset */\r
-#define P6SELC_M (0xff00) /* Port 6 Complement Select */\r
-/* PCIES[P5IES] Bits */\r
-#define P5IES_OFS ( 0) /* P5IES Offset */\r
-#define P5IES_M (0x00ff) /* Port 5 Interrupt Edge Select */\r
-/* PCIES[P6IES] Bits */\r
-#define P6IES_OFS ( 8) /* P6IES Offset */\r
-#define P6IES_M (0xff00) /* Port 6 Interrupt Edge Select */\r
-/* PCIE[P5IE] Bits */\r
-#define P5IE_OFS ( 0) /* P5IE Offset */\r
-#define P5IE_M (0x00ff) /* Port 5 Interrupt Enable */\r
-/* PCIE[P6IE] Bits */\r
-#define P6IE_OFS ( 8) /* P6IE Offset */\r
-#define P6IE_M (0xff00) /* Port 6 Interrupt Enable */\r
-/* PCIFG[P5IFG] Bits */\r
-#define P5IFG_OFS ( 0) /* P5IFG Offset */\r
-#define P5IFG_M (0x00ff) /* Port 5 Interrupt Flag */\r
-/* PCIFG[P6IFG] Bits */\r
-#define P6IFG_OFS ( 8) /* P6IFG Offset */\r
-#define P6IFG_M (0xff00) /* Port 6 Interrupt Flag */\r
-/* P6IV[P6IV] Bits */\r
-#define P6IV_OFS ( 0) /* P6IV Offset */\r
-#define P6IV_M (0x001f) /* Port 6 interrupt vector value */\r
-#define P6IV0 (0x0001) /* Port 6 interrupt vector value */\r
-#define P6IV1 (0x0002) /* Port 6 interrupt vector value */\r
-#define P6IV2 (0x0004) /* Port 6 interrupt vector value */\r
-#define P6IV3 (0x0008) /* Port 6 interrupt vector value */\r
-#define P6IV4 (0x0010) /* Port 6 interrupt vector value */\r
-#define P6IV_0 (0x0000) /* No interrupt pending */\r
-#define P6IV_2 (0x0002) /* Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */\r
-#define P6IV_4 (0x0004) /* Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */\r
-#define P6IV_6 (0x0006) /* Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */\r
-#define P6IV_8 (0x0008) /* Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */\r
-#define P6IV_10 (0x000a) /* Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */\r
-#define P6IV_12 (0x000c) /* Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */\r
-#define P6IV_14 (0x000e) /* Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */\r
-#define P6IV_16 (0x0010) /* Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */\r
-#define P6IV__NONE (0x0000) /* No interrupt pending */\r
-#define P6IV__P6IFG0 (0x0002) /* Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */\r
-#define P6IV__P6IFG1 (0x0004) /* Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */\r
-#define P6IV__P6IFG2 (0x0006) /* Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */\r
-#define P6IV__P6IFG3 (0x0008) /* Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */\r
-#define P6IV__P6IFG4 (0x000a) /* Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */\r
-#define P6IV__P6IFG5 (0x000c) /* Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */\r
-#define P6IV__P6IFG6 (0x000e) /* Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */\r
-#define P6IV__P6IFG7 (0x0010) /* Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */\r
-/* PDIN[P7IN] Bits */\r
-#define P7IN_OFS ( 0) /* P7IN Offset */\r
-#define P7IN_M (0x00ff) /* Port 7 Input */\r
-/* PDIN[P8IN] Bits */\r
-#define P8IN_OFS ( 8) /* P8IN Offset */\r
-#define P8IN_M (0xff00) /* Port 8 Input */\r
-/* PDOUT[P7OUT] Bits */\r
-#define P7OUT_OFS ( 0) /* P7OUT Offset */\r
-#define P7OUT_M (0x00ff) /* Port 7 Output */\r
-/* PDOUT[P8OUT] Bits */\r
-#define P8OUT_OFS ( 8) /* P8OUT Offset */\r
-#define P8OUT_M (0xff00) /* Port 8 Output */\r
-/* PDDIR[P7DIR] Bits */\r
-#define P7DIR_OFS ( 0) /* P7DIR Offset */\r
-#define P7DIR_M (0x00ff) /* Port 7 Direction */\r
-/* PDDIR[P8DIR] Bits */\r
-#define P8DIR_OFS ( 8) /* P8DIR Offset */\r
-#define P8DIR_M (0xff00) /* Port 8 Direction */\r
-/* PDREN[P7REN] Bits */\r
-#define P7REN_OFS ( 0) /* P7REN Offset */\r
-#define P7REN_M (0x00ff) /* Port 7 Resistor Enable */\r
-/* PDREN[P8REN] Bits */\r
-#define P8REN_OFS ( 8) /* P8REN Offset */\r
-#define P8REN_M (0xff00) /* Port 8 Resistor Enable */\r
-/* PDDS[P7DS] Bits */\r
-#define P7DS_OFS ( 0) /* P7DS Offset */\r
-#define P7DS_M (0x00ff) /* Port 7 Drive Strength */\r
-/* PDDS[P8DS] Bits */\r
-#define P8DS_OFS ( 8) /* P8DS Offset */\r
-#define P8DS_M (0xff00) /* Port 8 Drive Strength */\r
-/* PDSEL0[P7SEL0] Bits */\r
-#define P7SEL0_OFS ( 0) /* P7SEL0 Offset */\r
-#define P7SEL0_M (0x00ff) /* Port 7 Select 0 */\r
-/* PDSEL0[P8SEL0] Bits */\r
-#define P8SEL0_OFS ( 8) /* P8SEL0 Offset */\r
-#define P8SEL0_M (0xff00) /* Port 8 Select 0 */\r
-/* PDSEL1[P7SEL1] Bits */\r
-#define P7SEL1_OFS ( 0) /* P7SEL1 Offset */\r
-#define P7SEL1_M (0x00ff) /* Port 7 Select 1 */\r
-/* PDSEL1[P8SEL1] Bits */\r
-#define P8SEL1_OFS ( 8) /* P8SEL1 Offset */\r
-#define P8SEL1_M (0xff00) /* Port 8 Select 1 */\r
-/* P7IV[P7IV] Bits */\r
-#define P7IV_OFS ( 0) /* P7IV Offset */\r
-#define P7IV_M (0x001f) /* Port 7 interrupt vector value */\r
-#define P7IV0 (0x0001) /* Port 7 interrupt vector value */\r
-#define P7IV1 (0x0002) /* Port 7 interrupt vector value */\r
-#define P7IV2 (0x0004) /* Port 7 interrupt vector value */\r
-#define P7IV3 (0x0008) /* Port 7 interrupt vector value */\r
-#define P7IV4 (0x0010) /* Port 7 interrupt vector value */\r
-#define P7IV_0 (0x0000) /* No interrupt pending */\r
-#define P7IV_2 (0x0002) /* Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */\r
-#define P7IV_4 (0x0004) /* Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */\r
-#define P7IV_6 (0x0006) /* Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */\r
-#define P7IV_8 (0x0008) /* Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */\r
-#define P7IV_10 (0x000a) /* Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */\r
-#define P7IV_12 (0x000c) /* Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */\r
-#define P7IV_14 (0x000e) /* Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */\r
-#define P7IV_16 (0x0010) /* Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */\r
-#define P7IV__NONE (0x0000) /* No interrupt pending */\r
-#define P7IV__P7IFG0 (0x0002) /* Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */\r
-#define P7IV__P7IFG1 (0x0004) /* Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */\r
-#define P7IV__P7IFG2 (0x0006) /* Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */\r
-#define P7IV__P7IFG3 (0x0008) /* Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */\r
-#define P7IV__P7IFG4 (0x000a) /* Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */\r
-#define P7IV__P7IFG5 (0x000c) /* Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */\r
-#define P7IV__P7IFG6 (0x000e) /* Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */\r
-#define P7IV__P7IFG7 (0x0010) /* Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */\r
-/* PDSELC[P7SELC] Bits */\r
-#define P7SELC_OFS ( 0) /* P7SELC Offset */\r
-#define P7SELC_M (0x00ff) /* Port 7 Complement Select */\r
-/* PDSELC[P8SELC] Bits */\r
-#define P8SELC_OFS ( 8) /* P8SELC Offset */\r
-#define P8SELC_M (0xff00) /* Port 8 Complement Select */\r
-/* PDIES[P7IES] Bits */\r
-#define P7IES_OFS ( 0) /* P7IES Offset */\r
-#define P7IES_M (0x00ff) /* Port 7 Interrupt Edge Select */\r
-/* PDIES[P8IES] Bits */\r
-#define P8IES_OFS ( 8) /* P8IES Offset */\r
-#define P8IES_M (0xff00) /* Port 8 Interrupt Edge Select */\r
-/* PDIE[P7IE] Bits */\r
-#define P7IE_OFS ( 0) /* P7IE Offset */\r
-#define P7IE_M (0x00ff) /* Port 7 Interrupt Enable */\r
-/* PDIE[P8IE] Bits */\r
-#define P8IE_OFS ( 8) /* P8IE Offset */\r
-#define P8IE_M (0xff00) /* Port 8 Interrupt Enable */\r
-/* PDIFG[P7IFG] Bits */\r
-#define P7IFG_OFS ( 0) /* P7IFG Offset */\r
-#define P7IFG_M (0x00ff) /* Port 7 Interrupt Flag */\r
-/* PDIFG[P8IFG] Bits */\r
-#define P8IFG_OFS ( 8) /* P8IFG Offset */\r
-#define P8IFG_M (0xff00) /* Port 8 Interrupt Flag */\r
-/* P8IV[P8IV] Bits */\r
-#define P8IV_OFS ( 0) /* P8IV Offset */\r
-#define P8IV_M (0x001f) /* Port 8 interrupt vector value */\r
-#define P8IV0 (0x0001) /* Port 8 interrupt vector value */\r
-#define P8IV1 (0x0002) /* Port 8 interrupt vector value */\r
-#define P8IV2 (0x0004) /* Port 8 interrupt vector value */\r
-#define P8IV3 (0x0008) /* Port 8 interrupt vector value */\r
-#define P8IV4 (0x0010) /* Port 8 interrupt vector value */\r
-#define P8IV_0 (0x0000) /* No interrupt pending */\r
-#define P8IV_2 (0x0002) /* Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */\r
-#define P8IV_4 (0x0004) /* Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */\r
-#define P8IV_6 (0x0006) /* Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */\r
-#define P8IV_8 (0x0008) /* Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */\r
-#define P8IV_10 (0x000a) /* Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */\r
-#define P8IV_12 (0x000c) /* Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */\r
-#define P8IV_14 (0x000e) /* Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */\r
-#define P8IV_16 (0x0010) /* Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */\r
-#define P8IV__NONE (0x0000) /* No interrupt pending */\r
-#define P8IV__P8IFG0 (0x0002) /* Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */\r
-#define P8IV__P8IFG1 (0x0004) /* Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */\r
-#define P8IV__P8IFG2 (0x0006) /* Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */\r
-#define P8IV__P8IFG3 (0x0008) /* Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */\r
-#define P8IV__P8IFG4 (0x000a) /* Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */\r
-#define P8IV__P8IFG5 (0x000c) /* Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */\r
-#define P8IV__P8IFG6 (0x000e) /* Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */\r
-#define P8IV__P8IFG7 (0x0010) /* Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */\r
-/* PEIN[P9IN] Bits */\r
-#define P9IN_OFS ( 0) /* P9IN Offset */\r
-#define P9IN_M (0x00ff) /* Port 9 Input */\r
-/* PEIN[P10IN] Bits */\r
-#define P10IN_OFS ( 8) /* P10IN Offset */\r
-#define P10IN_M (0xff00) /* Port 10 Input */\r
-/* PEOUT[P9OUT] Bits */\r
-#define P9OUT_OFS ( 0) /* P9OUT Offset */\r
-#define P9OUT_M (0x00ff) /* Port 9 Output */\r
-/* PEOUT[P10OUT] Bits */\r
-#define P10OUT_OFS ( 8) /* P10OUT Offset */\r
-#define P10OUT_M (0xff00) /* Port 10 Output */\r
-/* PEDIR[P9DIR] Bits */\r
-#define P9DIR_OFS ( 0) /* P9DIR Offset */\r
-#define P9DIR_M (0x00ff) /* Port 9 Direction */\r
-/* PEDIR[P10DIR] Bits */\r
-#define P10DIR_OFS ( 8) /* P10DIR Offset */\r
-#define P10DIR_M (0xff00) /* Port 10 Direction */\r
-/* PEREN[P9REN] Bits */\r
-#define P9REN_OFS ( 0) /* P9REN Offset */\r
-#define P9REN_M (0x00ff) /* Port 9 Resistor Enable */\r
-/* PEREN[P10REN] Bits */\r
-#define P10REN_OFS ( 8) /* P10REN Offset */\r
-#define P10REN_M (0xff00) /* Port 10 Resistor Enable */\r
-/* PEDS[P9DS] Bits */\r
-#define P9DS_OFS ( 0) /* P9DS Offset */\r
-#define P9DS_M (0x00ff) /* Port 9 Drive Strength */\r
-/* PEDS[P10DS] Bits */\r
-#define P10DS_OFS ( 8) /* P10DS Offset */\r
-#define P10DS_M (0xff00) /* Port 10 Drive Strength */\r
-/* PESEL0[P9SEL0] Bits */\r
-#define P9SEL0_OFS ( 0) /* P9SEL0 Offset */\r
-#define P9SEL0_M (0x00ff) /* Port 9 Select 0 */\r
-/* PESEL0[P10SEL0] Bits */\r
-#define P10SEL0_OFS ( 8) /* P10SEL0 Offset */\r
-#define P10SEL0_M (0xff00) /* Port 10 Select 0 */\r
-/* PESEL1[P9SEL1] Bits */\r
-#define P9SEL1_OFS ( 0) /* P9SEL1 Offset */\r
-#define P9SEL1_M (0x00ff) /* Port 9 Select 1 */\r
-/* PESEL1[P10SEL1] Bits */\r
-#define P10SEL1_OFS ( 8) /* P10SEL1 Offset */\r
-#define P10SEL1_M (0xff00) /* Port 10 Select 1 */\r
-/* P9IV[P9IV] Bits */\r
-#define P9IV_OFS ( 0) /* P9IV Offset */\r
-#define P9IV_M (0x001f) /* Port 9 interrupt vector value */\r
-#define P9IV0 (0x0001) /* Port 9 interrupt vector value */\r
-#define P9IV1 (0x0002) /* Port 9 interrupt vector value */\r
-#define P9IV2 (0x0004) /* Port 9 interrupt vector value */\r
-#define P9IV3 (0x0008) /* Port 9 interrupt vector value */\r
-#define P9IV4 (0x0010) /* Port 9 interrupt vector value */\r
-#define P9IV_0 (0x0000) /* No interrupt pending */\r
-#define P9IV_2 (0x0002) /* Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */\r
-#define P9IV_4 (0x0004) /* Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */\r
-#define P9IV_6 (0x0006) /* Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */\r
-#define P9IV_8 (0x0008) /* Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */\r
-#define P9IV_10 (0x000a) /* Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */\r
-#define P9IV_12 (0x000c) /* Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */\r
-#define P9IV_14 (0x000e) /* Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */\r
-#define P9IV_16 (0x0010) /* Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */\r
-#define P9IV__NONE (0x0000) /* No interrupt pending */\r
-#define P9IV__P9IFG0 (0x0002) /* Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */\r
-#define P9IV__P9IFG1 (0x0004) /* Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */\r
-#define P9IV__P9IFG2 (0x0006) /* Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */\r
-#define P9IV__P9IFG3 (0x0008) /* Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */\r
-#define P9IV__P9IFG4 (0x000a) /* Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */\r
-#define P9IV__P9IFG5 (0x000c) /* Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */\r
-#define P9IV__P9IFG6 (0x000e) /* Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */\r
-#define P9IV__P9IFG7 (0x0010) /* Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */\r
-/* PESELC[P9SELC] Bits */\r
-#define P9SELC_OFS ( 0) /* P9SELC Offset */\r
-#define P9SELC_M (0x00ff) /* Port 9 Complement Select */\r
-/* PESELC[P10SELC] Bits */\r
-#define P10SELC_OFS ( 8) /* P10SELC Offset */\r
-#define P10SELC_M (0xff00) /* Port 10 Complement Select */\r
-/* PEIES[P9IES] Bits */\r
-#define P9IES_OFS ( 0) /* P9IES Offset */\r
-#define P9IES_M (0x00ff) /* Port 9 Interrupt Edge Select */\r
-/* PEIES[P10IES] Bits */\r
-#define P10IES_OFS ( 8) /* P10IES Offset */\r
-#define P10IES_M (0xff00) /* Port 10 Interrupt Edge Select */\r
-/* PEIE[P9IE] Bits */\r
-#define P9IE_OFS ( 0) /* P9IE Offset */\r
-#define P9IE_M (0x00ff) /* Port 9 Interrupt Enable */\r
-/* PEIE[P10IE] Bits */\r
-#define P10IE_OFS ( 8) /* P10IE Offset */\r
-#define P10IE_M (0xff00) /* Port 10 Interrupt Enable */\r
-/* PEIFG[P9IFG] Bits */\r
-#define P9IFG_OFS ( 0) /* P9IFG Offset */\r
-#define P9IFG_M (0x00ff) /* Port 9 Interrupt Flag */\r
-/* PEIFG[P10IFG] Bits */\r
-#define P10IFG_OFS ( 8) /* P10IFG Offset */\r
-#define P10IFG_M (0xff00) /* Port 10 Interrupt Flag */\r
-/* P10IV[P10IV] Bits */\r
-#define P10IV_OFS ( 0) /* P10IV Offset */\r
-#define P10IV_M (0x001f) /* Port 10 interrupt vector value */\r
-#define P10IV0 (0x0001) /* Port 10 interrupt vector value */\r
-#define P10IV1 (0x0002) /* Port 10 interrupt vector value */\r
-#define P10IV2 (0x0004) /* Port 10 interrupt vector value */\r
-#define P10IV3 (0x0008) /* Port 10 interrupt vector value */\r
-#define P10IV4 (0x0010) /* Port 10 interrupt vector value */\r
-#define P10IV_0 (0x0000) /* No interrupt pending */\r
-#define P10IV_2 (0x0002) /* Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */\r
-#define P10IV_4 (0x0004) /* Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */\r
-#define P10IV_6 (0x0006) /* Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */\r
-#define P10IV_8 (0x0008) /* Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */\r
-#define P10IV_10 (0x000a) /* Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */\r
-#define P10IV_12 (0x000c) /* Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */\r
-#define P10IV_14 (0x000e) /* Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */\r
-#define P10IV_16 (0x0010) /* Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */\r
-#define P10IV__NONE (0x0000) /* No interrupt pending */\r
-#define P10IV__P10IFG0 (0x0002) /* Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */\r
-#define P10IV__P10IFG1 (0x0004) /* Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */\r
-#define P10IV__P10IFG2 (0x0006) /* Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */\r
-#define P10IV__P10IFG3 (0x0008) /* Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */\r
-#define P10IV__P10IFG4 (0x000a) /* Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */\r
-#define P10IV__P10IFG5 (0x000c) /* Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */\r
-#define P10IV__P10IFG6 (0x000e) /* Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */\r
-#define P10IV__P10IFG7 (0x0010) /* Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */\r
-\r
-\r
-//*****************************************************************************\r
-// DMA Bits\r
-//*****************************************************************************\r
-/* DMA_DEVICE_CFG[DMA_DEVICE_CFG_NUM_DMA_CHANNELS] Bits */\r
-#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /* NUM_DMA_CHANNELS Offset */\r
-#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_M (0x000000ff) /* Number of DMA channels available */\r
-/* DMA_DEVICE_CFG[DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL] Bits */\r
-#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /* NUM_SRC_PER_CHANNEL Offset */\r
-#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_M (0x0000ff00) /* Number of DMA sources per channel */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH0] Bits */\r
-#define DMA_SW_CHTRIG_CH0_OFS ( 0) /* CH0 Offset */\r
-#define DMA_SW_CHTRIG_CH0 (0x00000001) /* Write 1, triggers DMA_CHANNEL0 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH1] Bits */\r
-#define DMA_SW_CHTRIG_CH1_OFS ( 1) /* CH1 Offset */\r
-#define DMA_SW_CHTRIG_CH1 (0x00000002) /* Write 1, triggers DMA_CHANNEL1 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH2] Bits */\r
-#define DMA_SW_CHTRIG_CH2_OFS ( 2) /* CH2 Offset */\r
-#define DMA_SW_CHTRIG_CH2 (0x00000004) /* Write 1, triggers DMA_CHANNEL2 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH3] Bits */\r
-#define DMA_SW_CHTRIG_CH3_OFS ( 3) /* CH3 Offset */\r
-#define DMA_SW_CHTRIG_CH3 (0x00000008) /* Write 1, triggers DMA_CHANNEL3 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH4] Bits */\r
-#define DMA_SW_CHTRIG_CH4_OFS ( 4) /* CH4 Offset */\r
-#define DMA_SW_CHTRIG_CH4 (0x00000010) /* Write 1, triggers DMA_CHANNEL4 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH5] Bits */\r
-#define DMA_SW_CHTRIG_CH5_OFS ( 5) /* CH5 Offset */\r
-#define DMA_SW_CHTRIG_CH5 (0x00000020) /* Write 1, triggers DMA_CHANNEL5 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH6] Bits */\r
-#define DMA_SW_CHTRIG_CH6_OFS ( 6) /* CH6 Offset */\r
-#define DMA_SW_CHTRIG_CH6 (0x00000040) /* Write 1, triggers DMA_CHANNEL6 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH7] Bits */\r
-#define DMA_SW_CHTRIG_CH7_OFS ( 7) /* CH7 Offset */\r
-#define DMA_SW_CHTRIG_CH7 (0x00000080) /* Write 1, triggers DMA_CHANNEL7 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH8] Bits */\r
-#define DMA_SW_CHTRIG_CH8_OFS ( 8) /* CH8 Offset */\r
-#define DMA_SW_CHTRIG_CH8 (0x00000100) /* Write 1, triggers DMA_CHANNEL8 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH9] Bits */\r
-#define DMA_SW_CHTRIG_CH9_OFS ( 9) /* CH9 Offset */\r
-#define DMA_SW_CHTRIG_CH9 (0x00000200) /* Write 1, triggers DMA_CHANNEL9 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH10] Bits */\r
-#define DMA_SW_CHTRIG_CH10_OFS (10) /* CH10 Offset */\r
-#define DMA_SW_CHTRIG_CH10 (0x00000400) /* Write 1, triggers DMA_CHANNEL10 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH11] Bits */\r
-#define DMA_SW_CHTRIG_CH11_OFS (11) /* CH11 Offset */\r
-#define DMA_SW_CHTRIG_CH11 (0x00000800) /* Write 1, triggers DMA_CHANNEL11 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH12] Bits */\r
-#define DMA_SW_CHTRIG_CH12_OFS (12) /* CH12 Offset */\r
-#define DMA_SW_CHTRIG_CH12 (0x00001000) /* Write 1, triggers DMA_CHANNEL12 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH13] Bits */\r
-#define DMA_SW_CHTRIG_CH13_OFS (13) /* CH13 Offset */\r
-#define DMA_SW_CHTRIG_CH13 (0x00002000) /* Write 1, triggers DMA_CHANNEL13 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH14] Bits */\r
-#define DMA_SW_CHTRIG_CH14_OFS (14) /* CH14 Offset */\r
-#define DMA_SW_CHTRIG_CH14 (0x00004000) /* Write 1, triggers DMA_CHANNEL14 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH15] Bits */\r
-#define DMA_SW_CHTRIG_CH15_OFS (15) /* CH15 Offset */\r
-#define DMA_SW_CHTRIG_CH15 (0x00008000) /* Write 1, triggers DMA_CHANNEL15 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH16] Bits */\r
-#define DMA_SW_CHTRIG_CH16_OFS (16) /* CH16 Offset */\r
-#define DMA_SW_CHTRIG_CH16 (0x00010000) /* Write 1, triggers DMA_CHANNEL16 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH17] Bits */\r
-#define DMA_SW_CHTRIG_CH17_OFS (17) /* CH17 Offset */\r
-#define DMA_SW_CHTRIG_CH17 (0x00020000) /* Write 1, triggers DMA_CHANNEL17 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH18] Bits */\r
-#define DMA_SW_CHTRIG_CH18_OFS (18) /* CH18 Offset */\r
-#define DMA_SW_CHTRIG_CH18 (0x00040000) /* Write 1, triggers DMA_CHANNEL18 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH19] Bits */\r
-#define DMA_SW_CHTRIG_CH19_OFS (19) /* CH19 Offset */\r
-#define DMA_SW_CHTRIG_CH19 (0x00080000) /* Write 1, triggers DMA_CHANNEL19 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH20] Bits */\r
-#define DMA_SW_CHTRIG_CH20_OFS (20) /* CH20 Offset */\r
-#define DMA_SW_CHTRIG_CH20 (0x00100000) /* Write 1, triggers DMA_CHANNEL20 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH21] Bits */\r
-#define DMA_SW_CHTRIG_CH21_OFS (21) /* CH21 Offset */\r
-#define DMA_SW_CHTRIG_CH21 (0x00200000) /* Write 1, triggers DMA_CHANNEL21 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH22] Bits */\r
-#define DMA_SW_CHTRIG_CH22_OFS (22) /* CH22 Offset */\r
-#define DMA_SW_CHTRIG_CH22 (0x00400000) /* Write 1, triggers DMA_CHANNEL22 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH23] Bits */\r
-#define DMA_SW_CHTRIG_CH23_OFS (23) /* CH23 Offset */\r
-#define DMA_SW_CHTRIG_CH23 (0x00800000) /* Write 1, triggers DMA_CHANNEL23 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH24] Bits */\r
-#define DMA_SW_CHTRIG_CH24_OFS (24) /* CH24 Offset */\r
-#define DMA_SW_CHTRIG_CH24 (0x01000000) /* Write 1, triggers DMA_CHANNEL24 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH25] Bits */\r
-#define DMA_SW_CHTRIG_CH25_OFS (25) /* CH25 Offset */\r
-#define DMA_SW_CHTRIG_CH25 (0x02000000) /* Write 1, triggers DMA_CHANNEL25 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH26] Bits */\r
-#define DMA_SW_CHTRIG_CH26_OFS (26) /* CH26 Offset */\r
-#define DMA_SW_CHTRIG_CH26 (0x04000000) /* Write 1, triggers DMA_CHANNEL26 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH27] Bits */\r
-#define DMA_SW_CHTRIG_CH27_OFS (27) /* CH27 Offset */\r
-#define DMA_SW_CHTRIG_CH27 (0x08000000) /* Write 1, triggers DMA_CHANNEL27 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH28] Bits */\r
-#define DMA_SW_CHTRIG_CH28_OFS (28) /* CH28 Offset */\r
-#define DMA_SW_CHTRIG_CH28 (0x10000000) /* Write 1, triggers DMA_CHANNEL28 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH29] Bits */\r
-#define DMA_SW_CHTRIG_CH29_OFS (29) /* CH29 Offset */\r
-#define DMA_SW_CHTRIG_CH29 (0x20000000) /* Write 1, triggers DMA_CHANNEL29 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH30] Bits */\r
-#define DMA_SW_CHTRIG_CH30_OFS (30) /* CH30 Offset */\r
-#define DMA_SW_CHTRIG_CH30 (0x40000000) /* Write 1, triggers DMA_CHANNEL30 */\r
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH31] Bits */\r
-#define DMA_SW_CHTRIG_CH31_OFS (31) /* CH31 Offset */\r
-#define DMA_SW_CHTRIG_CH31 (0x80000000) /* Write 1, triggers DMA_CHANNEL31 */\r
-/* DMA_CH_SRCCFG[DMA_CHN_SRCCFG_DMA_SRC] Bits */\r
-#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /* DMA_SRC Offset */\r
-#define DMA_CHN_SRCCFG_DMA_SRC_M (0x000000ff) /* Device level DMA source mapping to channel input */\r
-/* DMA_INT1_SRCCFG[DMA_INT1_SRCCFG_INT_SRC] Bits */\r
-#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /* INT_SRC Offset */\r
-#define DMA_INT1_SRCCFG_INT_SRC_M (0x0000001f) /* Controls which channel's completion event is mapped as a source of this Interrupt */\r
-/* DMA_INT1_SRCCFG[DMA_INT1_SRCCFG_EN] Bits */\r
-#define DMA_INT1_SRCCFG_EN_OFS ( 5) /* EN Offset */\r
-#define DMA_INT1_SRCCFG_EN (0x00000020) /* Enables DMA_INT1 mapping */\r
-/* DMA_INT2_SRCCFG[DMA_INT2_SRCCFG_INT_SRC] Bits */\r
-#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /* INT_SRC Offset */\r
-#define DMA_INT2_SRCCFG_INT_SRC_M (0x0000001f) /* Controls which channel's completion event is mapped as a source of this Interrupt */\r
-/* DMA_INT2_SRCCFG[DMA_INT2_SRCCFG_EN] Bits */\r
-#define DMA_INT2_SRCCFG_EN_OFS ( 5) /* EN Offset */\r
-#define DMA_INT2_SRCCFG_EN (0x00000020) /* Enables DMA_INT2 mapping */\r
-/* DMA_INT3_SRCCFG[DMA_INT3_SRCCFG_INT_SRC] Bits */\r
-#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /* INT_SRC Offset */\r
-#define DMA_INT3_SRCCFG_INT_SRC_M (0x0000001f) /* Controls which channel's completion event is mapped as a source of this Interrupt */\r
-/* DMA_INT3_SRCCFG[DMA_INT3_SRCCFG_EN] Bits */\r
-#define DMA_INT3_SRCCFG_EN_OFS ( 5) /* EN Offset */\r
-#define DMA_INT3_SRCCFG_EN (0x00000020) /* Enables DMA_INT3 mapping */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH0] Bits */\r
-#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /* CH0 Offset */\r
-#define DMA_INT0_SRCFLG_CH0 (0x00000001) /* Channel 0 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH1] Bits */\r
-#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /* CH1 Offset */\r
-#define DMA_INT0_SRCFLG_CH1 (0x00000002) /* Channel 1 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH2] Bits */\r
-#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /* CH2 Offset */\r
-#define DMA_INT0_SRCFLG_CH2 (0x00000004) /* Channel 2 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH3] Bits */\r
-#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /* CH3 Offset */\r
-#define DMA_INT0_SRCFLG_CH3 (0x00000008) /* Channel 3 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH4] Bits */\r
-#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /* CH4 Offset */\r
-#define DMA_INT0_SRCFLG_CH4 (0x00000010) /* Channel 4 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH5] Bits */\r
-#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /* CH5 Offset */\r
-#define DMA_INT0_SRCFLG_CH5 (0x00000020) /* Channel 5 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH6] Bits */\r
-#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /* CH6 Offset */\r
-#define DMA_INT0_SRCFLG_CH6 (0x00000040) /* Channel 6 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH7] Bits */\r
-#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /* CH7 Offset */\r
-#define DMA_INT0_SRCFLG_CH7 (0x00000080) /* Channel 7 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH8] Bits */\r
-#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /* CH8 Offset */\r
-#define DMA_INT0_SRCFLG_CH8 (0x00000100) /* Channel 8 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH9] Bits */\r
-#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /* CH9 Offset */\r
-#define DMA_INT0_SRCFLG_CH9 (0x00000200) /* Channel 9 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH10] Bits */\r
-#define DMA_INT0_SRCFLG_CH10_OFS (10) /* CH10 Offset */\r
-#define DMA_INT0_SRCFLG_CH10 (0x00000400) /* Channel 10 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH11] Bits */\r
-#define DMA_INT0_SRCFLG_CH11_OFS (11) /* CH11 Offset */\r
-#define DMA_INT0_SRCFLG_CH11 (0x00000800) /* Channel 11 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH12] Bits */\r
-#define DMA_INT0_SRCFLG_CH12_OFS (12) /* CH12 Offset */\r
-#define DMA_INT0_SRCFLG_CH12 (0x00001000) /* Channel 12 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH13] Bits */\r
-#define DMA_INT0_SRCFLG_CH13_OFS (13) /* CH13 Offset */\r
-#define DMA_INT0_SRCFLG_CH13 (0x00002000) /* Channel 13 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH14] Bits */\r
-#define DMA_INT0_SRCFLG_CH14_OFS (14) /* CH14 Offset */\r
-#define DMA_INT0_SRCFLG_CH14 (0x00004000) /* Channel 14 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH15] Bits */\r
-#define DMA_INT0_SRCFLG_CH15_OFS (15) /* CH15 Offset */\r
-#define DMA_INT0_SRCFLG_CH15 (0x00008000) /* Channel 15 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH16] Bits */\r
-#define DMA_INT0_SRCFLG_CH16_OFS (16) /* CH16 Offset */\r
-#define DMA_INT0_SRCFLG_CH16 (0x00010000) /* Channel 16 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH17] Bits */\r
-#define DMA_INT0_SRCFLG_CH17_OFS (17) /* CH17 Offset */\r
-#define DMA_INT0_SRCFLG_CH17 (0x00020000) /* Channel 17 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH18] Bits */\r
-#define DMA_INT0_SRCFLG_CH18_OFS (18) /* CH18 Offset */\r
-#define DMA_INT0_SRCFLG_CH18 (0x00040000) /* Channel 18 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH19] Bits */\r
-#define DMA_INT0_SRCFLG_CH19_OFS (19) /* CH19 Offset */\r
-#define DMA_INT0_SRCFLG_CH19 (0x00080000) /* Channel 19 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH20] Bits */\r
-#define DMA_INT0_SRCFLG_CH20_OFS (20) /* CH20 Offset */\r
-#define DMA_INT0_SRCFLG_CH20 (0x00100000) /* Channel 20 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH21] Bits */\r
-#define DMA_INT0_SRCFLG_CH21_OFS (21) /* CH21 Offset */\r
-#define DMA_INT0_SRCFLG_CH21 (0x00200000) /* Channel 21 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH22] Bits */\r
-#define DMA_INT0_SRCFLG_CH22_OFS (22) /* CH22 Offset */\r
-#define DMA_INT0_SRCFLG_CH22 (0x00400000) /* Channel 22 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH23] Bits */\r
-#define DMA_INT0_SRCFLG_CH23_OFS (23) /* CH23 Offset */\r
-#define DMA_INT0_SRCFLG_CH23 (0x00800000) /* Channel 23 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH24] Bits */\r
-#define DMA_INT0_SRCFLG_CH24_OFS (24) /* CH24 Offset */\r
-#define DMA_INT0_SRCFLG_CH24 (0x01000000) /* Channel 24 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH25] Bits */\r
-#define DMA_INT0_SRCFLG_CH25_OFS (25) /* CH25 Offset */\r
-#define DMA_INT0_SRCFLG_CH25 (0x02000000) /* Channel 25 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH26] Bits */\r
-#define DMA_INT0_SRCFLG_CH26_OFS (26) /* CH26 Offset */\r
-#define DMA_INT0_SRCFLG_CH26 (0x04000000) /* Channel 26 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH27] Bits */\r
-#define DMA_INT0_SRCFLG_CH27_OFS (27) /* CH27 Offset */\r
-#define DMA_INT0_SRCFLG_CH27 (0x08000000) /* Channel 27 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH28] Bits */\r
-#define DMA_INT0_SRCFLG_CH28_OFS (28) /* CH28 Offset */\r
-#define DMA_INT0_SRCFLG_CH28 (0x10000000) /* Channel 28 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH29] Bits */\r
-#define DMA_INT0_SRCFLG_CH29_OFS (29) /* CH29 Offset */\r
-#define DMA_INT0_SRCFLG_CH29 (0x20000000) /* Channel 29 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH30] Bits */\r
-#define DMA_INT0_SRCFLG_CH30_OFS (30) /* CH30 Offset */\r
-#define DMA_INT0_SRCFLG_CH30 (0x40000000) /* Channel 30 was the source of DMA_INT0 */\r
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH31] Bits */\r
-#define DMA_INT0_SRCFLG_CH31_OFS (31) /* CH31 Offset */\r
-#define DMA_INT0_SRCFLG_CH31 (0x80000000) /* Channel 31 was the source of DMA_INT0 */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH0] Bits */\r
-#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /* CH0 Offset */\r
-#define DMA_INT0_CLRFLG_CH0 (0x00000001) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH1] Bits */\r
-#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /* CH1 Offset */\r
-#define DMA_INT0_CLRFLG_CH1 (0x00000002) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH2] Bits */\r
-#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /* CH2 Offset */\r
-#define DMA_INT0_CLRFLG_CH2 (0x00000004) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH3] Bits */\r
-#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /* CH3 Offset */\r
-#define DMA_INT0_CLRFLG_CH3 (0x00000008) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH4] Bits */\r
-#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /* CH4 Offset */\r
-#define DMA_INT0_CLRFLG_CH4 (0x00000010) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH5] Bits */\r
-#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /* CH5 Offset */\r
-#define DMA_INT0_CLRFLG_CH5 (0x00000020) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH6] Bits */\r
-#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /* CH6 Offset */\r
-#define DMA_INT0_CLRFLG_CH6 (0x00000040) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH7] Bits */\r
-#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /* CH7 Offset */\r
-#define DMA_INT0_CLRFLG_CH7 (0x00000080) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH8] Bits */\r
-#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /* CH8 Offset */\r
-#define DMA_INT0_CLRFLG_CH8 (0x00000100) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH9] Bits */\r
-#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /* CH9 Offset */\r
-#define DMA_INT0_CLRFLG_CH9 (0x00000200) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH10] Bits */\r
-#define DMA_INT0_CLRFLG_CH10_OFS (10) /* CH10 Offset */\r
-#define DMA_INT0_CLRFLG_CH10 (0x00000400) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH11] Bits */\r
-#define DMA_INT0_CLRFLG_CH11_OFS (11) /* CH11 Offset */\r
-#define DMA_INT0_CLRFLG_CH11 (0x00000800) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH12] Bits */\r
-#define DMA_INT0_CLRFLG_CH12_OFS (12) /* CH12 Offset */\r
-#define DMA_INT0_CLRFLG_CH12 (0x00001000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH13] Bits */\r
-#define DMA_INT0_CLRFLG_CH13_OFS (13) /* CH13 Offset */\r
-#define DMA_INT0_CLRFLG_CH13 (0x00002000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH14] Bits */\r
-#define DMA_INT0_CLRFLG_CH14_OFS (14) /* CH14 Offset */\r
-#define DMA_INT0_CLRFLG_CH14 (0x00004000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH15] Bits */\r
-#define DMA_INT0_CLRFLG_CH15_OFS (15) /* CH15 Offset */\r
-#define DMA_INT0_CLRFLG_CH15 (0x00008000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH16] Bits */\r
-#define DMA_INT0_CLRFLG_CH16_OFS (16) /* CH16 Offset */\r
-#define DMA_INT0_CLRFLG_CH16 (0x00010000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH17] Bits */\r
-#define DMA_INT0_CLRFLG_CH17_OFS (17) /* CH17 Offset */\r
-#define DMA_INT0_CLRFLG_CH17 (0x00020000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH18] Bits */\r
-#define DMA_INT0_CLRFLG_CH18_OFS (18) /* CH18 Offset */\r
-#define DMA_INT0_CLRFLG_CH18 (0x00040000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH19] Bits */\r
-#define DMA_INT0_CLRFLG_CH19_OFS (19) /* CH19 Offset */\r
-#define DMA_INT0_CLRFLG_CH19 (0x00080000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH20] Bits */\r
-#define DMA_INT0_CLRFLG_CH20_OFS (20) /* CH20 Offset */\r
-#define DMA_INT0_CLRFLG_CH20 (0x00100000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH21] Bits */\r
-#define DMA_INT0_CLRFLG_CH21_OFS (21) /* CH21 Offset */\r
-#define DMA_INT0_CLRFLG_CH21 (0x00200000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH22] Bits */\r
-#define DMA_INT0_CLRFLG_CH22_OFS (22) /* CH22 Offset */\r
-#define DMA_INT0_CLRFLG_CH22 (0x00400000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH23] Bits */\r
-#define DMA_INT0_CLRFLG_CH23_OFS (23) /* CH23 Offset */\r
-#define DMA_INT0_CLRFLG_CH23 (0x00800000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH24] Bits */\r
-#define DMA_INT0_CLRFLG_CH24_OFS (24) /* CH24 Offset */\r
-#define DMA_INT0_CLRFLG_CH24 (0x01000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH25] Bits */\r
-#define DMA_INT0_CLRFLG_CH25_OFS (25) /* CH25 Offset */\r
-#define DMA_INT0_CLRFLG_CH25 (0x02000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH26] Bits */\r
-#define DMA_INT0_CLRFLG_CH26_OFS (26) /* CH26 Offset */\r
-#define DMA_INT0_CLRFLG_CH26 (0x04000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH27] Bits */\r
-#define DMA_INT0_CLRFLG_CH27_OFS (27) /* CH27 Offset */\r
-#define DMA_INT0_CLRFLG_CH27 (0x08000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH28] Bits */\r
-#define DMA_INT0_CLRFLG_CH28_OFS (28) /* CH28 Offset */\r
-#define DMA_INT0_CLRFLG_CH28 (0x10000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH29] Bits */\r
-#define DMA_INT0_CLRFLG_CH29_OFS (29) /* CH29 Offset */\r
-#define DMA_INT0_CLRFLG_CH29 (0x20000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH30] Bits */\r
-#define DMA_INT0_CLRFLG_CH30_OFS (30) /* CH30 Offset */\r
-#define DMA_INT0_CLRFLG_CH30 (0x40000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH31] Bits */\r
-#define DMA_INT0_CLRFLG_CH31_OFS (31) /* CH31 Offset */\r
-#define DMA_INT0_CLRFLG_CH31 (0x80000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */\r
-/* DMA_STAT[DMA_STAT_MASTEN] Bits */\r
-#define DMA_STAT_MASTEN_OFS ( 0) /* MASTEN Offset */\r
-#define DMA_STAT_MASTEN (0x00000001) /* */\r
-/* DMA_STAT[DMA_STAT_] Bits */\r
-#define DMA_STAT__OFS ( 4) /* STATE Offset */\r
-#define DMA_STAT__M (0x000000f0) /* */\r
-#define DMA_STAT_0 (0x00000010) /* */\r
-#define DMA_STAT_1 (0x00000020) /* */\r
-#define DMA_STAT_2 (0x00000040) /* */\r
-#define DMA_STAT_3 (0x00000080) /* */\r
-#define DMA_STAT__0 (0x00000000) /* idle */\r
-#define DMA_STAT__1 (0x00000010) /* reading channel controller data */\r
-#define DMA_STAT__2 (0x00000020) /* reading source data end pointer */\r
-#define DMA_STAT__3 (0x00000030) /* reading destination data end pointer */\r
-#define DMA_STAT__4 (0x00000040) /* reading source data */\r
-#define DMA_STAT__5 (0x00000050) /* writing destination data */\r
-#define DMA_STAT__6 (0x00000060) /* waiting for DMA request to clear */\r
-#define DMA_STAT__7 (0x00000070) /* writing channel controller data */\r
-#define DMA_STAT__8 (0x00000080) /* stalled */\r
-#define DMA_STAT__9 (0x00000090) /* done */\r
-#define DMA_STAT__10 (0x000000a0) /* peripheral scatter-gather transition */\r
-#define DMA_STAT__11 (0x000000b0) /* Reserved */\r
-#define DMA_STAT__12 (0x000000c0) /* Reserved */\r
-#define DMA_STAT__13 (0x000000d0) /* Reserved */\r
-#define DMA_STAT__14 (0x000000e0) /* Reserved */\r
-#define DMA_STAT__15 (0x000000f0) /* Reserved */\r
-/* DMA_STAT[DMA_STAT_] Bits */\r
-//#define DMA_STAT__OFS (16) /* DMACHANS Offset */\r
-//#define DMA_STAT__M (0x001f0000) /* */\r
-//#define DMA_STAT_0 (0x00010000) /* */\r
-//#define DMA_STAT_1 (0x00020000) /* */\r
-//#define DMA_STAT_2 (0x00040000) /* */\r
-//#define DMA_STAT_3 (0x00080000) /* */\r
-#define DMA_STAT_4 (0x00100000) /* */\r
-//#define DMA_STAT__0 (0x00000000) /* Controller configured to use 1 DMA channel */\r
-//#define DMA_STAT__1 (0x00010000) /* Controller configured to use 2 DMA channels */\r
-#define DMA_STAT__30 (0x001e0000) /* Controller configured to use 31 DMA channels */\r
-#define DMA_STAT__31 (0x001f0000) /* Controller configured to use 32 DMA channels */\r
-/* DMA_STAT[DMA_STAT_] Bits */\r
-//#define DMA_STAT__OFS (28) /* TESTSTAT Offset */\r
-//#define DMA_STAT__M (0xf0000000) /* */\r
-//#define DMA_STAT_0 (0x10000000) /* */\r
-//#define DMA_STAT_1 (0x20000000) /* */\r
-//#define DMA_STAT_2 (0x40000000) /* */\r
-//#define DMA_STAT_3 (0x80000000) /* */\r
-//#define DMA_STAT__0 (0x00000000) /* Controller does not include the integration test logic */\r
-//#define DMA_STAT__1 (0x10000000) /* Controller includes the integration test logic */\r
-/* DMA_CFG[DMA_CFG_] Bits */\r
-#define DMA_CFG__OFS ( 0) /* MASTEN Offset */\r
-#define DMA_CFG_ (0x00000001) /* */\r
-/* DMA_CFG[DMA_CFG_] Bits */\r
-//#define DMA_CFG__OFS ( 5) /* CHPROTCTRL Offset */\r
-#define DMA_CFG__M (0x000000e0) /* */\r
-/* DMA_CTLBASE[DMA_CTLBASE_] Bits */\r
-#define DMA_CTLBASE__OFS ( 5) /* ADDR Offset */\r
-#define DMA_CTLBASE__M (0xffffffe0) /* */\r
-/* DMA_ERRCLR[DMA_ERRCLR_] Bits */\r
-#define DMA_ERRCLR__OFS ( 0) /* ERRCLR Offset */\r
-#define DMA_ERRCLR_ (0x00000001) /* */\r
+#define CS_KEY_VAL ((uint32_t)0x0000695A) /* CS control key value */\r
+\r
+/******************************************************************************\r
+* DIO Bits\r
+******************************************************************************/\r
+/* DIO_IV[IV] Bits */\r
+#define DIO_PORT_IV_OFS ( 0) /**< DIO Port IV Bit Offset */\r
+#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /**< DIO Port IV Bit Mask */\r
+#define DIO_PORT_IV0 ((uint16_t)0x0001) /**< DIO Port IV Bit 0 */\r
+#define DIO_PORT_IV1 ((uint16_t)0x0002) /**< DIO Port IV Bit 1 */\r
+#define DIO_PORT_IV2 ((uint16_t)0x0004) /**< DIO Port IV Bit 2 */\r
+#define DIO_PORT_IV3 ((uint16_t)0x0008) /**< DIO Port IV Bit 3 */\r
+#define DIO_PORT_IV4 ((uint16_t)0x0010) /**< DIO Port IV Bit 4 */\r
+#define DIO_PORT_IV_0 ((uint16_t)0x0000) /**< No interrupt pending */\r
+#define DIO_PORT_IV_2 ((uint16_t)0x0002) /**< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */\r
+ /* Priority: Highest */\r
+#define DIO_PORT_IV_4 ((uint16_t)0x0004) /**< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */\r
+#define DIO_PORT_IV_6 ((uint16_t)0x0006) /**< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */\r
+#define DIO_PORT_IV_8 ((uint16_t)0x0008) /**< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */\r
+#define DIO_PORT_IV_10 ((uint16_t)0x000A) /**< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */\r
+#define DIO_PORT_IV_12 ((uint16_t)0x000C) /**< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */\r
+#define DIO_PORT_IV_14 ((uint16_t)0x000E) /**< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */\r
+#define DIO_PORT_IV_16 ((uint16_t)0x0010) /**< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */\r
+ /* Priority: Lowest */\r
+#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /**< No interrupt pending */\r
+#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /**< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */\r
+ /* Priority: Highest */\r
+#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /**< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */\r
+#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /**< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */\r
+#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /**< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */\r
+#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /**< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */\r
+#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /**< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */\r
+#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /**< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */\r
+#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /**< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */\r
+ /* Priority: Lowest */\r
+\r
+\r
+/******************************************************************************\r
+* DMA Bits\r
+******************************************************************************/\r
+/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */\r
+#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /**< NUM_DMA_CHANNELS Bit Offset */\r
+#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /**< NUM_DMA_CHANNELS Bit Mask */\r
+/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */\r
+#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /**< NUM_SRC_PER_CHANNEL Bit Offset */\r
+#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /**< NUM_SRC_PER_CHANNEL Bit Mask */\r
+/* DMA_SW_CHTRIG[CH0] Bits */\r
+#define DMA_SW_CHTRIG_CH0_OFS ( 0) /**< CH0 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /**< Write 1, triggers DMA_CHANNEL0 */\r
+/* DMA_SW_CHTRIG[CH1] Bits */\r
+#define DMA_SW_CHTRIG_CH1_OFS ( 1) /**< CH1 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /**< Write 1, triggers DMA_CHANNEL1 */\r
+/* DMA_SW_CHTRIG[CH2] Bits */\r
+#define DMA_SW_CHTRIG_CH2_OFS ( 2) /**< CH2 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /**< Write 1, triggers DMA_CHANNEL2 */\r
+/* DMA_SW_CHTRIG[CH3] Bits */\r
+#define DMA_SW_CHTRIG_CH3_OFS ( 3) /**< CH3 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /**< Write 1, triggers DMA_CHANNEL3 */\r
+/* DMA_SW_CHTRIG[CH4] Bits */\r
+#define DMA_SW_CHTRIG_CH4_OFS ( 4) /**< CH4 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /**< Write 1, triggers DMA_CHANNEL4 */\r
+/* DMA_SW_CHTRIG[CH5] Bits */\r
+#define DMA_SW_CHTRIG_CH5_OFS ( 5) /**< CH5 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /**< Write 1, triggers DMA_CHANNEL5 */\r
+/* DMA_SW_CHTRIG[CH6] Bits */\r
+#define DMA_SW_CHTRIG_CH6_OFS ( 6) /**< CH6 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /**< Write 1, triggers DMA_CHANNEL6 */\r
+/* DMA_SW_CHTRIG[CH7] Bits */\r
+#define DMA_SW_CHTRIG_CH7_OFS ( 7) /**< CH7 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /**< Write 1, triggers DMA_CHANNEL7 */\r
+/* DMA_SW_CHTRIG[CH8] Bits */\r
+#define DMA_SW_CHTRIG_CH8_OFS ( 8) /**< CH8 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /**< Write 1, triggers DMA_CHANNEL8 */\r
+/* DMA_SW_CHTRIG[CH9] Bits */\r
+#define DMA_SW_CHTRIG_CH9_OFS ( 9) /**< CH9 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /**< Write 1, triggers DMA_CHANNEL9 */\r
+/* DMA_SW_CHTRIG[CH10] Bits */\r
+#define DMA_SW_CHTRIG_CH10_OFS (10) /**< CH10 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /**< Write 1, triggers DMA_CHANNEL10 */\r
+/* DMA_SW_CHTRIG[CH11] Bits */\r
+#define DMA_SW_CHTRIG_CH11_OFS (11) /**< CH11 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /**< Write 1, triggers DMA_CHANNEL11 */\r
+/* DMA_SW_CHTRIG[CH12] Bits */\r
+#define DMA_SW_CHTRIG_CH12_OFS (12) /**< CH12 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /**< Write 1, triggers DMA_CHANNEL12 */\r
+/* DMA_SW_CHTRIG[CH13] Bits */\r
+#define DMA_SW_CHTRIG_CH13_OFS (13) /**< CH13 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /**< Write 1, triggers DMA_CHANNEL13 */\r
+/* DMA_SW_CHTRIG[CH14] Bits */\r
+#define DMA_SW_CHTRIG_CH14_OFS (14) /**< CH14 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /**< Write 1, triggers DMA_CHANNEL14 */\r
+/* DMA_SW_CHTRIG[CH15] Bits */\r
+#define DMA_SW_CHTRIG_CH15_OFS (15) /**< CH15 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /**< Write 1, triggers DMA_CHANNEL15 */\r
+/* DMA_SW_CHTRIG[CH16] Bits */\r
+#define DMA_SW_CHTRIG_CH16_OFS (16) /**< CH16 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /**< Write 1, triggers DMA_CHANNEL16 */\r
+/* DMA_SW_CHTRIG[CH17] Bits */\r
+#define DMA_SW_CHTRIG_CH17_OFS (17) /**< CH17 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /**< Write 1, triggers DMA_CHANNEL17 */\r
+/* DMA_SW_CHTRIG[CH18] Bits */\r
+#define DMA_SW_CHTRIG_CH18_OFS (18) /**< CH18 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /**< Write 1, triggers DMA_CHANNEL18 */\r
+/* DMA_SW_CHTRIG[CH19] Bits */\r
+#define DMA_SW_CHTRIG_CH19_OFS (19) /**< CH19 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /**< Write 1, triggers DMA_CHANNEL19 */\r
+/* DMA_SW_CHTRIG[CH20] Bits */\r
+#define DMA_SW_CHTRIG_CH20_OFS (20) /**< CH20 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /**< Write 1, triggers DMA_CHANNEL20 */\r
+/* DMA_SW_CHTRIG[CH21] Bits */\r
+#define DMA_SW_CHTRIG_CH21_OFS (21) /**< CH21 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /**< Write 1, triggers DMA_CHANNEL21 */\r
+/* DMA_SW_CHTRIG[CH22] Bits */\r
+#define DMA_SW_CHTRIG_CH22_OFS (22) /**< CH22 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /**< Write 1, triggers DMA_CHANNEL22 */\r
+/* DMA_SW_CHTRIG[CH23] Bits */\r
+#define DMA_SW_CHTRIG_CH23_OFS (23) /**< CH23 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /**< Write 1, triggers DMA_CHANNEL23 */\r
+/* DMA_SW_CHTRIG[CH24] Bits */\r
+#define DMA_SW_CHTRIG_CH24_OFS (24) /**< CH24 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /**< Write 1, triggers DMA_CHANNEL24 */\r
+/* DMA_SW_CHTRIG[CH25] Bits */\r
+#define DMA_SW_CHTRIG_CH25_OFS (25) /**< CH25 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /**< Write 1, triggers DMA_CHANNEL25 */\r
+/* DMA_SW_CHTRIG[CH26] Bits */\r
+#define DMA_SW_CHTRIG_CH26_OFS (26) /**< CH26 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /**< Write 1, triggers DMA_CHANNEL26 */\r
+/* DMA_SW_CHTRIG[CH27] Bits */\r
+#define DMA_SW_CHTRIG_CH27_OFS (27) /**< CH27 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /**< Write 1, triggers DMA_CHANNEL27 */\r
+/* DMA_SW_CHTRIG[CH28] Bits */\r
+#define DMA_SW_CHTRIG_CH28_OFS (28) /**< CH28 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /**< Write 1, triggers DMA_CHANNEL28 */\r
+/* DMA_SW_CHTRIG[CH29] Bits */\r
+#define DMA_SW_CHTRIG_CH29_OFS (29) /**< CH29 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /**< Write 1, triggers DMA_CHANNEL29 */\r
+/* DMA_SW_CHTRIG[CH30] Bits */\r
+#define DMA_SW_CHTRIG_CH30_OFS (30) /**< CH30 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /**< Write 1, triggers DMA_CHANNEL30 */\r
+/* DMA_SW_CHTRIG[CH31] Bits */\r
+#define DMA_SW_CHTRIG_CH31_OFS (31) /**< CH31 Bit Offset */\r
+#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /**< Write 1, triggers DMA_CHANNEL31 */\r
+/* DMA_CHN_SRCCFG[DMA_SRC] Bits */\r
+#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /**< DMA_SRC Bit Offset */\r
+#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /**< DMA_SRC Bit Mask */\r
+/* DMA_INT1_SRCCFG[INT_SRC] Bits */\r
+#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /**< INT_SRC Bit Offset */\r
+#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /**< INT_SRC Bit Mask */\r
+/* DMA_INT1_SRCCFG[EN] Bits */\r
+#define DMA_INT1_SRCCFG_EN_OFS ( 5) /**< EN Bit Offset */\r
+#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /**< Enables DMA_INT1 mapping */\r
+/* DMA_INT2_SRCCFG[INT_SRC] Bits */\r
+#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /**< INT_SRC Bit Offset */\r
+#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /**< INT_SRC Bit Mask */\r
+/* DMA_INT2_SRCCFG[EN] Bits */\r
+#define DMA_INT2_SRCCFG_EN_OFS ( 5) /**< EN Bit Offset */\r
+#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /**< Enables DMA_INT2 mapping */\r
+/* DMA_INT3_SRCCFG[INT_SRC] Bits */\r
+#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /**< INT_SRC Bit Offset */\r
+#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /**< INT_SRC Bit Mask */\r
+/* DMA_INT3_SRCCFG[EN] Bits */\r
+#define DMA_INT3_SRCCFG_EN_OFS ( 5) /**< EN Bit Offset */\r
+#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /**< Enables DMA_INT3 mapping */\r
+/* DMA_INT0_SRCFLG[CH0] Bits */\r
+#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /**< CH0 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /**< Channel 0 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH1] Bits */\r
+#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /**< CH1 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /**< Channel 1 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH2] Bits */\r
+#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /**< CH2 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /**< Channel 2 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH3] Bits */\r
+#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /**< CH3 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /**< Channel 3 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH4] Bits */\r
+#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /**< CH4 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /**< Channel 4 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH5] Bits */\r
+#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /**< CH5 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /**< Channel 5 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH6] Bits */\r
+#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /**< CH6 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /**< Channel 6 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH7] Bits */\r
+#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /**< CH7 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /**< Channel 7 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH8] Bits */\r
+#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /**< CH8 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /**< Channel 8 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH9] Bits */\r
+#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /**< CH9 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /**< Channel 9 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH10] Bits */\r
+#define DMA_INT0_SRCFLG_CH10_OFS (10) /**< CH10 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /**< Channel 10 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH11] Bits */\r
+#define DMA_INT0_SRCFLG_CH11_OFS (11) /**< CH11 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /**< Channel 11 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH12] Bits */\r
+#define DMA_INT0_SRCFLG_CH12_OFS (12) /**< CH12 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /**< Channel 12 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH13] Bits */\r
+#define DMA_INT0_SRCFLG_CH13_OFS (13) /**< CH13 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /**< Channel 13 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH14] Bits */\r
+#define DMA_INT0_SRCFLG_CH14_OFS (14) /**< CH14 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /**< Channel 14 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH15] Bits */\r
+#define DMA_INT0_SRCFLG_CH15_OFS (15) /**< CH15 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /**< Channel 15 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH16] Bits */\r
+#define DMA_INT0_SRCFLG_CH16_OFS (16) /**< CH16 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /**< Channel 16 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH17] Bits */\r
+#define DMA_INT0_SRCFLG_CH17_OFS (17) /**< CH17 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /**< Channel 17 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH18] Bits */\r
+#define DMA_INT0_SRCFLG_CH18_OFS (18) /**< CH18 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /**< Channel 18 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH19] Bits */\r
+#define DMA_INT0_SRCFLG_CH19_OFS (19) /**< CH19 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /**< Channel 19 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH20] Bits */\r
+#define DMA_INT0_SRCFLG_CH20_OFS (20) /**< CH20 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /**< Channel 20 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH21] Bits */\r
+#define DMA_INT0_SRCFLG_CH21_OFS (21) /**< CH21 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /**< Channel 21 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH22] Bits */\r
+#define DMA_INT0_SRCFLG_CH22_OFS (22) /**< CH22 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /**< Channel 22 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH23] Bits */\r
+#define DMA_INT0_SRCFLG_CH23_OFS (23) /**< CH23 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /**< Channel 23 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH24] Bits */\r
+#define DMA_INT0_SRCFLG_CH24_OFS (24) /**< CH24 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /**< Channel 24 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH25] Bits */\r
+#define DMA_INT0_SRCFLG_CH25_OFS (25) /**< CH25 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /**< Channel 25 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH26] Bits */\r
+#define DMA_INT0_SRCFLG_CH26_OFS (26) /**< CH26 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /**< Channel 26 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH27] Bits */\r
+#define DMA_INT0_SRCFLG_CH27_OFS (27) /**< CH27 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /**< Channel 27 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH28] Bits */\r
+#define DMA_INT0_SRCFLG_CH28_OFS (28) /**< CH28 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /**< Channel 28 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH29] Bits */\r
+#define DMA_INT0_SRCFLG_CH29_OFS (29) /**< CH29 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /**< Channel 29 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH30] Bits */\r
+#define DMA_INT0_SRCFLG_CH30_OFS (30) /**< CH30 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /**< Channel 30 was the source of DMA_INT0 */\r
+/* DMA_INT0_SRCFLG[CH31] Bits */\r
+#define DMA_INT0_SRCFLG_CH31_OFS (31) /**< CH31 Bit Offset */\r
+#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /**< Channel 31 was the source of DMA_INT0 */\r
+/* DMA_INT0_CLRFLG[CH0] Bits */\r
+#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /**< CH0 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH1] Bits */\r
+#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /**< CH1 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH2] Bits */\r
+#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /**< CH2 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH3] Bits */\r
+#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /**< CH3 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH4] Bits */\r
+#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /**< CH4 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH5] Bits */\r
+#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /**< CH5 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH6] Bits */\r
+#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /**< CH6 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH7] Bits */\r
+#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /**< CH7 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH8] Bits */\r
+#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /**< CH8 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH9] Bits */\r
+#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /**< CH9 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH10] Bits */\r
+#define DMA_INT0_CLRFLG_CH10_OFS (10) /**< CH10 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH11] Bits */\r
+#define DMA_INT0_CLRFLG_CH11_OFS (11) /**< CH11 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH12] Bits */\r
+#define DMA_INT0_CLRFLG_CH12_OFS (12) /**< CH12 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH13] Bits */\r
+#define DMA_INT0_CLRFLG_CH13_OFS (13) /**< CH13 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH14] Bits */\r
+#define DMA_INT0_CLRFLG_CH14_OFS (14) /**< CH14 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH15] Bits */\r
+#define DMA_INT0_CLRFLG_CH15_OFS (15) /**< CH15 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH16] Bits */\r
+#define DMA_INT0_CLRFLG_CH16_OFS (16) /**< CH16 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH17] Bits */\r
+#define DMA_INT0_CLRFLG_CH17_OFS (17) /**< CH17 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH18] Bits */\r
+#define DMA_INT0_CLRFLG_CH18_OFS (18) /**< CH18 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH19] Bits */\r
+#define DMA_INT0_CLRFLG_CH19_OFS (19) /**< CH19 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH20] Bits */\r
+#define DMA_INT0_CLRFLG_CH20_OFS (20) /**< CH20 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH21] Bits */\r
+#define DMA_INT0_CLRFLG_CH21_OFS (21) /**< CH21 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH22] Bits */\r
+#define DMA_INT0_CLRFLG_CH22_OFS (22) /**< CH22 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH23] Bits */\r
+#define DMA_INT0_CLRFLG_CH23_OFS (23) /**< CH23 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH24] Bits */\r
+#define DMA_INT0_CLRFLG_CH24_OFS (24) /**< CH24 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH25] Bits */\r
+#define DMA_INT0_CLRFLG_CH25_OFS (25) /**< CH25 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH26] Bits */\r
+#define DMA_INT0_CLRFLG_CH26_OFS (26) /**< CH26 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH27] Bits */\r
+#define DMA_INT0_CLRFLG_CH27_OFS (27) /**< CH27 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH28] Bits */\r
+#define DMA_INT0_CLRFLG_CH28_OFS (28) /**< CH28 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH29] Bits */\r
+#define DMA_INT0_CLRFLG_CH29_OFS (29) /**< CH29 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH30] Bits */\r
+#define DMA_INT0_CLRFLG_CH30_OFS (30) /**< CH30 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_INT0_CLRFLG[CH31] Bits */\r
+#define DMA_INT0_CLRFLG_CH31_OFS (31) /**< CH31 Bit Offset */\r
+#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */\r
+/* DMA_STAT[MASTEN] Bits */\r
+#define DMA_STAT_MASTEN_OFS ( 0) /**< MASTEN Bit Offset */\r
+#define DMA_STAT_MASTEN ((uint32_t)0x00000001)\r
+/* DMA_STAT[STATE] Bits */\r
+#define DMA_STAT_STATE_OFS ( 4) /**< STATE Bit Offset */\r
+#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /**< STATE Bit Mask */\r
+#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /**< STATE Bit 0 */\r
+#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /**< STATE Bit 1 */\r
+#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /**< STATE Bit 2 */\r
+#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /**< STATE Bit 3 */\r
+#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /**< idle */\r
+#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /**< reading channel controller data */\r
+#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /**< reading source data end pointer */\r
+#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /**< reading destination data end pointer */\r
+#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /**< reading source data */\r
+#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /**< writing destination data */\r
+#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /**< waiting for DMA request to clear */\r
+#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /**< writing channel controller data */\r
+#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /**< stalled */\r
+#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /**< done */\r
+#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /**< peripheral scatter-gather transition */\r
+#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /**< Reserved */\r
+#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /**< Reserved */\r
+#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /**< Reserved */\r
+#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /**< Reserved */\r
+#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /**< Reserved */\r
+/* DMA_STAT[DMACHANS] Bits */\r
+#define DMA_STAT_DMACHANS_OFS (16) /**< DMACHANS Bit Offset */\r
+#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /**< DMACHANS Bit Mask */\r
+#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /**< DMACHANS Bit 0 */\r
+#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /**< DMACHANS Bit 1 */\r
+#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /**< DMACHANS Bit 2 */\r
+#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /**< DMACHANS Bit 3 */\r
+#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /**< DMACHANS Bit 4 */\r
+#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /**< Controller configured to use 1 DMA channel */\r
+#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /**< Controller configured to use 2 DMA channels */\r
+#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /**< Controller configured to use 31 DMA channels */\r
+#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /**< Controller configured to use 32 DMA channels */\r
+/* DMA_STAT[TESTSTAT] Bits */\r
+#define DMA_STAT_TESTSTAT_OFS (28) /**< TESTSTAT Bit Offset */\r
+#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /**< TESTSTAT Bit Mask */\r
+#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /**< TESTSTAT Bit 0 */\r
+#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /**< TESTSTAT Bit 1 */\r
+#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /**< TESTSTAT Bit 2 */\r
+#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /**< TESTSTAT Bit 3 */\r
+#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /**< Controller does not include the integration test logic */\r
+#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /**< Controller includes the integration test logic */\r
+/* DMA_CFG[MASTEN] Bits */\r
+#define DMA_CFG_MASTEN_OFS ( 0) /**< MASTEN Bit Offset */\r
+#define DMA_CFG_MASTEN ((uint32_t)0x00000001)\r
+/* DMA_CFG[CHPROTCTRL] Bits */\r
+#define DMA_CFG_CHPROTCTRL_OFS ( 5) /**< CHPROTCTRL Bit Offset */\r
+#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /**< CHPROTCTRL Bit Mask */\r
+/* DMA_CTLBASE[ADDR] Bits */\r
+#define DMA_CTLBASE_ADDR_OFS ( 5) /**< ADDR Bit Offset */\r
+#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /**< ADDR Bit Mask */\r
+/* DMA_ERRCLR[ERRCLR] Bits */\r
+#define DMA_ERRCLR_ERRCLR_OFS ( 0) /**< ERRCLR Bit Offset */\r
+#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001)\r
\r
/* UDMA_STAT Control Bits */\r
-#define UDMA_STAT_DMACHANS_M 0x001F0000 /* Available uDMA Channels Minus 1 */\r
-#define UDMA_STAT_STATE_M 0x000000F0 /* Control State Machine Status */\r
-#define UDMA_STAT_STATE_IDLE 0x00000000 /* Idle */\r
-#define UDMA_STAT_STATE_RD_CTRL 0x00000010 /* Reading channel controller data */\r
-#define UDMA_STAT_STATE_RD_SRCENDP 0x00000020 /* Reading source end pointer */\r
-#define UDMA_STAT_STATE_RD_DSTENDP 0x00000030 /* Reading destination end pointer */\r
-#define UDMA_STAT_STATE_RD_SRCDAT 0x00000040 /* Reading source data */\r
-#define UDMA_STAT_STATE_WR_DSTDAT 0x00000050 /* Writing destination data */\r
-#define UDMA_STAT_STATE_WAIT 0x00000060 /* Waiting for uDMA request to */\r
- /* clear */\r
-#define UDMA_STAT_STATE_WR_CTRL 0x00000070 /* Writing channel controller data */\r
-#define UDMA_STAT_STATE_STALL 0x00000080 /* Stalled */\r
-#define UDMA_STAT_STATE_DONE 0x00000090 /* Done */\r
-#define UDMA_STAT_STATE_UNDEF 0x000000A0 /* Undefined */\r
-#define UDMA_STAT_MASTEN 0x00000001 /* Master Enable Status */\r
-#define UDMA_STAT_DMACHANS_S 16\r
+#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /* Available uDMA Channels Minus 1 */\r
+#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /* Control State Machine Status */\r
+#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /* Idle */\r
+#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /* Reading channel controller data */\r
+#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /* Reading source end pointer */\r
+#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /* Reading destination end pointer */\r
+#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /* Reading source data */\r
+#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /* Writing destination data */\r
+#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /* Waiting for uDMA request to clear */\r
+#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /* Writing channel controller data */\r
+#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /* Stalled */\r
+#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /* Done */\r
+#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /* Undefined */\r
+#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /* Master Enable Status */\r
+#define UDMA_STAT_DMACHANS_S (16)\r
\r
/* UDMA_CFG Control Bits */\r
-#define UDMA_CFG_MASTEN 0x00000001 /* Controller Master Enable */\r
+#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /* Controller Master Enable */\r
\r
/* UDMA_CTLBASE Control Bits */\r
-#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 /* Channel Control Base Address */\r
-#define UDMA_CTLBASE_ADDR_S 10\r
+#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /* Channel Control Base Address */\r
+#define UDMA_CTLBASE_ADDR_S (10)\r
\r
/* UDMA_ALTBASE Control Bits */\r
-#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF /* Alternate Channel Address Pointer */\r
-#define UDMA_ALTBASE_ADDR_S 0\r
+#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /* Alternate Channel Address Pointer */\r
+#define UDMA_ALTBASE_ADDR_S ( 0)\r
\r
/* UDMA_WAITSTAT Control Bits */\r
-#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF /* Channel [n] Wait Status */\r
+#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Wait Status */\r
\r
/* UDMA_SWREQ Control Bits */\r
-#define UDMA_SWREQ_M 0xFFFFFFFF /* Channel [n] Software Request */\r
+#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Software Request */\r
\r
/* UDMA_USEBURSTSET Control Bits */\r
-#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF /* Channel [n] Useburst Set */\r
+#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Useburst Set */\r
\r
/* UDMA_USEBURSTCLR Control Bits */\r
-#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF /* Channel [n] Useburst Clear */\r
+#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Useburst Clear */\r
\r
/* UDMA_REQMASKSET Control Bits */\r
-#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF /* Channel [n] Request Mask Set */\r
+#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Request Mask Set */\r
\r
/* UDMA_REQMASKCLR Control Bits */\r
-#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF /* Channel [n] Request Mask Clear */\r
+#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Request Mask Clear */\r
\r
/* UDMA_ENASET Control Bits */\r
-#define UDMA_ENASET_SET_M 0xFFFFFFFF /* Channel [n] Enable Set */\r
+#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Enable Set */\r
\r
/* UDMA_ENACLR Control Bits */\r
-#define UDMA_ENACLR_CLR_M 0xFFFFFFFF /* Clear Channel [n] Enable Clear */\r
+#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Clear Channel [n] Enable Clear */\r
\r
/* UDMA_ALTSET Control Bits */\r
-#define UDMA_ALTSET_SET_M 0xFFFFFFFF /* Channel [n] Alternate Set */\r
+#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Alternate Set */\r
\r
/* UDMA_ALTCLR Control Bits */\r
-#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF /* Channel [n] Alternate Clear */\r
+#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Alternate Clear */\r
\r
/* UDMA_PRIOSET Control Bits */\r
-#define UDMA_PRIOSET_SET_M 0xFFFFFFFF /* Channel [n] Priority Set */\r
+#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Priority Set */\r
\r
/* UDMA_PRIOCLR Control Bits */\r
-#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF /* Channel [n] Priority Clear */\r
+#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Priority Clear */\r
\r
/* UDMA_ERRCLR Control Bits */\r
-#define UDMA_ERRCLR_ERRCLR 0x00000001 /* uDMA Bus Error Status */\r
+#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /* uDMA Bus Error Status */\r
\r
/* UDMA_CHASGN Control Bits */\r
-#define UDMA_CHASGN_M 0xFFFFFFFF /* Channel [n] Assignment Select */\r
-#define UDMA_CHASGN_PRIMARY 0x00000000 /* Use the primary channel */\r
- /* assignment */\r
-#define UDMA_CHASGN_SECONDARY 0x00000001 /* Use the secondary channel */\r
- /* assignment */\r
+#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Assignment Select */\r
+#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /* Use the primary channel assignment */\r
+#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /* Use the secondary channel assignment */\r
\r
/* Micro Direct Memory Access (uDMA) offsets */\r
-#define UDMA_O_SRCENDP 0x00000000 /* DMA Channel Source Address End */\r
- /* Pointer */\r
-#define UDMA_O_DSTENDP 0x00000004 /* DMA Channel Destination Address */\r
- /* End Pointer */\r
-#define UDMA_O_CHCTL 0x00000008 /* DMA Channel Control Word */\r
+#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /* DMA Channel Source Address End Pointer */\r
+#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /* DMA Channel Destination Address End Pointer */\r
+#define UDMA_O_CHCTL ((uint32_t)0x00000008) /* DMA Channel Control Word */\r
\r
/* UDMA_O_SRCENDP Control Bits */\r
-#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF /* Source Address End Pointer */\r
-#define UDMA_SRCENDP_ADDR_S 0\r
+#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /* Source Address End Pointer */\r
+#define UDMA_SRCENDP_ADDR_S ( 0)\r
\r
/* UDMA_O_DSTENDP Control Bits */\r
-#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF /* Destination Address End Pointer */\r
-#define UDMA_DSTENDP_ADDR_S 0\r
+#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /* Destination Address End Pointer */\r
+#define UDMA_DSTENDP_ADDR_S ( 0)\r
\r
/* UDMA_O_CHCTL Control Bits */\r
-#define UDMA_CHCTL_DSTINC_M 0xC0000000 /* Destination Address Increment */\r
-#define UDMA_CHCTL_DSTINC_8 0x00000000 /* Byte */\r
-#define UDMA_CHCTL_DSTINC_16 0x40000000 /* Half-word */\r
-#define UDMA_CHCTL_DSTINC_32 0x80000000 /* Word */\r
-#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 /* No increment */\r
-#define UDMA_CHCTL_DSTSIZE_M 0x30000000 /* Destination Data Size */\r
-#define UDMA_CHCTL_DSTSIZE_8 0x00000000 /* Byte */\r
-#define UDMA_CHCTL_DSTSIZE_16 0x10000000 /* Half-word */\r
-#define UDMA_CHCTL_DSTSIZE_32 0x20000000 /* Word */\r
-#define UDMA_CHCTL_SRCINC_M 0x0C000000 /* Source Address Increment */\r
-#define UDMA_CHCTL_SRCINC_8 0x00000000 /* Byte */\r
-#define UDMA_CHCTL_SRCINC_16 0x04000000 /* Half-word */\r
-#define UDMA_CHCTL_SRCINC_32 0x08000000 /* Word */\r
-#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 /* No increment */\r
-#define UDMA_CHCTL_SRCSIZE_M 0x03000000 /* Source Data Size */\r
-#define UDMA_CHCTL_SRCSIZE_8 0x00000000 /* Byte */\r
-#define UDMA_CHCTL_SRCSIZE_16 0x01000000 /* Half-word */\r
-#define UDMA_CHCTL_SRCSIZE_32 0x02000000 /* Word */\r
-#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 /* Arbitration Size */\r
-#define UDMA_CHCTL_ARBSIZE_1 0x00000000 /* 1 Transfer */\r
-#define UDMA_CHCTL_ARBSIZE_2 0x00004000 /* 2 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_4 0x00008000 /* 4 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 /* 8 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_16 0x00010000 /* 16 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_32 0x00014000 /* 32 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_64 0x00018000 /* 64 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 /* 128 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_256 0x00020000 /* 256 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_512 0x00024000 /* 512 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 /* 1024 Transfers */\r
-#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 /* Transfer Size (minus 1) */\r
-#define UDMA_CHCTL_NXTUSEBURST 0x00000008 /* Next Useburst */\r
-#define UDMA_CHCTL_XFERMODE_M 0x00000007 /* uDMA Transfer Mode */\r
-#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 /* Stop */\r
-#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 /* Basic */\r
-#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 /* Auto-Request */\r
-#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 /* Ping-Pong */\r
-#define UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 /* Memory Scatter-Gather */\r
-#define UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 /* Alternate Memory Scatter-Gather */\r
-#define UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 /* Peripheral Scatter-Gather */\r
-#define UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 /* Alternate Peripheral */\r
- /* Scatter-Gather */\r
-#define UDMA_CHCTL_XFERSIZE_S 4\r
-\r
-\r
-//*****************************************************************************\r
-// DWT Bits\r
-//*****************************************************************************\r
-/* DWT_CTRL[DWT_CTRL_CYCCNTENA] Bits */\r
-#define DWT_CTRL_CYCCNTENA_OFS ( 0) /* CYCCNTENA Offset */\r
-#define DWT_CTRL_CYCCNTENA (0x00000001) /* */\r
-/* DWT_CTRL[DWT_CTRL_POSTPRESET] Bits */\r
-#define DWT_CTRL_POSTPRESET_OFS ( 1) /* POSTPRESET Offset */\r
-#define DWT_CTRL_POSTPRESET_M (0x0000001e) /* */\r
-/* DWT_CTRL[DWT_CTRL_POSTCNT] Bits */\r
-#define DWT_CTRL_POSTCNT_OFS ( 5) /* POSTCNT Offset */\r
-#define DWT_CTRL_POSTCNT_M (0x000001e0) /* */\r
-/* DWT_CTRL[DWT_CTRL_CYCTAP] Bits */\r
-#define DWT_CTRL_CYCTAP_OFS ( 9) /* CYCTAP Offset */\r
-#define DWT_CTRL_CYCTAP (0x00000200) /* */\r
-/* DWT_CTRL[DWT_CTRL_SYNCTAP] Bits */\r
-#define DWT_CTRL_SYNCTAP_OFS (10) /* SYNCTAP Offset */\r
-#define DWT_CTRL_SYNCTAP_M (0x00000c00) /* */\r
-#define DWT_CTRL_SYNCTAP0 (0x00000400) /* */\r
-#define DWT_CTRL_SYNCTAP1 (0x00000800) /* */\r
-#define DWT_CTRL_SYNCTAP_0 (0x00000000) /* Disabled. No synch counting. */\r
-#define DWT_CTRL_SYNCTAP_1 (0x00000400) /* Tap at CYCCNT bit 24. */\r
-#define DWT_CTRL_SYNCTAP_2 (0x00000800) /* Tap at CYCCNT bit 26. */\r
-#define DWT_CTRL_SYNCTAP_3 (0x00000c00) /* Tap at CYCCNT bit 28. */\r
-/* DWT_CTRL[DWT_CTRL_PCSAMPLEENA] Bits */\r
-#define DWT_CTRL_PCSAMPLEENA_OFS (12) /* PCSAMPLEENA Offset */\r
-#define DWT_CTRL_PCSAMPLEENA (0x00001000) /* */\r
-/* DWT_CTRL[DWT_CTRL_EXCTRCENA] Bits */\r
-#define DWT_CTRL_EXCTRCENA_OFS (16) /* EXCTRCENA Offset */\r
-#define DWT_CTRL_EXCTRCENA (0x00010000) /* */\r
-/* DWT_CTRL[DWT_CTRL_CPIEVTENA] Bits */\r
-#define DWT_CTRL_CPIEVTENA_OFS (17) /* CPIEVTENA Offset */\r
-#define DWT_CTRL_CPIEVTENA (0x00020000) /* */\r
-/* DWT_CTRL[DWT_CTRL_EXCEVTENA] Bits */\r
-#define DWT_CTRL_EXCEVTENA_OFS (18) /* EXCEVTENA Offset */\r
-#define DWT_CTRL_EXCEVTENA (0x00040000) /* */\r
-/* DWT_CTRL[DWT_CTRL_SLEEPEVTENA] Bits */\r
-#define DWT_CTRL_SLEEPEVTENA_OFS (19) /* SLEEPEVTENA Offset */\r
-#define DWT_CTRL_SLEEPEVTENA (0x00080000) /* */\r
-/* DWT_CTRL[DWT_CTRL_LSUEVTENA] Bits */\r
-#define DWT_CTRL_LSUEVTENA_OFS (20) /* LSUEVTENA Offset */\r
-#define DWT_CTRL_LSUEVTENA (0x00100000) /* */\r
-/* DWT_CTRL[DWT_CTRL_FOLDEVTENA] Bits */\r
-#define DWT_CTRL_FOLDEVTENA_OFS (21) /* FOLDEVTENA Offset */\r
-#define DWT_CTRL_FOLDEVTENA (0x00200000) /* */\r
-/* DWT_CTRL[DWT_CTRL_CYCEVTENA] Bits */\r
-#define DWT_CTRL_CYCEVTENA_OFS (22) /* CYCEVTENA Offset */\r
-#define DWT_CTRL_CYCEVTENA (0x00400000) /* */\r
-/* DWT_CTRL[DWT_CTRL_NOPRFCNT] Bits */\r
-#define DWT_CTRL_NOPRFCNT_OFS (24) /* NOPRFCNT Offset */\r
-#define DWT_CTRL_NOPRFCNT (0x01000000) /* */\r
-/* DWT_CTRL[DWT_CTRL_NOCYCCNT] Bits */\r
-#define DWT_CTRL_NOCYCCNT_OFS (25) /* NOCYCCNT Offset */\r
-#define DWT_CTRL_NOCYCCNT (0x02000000) /* */\r
-/* DWT_CPICNT[DWT_CPICNT_CPICNT] Bits */\r
-#define DWT_CPICNT_CPICNT_OFS ( 0) /* CPICNT Offset */\r
-#define DWT_CPICNT_CPICNT_M (0x000000ff) /* */\r
-/* DWT_EXCCNT[DWT_EXCCNT_EXCCNT] Bits */\r
-#define DWT_EXCCNT_EXCCNT_OFS ( 0) /* EXCCNT Offset */\r
-#define DWT_EXCCNT_EXCCNT_M (0x000000ff) /* */\r
-/* DWT_SLEEPCNT[DWT_SLEEPCNT_SLEEPCNT] Bits */\r
-#define DWT_SLEEPCNT_SLEEPCNT_OFS ( 0) /* SLEEPCNT Offset */\r
-#define DWT_SLEEPCNT_SLEEPCNT_M (0x000000ff) /* */\r
-/* DWT_LSUCNT[DWT_LSUCNT_LSUCNT] Bits */\r
-#define DWT_LSUCNT_LSUCNT_OFS ( 0) /* LSUCNT Offset */\r
-#define DWT_LSUCNT_LSUCNT_M (0x000000ff) /* */\r
-/* DWT_FOLDCNT[DWT_FOLDCNT_FOLDCNT] Bits */\r
-#define DWT_FOLDCNT_FOLDCNT_OFS ( 0) /* FOLDCNT Offset */\r
-#define DWT_FOLDCNT_FOLDCNT_M (0x000000ff) /* */\r
-/* DWT_MASK0[DWT_MASK0_MASK] Bits */\r
-#define DWT_MASK0_MASK_OFS ( 0) /* MASK Offset */\r
-#define DWT_MASK0_MASK_M (0x0000000f) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_FUNCTION] Bits */\r
-#define DWT_FUNCTION0_FUNCTION_OFS ( 0) /* FUNCTION Offset */\r
-#define DWT_FUNCTION0_FUNCTION_M (0x0000000f) /* */\r
-#define DWT_FUNCTION0_FUNCTION0 (0x00000001) /* */\r
-#define DWT_FUNCTION0_FUNCTION1 (0x00000002) /* */\r
-#define DWT_FUNCTION0_FUNCTION2 (0x00000004) /* */\r
-#define DWT_FUNCTION0_FUNCTION3 (0x00000008) /* */\r
-#define DWT_FUNCTION0_FUNCTION_0 (0x00000000) /* Disabled */\r
-#define DWT_FUNCTION0_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */\r
-#define DWT_FUNCTION0_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */\r
-#define DWT_FUNCTION0_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */\r
-#define DWT_FUNCTION0_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */\r
-#define DWT_FUNCTION0_FUNCTION_5 (0x00000005) /* Watchpoint on read. */\r
-#define DWT_FUNCTION0_FUNCTION_6 (0x00000006) /* Watchpoint on write. */\r
-#define DWT_FUNCTION0_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */\r
-#define DWT_FUNCTION0_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */\r
-#define DWT_FUNCTION0_FUNCTION_9 (0x00000009) /* ETM trigger on read */\r
-#define DWT_FUNCTION0_FUNCTION_10 (0x0000000a) /* ETM trigger on write */\r
-#define DWT_FUNCTION0_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */\r
-#define DWT_FUNCTION0_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */\r
-#define DWT_FUNCTION0_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */\r
-#define DWT_FUNCTION0_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */\r
-#define DWT_FUNCTION0_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_EMITRANGE] Bits */\r
-#define DWT_FUNCTION0_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */\r
-#define DWT_FUNCTION0_EMITRANGE (0x00000020) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVMATCH] Bits */\r
-#define DWT_FUNCTION0_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */\r
-#define DWT_FUNCTION0_DATAVMATCH (0x00000100) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_LNK1ENA] Bits */\r
-#define DWT_FUNCTION0_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */\r
-#define DWT_FUNCTION0_LNK1ENA (0x00000200) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVSIZE] Bits */\r
-#define DWT_FUNCTION0_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */\r
-#define DWT_FUNCTION0_DATAVSIZE_M (0x00000c00) /* */\r
-#define DWT_FUNCTION0_DATAVSIZE0 (0x00000400) /* */\r
-#define DWT_FUNCTION0_DATAVSIZE1 (0x00000800) /* */\r
-#define DWT_FUNCTION0_DATAVSIZE_0 (0x00000000) /* byte */\r
-#define DWT_FUNCTION0_DATAVSIZE_1 (0x00000400) /* halfword */\r
-#define DWT_FUNCTION0_DATAVSIZE_2 (0x00000800) /* word */\r
-#define DWT_FUNCTION0_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR0] Bits */\r
-#define DWT_FUNCTION0_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */\r
-#define DWT_FUNCTION0_DATAVADDR0_M (0x0000f000) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR1] Bits */\r
-#define DWT_FUNCTION0_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */\r
-#define DWT_FUNCTION0_DATAVADDR1_M (0x000f0000) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_MATCHED] Bits */\r
-#define DWT_FUNCTION0_MATCHED_OFS (24) /* MATCHED Offset */\r
-#define DWT_FUNCTION0_MATCHED (0x01000000) /* */\r
-/* DWT_MASK1[DWT_MASK1_MASK] Bits */\r
-#define DWT_MASK1_MASK_OFS ( 0) /* MASK Offset */\r
-#define DWT_MASK1_MASK_M (0x0000000f) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_FUNCTION] Bits */\r
-#define DWT_FUNCTION1_FUNCTION_OFS ( 0) /* FUNCTION Offset */\r
-#define DWT_FUNCTION1_FUNCTION_M (0x0000000f) /* */\r
-#define DWT_FUNCTION1_FUNCTION0 (0x00000001) /* */\r
-#define DWT_FUNCTION1_FUNCTION1 (0x00000002) /* */\r
-#define DWT_FUNCTION1_FUNCTION2 (0x00000004) /* */\r
-#define DWT_FUNCTION1_FUNCTION3 (0x00000008) /* */\r
-#define DWT_FUNCTION1_FUNCTION_0 (0x00000000) /* Disabled */\r
-#define DWT_FUNCTION1_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */\r
-#define DWT_FUNCTION1_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */\r
-#define DWT_FUNCTION1_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */\r
-#define DWT_FUNCTION1_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */\r
-#define DWT_FUNCTION1_FUNCTION_5 (0x00000005) /* Watchpoint on read. */\r
-#define DWT_FUNCTION1_FUNCTION_6 (0x00000006) /* Watchpoint on write. */\r
-#define DWT_FUNCTION1_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */\r
-#define DWT_FUNCTION1_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */\r
-#define DWT_FUNCTION1_FUNCTION_9 (0x00000009) /* ETM trigger on read */\r
-#define DWT_FUNCTION1_FUNCTION_10 (0x0000000a) /* ETM trigger on write */\r
-#define DWT_FUNCTION1_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */\r
-#define DWT_FUNCTION1_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */\r
-#define DWT_FUNCTION1_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */\r
-#define DWT_FUNCTION1_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */\r
-#define DWT_FUNCTION1_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_EMITRANGE] Bits */\r
-#define DWT_FUNCTION1_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */\r
-#define DWT_FUNCTION1_EMITRANGE (0x00000020) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_CYCMATCH] Bits */\r
-#define DWT_FUNCTION1_CYCMATCH_OFS ( 7) /* CYCMATCH Offset */\r
-#define DWT_FUNCTION1_CYCMATCH (0x00000080) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVMATCH] Bits */\r
-#define DWT_FUNCTION1_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */\r
-#define DWT_FUNCTION1_DATAVMATCH (0x00000100) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_LNK1ENA] Bits */\r
-#define DWT_FUNCTION1_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */\r
-#define DWT_FUNCTION1_LNK1ENA (0x00000200) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVSIZE] Bits */\r
-#define DWT_FUNCTION1_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */\r
-#define DWT_FUNCTION1_DATAVSIZE_M (0x00000c00) /* */\r
-#define DWT_FUNCTION1_DATAVSIZE0 (0x00000400) /* */\r
-#define DWT_FUNCTION1_DATAVSIZE1 (0x00000800) /* */\r
-#define DWT_FUNCTION1_DATAVSIZE_0 (0x00000000) /* byte */\r
-#define DWT_FUNCTION1_DATAVSIZE_1 (0x00000400) /* halfword */\r
-#define DWT_FUNCTION1_DATAVSIZE_2 (0x00000800) /* word */\r
-#define DWT_FUNCTION1_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR0] Bits */\r
-#define DWT_FUNCTION1_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */\r
-#define DWT_FUNCTION1_DATAVADDR0_M (0x0000f000) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR1] Bits */\r
-#define DWT_FUNCTION1_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */\r
-#define DWT_FUNCTION1_DATAVADDR1_M (0x000f0000) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_MATCHED] Bits */\r
-#define DWT_FUNCTION1_MATCHED_OFS (24) /* MATCHED Offset */\r
-#define DWT_FUNCTION1_MATCHED (0x01000000) /* */\r
-/* DWT_MASK2[DWT_MASK2_MASK] Bits */\r
-#define DWT_MASK2_MASK_OFS ( 0) /* MASK Offset */\r
-#define DWT_MASK2_MASK_M (0x0000000f) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_FUNCTION] Bits */\r
-#define DWT_FUNCTION2_FUNCTION_OFS ( 0) /* FUNCTION Offset */\r
-#define DWT_FUNCTION2_FUNCTION_M (0x0000000f) /* */\r
-#define DWT_FUNCTION2_FUNCTION0 (0x00000001) /* */\r
-#define DWT_FUNCTION2_FUNCTION1 (0x00000002) /* */\r
-#define DWT_FUNCTION2_FUNCTION2 (0x00000004) /* */\r
-#define DWT_FUNCTION2_FUNCTION3 (0x00000008) /* */\r
-#define DWT_FUNCTION2_FUNCTION_0 (0x00000000) /* Disabled */\r
-#define DWT_FUNCTION2_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */\r
-#define DWT_FUNCTION2_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */\r
-#define DWT_FUNCTION2_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */\r
-#define DWT_FUNCTION2_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */\r
-#define DWT_FUNCTION2_FUNCTION_5 (0x00000005) /* Watchpoint on read. */\r
-#define DWT_FUNCTION2_FUNCTION_6 (0x00000006) /* Watchpoint on write. */\r
-#define DWT_FUNCTION2_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */\r
-#define DWT_FUNCTION2_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */\r
-#define DWT_FUNCTION2_FUNCTION_9 (0x00000009) /* ETM trigger on read */\r
-#define DWT_FUNCTION2_FUNCTION_10 (0x0000000a) /* ETM trigger on write */\r
-#define DWT_FUNCTION2_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */\r
-#define DWT_FUNCTION2_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */\r
-#define DWT_FUNCTION2_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */\r
-#define DWT_FUNCTION2_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */\r
-#define DWT_FUNCTION2_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_EMITRANGE] Bits */\r
-#define DWT_FUNCTION2_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */\r
-#define DWT_FUNCTION2_EMITRANGE (0x00000020) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVMATCH] Bits */\r
-#define DWT_FUNCTION2_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */\r
-#define DWT_FUNCTION2_DATAVMATCH (0x00000100) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_LNK1ENA] Bits */\r
-#define DWT_FUNCTION2_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */\r
-#define DWT_FUNCTION2_LNK1ENA (0x00000200) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVSIZE] Bits */\r
-#define DWT_FUNCTION2_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */\r
-#define DWT_FUNCTION2_DATAVSIZE_M (0x00000c00) /* */\r
-#define DWT_FUNCTION2_DATAVSIZE0 (0x00000400) /* */\r
-#define DWT_FUNCTION2_DATAVSIZE1 (0x00000800) /* */\r
-#define DWT_FUNCTION2_DATAVSIZE_0 (0x00000000) /* byte */\r
-#define DWT_FUNCTION2_DATAVSIZE_1 (0x00000400) /* halfword */\r
-#define DWT_FUNCTION2_DATAVSIZE_2 (0x00000800) /* word */\r
-#define DWT_FUNCTION2_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR0] Bits */\r
-#define DWT_FUNCTION2_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */\r
-#define DWT_FUNCTION2_DATAVADDR0_M (0x0000f000) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR1] Bits */\r
-#define DWT_FUNCTION2_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */\r
-#define DWT_FUNCTION2_DATAVADDR1_M (0x000f0000) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_MATCHED] Bits */\r
-#define DWT_FUNCTION2_MATCHED_OFS (24) /* MATCHED Offset */\r
-#define DWT_FUNCTION2_MATCHED (0x01000000) /* */\r
-/* DWT_MASK3[DWT_MASK3_MASK] Bits */\r
-#define DWT_MASK3_MASK_OFS ( 0) /* MASK Offset */\r
-#define DWT_MASK3_MASK_M (0x0000000f) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_FUNCTION] Bits */\r
-#define DWT_FUNCTION3_FUNCTION_OFS ( 0) /* FUNCTION Offset */\r
-#define DWT_FUNCTION3_FUNCTION_M (0x0000000f) /* */\r
-#define DWT_FUNCTION3_FUNCTION0 (0x00000001) /* */\r
-#define DWT_FUNCTION3_FUNCTION1 (0x00000002) /* */\r
-#define DWT_FUNCTION3_FUNCTION2 (0x00000004) /* */\r
-#define DWT_FUNCTION3_FUNCTION3 (0x00000008) /* */\r
-#define DWT_FUNCTION3_FUNCTION_0 (0x00000000) /* Disabled */\r
-#define DWT_FUNCTION3_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */\r
-#define DWT_FUNCTION3_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */\r
-#define DWT_FUNCTION3_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */\r
-#define DWT_FUNCTION3_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */\r
-#define DWT_FUNCTION3_FUNCTION_5 (0x00000005) /* Watchpoint on read. */\r
-#define DWT_FUNCTION3_FUNCTION_6 (0x00000006) /* Watchpoint on write. */\r
-#define DWT_FUNCTION3_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */\r
-#define DWT_FUNCTION3_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */\r
-#define DWT_FUNCTION3_FUNCTION_9 (0x00000009) /* ETM trigger on read */\r
-#define DWT_FUNCTION3_FUNCTION_10 (0x0000000a) /* ETM trigger on write */\r
-#define DWT_FUNCTION3_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */\r
-#define DWT_FUNCTION3_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */\r
-#define DWT_FUNCTION3_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */\r
-#define DWT_FUNCTION3_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */\r
-#define DWT_FUNCTION3_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_EMITRANGE] Bits */\r
-#define DWT_FUNCTION3_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */\r
-#define DWT_FUNCTION3_EMITRANGE (0x00000020) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVMATCH] Bits */\r
-#define DWT_FUNCTION3_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */\r
-#define DWT_FUNCTION3_DATAVMATCH (0x00000100) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_LNK1ENA] Bits */\r
-#define DWT_FUNCTION3_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */\r
-#define DWT_FUNCTION3_LNK1ENA (0x00000200) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVSIZE] Bits */\r
-#define DWT_FUNCTION3_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */\r
-#define DWT_FUNCTION3_DATAVSIZE_M (0x00000c00) /* */\r
-#define DWT_FUNCTION3_DATAVSIZE0 (0x00000400) /* */\r
-#define DWT_FUNCTION3_DATAVSIZE1 (0x00000800) /* */\r
-#define DWT_FUNCTION3_DATAVSIZE_0 (0x00000000) /* byte */\r
-#define DWT_FUNCTION3_DATAVSIZE_1 (0x00000400) /* halfword */\r
-#define DWT_FUNCTION3_DATAVSIZE_2 (0x00000800) /* word */\r
-#define DWT_FUNCTION3_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR0] Bits */\r
-#define DWT_FUNCTION3_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */\r
-#define DWT_FUNCTION3_DATAVADDR0_M (0x0000f000) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR1] Bits */\r
-#define DWT_FUNCTION3_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */\r
-#define DWT_FUNCTION3_DATAVADDR1_M (0x000f0000) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_MATCHED] Bits */\r
-#define DWT_FUNCTION3_MATCHED_OFS (24) /* MATCHED Offset */\r
-#define DWT_FUNCTION3_MATCHED (0x01000000) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A0 Bits\r
-//*****************************************************************************\r
-/* UCA0CTLW0[UCSWRST] Bits */\r
-#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA0CTLW0[UCTXBRK] Bits */\r
-#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */\r
-#define UCTXBRK (0x0002) /* Transmit break */\r
-/* UCA0CTLW0[UCTXADDR] Bits */\r
-#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */\r
-#define UCTXADDR (0x0004) /* Transmit address */\r
-/* UCA0CTLW0[UCDORM] Bits */\r
-#define UCDORM_OFS ( 3) /* UCDORM Offset */\r
-#define UCDORM (0x0008) /* Dormant */\r
-/* UCA0CTLW0[UCBRKIE] Bits */\r
-#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */\r
-#define UCBRKIE (0x0010) /* Receive break character interrupt enable */\r
-/* UCA0CTLW0[UCRXEIE] Bits */\r
-#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */\r
-#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */\r
-/* UCA0CTLW0[UCSSEL] Bits */\r
-#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-#define UCSSEL_0 (0x0000) /* UCLK */\r
-#define UCSSEL_1 (0x0040) /* ACLK */\r
-#define UCSSEL_2 (0x0080) /* SMCLK */\r
-#define UCSSEL__UCLK (0x0000) /* UCLK */\r
-#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA0CTLW0[UCSYNC] Bits */\r
-#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA0CTLW0[UCMODE] Bits */\r
-#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-#define UCMODE_M (0x0600) /* eUSCI_A mode */\r
-#define UCMODE0 (0x0200) /* eUSCI_A mode */\r
-#define UCMODE1 (0x0400) /* eUSCI_A mode */\r
-#define UCMODE_0 (0x0000) /* UART mode */\r
-#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */\r
-#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */\r
-#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */\r
-/* UCA0CTLW0[UCSPB] Bits */\r
-#define UCSPB_OFS (11) /* UCSPB Offset */\r
-#define UCSPB (0x0800) /* Stop bit select */\r
-/* UCA0CTLW0[UC7BIT] Bits */\r
-#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-#define UC7BIT (0x1000) /* Character length */\r
-/* UCA0CTLW0[UCMSB] Bits */\r
-#define UCMSB_OFS (13) /* UCMSB Offset */\r
-#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA0CTLW0[UCPAR] Bits */\r
-#define UCPAR_OFS (14) /* UCPAR Offset */\r
-#define UCPAR (0x4000) /* Parity select */\r
-/* UCA0CTLW0[UCPEN] Bits */\r
-#define UCPEN_OFS (15) /* UCPEN Offset */\r
-#define UCPEN (0x8000) /* Parity enable */\r
-/* UCA0CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA0CTLW0_SPI[UCSTEM] Bits */\r
-#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCA0CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA0CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA0CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-/* UCA0CTLW0_SPI[UCMST] Bits */\r
-#define UCMST_OFS (11) /* UCMST Offset */\r
-#define UCMST (0x0800) /* Master mode select */\r
-/* UCA0CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA0CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA0CTLW0_SPI[UCCKPL] Bits */\r
-#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCA0CTLW0_SPI[UCCKPH] Bits */\r
-#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCA0CTLW1[UCGLIT] Bits */\r
-#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-#define UCGLIT_M (0x0003) /* Deglitch time */\r
-#define UCGLIT0 (0x0001) /* Deglitch time */\r
-#define UCGLIT1 (0x0002) /* Deglitch time */\r
-#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */\r
-#define UCGLIT_1 (0x0001) /* Approximately 50 ns */\r
-#define UCGLIT_2 (0x0002) /* Approximately 100 ns */\r
-#define UCGLIT_3 (0x0003) /* Approximately 200 ns */\r
-/* UCA0MCTLW[UCOS16] Bits */\r
-#define UCOS16_OFS ( 0) /* UCOS16 Offset */\r
-#define UCOS16 (0x0001) /* Oversampling mode enabled */\r
-/* UCA0MCTLW[UCBRF] Bits */\r
-#define UCBRF_OFS ( 4) /* UCBRF Offset */\r
-#define UCBRF_M (0x00f0) /* First modulation stage select */\r
-/* UCA0MCTLW[UCBRS] Bits */\r
-#define UCBRS_OFS ( 8) /* UCBRS Offset */\r
-#define UCBRS_M (0xff00) /* Second modulation stage select */\r
-/* UCA0STATW[UCBUSY] Bits */\r
-#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA0STATW[UCADDR_UCIDLE] Bits */\r
-#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */\r
-#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */\r
-/* UCA0STATW[UCRXERR] Bits */\r
-#define UCRXERR_OFS ( 2) /* UCRXERR Offset */\r
-#define UCRXERR (0x0004) /* Receive error flag */\r
-/* UCA0STATW[UCBRK] Bits */\r
-#define UCBRK_OFS ( 3) /* UCBRK Offset */\r
-#define UCBRK (0x0008) /* Break detect flag */\r
-/* UCA0STATW[UCPE] Bits */\r
-#define UCPE_OFS ( 4) /* UCPE Offset */\r
-#define UCPE (0x0010) /* */\r
-/* UCA0STATW[UCOE] Bits */\r
-#define UCOE_OFS ( 5) /* UCOE Offset */\r
-#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA0STATW[UCFE] Bits */\r
-#define UCFE_OFS ( 6) /* UCFE Offset */\r
-#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA0STATW[UCLISTEN] Bits */\r
-#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA0STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA0STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA0STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA0STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA0RXBUF[UCRXBUF] Bits */\r
-#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA0RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA0TXBUF[UCTXBUF] Bits */\r
-#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA0TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA0ABCTL[UCABDEN] Bits */\r
-#define UCABDEN_OFS ( 0) /* UCABDEN Offset */\r
-#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */\r
-/* UCA0ABCTL[UCBTOE] Bits */\r
-#define UCBTOE_OFS ( 2) /* UCBTOE Offset */\r
-#define UCBTOE (0x0004) /* Break time out error */\r
-/* UCA0ABCTL[UCSTOE] Bits */\r
-#define UCSTOE_OFS ( 3) /* UCSTOE Offset */\r
-#define UCSTOE (0x0008) /* Synch field time out error */\r
-/* UCA0ABCTL[UCDELIM] Bits */\r
-#define UCDELIM_OFS ( 4) /* UCDELIM Offset */\r
-#define UCDELIM_M (0x0030) /* Break/synch delimiter length */\r
-#define UCDELIM0 (0x0010) /* Break/synch delimiter length */\r
-#define UCDELIM1 (0x0020) /* Break/synch delimiter length */\r
-#define UCDELIM_0 (0x0000) /* 1 bit time */\r
-#define UCDELIM_1 (0x0010) /* 2 bit times */\r
-#define UCDELIM_2 (0x0020) /* 3 bit times */\r
-#define UCDELIM_3 (0x0030) /* 4 bit times */\r
-/* UCA0IRCTL[UCIREN] Bits */\r
-#define UCIREN_OFS ( 0) /* UCIREN Offset */\r
-#define UCIREN (0x0001) /* IrDA encoder/decoder enable */\r
-/* UCA0IRCTL[UCIRTXCLK] Bits */\r
-#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */\r
-#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */\r
-/* UCA0IRCTL[UCIRTXPL] Bits */\r
-#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */\r
-#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */\r
-/* UCA0IRCTL[UCIRRXFE] Bits */\r
-#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */\r
-#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */\r
-/* UCA0IRCTL[UCIRRXPL] Bits */\r
-#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */\r
-#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */\r
-/* UCA0IRCTL[UCIRRXFL] Bits */\r
-#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */\r
-#define UCIRRXFL_M (0x3c00) /* Receive filter length */\r
-/* UCA0IE[UCRXIE] Bits */\r
-#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA0IE[UCTXIE] Bits */\r
-#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA0IE[UCSTTIE] Bits */\r
-#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-#define UCSTTIE (0x0004) /* Start bit interrupt enable */\r
-/* UCA0IE[UCTXCPTIE] Bits */\r
-#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */\r
-#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */\r
-/* UCA0IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA0IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA0IFG[UCRXIFG] Bits */\r
-#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA0IFG[UCTXIFG] Bits */\r
-#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-/* UCA0IFG[UCSTTIFG] Bits */\r
-#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-#define UCSTTIFG (0x0004) /* Start bit interrupt flag */\r
-/* UCA0IFG[UCTXCPTIFG] Bits */\r
-#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */\r
-#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */\r
-/* UCA0IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA0IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A1 Bits\r
-//*****************************************************************************\r
-/* UCA1CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA1CTLW0[UCTXBRK] Bits */\r
-//#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */\r
-//#define UCTXBRK (0x0002) /* Transmit break */\r
-/* UCA1CTLW0[UCTXADDR] Bits */\r
-//#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */\r
-//#define UCTXADDR (0x0004) /* Transmit address */\r
-/* UCA1CTLW0[UCDORM] Bits */\r
-//#define UCDORM_OFS ( 3) /* UCDORM Offset */\r
-//#define UCDORM (0x0008) /* Dormant */\r
-/* UCA1CTLW0[UCBRKIE] Bits */\r
-//#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */\r
-//#define UCBRKIE (0x0010) /* Receive break character interrupt enable */\r
-/* UCA1CTLW0[UCRXEIE] Bits */\r
-//#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */\r
-//#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */\r
-/* UCA1CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLK */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLK (0x0000) /* UCLK */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA1CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA1CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_A mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_A mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_A mode */\r
-//#define UCMODE_0 (0x0000) /* UART mode */\r
-//#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */\r
-//#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */\r
-//#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */\r
-/* UCA1CTLW0[UCSPB] Bits */\r
-//#define UCSPB_OFS (11) /* UCSPB Offset */\r
-//#define UCSPB (0x0800) /* Stop bit select */\r
-/* UCA1CTLW0[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA1CTLW0[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA1CTLW0[UCPAR] Bits */\r
-//#define UCPAR_OFS (14) /* UCPAR Offset */\r
-//#define UCPAR (0x4000) /* Parity select */\r
-/* UCA1CTLW0[UCPEN] Bits */\r
-//#define UCPEN_OFS (15) /* UCPEN Offset */\r
-//#define UCPEN (0x8000) /* Parity enable */\r
-/* UCA1CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA1CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCA1CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA1CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA1CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-/* UCA1CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCA1CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA1CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA1CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCA1CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCA1CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */\r
-//#define UCGLIT_1 (0x0001) /* Approximately 50 ns */\r
-//#define UCGLIT_2 (0x0002) /* Approximately 100 ns */\r
-//#define UCGLIT_3 (0x0003) /* Approximately 200 ns */\r
-/* UCA1MCTLW[UCOS16] Bits */\r
-//#define UCOS16_OFS ( 0) /* UCOS16 Offset */\r
-//#define UCOS16 (0x0001) /* Oversampling mode enabled */\r
-/* UCA1MCTLW[UCBRF] Bits */\r
-//#define UCBRF_OFS ( 4) /* UCBRF Offset */\r
-//#define UCBRF_M (0x00f0) /* First modulation stage select */\r
-/* UCA1MCTLW[UCBRS] Bits */\r
-//#define UCBRS_OFS ( 8) /* UCBRS Offset */\r
-//#define UCBRS_M (0xff00) /* Second modulation stage select */\r
-/* UCA1STATW[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA1STATW[UCADDR_UCIDLE] Bits */\r
-//#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */\r
-//#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */\r
-/* UCA1STATW[UCRXERR] Bits */\r
-//#define UCRXERR_OFS ( 2) /* UCRXERR Offset */\r
-//#define UCRXERR (0x0004) /* Receive error flag */\r
-/* UCA1STATW[UCBRK] Bits */\r
-//#define UCBRK_OFS ( 3) /* UCBRK Offset */\r
-//#define UCBRK (0x0008) /* Break detect flag */\r
-/* UCA1STATW[UCPE] Bits */\r
-//#define UCPE_OFS ( 4) /* UCPE Offset */\r
-//#define UCPE (0x0010) /* */\r
-/* UCA1STATW[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA1STATW[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA1STATW[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA1STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA1STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA1STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA1STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA1RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA1RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA1TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA1TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA1ABCTL[UCABDEN] Bits */\r
-//#define UCABDEN_OFS ( 0) /* UCABDEN Offset */\r
-//#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */\r
-/* UCA1ABCTL[UCBTOE] Bits */\r
-//#define UCBTOE_OFS ( 2) /* UCBTOE Offset */\r
-//#define UCBTOE (0x0004) /* Break time out error */\r
-/* UCA1ABCTL[UCSTOE] Bits */\r
-//#define UCSTOE_OFS ( 3) /* UCSTOE Offset */\r
-//#define UCSTOE (0x0008) /* Synch field time out error */\r
-/* UCA1ABCTL[UCDELIM] Bits */\r
-//#define UCDELIM_OFS ( 4) /* UCDELIM Offset */\r
-//#define UCDELIM_M (0x0030) /* Break/synch delimiter length */\r
-//#define UCDELIM0 (0x0010) /* Break/synch delimiter length */\r
-//#define UCDELIM1 (0x0020) /* Break/synch delimiter length */\r
-//#define UCDELIM_0 (0x0000) /* 1 bit time */\r
-//#define UCDELIM_1 (0x0010) /* 2 bit times */\r
-//#define UCDELIM_2 (0x0020) /* 3 bit times */\r
-//#define UCDELIM_3 (0x0030) /* 4 bit times */\r
-/* UCA1IRCTL[UCIREN] Bits */\r
-//#define UCIREN_OFS ( 0) /* UCIREN Offset */\r
-//#define UCIREN (0x0001) /* IrDA encoder/decoder enable */\r
-/* UCA1IRCTL[UCIRTXCLK] Bits */\r
-//#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */\r
-//#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */\r
-/* UCA1IRCTL[UCIRTXPL] Bits */\r
-//#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */\r
-//#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */\r
-/* UCA1IRCTL[UCIRRXFE] Bits */\r
-//#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */\r
-//#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */\r
-/* UCA1IRCTL[UCIRRXPL] Bits */\r
-//#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */\r
-//#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */\r
-/* UCA1IRCTL[UCIRRXFL] Bits */\r
-//#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */\r
-//#define UCIRRXFL_M (0x3c00) /* Receive filter length */\r
-/* UCA1IE[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA1IE[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA1IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* Start bit interrupt enable */\r
-/* UCA1IE[UCTXCPTIE] Bits */\r
-//#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */\r
-//#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */\r
-/* UCA1IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA1IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA1IFG[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA1IFG[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-/* UCA1IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* Start bit interrupt flag */\r
-/* UCA1IFG[UCTXCPTIFG] Bits */\r
-//#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */\r
-//#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */\r
-/* UCA1IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA1IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A2 Bits\r
-//*****************************************************************************\r
-/* UCA2CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA2CTLW0[UCTXBRK] Bits */\r
-//#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */\r
-//#define UCTXBRK (0x0002) /* Transmit break */\r
-/* UCA2CTLW0[UCTXADDR] Bits */\r
-//#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */\r
-//#define UCTXADDR (0x0004) /* Transmit address */\r
-/* UCA2CTLW0[UCDORM] Bits */\r
-//#define UCDORM_OFS ( 3) /* UCDORM Offset */\r
-//#define UCDORM (0x0008) /* Dormant */\r
-/* UCA2CTLW0[UCBRKIE] Bits */\r
-//#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */\r
-//#define UCBRKIE (0x0010) /* Receive break character interrupt enable */\r
-/* UCA2CTLW0[UCRXEIE] Bits */\r
-//#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */\r
-//#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */\r
-/* UCA2CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLK */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLK (0x0000) /* UCLK */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA2CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA2CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_A mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_A mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_A mode */\r
-//#define UCMODE_0 (0x0000) /* UART mode */\r
-//#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */\r
-//#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */\r
-//#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */\r
-/* UCA2CTLW0[UCSPB] Bits */\r
-//#define UCSPB_OFS (11) /* UCSPB Offset */\r
-//#define UCSPB (0x0800) /* Stop bit select */\r
-/* UCA2CTLW0[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA2CTLW0[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA2CTLW0[UCPAR] Bits */\r
-//#define UCPAR_OFS (14) /* UCPAR Offset */\r
-//#define UCPAR (0x4000) /* Parity select */\r
-/* UCA2CTLW0[UCPEN] Bits */\r
-//#define UCPEN_OFS (15) /* UCPEN Offset */\r
-//#define UCPEN (0x8000) /* Parity enable */\r
-/* UCA2CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA2CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCA2CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA2CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA2CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-/* UCA2CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCA2CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA2CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA2CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCA2CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCA2CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */\r
-//#define UCGLIT_1 (0x0001) /* Approximately 50 ns */\r
-//#define UCGLIT_2 (0x0002) /* Approximately 100 ns */\r
-//#define UCGLIT_3 (0x0003) /* Approximately 200 ns */\r
-/* UCA2MCTLW[UCOS16] Bits */\r
-//#define UCOS16_OFS ( 0) /* UCOS16 Offset */\r
-//#define UCOS16 (0x0001) /* Oversampling mode enabled */\r
-/* UCA2MCTLW[UCBRF] Bits */\r
-//#define UCBRF_OFS ( 4) /* UCBRF Offset */\r
-//#define UCBRF_M (0x00f0) /* First modulation stage select */\r
-/* UCA2MCTLW[UCBRS] Bits */\r
-//#define UCBRS_OFS ( 8) /* UCBRS Offset */\r
-//#define UCBRS_M (0xff00) /* Second modulation stage select */\r
-/* UCA2STATW[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA2STATW[UCADDR_UCIDLE] Bits */\r
-//#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */\r
-//#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */\r
-/* UCA2STATW[UCRXERR] Bits */\r
-//#define UCRXERR_OFS ( 2) /* UCRXERR Offset */\r
-//#define UCRXERR (0x0004) /* Receive error flag */\r
-/* UCA2STATW[UCBRK] Bits */\r
-//#define UCBRK_OFS ( 3) /* UCBRK Offset */\r
-//#define UCBRK (0x0008) /* Break detect flag */\r
-/* UCA2STATW[UCPE] Bits */\r
-//#define UCPE_OFS ( 4) /* UCPE Offset */\r
-//#define UCPE (0x0010) /* */\r
-/* UCA2STATW[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA2STATW[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA2STATW[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA2STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA2STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA2STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA2STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA2RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA2RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA2TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA2TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA2ABCTL[UCABDEN] Bits */\r
-//#define UCABDEN_OFS ( 0) /* UCABDEN Offset */\r
-//#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */\r
-/* UCA2ABCTL[UCBTOE] Bits */\r
-//#define UCBTOE_OFS ( 2) /* UCBTOE Offset */\r
-//#define UCBTOE (0x0004) /* Break time out error */\r
-/* UCA2ABCTL[UCSTOE] Bits */\r
-//#define UCSTOE_OFS ( 3) /* UCSTOE Offset */\r
-//#define UCSTOE (0x0008) /* Synch field time out error */\r
-/* UCA2ABCTL[UCDELIM] Bits */\r
-//#define UCDELIM_OFS ( 4) /* UCDELIM Offset */\r
-//#define UCDELIM_M (0x0030) /* Break/synch delimiter length */\r
-//#define UCDELIM0 (0x0010) /* Break/synch delimiter length */\r
-//#define UCDELIM1 (0x0020) /* Break/synch delimiter length */\r
-//#define UCDELIM_0 (0x0000) /* 1 bit time */\r
-//#define UCDELIM_1 (0x0010) /* 2 bit times */\r
-//#define UCDELIM_2 (0x0020) /* 3 bit times */\r
-//#define UCDELIM_3 (0x0030) /* 4 bit times */\r
-/* UCA2IRCTL[UCIREN] Bits */\r
-//#define UCIREN_OFS ( 0) /* UCIREN Offset */\r
-//#define UCIREN (0x0001) /* IrDA encoder/decoder enable */\r
-/* UCA2IRCTL[UCIRTXCLK] Bits */\r
-//#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */\r
-//#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */\r
-/* UCA2IRCTL[UCIRTXPL] Bits */\r
-//#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */\r
-//#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */\r
-/* UCA2IRCTL[UCIRRXFE] Bits */\r
-//#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */\r
-//#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */\r
-/* UCA2IRCTL[UCIRRXPL] Bits */\r
-//#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */\r
-//#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */\r
-/* UCA2IRCTL[UCIRRXFL] Bits */\r
-//#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */\r
-//#define UCIRRXFL_M (0x3c00) /* Receive filter length */\r
-/* UCA2IE[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA2IE[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA2IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* Start bit interrupt enable */\r
-/* UCA2IE[UCTXCPTIE] Bits */\r
-//#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */\r
-//#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */\r
-/* UCA2IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA2IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA2IFG[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA2IFG[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-/* UCA2IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* Start bit interrupt flag */\r
-/* UCA2IFG[UCTXCPTIFG] Bits */\r
-//#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */\r
-//#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */\r
-/* UCA2IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA2IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A3 Bits\r
-//*****************************************************************************\r
-/* UCA3CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA3CTLW0[UCTXBRK] Bits */\r
-//#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */\r
-//#define UCTXBRK (0x0002) /* Transmit break */\r
-/* UCA3CTLW0[UCTXADDR] Bits */\r
-//#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */\r
-//#define UCTXADDR (0x0004) /* Transmit address */\r
-/* UCA3CTLW0[UCDORM] Bits */\r
-//#define UCDORM_OFS ( 3) /* UCDORM Offset */\r
-//#define UCDORM (0x0008) /* Dormant */\r
-/* UCA3CTLW0[UCBRKIE] Bits */\r
-//#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */\r
-//#define UCBRKIE (0x0010) /* Receive break character interrupt enable */\r
-/* UCA3CTLW0[UCRXEIE] Bits */\r
-//#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */\r
-//#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */\r
-/* UCA3CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLK */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLK (0x0000) /* UCLK */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA3CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA3CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_A mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_A mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_A mode */\r
-//#define UCMODE_0 (0x0000) /* UART mode */\r
-//#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */\r
-//#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */\r
-//#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */\r
-/* UCA3CTLW0[UCSPB] Bits */\r
-//#define UCSPB_OFS (11) /* UCSPB Offset */\r
-//#define UCSPB (0x0800) /* Stop bit select */\r
-/* UCA3CTLW0[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA3CTLW0[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA3CTLW0[UCPAR] Bits */\r
-//#define UCPAR_OFS (14) /* UCPAR Offset */\r
-//#define UCPAR (0x4000) /* Parity select */\r
-/* UCA3CTLW0[UCPEN] Bits */\r
-//#define UCPEN_OFS (15) /* UCPEN Offset */\r
-//#define UCPEN (0x8000) /* Parity enable */\r
-/* UCA3CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA3CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCA3CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA3CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA3CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-/* UCA3CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCA3CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA3CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA3CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCA3CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCA3CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */\r
-//#define UCGLIT_1 (0x0001) /* Approximately 50 ns */\r
-//#define UCGLIT_2 (0x0002) /* Approximately 100 ns */\r
-//#define UCGLIT_3 (0x0003) /* Approximately 200 ns */\r
-/* UCA3MCTLW[UCOS16] Bits */\r
-//#define UCOS16_OFS ( 0) /* UCOS16 Offset */\r
-//#define UCOS16 (0x0001) /* Oversampling mode enabled */\r
-/* UCA3MCTLW[UCBRF] Bits */\r
-//#define UCBRF_OFS ( 4) /* UCBRF Offset */\r
-//#define UCBRF_M (0x00f0) /* First modulation stage select */\r
-/* UCA3MCTLW[UCBRS] Bits */\r
-//#define UCBRS_OFS ( 8) /* UCBRS Offset */\r
-//#define UCBRS_M (0xff00) /* Second modulation stage select */\r
-/* UCA3STATW[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA3STATW[UCADDR_UCIDLE] Bits */\r
-//#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */\r
-//#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */\r
-/* UCA3STATW[UCRXERR] Bits */\r
-//#define UCRXERR_OFS ( 2) /* UCRXERR Offset */\r
-//#define UCRXERR (0x0004) /* Receive error flag */\r
-/* UCA3STATW[UCBRK] Bits */\r
-//#define UCBRK_OFS ( 3) /* UCBRK Offset */\r
-//#define UCBRK (0x0008) /* Break detect flag */\r
-/* UCA3STATW[UCPE] Bits */\r
-//#define UCPE_OFS ( 4) /* UCPE Offset */\r
-//#define UCPE (0x0010) /* */\r
-/* UCA3STATW[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA3STATW[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA3STATW[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA3STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA3STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA3STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA3STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA3RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA3RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA3TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA3TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA3ABCTL[UCABDEN] Bits */\r
-//#define UCABDEN_OFS ( 0) /* UCABDEN Offset */\r
-//#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */\r
-/* UCA3ABCTL[UCBTOE] Bits */\r
-//#define UCBTOE_OFS ( 2) /* UCBTOE Offset */\r
-//#define UCBTOE (0x0004) /* Break time out error */\r
-/* UCA3ABCTL[UCSTOE] Bits */\r
-//#define UCSTOE_OFS ( 3) /* UCSTOE Offset */\r
-//#define UCSTOE (0x0008) /* Synch field time out error */\r
-/* UCA3ABCTL[UCDELIM] Bits */\r
-//#define UCDELIM_OFS ( 4) /* UCDELIM Offset */\r
-//#define UCDELIM_M (0x0030) /* Break/synch delimiter length */\r
-//#define UCDELIM0 (0x0010) /* Break/synch delimiter length */\r
-//#define UCDELIM1 (0x0020) /* Break/synch delimiter length */\r
-//#define UCDELIM_0 (0x0000) /* 1 bit time */\r
-//#define UCDELIM_1 (0x0010) /* 2 bit times */\r
-//#define UCDELIM_2 (0x0020) /* 3 bit times */\r
-//#define UCDELIM_3 (0x0030) /* 4 bit times */\r
-/* UCA3IRCTL[UCIREN] Bits */\r
-//#define UCIREN_OFS ( 0) /* UCIREN Offset */\r
-//#define UCIREN (0x0001) /* IrDA encoder/decoder enable */\r
-/* UCA3IRCTL[UCIRTXCLK] Bits */\r
-//#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */\r
-//#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */\r
-/* UCA3IRCTL[UCIRTXPL] Bits */\r
-//#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */\r
-//#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */\r
-/* UCA3IRCTL[UCIRRXFE] Bits */\r
-//#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */\r
-//#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */\r
-/* UCA3IRCTL[UCIRRXPL] Bits */\r
-//#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */\r
-//#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */\r
-/* UCA3IRCTL[UCIRRXFL] Bits */\r
-//#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */\r
-//#define UCIRRXFL_M (0x3c00) /* Receive filter length */\r
-/* UCA3IE[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA3IE[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA3IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* Start bit interrupt enable */\r
-/* UCA3IE[UCTXCPTIE] Bits */\r
-//#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */\r
-//#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */\r
-/* UCA3IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA3IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA3IFG[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA3IFG[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-/* UCA3IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* Start bit interrupt flag */\r
-/* UCA3IFG[UCTXCPTIFG] Bits */\r
-//#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */\r
-//#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */\r
-/* UCA3IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA3IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B0 Bits\r
-//*****************************************************************************\r
-/* UCB0CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB0CTLW0[UCTXSTT] Bits */\r
-#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */\r
-#define UCTXSTT (0x0002) /* Transmit START condition in master mode */\r
-/* UCB0CTLW0[UCTXSTP] Bits */\r
-#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */\r
-#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */\r
-/* UCB0CTLW0[UCTXNACK] Bits */\r
-#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */\r
-#define UCTXNACK (0x0008) /* Transmit a NACK */\r
-/* UCB0CTLW0[UCTR] Bits */\r
-#define UCTR_OFS ( 4) /* UCTR Offset */\r
-#define UCTR (0x0010) /* Transmitter/receiver */\r
-/* UCB0CTLW0[UCTXACK] Bits */\r
-#define UCTXACK_OFS ( 5) /* UCTXACK Offset */\r
-#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */\r
-/* UCB0CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLKI */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-#define UCSSEL__UCLKI (0x0000) /* UCLKI */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB0CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB0CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB0CTLW0[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB0CTLW0[UCMM] Bits */\r
-#define UCMM_OFS (13) /* UCMM Offset */\r
-#define UCMM (0x2000) /* Multi-master environment select */\r
-/* UCB0CTLW0[UCSLA10] Bits */\r
-#define UCSLA10_OFS (14) /* UCSLA10 Offset */\r
-#define UCSLA10 (0x4000) /* Slave addressing mode select */\r
-/* UCB0CTLW0[UCA10] Bits */\r
-#define UCA10_OFS (15) /* UCA10 Offset */\r
-#define UCA10 (0x8000) /* Own addressing mode select */\r
-/* UCB0CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB0CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCB0CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB0CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB0CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB0CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB0CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCB0CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCB0CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCB0CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCB0CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* 50 ns */\r
-//#define UCGLIT_1 (0x0001) /* 25 ns */\r
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */\r
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */\r
-/* UCB0CTLW1[UCASTP] Bits */\r
-#define UCASTP_OFS ( 2) /* UCASTP Offset */\r
-#define UCASTP_M (0x000c) /* Automatic STOP condition generation */\r
-#define UCASTP0 (0x0004) /* Automatic STOP condition generation */\r
-#define UCASTP1 (0x0008) /* Automatic STOP condition generation */\r
-#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
-#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */\r
-#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */\r
-/* UCB0CTLW1[UCSWACK] Bits */\r
-#define UCSWACK_OFS ( 4) /* UCSWACK Offset */\r
-#define UCSWACK (0x0010) /* SW or HW ACK control */\r
-/* UCB0CTLW1[UCSTPNACK] Bits */\r
-#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */\r
-#define UCSTPNACK (0x0020) /* ACK all master bytes */\r
-/* UCB0CTLW1[UCCLTO] Bits */\r
-#define UCCLTO_OFS ( 6) /* UCCLTO Offset */\r
-#define UCCLTO_M (0x00c0) /* Clock low timeout select */\r
-#define UCCLTO0 (0x0040) /* Clock low timeout select */\r
-#define UCCLTO1 (0x0080) /* Clock low timeout select */\r
-#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */\r
-#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */\r
-#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */\r
-#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */\r
-/* UCB0CTLW1[UCETXINT] Bits */\r
-#define UCETXINT_OFS ( 8) /* UCETXINT Offset */\r
-#define UCETXINT (0x0100) /* Early UCTXIFG0 */\r
-/* UCB0STATW[UCBBUSY] Bits */\r
-#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */\r
-#define UCBBUSY (0x0010) /* Bus busy */\r
-/* UCB0STATW[UCGC] Bits */\r
-#define UCGC_OFS ( 5) /* UCGC Offset */\r
-#define UCGC (0x0020) /* General call address received */\r
-/* UCB0STATW[UCSCLLOW] Bits */\r
-#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */\r
-#define UCSCLLOW (0x0040) /* SCL low */\r
-/* UCB0STATW[UCBCNT] Bits */\r
-#define UCBCNT_OFS ( 8) /* UCBCNT Offset */\r
-#define UCBCNT_M (0xff00) /* Hardware byte counter value */\r
-/* UCB0STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_B busy */\r
-/* UCB0STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCB0STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCB0STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCB0TBCNT[UCTBCNT] Bits */\r
-#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */\r
-#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */\r
-/* UCB0RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB0RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB0TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB0TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB0I2COA0[I2COA0] Bits */\r
-#define I2COA0_OFS ( 0) /* I2COA0 Offset */\r
-#define I2COA0_M (0x03ff) /* I2C own address */\r
-/* UCB0I2COA0[UCOAEN] Bits */\r
-#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB0I2COA0[UCGCEN] Bits */\r
-#define UCGCEN_OFS (15) /* UCGCEN Offset */\r
-#define UCGCEN (0x8000) /* General call response enable */\r
-/* UCB0I2COA1[I2COA1] Bits */\r
-#define I2COA1_OFS ( 0) /* I2COA1 Offset */\r
-#define I2COA1_M (0x03ff) /* I2C own address */\r
-/* UCB0I2COA1[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB0I2COA2[I2COA2] Bits */\r
-#define I2COA2_OFS ( 0) /* I2COA2 Offset */\r
-#define I2COA2_M (0x03ff) /* I2C own address */\r
-/* UCB0I2COA2[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB0I2COA3[I2COA3] Bits */\r
-#define I2COA3_OFS ( 0) /* I2COA3 Offset */\r
-#define I2COA3_M (0x03ff) /* I2C own address */\r
-/* UCB0I2COA3[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB0ADDRX[ADDRX] Bits */\r
-#define ADDRX_OFS ( 0) /* ADDRX Offset */\r
-#define ADDRX_M (0x03ff) /* Received Address Register */\r
-/* UCB0ADDMASK[ADDMASK] Bits */\r
-#define ADDMASK_OFS ( 0) /* ADDMASK Offset */\r
-#define ADDMASK_M (0x03ff) /* */\r
-/* UCB0I2CSA[I2CSA] Bits */\r
-#define I2CSA_OFS ( 0) /* I2CSA Offset */\r
-#define I2CSA_M (0x03ff) /* I2C slave address */\r
-/* UCB0IE[UCRXIE0] Bits */\r
-#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */\r
-#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */\r
-/* UCB0IE[UCTXIE0] Bits */\r
-#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */\r
-#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */\r
-/* UCB0IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */\r
-/* UCB0IE[UCSTPIE] Bits */\r
-#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */\r
-#define UCSTPIE (0x0008) /* STOP condition interrupt enable */\r
-/* UCB0IE[UCALIE] Bits */\r
-#define UCALIE_OFS ( 4) /* UCALIE Offset */\r
-#define UCALIE (0x0010) /* Arbitration lost interrupt enable */\r
-/* UCB0IE[UCNACKIE] Bits */\r
-#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */\r
-#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */\r
-/* UCB0IE[UCBCNTIE] Bits */\r
-#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */\r
-#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */\r
-/* UCB0IE[UCCLTOIE] Bits */\r
-#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */\r
-#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */\r
-/* UCB0IE[UCRXIE1] Bits */\r
-#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */\r
-#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */\r
-/* UCB0IE[UCTXIE1] Bits */\r
-#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */\r
-#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */\r
-/* UCB0IE[UCRXIE2] Bits */\r
-#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */\r
-#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */\r
-/* UCB0IE[UCTXIE2] Bits */\r
-#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */\r
-#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */\r
-/* UCB0IE[UCRXIE3] Bits */\r
-#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */\r
-#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */\r
-/* UCB0IE[UCTXIE3] Bits */\r
-#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */\r
-#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */\r
-/* UCB0IE[UCBIT9IE] Bits */\r
-#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */\r
-#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */\r
-/* UCB0IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCB0IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCB0IFG[UCRXIFG0] Bits */\r
-#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */\r
-#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */\r
-/* UCB0IFG[UCTXIFG0] Bits */\r
-#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */\r
-#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */\r
-/* UCB0IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */\r
-/* UCB0IFG[UCSTPIFG] Bits */\r
-#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */\r
-#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */\r
-/* UCB0IFG[UCALIFG] Bits */\r
-#define UCALIFG_OFS ( 4) /* UCALIFG Offset */\r
-#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */\r
-/* UCB0IFG[UCNACKIFG] Bits */\r
-#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */\r
-#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */\r
-/* UCB0IFG[UCBCNTIFG] Bits */\r
-#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */\r
-#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */\r
-/* UCB0IFG[UCCLTOIFG] Bits */\r
-#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */\r
-#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */\r
-/* UCB0IFG[UCRXIFG1] Bits */\r
-#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */\r
-#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */\r
-/* UCB0IFG[UCTXIFG1] Bits */\r
-#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */\r
-#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */\r
-/* UCB0IFG[UCRXIFG2] Bits */\r
-#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */\r
-#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */\r
-/* UCB0IFG[UCTXIFG2] Bits */\r
-#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */\r
-#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */\r
-/* UCB0IFG[UCRXIFG3] Bits */\r
-#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */\r
-#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */\r
-/* UCB0IFG[UCTXIFG3] Bits */\r
-#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */\r
-#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */\r
-/* UCB0IFG[UCBIT9IFG] Bits */\r
-#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */\r
-#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */\r
-/* UCB0IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCB0IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B1 Bits\r
-//*****************************************************************************\r
-/* UCB1CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB1CTLW0[UCTXSTT] Bits */\r
-//#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */\r
-//#define UCTXSTT (0x0002) /* Transmit START condition in master mode */\r
-/* UCB1CTLW0[UCTXSTP] Bits */\r
-//#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */\r
-//#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */\r
-/* UCB1CTLW0[UCTXNACK] Bits */\r
-//#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */\r
-//#define UCTXNACK (0x0008) /* Transmit a NACK */\r
-/* UCB1CTLW0[UCTR] Bits */\r
-//#define UCTR_OFS ( 4) /* UCTR Offset */\r
-//#define UCTR (0x0010) /* Transmitter/receiver */\r
-/* UCB1CTLW0[UCTXACK] Bits */\r
-//#define UCTXACK_OFS ( 5) /* UCTXACK Offset */\r
-//#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */\r
-/* UCB1CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLKI */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLKI (0x0000) /* UCLKI */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB1CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB1CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB1CTLW0[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB1CTLW0[UCMM] Bits */\r
-//#define UCMM_OFS (13) /* UCMM Offset */\r
-//#define UCMM (0x2000) /* Multi-master environment select */\r
-/* UCB1CTLW0[UCSLA10] Bits */\r
-//#define UCSLA10_OFS (14) /* UCSLA10 Offset */\r
-//#define UCSLA10 (0x4000) /* Slave addressing mode select */\r
-/* UCB1CTLW0[UCA10] Bits */\r
-//#define UCA10_OFS (15) /* UCA10 Offset */\r
-//#define UCA10 (0x8000) /* Own addressing mode select */\r
-/* UCB1CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB1CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCB1CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB1CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB1CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB1CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB1CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCB1CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCB1CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCB1CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCB1CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* 50 ns */\r
-//#define UCGLIT_1 (0x0001) /* 25 ns */\r
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */\r
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */\r
-/* UCB1CTLW1[UCASTP] Bits */\r
-//#define UCASTP_OFS ( 2) /* UCASTP Offset */\r
-//#define UCASTP_M (0x000c) /* Automatic STOP condition generation */\r
-//#define UCASTP0 (0x0004) /* Automatic STOP condition generation */\r
-//#define UCASTP1 (0x0008) /* Automatic STOP condition generation */\r
-//#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
-//#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */\r
-//#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */\r
-/* UCB1CTLW1[UCSWACK] Bits */\r
-//#define UCSWACK_OFS ( 4) /* UCSWACK Offset */\r
-//#define UCSWACK (0x0010) /* SW or HW ACK control */\r
-/* UCB1CTLW1[UCSTPNACK] Bits */\r
-//#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */\r
-//#define UCSTPNACK (0x0020) /* ACK all master bytes */\r
-/* UCB1CTLW1[UCCLTO] Bits */\r
-//#define UCCLTO_OFS ( 6) /* UCCLTO Offset */\r
-//#define UCCLTO_M (0x00c0) /* Clock low timeout select */\r
-//#define UCCLTO0 (0x0040) /* Clock low timeout select */\r
-//#define UCCLTO1 (0x0080) /* Clock low timeout select */\r
-//#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */\r
-//#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */\r
-//#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */\r
-//#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */\r
-/* UCB1CTLW1[UCETXINT] Bits */\r
-//#define UCETXINT_OFS ( 8) /* UCETXINT Offset */\r
-//#define UCETXINT (0x0100) /* Early UCTXIFG0 */\r
-/* UCB1STATW[UCBBUSY] Bits */\r
-//#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */\r
-//#define UCBBUSY (0x0010) /* Bus busy */\r
-/* UCB1STATW[UCGC] Bits */\r
-//#define UCGC_OFS ( 5) /* UCGC Offset */\r
-//#define UCGC (0x0020) /* General call address received */\r
-/* UCB1STATW[UCSCLLOW] Bits */\r
-//#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */\r
-//#define UCSCLLOW (0x0040) /* SCL low */\r
-/* UCB1STATW[UCBCNT] Bits */\r
-//#define UCBCNT_OFS ( 8) /* UCBCNT Offset */\r
-//#define UCBCNT_M (0xff00) /* Hardware byte counter value */\r
-/* UCB1STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_B busy */\r
-/* UCB1STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCB1STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCB1STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCB1TBCNT[UCTBCNT] Bits */\r
-//#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */\r
-//#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */\r
-/* UCB1RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB1RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB1TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB1TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB1I2COA0[I2COA0] Bits */\r
-//#define I2COA0_OFS ( 0) /* I2COA0 Offset */\r
-//#define I2COA0_M (0x03ff) /* I2C own address */\r
-/* UCB1I2COA0[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB1I2COA0[UCGCEN] Bits */\r
-//#define UCGCEN_OFS (15) /* UCGCEN Offset */\r
-//#define UCGCEN (0x8000) /* General call response enable */\r
-/* UCB1I2COA1[I2COA1] Bits */\r
-//#define I2COA1_OFS ( 0) /* I2COA1 Offset */\r
-//#define I2COA1_M (0x03ff) /* I2C own address */\r
-/* UCB1I2COA1[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB1I2COA2[I2COA2] Bits */\r
-//#define I2COA2_OFS ( 0) /* I2COA2 Offset */\r
-//#define I2COA2_M (0x03ff) /* I2C own address */\r
-/* UCB1I2COA2[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB1I2COA3[I2COA3] Bits */\r
-//#define I2COA3_OFS ( 0) /* I2COA3 Offset */\r
-//#define I2COA3_M (0x03ff) /* I2C own address */\r
-/* UCB1I2COA3[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB1ADDRX[ADDRX] Bits */\r
-//#define ADDRX_OFS ( 0) /* ADDRX Offset */\r
-//#define ADDRX_M (0x03ff) /* Received Address Register */\r
-/* UCB1ADDMASK[ADDMASK] Bits */\r
-//#define ADDMASK_OFS ( 0) /* ADDMASK Offset */\r
-//#define ADDMASK_M (0x03ff) /* */\r
-/* UCB1I2CSA[I2CSA] Bits */\r
-//#define I2CSA_OFS ( 0) /* I2CSA Offset */\r
-//#define I2CSA_M (0x03ff) /* I2C slave address */\r
-/* UCB1IE[UCRXIE0] Bits */\r
-//#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */\r
-//#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */\r
-/* UCB1IE[UCTXIE0] Bits */\r
-//#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */\r
-//#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */\r
-/* UCB1IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */\r
-/* UCB1IE[UCSTPIE] Bits */\r
-//#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */\r
-//#define UCSTPIE (0x0008) /* STOP condition interrupt enable */\r
-/* UCB1IE[UCALIE] Bits */\r
-//#define UCALIE_OFS ( 4) /* UCALIE Offset */\r
-//#define UCALIE (0x0010) /* Arbitration lost interrupt enable */\r
-/* UCB1IE[UCNACKIE] Bits */\r
-//#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */\r
-//#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */\r
-/* UCB1IE[UCBCNTIE] Bits */\r
-//#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */\r
-//#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */\r
-/* UCB1IE[UCCLTOIE] Bits */\r
-//#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */\r
-//#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */\r
-/* UCB1IE[UCRXIE1] Bits */\r
-//#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */\r
-//#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */\r
-/* UCB1IE[UCTXIE1] Bits */\r
-//#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */\r
-//#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */\r
-/* UCB1IE[UCRXIE2] Bits */\r
-//#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */\r
-//#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */\r
-/* UCB1IE[UCTXIE2] Bits */\r
-//#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */\r
-//#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */\r
-/* UCB1IE[UCRXIE3] Bits */\r
-//#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */\r
-//#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */\r
-/* UCB1IE[UCTXIE3] Bits */\r
-//#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */\r
-//#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */\r
-/* UCB1IE[UCBIT9IE] Bits */\r
-//#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */\r
-//#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */\r
-/* UCB1IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCB1IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCB1IFG[UCRXIFG0] Bits */\r
-//#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */\r
-//#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */\r
-/* UCB1IFG[UCTXIFG0] Bits */\r
-//#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */\r
-//#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */\r
-/* UCB1IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */\r
-/* UCB1IFG[UCSTPIFG] Bits */\r
-//#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */\r
-//#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */\r
-/* UCB1IFG[UCALIFG] Bits */\r
-//#define UCALIFG_OFS ( 4) /* UCALIFG Offset */\r
-//#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */\r
-/* UCB1IFG[UCNACKIFG] Bits */\r
-//#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */\r
-//#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */\r
-/* UCB1IFG[UCBCNTIFG] Bits */\r
-//#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */\r
-//#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */\r
-/* UCB1IFG[UCCLTOIFG] Bits */\r
-//#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */\r
-//#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */\r
-/* UCB1IFG[UCRXIFG1] Bits */\r
-//#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */\r
-//#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */\r
-/* UCB1IFG[UCTXIFG1] Bits */\r
-//#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */\r
-//#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */\r
-/* UCB1IFG[UCRXIFG2] Bits */\r
-//#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */\r
-//#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */\r
-/* UCB1IFG[UCTXIFG2] Bits */\r
-//#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */\r
-//#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */\r
-/* UCB1IFG[UCRXIFG3] Bits */\r
-//#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */\r
-//#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */\r
-/* UCB1IFG[UCTXIFG3] Bits */\r
-//#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */\r
-//#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */\r
-/* UCB1IFG[UCBIT9IFG] Bits */\r
-//#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */\r
-//#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */\r
-/* UCB1IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCB1IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B2 Bits\r
-//*****************************************************************************\r
-/* UCB2CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB2CTLW0[UCTXSTT] Bits */\r
-//#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */\r
-//#define UCTXSTT (0x0002) /* Transmit START condition in master mode */\r
-/* UCB2CTLW0[UCTXSTP] Bits */\r
-//#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */\r
-//#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */\r
-/* UCB2CTLW0[UCTXNACK] Bits */\r
-//#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */\r
-//#define UCTXNACK (0x0008) /* Transmit a NACK */\r
-/* UCB2CTLW0[UCTR] Bits */\r
-//#define UCTR_OFS ( 4) /* UCTR Offset */\r
-//#define UCTR (0x0010) /* Transmitter/receiver */\r
-/* UCB2CTLW0[UCTXACK] Bits */\r
-//#define UCTXACK_OFS ( 5) /* UCTXACK Offset */\r
-//#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */\r
-/* UCB2CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLKI */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLKI (0x0000) /* UCLKI */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB2CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB2CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB2CTLW0[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB2CTLW0[UCMM] Bits */\r
-//#define UCMM_OFS (13) /* UCMM Offset */\r
-//#define UCMM (0x2000) /* Multi-master environment select */\r
-/* UCB2CTLW0[UCSLA10] Bits */\r
-//#define UCSLA10_OFS (14) /* UCSLA10 Offset */\r
-//#define UCSLA10 (0x4000) /* Slave addressing mode select */\r
-/* UCB2CTLW0[UCA10] Bits */\r
-//#define UCA10_OFS (15) /* UCA10 Offset */\r
-//#define UCA10 (0x8000) /* Own addressing mode select */\r
-/* UCB2CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB2CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCB2CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB2CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB2CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB2CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB2CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCB2CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCB2CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCB2CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCB2CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* 50 ns */\r
-//#define UCGLIT_1 (0x0001) /* 25 ns */\r
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */\r
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */\r
-/* UCB2CTLW1[UCASTP] Bits */\r
-//#define UCASTP_OFS ( 2) /* UCASTP Offset */\r
-//#define UCASTP_M (0x000c) /* Automatic STOP condition generation */\r
-//#define UCASTP0 (0x0004) /* Automatic STOP condition generation */\r
-//#define UCASTP1 (0x0008) /* Automatic STOP condition generation */\r
-//#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
-//#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */\r
-//#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */\r
-/* UCB2CTLW1[UCSWACK] Bits */\r
-//#define UCSWACK_OFS ( 4) /* UCSWACK Offset */\r
-//#define UCSWACK (0x0010) /* SW or HW ACK control */\r
-/* UCB2CTLW1[UCSTPNACK] Bits */\r
-//#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */\r
-//#define UCSTPNACK (0x0020) /* ACK all master bytes */\r
-/* UCB2CTLW1[UCCLTO] Bits */\r
-//#define UCCLTO_OFS ( 6) /* UCCLTO Offset */\r
-//#define UCCLTO_M (0x00c0) /* Clock low timeout select */\r
-//#define UCCLTO0 (0x0040) /* Clock low timeout select */\r
-//#define UCCLTO1 (0x0080) /* Clock low timeout select */\r
-//#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */\r
-//#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */\r
-//#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */\r
-//#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */\r
-/* UCB2CTLW1[UCETXINT] Bits */\r
-//#define UCETXINT_OFS ( 8) /* UCETXINT Offset */\r
-//#define UCETXINT (0x0100) /* Early UCTXIFG0 */\r
-/* UCB2STATW[UCBBUSY] Bits */\r
-//#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */\r
-//#define UCBBUSY (0x0010) /* Bus busy */\r
-/* UCB2STATW[UCGC] Bits */\r
-//#define UCGC_OFS ( 5) /* UCGC Offset */\r
-//#define UCGC (0x0020) /* General call address received */\r
-/* UCB2STATW[UCSCLLOW] Bits */\r
-//#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */\r
-//#define UCSCLLOW (0x0040) /* SCL low */\r
-/* UCB2STATW[UCBCNT] Bits */\r
-//#define UCBCNT_OFS ( 8) /* UCBCNT Offset */\r
-//#define UCBCNT_M (0xff00) /* Hardware byte counter value */\r
-/* UCB2STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_B busy */\r
-/* UCB2STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCB2STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCB2STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCB2TBCNT[UCTBCNT] Bits */\r
-//#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */\r
-//#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */\r
-/* UCB2RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB2RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB2TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB2TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB2I2COA0[I2COA0] Bits */\r
-//#define I2COA0_OFS ( 0) /* I2COA0 Offset */\r
-//#define I2COA0_M (0x03ff) /* I2C own address */\r
-/* UCB2I2COA0[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB2I2COA0[UCGCEN] Bits */\r
-//#define UCGCEN_OFS (15) /* UCGCEN Offset */\r
-//#define UCGCEN (0x8000) /* General call response enable */\r
-/* UCB2I2COA1[I2COA1] Bits */\r
-//#define I2COA1_OFS ( 0) /* I2COA1 Offset */\r
-//#define I2COA1_M (0x03ff) /* I2C own address */\r
-/* UCB2I2COA1[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB2I2COA2[I2COA2] Bits */\r
-//#define I2COA2_OFS ( 0) /* I2COA2 Offset */\r
-//#define I2COA2_M (0x03ff) /* I2C own address */\r
-/* UCB2I2COA2[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB2I2COA3[I2COA3] Bits */\r
-//#define I2COA3_OFS ( 0) /* I2COA3 Offset */\r
-//#define I2COA3_M (0x03ff) /* I2C own address */\r
-/* UCB2I2COA3[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB2ADDRX[ADDRX] Bits */\r
-//#define ADDRX_OFS ( 0) /* ADDRX Offset */\r
-//#define ADDRX_M (0x03ff) /* Received Address Register */\r
-/* UCB2ADDMASK[ADDMASK] Bits */\r
-//#define ADDMASK_OFS ( 0) /* ADDMASK Offset */\r
-//#define ADDMASK_M (0x03ff) /* */\r
-/* UCB2I2CSA[I2CSA] Bits */\r
-//#define I2CSA_OFS ( 0) /* I2CSA Offset */\r
-//#define I2CSA_M (0x03ff) /* I2C slave address */\r
-/* UCB2IE[UCRXIE0] Bits */\r
-//#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */\r
-//#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */\r
-/* UCB2IE[UCTXIE0] Bits */\r
-//#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */\r
-//#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */\r
-/* UCB2IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */\r
-/* UCB2IE[UCSTPIE] Bits */\r
-//#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */\r
-//#define UCSTPIE (0x0008) /* STOP condition interrupt enable */\r
-/* UCB2IE[UCALIE] Bits */\r
-//#define UCALIE_OFS ( 4) /* UCALIE Offset */\r
-//#define UCALIE (0x0010) /* Arbitration lost interrupt enable */\r
-/* UCB2IE[UCNACKIE] Bits */\r
-//#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */\r
-//#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */\r
-/* UCB2IE[UCBCNTIE] Bits */\r
-//#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */\r
-//#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */\r
-/* UCB2IE[UCCLTOIE] Bits */\r
-//#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */\r
-//#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */\r
-/* UCB2IE[UCRXIE1] Bits */\r
-//#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */\r
-//#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */\r
-/* UCB2IE[UCTXIE1] Bits */\r
-//#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */\r
-//#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */\r
-/* UCB2IE[UCRXIE2] Bits */\r
-//#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */\r
-//#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */\r
-/* UCB2IE[UCTXIE2] Bits */\r
-//#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */\r
-//#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */\r
-/* UCB2IE[UCRXIE3] Bits */\r
-//#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */\r
-//#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */\r
-/* UCB2IE[UCTXIE3] Bits */\r
-//#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */\r
-//#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */\r
-/* UCB2IE[UCBIT9IE] Bits */\r
-//#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */\r
-//#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */\r
-/* UCB2IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCB2IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCB2IFG[UCRXIFG0] Bits */\r
-//#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */\r
-//#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */\r
-/* UCB2IFG[UCTXIFG0] Bits */\r
-//#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */\r
-//#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */\r
-/* UCB2IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */\r
-/* UCB2IFG[UCSTPIFG] Bits */\r
-//#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */\r
-//#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */\r
-/* UCB2IFG[UCALIFG] Bits */\r
-//#define UCALIFG_OFS ( 4) /* UCALIFG Offset */\r
-//#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */\r
-/* UCB2IFG[UCNACKIFG] Bits */\r
-//#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */\r
-//#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */\r
-/* UCB2IFG[UCBCNTIFG] Bits */\r
-//#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */\r
-//#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */\r
-/* UCB2IFG[UCCLTOIFG] Bits */\r
-//#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */\r
-//#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */\r
-/* UCB2IFG[UCRXIFG1] Bits */\r
-//#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */\r
-//#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */\r
-/* UCB2IFG[UCTXIFG1] Bits */\r
-//#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */\r
-//#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */\r
-/* UCB2IFG[UCRXIFG2] Bits */\r
-//#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */\r
-//#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */\r
-/* UCB2IFG[UCTXIFG2] Bits */\r
-//#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */\r
-//#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */\r
-/* UCB2IFG[UCRXIFG3] Bits */\r
-//#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */\r
-//#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */\r
-/* UCB2IFG[UCTXIFG3] Bits */\r
-//#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */\r
-//#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */\r
-/* UCB2IFG[UCBIT9IFG] Bits */\r
-//#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */\r
-//#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */\r
-/* UCB2IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCB2IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B3 Bits\r
-//*****************************************************************************\r
-/* UCB3CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB3CTLW0[UCTXSTT] Bits */\r
-//#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */\r
-//#define UCTXSTT (0x0002) /* Transmit START condition in master mode */\r
-/* UCB3CTLW0[UCTXSTP] Bits */\r
-//#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */\r
-//#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */\r
-/* UCB3CTLW0[UCTXNACK] Bits */\r
-//#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */\r
-//#define UCTXNACK (0x0008) /* Transmit a NACK */\r
-/* UCB3CTLW0[UCTR] Bits */\r
-//#define UCTR_OFS ( 4) /* UCTR Offset */\r
-//#define UCTR (0x0010) /* Transmitter/receiver */\r
-/* UCB3CTLW0[UCTXACK] Bits */\r
-//#define UCTXACK_OFS ( 5) /* UCTXACK Offset */\r
-//#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */\r
-/* UCB3CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLKI */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLKI (0x0000) /* UCLKI */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB3CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB3CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB3CTLW0[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB3CTLW0[UCMM] Bits */\r
-//#define UCMM_OFS (13) /* UCMM Offset */\r
-//#define UCMM (0x2000) /* Multi-master environment select */\r
-/* UCB3CTLW0[UCSLA10] Bits */\r
-//#define UCSLA10_OFS (14) /* UCSLA10 Offset */\r
-//#define UCSLA10 (0x4000) /* Slave addressing mode select */\r
-/* UCB3CTLW0[UCA10] Bits */\r
-//#define UCA10_OFS (15) /* UCA10 Offset */\r
-//#define UCA10 (0x8000) /* Own addressing mode select */\r
-/* UCB3CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB3CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCB3CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB3CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB3CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB3CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB3CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCB3CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCB3CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCB3CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCB3CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* 50 ns */\r
-//#define UCGLIT_1 (0x0001) /* 25 ns */\r
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */\r
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */\r
-/* UCB3CTLW1[UCASTP] Bits */\r
-//#define UCASTP_OFS ( 2) /* UCASTP Offset */\r
-//#define UCASTP_M (0x000c) /* Automatic STOP condition generation */\r
-//#define UCASTP0 (0x0004) /* Automatic STOP condition generation */\r
-//#define UCASTP1 (0x0008) /* Automatic STOP condition generation */\r
-//#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
-//#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */\r
-//#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */\r
-/* UCB3CTLW1[UCSWACK] Bits */\r
-//#define UCSWACK_OFS ( 4) /* UCSWACK Offset */\r
-//#define UCSWACK (0x0010) /* SW or HW ACK control */\r
-/* UCB3CTLW1[UCSTPNACK] Bits */\r
-//#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */\r
-//#define UCSTPNACK (0x0020) /* ACK all master bytes */\r
-/* UCB3CTLW1[UCCLTO] Bits */\r
-//#define UCCLTO_OFS ( 6) /* UCCLTO Offset */\r
-//#define UCCLTO_M (0x00c0) /* Clock low timeout select */\r
-//#define UCCLTO0 (0x0040) /* Clock low timeout select */\r
-//#define UCCLTO1 (0x0080) /* Clock low timeout select */\r
-//#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */\r
-//#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */\r
-//#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */\r
-//#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */\r
-/* UCB3CTLW1[UCETXINT] Bits */\r
-//#define UCETXINT_OFS ( 8) /* UCETXINT Offset */\r
-//#define UCETXINT (0x0100) /* Early UCTXIFG0 */\r
-/* UCB3STATW[UCBBUSY] Bits */\r
-//#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */\r
-//#define UCBBUSY (0x0010) /* Bus busy */\r
-/* UCB3STATW[UCGC] Bits */\r
-//#define UCGC_OFS ( 5) /* UCGC Offset */\r
-//#define UCGC (0x0020) /* General call address received */\r
-/* UCB3STATW[UCSCLLOW] Bits */\r
-//#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */\r
-//#define UCSCLLOW (0x0040) /* SCL low */\r
-/* UCB3STATW[UCBCNT] Bits */\r
-//#define UCBCNT_OFS ( 8) /* UCBCNT Offset */\r
-//#define UCBCNT_M (0xff00) /* Hardware byte counter value */\r
-/* UCB3STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_B busy */\r
-/* UCB3STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCB3STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCB3STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCB3TBCNT[UCTBCNT] Bits */\r
-//#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */\r
-//#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */\r
-/* UCB3RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB3RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB3TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB3TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB3I2COA0[I2COA0] Bits */\r
-//#define I2COA0_OFS ( 0) /* I2COA0 Offset */\r
-//#define I2COA0_M (0x03ff) /* I2C own address */\r
-/* UCB3I2COA0[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB3I2COA0[UCGCEN] Bits */\r
-//#define UCGCEN_OFS (15) /* UCGCEN Offset */\r
-//#define UCGCEN (0x8000) /* General call response enable */\r
-/* UCB3I2COA1[I2COA1] Bits */\r
-//#define I2COA1_OFS ( 0) /* I2COA1 Offset */\r
-//#define I2COA1_M (0x03ff) /* I2C own address */\r
-/* UCB3I2COA1[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB3I2COA2[I2COA2] Bits */\r
-//#define I2COA2_OFS ( 0) /* I2COA2 Offset */\r
-//#define I2COA2_M (0x03ff) /* I2C own address */\r
-/* UCB3I2COA2[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB3I2COA3[I2COA3] Bits */\r
-//#define I2COA3_OFS ( 0) /* I2COA3 Offset */\r
-//#define I2COA3_M (0x03ff) /* I2C own address */\r
-/* UCB3I2COA3[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB3ADDRX[ADDRX] Bits */\r
-//#define ADDRX_OFS ( 0) /* ADDRX Offset */\r
-//#define ADDRX_M (0x03ff) /* Received Address Register */\r
-/* UCB3ADDMASK[ADDMASK] Bits */\r
-//#define ADDMASK_OFS ( 0) /* ADDMASK Offset */\r
-//#define ADDMASK_M (0x03ff) /* */\r
-/* UCB3I2CSA[I2CSA] Bits */\r
-//#define I2CSA_OFS ( 0) /* I2CSA Offset */\r
-//#define I2CSA_M (0x03ff) /* I2C slave address */\r
-/* UCB3IE[UCRXIE0] Bits */\r
-//#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */\r
-//#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */\r
-/* UCB3IE[UCTXIE0] Bits */\r
-//#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */\r
-//#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */\r
-/* UCB3IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */\r
-/* UCB3IE[UCSTPIE] Bits */\r
-//#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */\r
-//#define UCSTPIE (0x0008) /* STOP condition interrupt enable */\r
-/* UCB3IE[UCALIE] Bits */\r
-//#define UCALIE_OFS ( 4) /* UCALIE Offset */\r
-//#define UCALIE (0x0010) /* Arbitration lost interrupt enable */\r
-/* UCB3IE[UCNACKIE] Bits */\r
-//#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */\r
-//#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */\r
-/* UCB3IE[UCBCNTIE] Bits */\r
-//#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */\r
-//#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */\r
-/* UCB3IE[UCCLTOIE] Bits */\r
-//#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */\r
-//#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */\r
-/* UCB3IE[UCRXIE1] Bits */\r
-//#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */\r
-//#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */\r
-/* UCB3IE[UCTXIE1] Bits */\r
-//#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */\r
-//#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */\r
-/* UCB3IE[UCRXIE2] Bits */\r
-//#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */\r
-//#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */\r
-/* UCB3IE[UCTXIE2] Bits */\r
-//#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */\r
-//#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */\r
-/* UCB3IE[UCRXIE3] Bits */\r
-//#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */\r
-//#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */\r
-/* UCB3IE[UCTXIE3] Bits */\r
-//#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */\r
-//#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */\r
-/* UCB3IE[UCBIT9IE] Bits */\r
-//#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */\r
-//#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */\r
-/* UCB3IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCB3IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCB3IFG[UCRXIFG0] Bits */\r
-//#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */\r
-//#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */\r
-/* UCB3IFG[UCTXIFG0] Bits */\r
-//#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */\r
-//#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */\r
-/* UCB3IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */\r
-/* UCB3IFG[UCSTPIFG] Bits */\r
-//#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */\r
-//#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */\r
-/* UCB3IFG[UCALIFG] Bits */\r
-//#define UCALIFG_OFS ( 4) /* UCALIFG Offset */\r
-//#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */\r
-/* UCB3IFG[UCNACKIFG] Bits */\r
-//#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */\r
-//#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */\r
-/* UCB3IFG[UCBCNTIFG] Bits */\r
-//#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */\r
-//#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */\r
-/* UCB3IFG[UCCLTOIFG] Bits */\r
-//#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */\r
-//#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */\r
-/* UCB3IFG[UCRXIFG1] Bits */\r
-//#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */\r
-//#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */\r
-/* UCB3IFG[UCTXIFG1] Bits */\r
-//#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */\r
-//#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */\r
-/* UCB3IFG[UCRXIFG2] Bits */\r
-//#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */\r
-//#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */\r
-/* UCB3IFG[UCTXIFG2] Bits */\r
-//#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */\r
-//#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */\r
-/* UCB3IFG[UCRXIFG3] Bits */\r
-//#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */\r
-//#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */\r
-/* UCB3IFG[UCTXIFG3] Bits */\r
-//#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */\r
-//#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */\r
-/* UCB3IFG[UCBIT9IFG] Bits */\r
-//#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */\r
-//#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */\r
-/* UCB3IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCB3IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// FLCTL Bits\r
-//*****************************************************************************\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_PSTAT] Bits */\r
-#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /* PSTAT Offset */\r
-#define FLCTL_POWER_STAT_PSTAT_M (0x00000007) /* */\r
-#define FLCTL_POWER_STAT_PSTAT0 (0x00000001) /* */\r
-#define FLCTL_POWER_STAT_PSTAT1 (0x00000002) /* */\r
-#define FLCTL_POWER_STAT_PSTAT2 (0x00000004) /* */\r
-#define FLCTL_POWER_STAT_PSTAT_0 (0x00000000) /* Flash IP in power-down mode */\r
-#define FLCTL_POWER_STAT_PSTAT_1 (0x00000001) /* Flash IP Vdd domain power-up in progress */\r
-#define FLCTL_POWER_STAT_PSTAT_2 (0x00000002) /* PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */\r
-#define FLCTL_POWER_STAT_PSTAT_3 (0x00000003) /* Flash IP SAFE_LV check in progress */\r
-#define FLCTL_POWER_STAT_PSTAT_4 (0x00000004) /* Flash IP Active */\r
-#define FLCTL_POWER_STAT_PSTAT_5 (0x00000005) /* Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */\r
-#define FLCTL_POWER_STAT_PSTAT_6 (0x00000006) /* Flash IP in Standby mode */\r
-#define FLCTL_POWER_STAT_PSTAT_7 (0x00000007) /* Flash IP in Current mirror boost state */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_LDOSTAT] Bits */\r
-#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /* LDOSTAT Offset */\r
-#define FLCTL_POWER_STAT_LDOSTAT (0x00000008) /* PSS FLDO GOOD status */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_VREFSTAT] Bits */\r
-#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /* VREFSTAT Offset */\r
-#define FLCTL_POWER_STAT_VREFSTAT (0x00000010) /* PSS VREF stable status */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_IREFSTAT] Bits */\r
-#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /* IREFSTAT Offset */\r
-#define FLCTL_POWER_STAT_IREFSTAT (0x00000020) /* PSS IREF stable status */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_TRIMSTAT] Bits */\r
-#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /* TRIMSTAT Offset */\r
-#define FLCTL_POWER_STAT_TRIMSTAT (0x00000040) /* PSS trim done status */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_RD_2T] Bits */\r
-#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /* RD_2T Offset */\r
-#define FLCTL_POWER_STAT_RD_2T (0x00000080) /* Indicates if Flash is being accessed in 2T mode */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE] Bits */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /* RD_MODE Offset */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_M (0x0000000f) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE0 (0x00000001) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE1 (0x00000002) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE2 (0x00000004) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE3 (0x00000008) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_0 (0x00000000) /* Normal read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_1 (0x00000001) /* Read Margin 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_2 (0x00000002) /* Read Margin 1 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_3 (0x00000003) /* Program Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_4 (0x00000004) /* Erase Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_5 (0x00000005) /* Leakage Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_9 (0x00000009) /* Read Margin 0B */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_10 (0x0000000a) /* Read Margin 1B */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFI] Bits */\r
-#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /* BUFI Offset */\r
-#define FLCTL_BANK0_RDCTL_BUFI (0x00000010) /* Enables read buffering feature for instruction fetches to this Bank */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFD] Bits */\r
-#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /* BUFD Offset */\r
-#define FLCTL_BANK0_RDCTL_BUFD (0x00000020) /* Enables read buffering feature for data reads to this Bank */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_WAIT] Bits */\r
-#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /* WAIT Offset */\r
-#define FLCTL_BANK0_RDCTL_WAIT_M (0x0000f000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT0 (0x00001000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT1 (0x00002000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT2 (0x00004000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT3 (0x00008000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT_0 (0x00000000) /* 0 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_1 (0x00001000) /* 1 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_2 (0x00002000) /* 2 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_3 (0x00003000) /* 3 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_4 (0x00004000) /* 4 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_5 (0x00005000) /* 5 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_6 (0x00006000) /* 6 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_7 (0x00007000) /* 7 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_8 (0x00008000) /* 8 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_9 (0x00009000) /* 9 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_10 (0x0000a000) /* 10 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_11 (0x0000b000) /* 11 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_12 (0x0000c000) /* 12 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_13 (0x0000d000) /* 13 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_14 (0x0000e000) /* 14 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_15 (0x0000f000) /* 15 wait states */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE_STATUS] Bits */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /* RD_MODE_STATUS Offset */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_M (0x000f0000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 (0x00010000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 (0x00020000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 (0x00040000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 (0x00080000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 (0x00000000) /* Normal read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 (0x00010000) /* Read Margin 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 (0x00020000) /* Read Margin 1 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 (0x00030000) /* Program Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 (0x00040000) /* Erase Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 (0x00050000) /* Leakage Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 (0x00090000) /* Read Margin 0B */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 (0x000a0000) /* Read Margin 1B */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE] Bits */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /* RD_MODE Offset */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_M (0x0000000f) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE0 (0x00000001) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE1 (0x00000002) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE2 (0x00000004) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE3 (0x00000008) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_0 (0x00000000) /* Normal read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_1 (0x00000001) /* Read Margin 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_2 (0x00000002) /* Read Margin 1 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_3 (0x00000003) /* Program Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_4 (0x00000004) /* Erase Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_5 (0x00000005) /* Leakage Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_9 (0x00000009) /* Read Margin 0B */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_10 (0x0000000a) /* Read Margin 1B */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFI] Bits */\r
-#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /* BUFI Offset */\r
-#define FLCTL_BANK1_RDCTL_BUFI (0x00000010) /* Enables read buffering feature for instruction fetches to this Bank */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFD] Bits */\r
-#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /* BUFD Offset */\r
-#define FLCTL_BANK1_RDCTL_BUFD (0x00000020) /* Enables read buffering feature for data reads to this Bank */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE_STATUS] Bits */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /* RD_MODE_STATUS Offset */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_M (0x000f0000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 (0x00010000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 (0x00020000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 (0x00040000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 (0x00080000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 (0x00000000) /* Normal read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 (0x00010000) /* Read Margin 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 (0x00020000) /* Read Margin 1 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 (0x00030000) /* Program Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 (0x00040000) /* Erase Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 (0x00050000) /* Leakage Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 (0x00090000) /* Read Margin 0B */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 (0x000a0000) /* Read Margin 1B */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_WAIT] Bits */\r
-#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /* WAIT Offset */\r
-#define FLCTL_BANK1_RDCTL_WAIT_M (0x0000f000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT0 (0x00001000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT1 (0x00002000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT2 (0x00004000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT3 (0x00008000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT_0 (0x00000000) /* 0 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_1 (0x00001000) /* 1 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_2 (0x00002000) /* 2 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_3 (0x00003000) /* 3 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_4 (0x00004000) /* 4 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_5 (0x00005000) /* 5 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_6 (0x00006000) /* 6 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_7 (0x00007000) /* 7 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_8 (0x00008000) /* 8 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_9 (0x00009000) /* 9 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_10 (0x0000a000) /* 10 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_11 (0x0000b000) /* 11 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_12 (0x0000c000) /* 12 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_13 (0x0000d000) /* 13 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_14 (0x0000e000) /* 14 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_15 (0x0000f000) /* 15 wait states */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_START] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /* START Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_START (0x00000001) /* Start of burst/compare operation */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_MEM_TYPE] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /* MEM_TYPE Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M (0x00000006) /* Type of memory that burst is carried out on */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 (0x00000002) /* Type of memory that burst is carried out on */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 (0x00000004) /* Type of memory that burst is carried out on */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 (0x00000000) /* Main Memory */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 (0x00000002) /* Information Memory */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 (0x00000004) /* Reserved */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 (0x00000006) /* Engineering Memory */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_STOP_FAIL] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /* STOP_FAIL Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL (0x00000008) /* Terminate burst/compare operation */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_DATA_CMP] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /* DATA_CMP Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_DATA_CMP (0x00000010) /* Data pattern used for comparison against memory read data */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_TEST_EN] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /* TEST_EN Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_TEST_EN (0x00000040) /* Enable comparison against test data compare registers */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_BRST_STAT] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /* BRST_STAT Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_M (0x00030000) /* Status of Burst/Compare operation */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 (0x00010000) /* Status of Burst/Compare operation */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 (0x00020000) /* Status of Burst/Compare operation */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 (0x00000000) /* Idle */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 (0x00010000) /* Burst/Compare START bit written, but operation pending */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 (0x00020000) /* Burst/Compare in progress */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 (0x00030000) /* Burst complete (status of completed burst remains in this state unless explicitly cleared by SW) */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CMP_ERR] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /* CMP_ERR Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_CMP_ERR (0x00040000) /* Burst/Compare Operation encountered atleast one data */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_ADDR_ERR] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /* ADDR_ERR Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR (0x00080000) /* Burst/Compare Operation was terminated due to access to */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CLR_STAT] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /* CLR_STAT Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_CLR_STAT (0x00800000) /* Clear status bits 19-16 of this register */\r
-/* FLCTL_RDBRST_STARTADDR[FLCTL_RDBRST_STARTADDR_START_ADDRESS] Bits */\r
-#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /* START_ADDRESS Offset */\r
-#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_M (0x001fffff) /* Start Address of Burst Operation */\r
-/* FLCTL_RDBRST_LEN[FLCTL_RDBRST_LEN_BURST_LENGTH] Bits */\r
-#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /* BURST_LENGTH Offset */\r
-#define FLCTL_RDBRST_LEN_BURST_LENGTH_M (0x001fffff) /* Length of Burst Operation */\r
-/* FLCTL_RDBRST_FAILADDR[FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS] Bits */\r
-#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /* FAIL_ADDRESS Offset */\r
-#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_M (0x001fffff) /* Reflects address of last failed compare */\r
-/* FLCTL_RDBRST_FAILCNT[FLCTL_RDBRST_FAILCNT_FAIL_COUNT] Bits */\r
-#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /* FAIL_COUNT Offset */\r
-#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_M (0x0001ffff) /* Number of failures encountered in burst operation */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_ENABLE] Bits */\r
-#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FLCTL_PRG_CTLSTAT_ENABLE (0x00000001) /* Master control for all word program operations */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_MODE] Bits */\r
-#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /* MODE Offset */\r
-#define FLCTL_PRG_CTLSTAT_MODE (0x00000002) /* Write mode */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PRE] Bits */\r
-#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /* VER_PRE Offset */\r
-#define FLCTL_PRG_CTLSTAT_VER_PRE (0x00000004) /* Controls automatic pre program verify operations */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PST] Bits */\r
-#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /* VER_PST Offset */\r
-#define FLCTL_PRG_CTLSTAT_VER_PST (0x00000008) /* Controls automatic post program verify operations */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_STATUS] Bits */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /* STATUS Offset */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_M (0x00030000) /* Status of program operations in the Flash memory */\r
-#define FLCTL_PRG_CTLSTAT_STATUS0 (0x00010000) /* Status of program operations in the Flash memory */\r
-#define FLCTL_PRG_CTLSTAT_STATUS1 (0x00020000) /* Status of program operations in the Flash memory */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_0 (0x00000000) /* Idle (no program operation currently active) */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_1 (0x00010000) /* Single word program operation triggered, but pending */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_2 (0x00020000) /* Single word program in progress */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_3 (0x00030000) /* Reserved (Idle) */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_BNK_ACT] Bits */\r
-#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /* BNK_ACT Offset */\r
-#define FLCTL_PRG_CTLSTAT_BNK_ACT (0x00040000) /* Bank active */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_START] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /* START Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_START (0x00000001) /* Trigger start of burst program operation */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_TYPE] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /* TYPE Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_M (0x00000006) /* Type of memory that burst program is carried out on */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE0 (0x00000002) /* Type of memory that burst program is carried out on */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE1 (0x00000004) /* Type of memory that burst program is carried out on */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 (0x00000000) /* Main Memory */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 (0x00000002) /* Information Memory */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 (0x00000004) /* Reserved */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 (0x00000006) /* Engineering Memory */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_LEN] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /* LEN Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_M (0x00000038) /* Length of burst */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN0 (0x00000008) /* Length of burst */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN1 (0x00000010) /* Length of burst */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN2 (0x00000020) /* Length of burst */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_0 (0x00000000) /* No burst operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_1 (0x00000008) /* 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_2 (0x00000010) /* 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_3 (0x00000018) /* 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_4 (0x00000020) /* 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PRE] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /* AUTO_PRE Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE (0x00000040) /* Auto-Verify operation before the Burst Program */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PST] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /* AUTO_PST Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST (0x00000080) /* Auto-Verify operation after the Burst Program */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_BURST_STATUS] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /* BURST_STATUS Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_M (0x00070000) /* Status of a Burst Operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 (0x00010000) /* Status of a Burst Operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 (0x00020000) /* Status of a Burst Operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 (0x00040000) /* Status of a Burst Operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 (0x00000000) /* Idle (Burst not active) */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 (0x00010000) /* Burst program started but pending */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 (0x00020000) /* Burst active, with 1st 128 bit word being written into Flash */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 (0x00030000) /* Burst active, with 2nd 128 bit word being written into Flash */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 (0x00040000) /* Burst active, with 3rd 128 bit word being written into Flash */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 (0x00050000) /* Burst active, with 4th 128 bit word being written into Flash */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 (0x00060000) /* Reserved (Idle) */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 (0x00070000) /* Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW) */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PRE_ERR] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /* PRE_ERR Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR (0x00080000) /* Burst Operation encountered preprogram auto-verify errors */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PST_ERR] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /* PST_ERR Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_PST_ERR (0x00100000) /* Burst Operation encountered postprogram auto-verify errors */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_ADDR_ERR] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /* ADDR_ERR Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR (0x00200000) /* Burst Operation was terminated due to attempted program of reserved memory */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_CLR_STAT] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /* CLR_STAT Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT (0x00800000) /* Clear status bits 21-16 of this register */\r
-/* FLCTL_PRGBRST_STARTADDR[FLCTL_PRGBRST_STARTADDR_START_ADDRESS] Bits */\r
-#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /* START_ADDRESS Offset */\r
-#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_M (0x003fffff) /* Start Address of Program Burst Operation */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_START] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /* START Offset */\r
-#define FLCTL_ERASE_CTLSTAT_START (0x00000001) /* Start of Erase operation */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_MODE] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /* MODE Offset */\r
-#define FLCTL_ERASE_CTLSTAT_MODE (0x00000002) /* Erase mode selected by application */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_TYPE] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /* TYPE Offset */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_M (0x0000000c) /* Type of memory that erase operation is carried out on */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE0 (0x00000004) /* Type of memory that erase operation is carried out on */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE1 (0x00000008) /* Type of memory that erase operation is carried out on */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_0 (0x00000000) /* Main Memory */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_1 (0x00000004) /* Information Memory */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_2 (0x00000008) /* Reserved */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_3 (0x0000000c) /* Engineering Memory */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_STATUS] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /* STATUS Offset */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_M (0x00030000) /* Status of erase operations in the Flash memory */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS0 (0x00010000) /* Status of erase operations in the Flash memory */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS1 (0x00020000) /* Status of erase operations in the Flash memory */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_0 (0x00000000) /* Idle (no program operation currently active) */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_1 (0x00010000) /* Erase operation triggered to START but pending */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_2 (0x00020000) /* Erase operation in progress */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_3 (0x00030000) /* Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW) */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_ADDR_ERR] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /* ADDR_ERR Offset */\r
-#define FLCTL_ERASE_CTLSTAT_ADDR_ERR (0x00040000) /* Erase Operation was terminated due to attempted erase of reserved memory address */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_CLR_STAT] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /* CLR_STAT Offset */\r
-#define FLCTL_ERASE_CTLSTAT_CLR_STAT (0x00080000) /* Clear status bits 18-16 of this register */\r
-/* FLCTL_ERASE_SECTADDR[FLCTL_ERASE_SECTADDR_SECT_ADDRESS] Bits */\r
-#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /* SECT_ADDRESS Offset */\r
-#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_M (0x003fffff) /* Address of Sector being Erased */\r
-/* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT0] Bits */\r
-#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */\r
-#define FLCTL_BANK0_INFO_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase */\r
-/* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT1] Bits */\r
-#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */\r
-#define FLCTL_BANK0_INFO_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT0] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT1] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT2] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /* PROT2 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT2 (0x00000004) /* Protects Sector 2 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT3] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /* PROT3 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT3 (0x00000008) /* Protects Sector 3 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT4] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /* PROT4 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT4 (0x00000010) /* Protects Sector 4 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT5] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /* PROT5 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT5 (0x00000020) /* Protects Sector 5 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT6] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /* PROT6 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT6 (0x00000040) /* Protects Sector 6 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT7] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /* PROT7 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT7 (0x00000080) /* Protects Sector 7 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT8] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /* PROT8 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT8 (0x00000100) /* Protects Sector 8 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT9] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /* PROT9 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT9 (0x00000200) /* Protects Sector 9 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT10] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /* PROT10 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT10 (0x00000400) /* Protects Sector 10 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT11] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /* PROT11 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT11 (0x00000800) /* Protects Sector 11 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT12] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /* PROT12 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT12 (0x00001000) /* Protects Sector 12 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT13] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /* PROT13 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT13 (0x00002000) /* Protects Sector 13 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT14] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /* PROT14 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT14 (0x00004000) /* Protects Sector 14 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT15] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /* PROT15 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT15 (0x00008000) /* Protects Sector 15 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT16] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /* PROT16 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT16 (0x00010000) /* Protects Sector 16 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT17] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /* PROT17 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT17 (0x00020000) /* Protects Sector 17 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT18] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /* PROT18 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT18 (0x00040000) /* Protects Sector 18 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT19] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /* PROT19 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT19 (0x00080000) /* Protects Sector 19 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT20] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /* PROT20 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT20 (0x00100000) /* Protects Sector 20 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT21] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /* PROT21 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT21 (0x00200000) /* Protects Sector 21 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT22] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /* PROT22 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT22 (0x00400000) /* Protects Sector 22 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT23] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /* PROT23 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT23 (0x00800000) /* Protects Sector 23 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT24] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /* PROT24 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT24 (0x01000000) /* Protects Sector 24 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT25] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /* PROT25 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT25 (0x02000000) /* Protects Sector 25 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT26] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /* PROT26 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT26 (0x04000000) /* Protects Sector 26 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT27] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /* PROT27 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT27 (0x08000000) /* Protects Sector 27 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT28] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /* PROT28 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT28 (0x10000000) /* Protects Sector 28 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT29] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /* PROT29 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT29 (0x20000000) /* Protects Sector 29 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT30] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /* PROT30 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT30 (0x40000000) /* Protects Sector 30 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT31] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /* PROT31 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT31 (0x80000000) /* Protects Sector 31 from program or erase */\r
-/* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT0] Bits */\r
-#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */\r
-#define FLCTL_BANK1_INFO_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase operations */\r
-/* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT1] Bits */\r
-#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */\r
-#define FLCTL_BANK1_INFO_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT0] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT1] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT2] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /* PROT2 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT2 (0x00000004) /* Protects Sector 2 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT3] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /* PROT3 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT3 (0x00000008) /* Protects Sector 3 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT4] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /* PROT4 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT4 (0x00000010) /* Protects Sector 4 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT5] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /* PROT5 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT5 (0x00000020) /* Protects Sector 5 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT6] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /* PROT6 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT6 (0x00000040) /* Protects Sector 6 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT7] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /* PROT7 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT7 (0x00000080) /* Protects Sector 7 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT8] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /* PROT8 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT8 (0x00000100) /* Protects Sector 8 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT9] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /* PROT9 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT9 (0x00000200) /* Protects Sector 9 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT10] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /* PROT10 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT10 (0x00000400) /* Protects Sector 10 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT11] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /* PROT11 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT11 (0x00000800) /* Protects Sector 11 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT12] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /* PROT12 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT12 (0x00001000) /* Protects Sector 12 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT13] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /* PROT13 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT13 (0x00002000) /* Protects Sector 13 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT14] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /* PROT14 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT14 (0x00004000) /* Protects Sector 14 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT15] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /* PROT15 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT15 (0x00008000) /* Protects Sector 15 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT16] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /* PROT16 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT16 (0x00010000) /* Protects Sector 16 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT17] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /* PROT17 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT17 (0x00020000) /* Protects Sector 17 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT18] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /* PROT18 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT18 (0x00040000) /* Protects Sector 18 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT19] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /* PROT19 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT19 (0x00080000) /* Protects Sector 19 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT20] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /* PROT20 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT20 (0x00100000) /* Protects Sector 20 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT21] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /* PROT21 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT21 (0x00200000) /* Protects Sector 21 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT22] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /* PROT22 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT22 (0x00400000) /* Protects Sector 22 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT23] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /* PROT23 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT23 (0x00800000) /* Protects Sector 23 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT24] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /* PROT24 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT24 (0x01000000) /* Protects Sector 24 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT25] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /* PROT25 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT25 (0x02000000) /* Protects Sector 25 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT26] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /* PROT26 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT26 (0x04000000) /* Protects Sector 26 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT27] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /* PROT27 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT27 (0x08000000) /* Protects Sector 27 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT28] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /* PROT28 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT28 (0x10000000) /* Protects Sector 28 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT29] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /* PROT29 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT29 (0x20000000) /* Protects Sector 29 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT30] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /* PROT30 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT30 (0x40000000) /* Protects Sector 30 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT31] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /* PROT31 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT31 (0x80000000) /* Protects Sector 31 from program or erase operations */\r
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_I_BMRK] Bits */\r
-#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /* I_BMRK Offset */\r
-#define FLCTL_BMRK_CTLSTAT_I_BMRK (0x00000001) /* */\r
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_D_BMRK] Bits */\r
-#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /* D_BMRK Offset */\r
-#define FLCTL_BMRK_CTLSTAT_D_BMRK (0x00000002) /* */\r
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_EN] Bits */\r
-#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /* CMP_EN Offset */\r
-#define FLCTL_BMRK_CTLSTAT_CMP_EN (0x00000004) /* */\r
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_SEL] Bits */\r
-#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /* CMP_SEL Offset */\r
-#define FLCTL_BMRK_CTLSTAT_CMP_SEL (0x00000008) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_RDBRST] Bits */\r
-#define FLCTL_IFG_RDBRST_OFS ( 0) /* RDBRST Offset */\r
-#define FLCTL_IFG_RDBRST (0x00000001) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_AVPRE] Bits */\r
-#define FLCTL_IFG_AVPRE_OFS ( 1) /* AVPRE Offset */\r
-#define FLCTL_IFG_AVPRE (0x00000002) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_AVPST] Bits */\r
-#define FLCTL_IFG_AVPST_OFS ( 2) /* AVPST Offset */\r
-#define FLCTL_IFG_AVPST (0x00000004) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_PRG] Bits */\r
-#define FLCTL_IFG_PRG_OFS ( 3) /* PRG Offset */\r
-#define FLCTL_IFG_PRG (0x00000008) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_PRGB] Bits */\r
-#define FLCTL_IFG_PRGB_OFS ( 4) /* PRGB Offset */\r
-#define FLCTL_IFG_PRGB (0x00000010) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_ERASE] Bits */\r
-#define FLCTL_IFG_ERASE_OFS ( 5) /* ERASE Offset */\r
-#define FLCTL_IFG_ERASE (0x00000020) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_BMRK] Bits */\r
-#define FLCTL_IFG_BMRK_OFS ( 8) /* BMRK Offset */\r
-#define FLCTL_IFG_BMRK (0x00000100) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_PRG_ERR] Bits */\r
-#define FLCTL_IFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */\r
-#define FLCTL_IFG_PRG_ERR (0x00000200) /* */\r
-/* FLCTL_IE[FLCTL_IE_RDBRST] Bits */\r
-#define FLCTL_IE_RDBRST_OFS ( 0) /* RDBRST Offset */\r
-#define FLCTL_IE_RDBRST (0x00000001) /* */\r
-/* FLCTL_IE[FLCTL_IE_AVPRE] Bits */\r
-#define FLCTL_IE_AVPRE_OFS ( 1) /* AVPRE Offset */\r
-#define FLCTL_IE_AVPRE (0x00000002) /* */\r
-/* FLCTL_IE[FLCTL_IE_AVPST] Bits */\r
-#define FLCTL_IE_AVPST_OFS ( 2) /* AVPST Offset */\r
-#define FLCTL_IE_AVPST (0x00000004) /* */\r
-/* FLCTL_IE[FLCTL_IE_PRG] Bits */\r
-#define FLCTL_IE_PRG_OFS ( 3) /* PRG Offset */\r
-#define FLCTL_IE_PRG (0x00000008) /* */\r
-/* FLCTL_IE[FLCTL_IE_PRGB] Bits */\r
-#define FLCTL_IE_PRGB_OFS ( 4) /* PRGB Offset */\r
-#define FLCTL_IE_PRGB (0x00000010) /* */\r
-/* FLCTL_IE[FLCTL_IE_ERASE] Bits */\r
-#define FLCTL_IE_ERASE_OFS ( 5) /* ERASE Offset */\r
-#define FLCTL_IE_ERASE (0x00000020) /* */\r
-/* FLCTL_IE[FLCTL_IE_BMRK] Bits */\r
-#define FLCTL_IE_BMRK_OFS ( 8) /* BMRK Offset */\r
-#define FLCTL_IE_BMRK (0x00000100) /* */\r
-/* FLCTL_IE[FLCTL_IE_PRG_ERR] Bits */\r
-#define FLCTL_IE_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */\r
-#define FLCTL_IE_PRG_ERR (0x00000200) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_RDBRST] Bits */\r
-#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /* RDBRST Offset */\r
-#define FLCTL_CLRIFG_RDBRST (0x00000001) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPRE] Bits */\r
-#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /* AVPRE Offset */\r
-#define FLCTL_CLRIFG_AVPRE (0x00000002) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPST] Bits */\r
-#define FLCTL_CLRIFG_AVPST_OFS ( 2) /* AVPST Offset */\r
-#define FLCTL_CLRIFG_AVPST (0x00000004) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG] Bits */\r
-#define FLCTL_CLRIFG_PRG_OFS ( 3) /* PRG Offset */\r
-#define FLCTL_CLRIFG_PRG (0x00000008) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRGB] Bits */\r
-#define FLCTL_CLRIFG_PRGB_OFS ( 4) /* PRGB Offset */\r
-#define FLCTL_CLRIFG_PRGB (0x00000010) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_ERASE] Bits */\r
-#define FLCTL_CLRIFG_ERASE_OFS ( 5) /* ERASE Offset */\r
-#define FLCTL_CLRIFG_ERASE (0x00000020) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_BMRK] Bits */\r
-#define FLCTL_CLRIFG_BMRK_OFS ( 8) /* BMRK Offset */\r
-#define FLCTL_CLRIFG_BMRK (0x00000100) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG_ERR] Bits */\r
-#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */\r
-#define FLCTL_CLRIFG_PRG_ERR (0x00000200) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_RDBRST] Bits */\r
-#define FLCTL_SETIFG_RDBRST_OFS ( 0) /* RDBRST Offset */\r
-#define FLCTL_SETIFG_RDBRST (0x00000001) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_AVPRE] Bits */\r
-#define FLCTL_SETIFG_AVPRE_OFS ( 1) /* AVPRE Offset */\r
-#define FLCTL_SETIFG_AVPRE (0x00000002) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_AVPST] Bits */\r
-#define FLCTL_SETIFG_AVPST_OFS ( 2) /* AVPST Offset */\r
-#define FLCTL_SETIFG_AVPST (0x00000004) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_PRG] Bits */\r
-#define FLCTL_SETIFG_PRG_OFS ( 3) /* PRG Offset */\r
-#define FLCTL_SETIFG_PRG (0x00000008) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_PRGB] Bits */\r
-#define FLCTL_SETIFG_PRGB_OFS ( 4) /* PRGB Offset */\r
-#define FLCTL_SETIFG_PRGB (0x00000010) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_ERASE] Bits */\r
-#define FLCTL_SETIFG_ERASE_OFS ( 5) /* ERASE Offset */\r
-#define FLCTL_SETIFG_ERASE (0x00000020) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_BMRK] Bits */\r
-#define FLCTL_SETIFG_BMRK_OFS ( 8) /* BMRK Offset */\r
-#define FLCTL_SETIFG_BMRK (0x00000100) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_PRG_ERR] Bits */\r
-#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */\r
-#define FLCTL_SETIFG_PRG_ERR (0x00000200) /* */\r
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP] Bits */\r
-#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_READ_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_HOLD] Bits */\r
-#define FLCTL_READ_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */\r
-#define FLCTL_READ_TIMCTL_HOLD_M (0x00000f00) /* */\r
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_IREF_BOOST1] Bits */\r
-#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /* IREF_BOOST1 Offset */\r
-#define FLCTL_READ_TIMCTL_IREF_BOOST1_M (0x0000f000) /* */\r
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP_LONG] Bits */\r
-#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /* SETUP_LONG Offset */\r
-#define FLCTL_READ_TIMCTL_SETUP_LONG_M (0x00ff0000) /* */\r
-/* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_SETUP] Bits */\r
-#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_READMARGIN_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_HOLD] Bits */\r
-#define FLCTL_READMARGIN_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */\r
-#define FLCTL_READMARGIN_TIMCTL_HOLD_M (0x00000f00) /* */\r
-/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_SETUP] Bits */\r
-#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_PRGVER_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_ACTIVE] Bits */\r
-#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */\r
-#define FLCTL_PRGVER_TIMCTL_ACTIVE_M (0x00000f00) /* */\r
-/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_HOLD] Bits */\r
-#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /* HOLD Offset */\r
-#define FLCTL_PRGVER_TIMCTL_HOLD_M (0x0000f000) /* */\r
-/* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_SETUP] Bits */\r
-#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_ERSVER_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_HOLD] Bits */\r
-#define FLCTL_ERSVER_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */\r
-#define FLCTL_ERSVER_TIMCTL_HOLD_M (0x00000f00) /* */\r
-/* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_SETUP] Bits */\r
-#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_LKGVER_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_HOLD] Bits */\r
-#define FLCTL_LKGVER_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */\r
-#define FLCTL_LKGVER_TIMCTL_HOLD_M (0x00000f00) /* */\r
-/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_SETUP] Bits */\r
-#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_PROGRAM_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_ACTIVE] Bits */\r
-#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */\r
-#define FLCTL_PROGRAM_TIMCTL_ACTIVE_M (0x0fffff00) /* */\r
-/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_HOLD] Bits */\r
-#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /* HOLD Offset */\r
-#define FLCTL_PROGRAM_TIMCTL_HOLD_M (0xf0000000) /* */\r
-/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_SETUP] Bits */\r
-#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_ERASE_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_ACTIVE] Bits */\r
-#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */\r
-#define FLCTL_ERASE_TIMCTL_ACTIVE_M (0x0fffff00) /* */\r
-/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_HOLD] Bits */\r
-#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /* HOLD Offset */\r
-#define FLCTL_ERASE_TIMCTL_HOLD_M (0xf0000000) /* */\r
-/* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE] Bits */\r
-#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /* BOOST_ACTIVE Offset */\r
-#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_M (0x000000ff) /* */\r
-/* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_HOLD] Bits */\r
-#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /* BOOST_HOLD Offset */\r
-#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_M (0x0000ff00) /* */\r
-/* FLCTL_BURSTPRG_TIMCTL[FLCTL_BURSTPRG_TIMCTL_ACTIVE] Bits */\r
-#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */\r
-#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_M (0x0fffff00) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// FPB Bits\r
-//*****************************************************************************\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_ENABLE] Bits */\r
-#define FPB_FP_CTRL_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_CTRL_ENABLE (0x00000001) /* */\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_KEY] Bits */\r
-#define FPB_FP_CTRL_KEY_OFS ( 1) /* KEY Offset */\r
-#define FPB_FP_CTRL_KEY (0x00000002) /* */\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE1] Bits */\r
-#define FPB_FP_CTRL_NUM_CODE1_OFS ( 4) /* NUM_CODE1 Offset */\r
-#define FPB_FP_CTRL_NUM_CODE1_M (0x000000f0) /* */\r
-#define FPB_FP_CTRL_NUM_CODE10 (0x00000010) /* */\r
-#define FPB_FP_CTRL_NUM_CODE11 (0x00000020) /* */\r
-#define FPB_FP_CTRL_NUM_CODE12 (0x00000040) /* */\r
-#define FPB_FP_CTRL_NUM_CODE13 (0x00000080) /* */\r
-#define FPB_FP_CTRL_NUM_CODE1_0 (0x00000000) /* no code slots */\r
-#define FPB_FP_CTRL_NUM_CODE1_2 (0x00000020) /* two code slots */\r
-#define FPB_FP_CTRL_NUM_CODE1_6 (0x00000060) /* six code slots */\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_LIT] Bits */\r
-#define FPB_FP_CTRL_NUM_LIT_OFS ( 8) /* NUM_LIT Offset */\r
-#define FPB_FP_CTRL_NUM_LIT_M (0x00000f00) /* */\r
-#define FPB_FP_CTRL_NUM_LIT0 (0x00000100) /* */\r
-#define FPB_FP_CTRL_NUM_LIT1 (0x00000200) /* */\r
-#define FPB_FP_CTRL_NUM_LIT2 (0x00000400) /* */\r
-#define FPB_FP_CTRL_NUM_LIT3 (0x00000800) /* */\r
-#define FPB_FP_CTRL_NUM_LIT_0 (0x00000000) /* no literal slots */\r
-#define FPB_FP_CTRL_NUM_LIT_2 (0x00000200) /* two literal slots */\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE2] Bits */\r
-#define FPB_FP_CTRL_NUM_CODE2_OFS (12) /* NUM_CODE2 Offset */\r
-#define FPB_FP_CTRL_NUM_CODE2_M (0x00003000) /* */\r
-/* FPB_FP_REMAP[FPB_FP_REMAP_REMAP] Bits */\r
-#define FPB_FP_REMAP_REMAP_OFS ( 5) /* REMAP Offset */\r
-#define FPB_FP_REMAP_REMAP_M (0x1fffffe0) /* */\r
-/* FPB_FP_COMP0[FPB_FP_COMP0_ENABLE] Bits */\r
-#define FPB_FP_COMP0_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP0_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP0[FPB_FP_COMP0_COMP] Bits */\r
-#define FPB_FP_COMP0_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP0_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP0[FPB_FP_COMP0_REPLACE] Bits */\r
-#define FPB_FP_COMP0_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP0_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP0_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP0_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP0_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP0_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP0_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP0_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP1[FPB_FP_COMP1_ENABLE] Bits */\r
-#define FPB_FP_COMP1_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP1_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP1[FPB_FP_COMP1_COMP] Bits */\r
-#define FPB_FP_COMP1_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP1_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP1[FPB_FP_COMP1_REPLACE] Bits */\r
-#define FPB_FP_COMP1_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP1_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP1_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP1_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP1_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP1_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP1_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP1_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP2[FPB_FP_COMP2_ENABLE] Bits */\r
-#define FPB_FP_COMP2_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP2_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP2[FPB_FP_COMP2_COMP] Bits */\r
-#define FPB_FP_COMP2_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP2_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP2[FPB_FP_COMP2_REPLACE] Bits */\r
-#define FPB_FP_COMP2_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP2_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP2_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP2_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP2_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP2_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP2_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP2_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP3[FPB_FP_COMP3_ENABLE] Bits */\r
-#define FPB_FP_COMP3_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP3_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP3[FPB_FP_COMP3_COMP] Bits */\r
-#define FPB_FP_COMP3_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP3_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP3[FPB_FP_COMP3_REPLACE] Bits */\r
-#define FPB_FP_COMP3_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP3_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP3_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP3_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP3_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP3_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP3_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP3_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP4[FPB_FP_COMP4_ENABLE] Bits */\r
-#define FPB_FP_COMP4_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP4_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP4[FPB_FP_COMP4_COMP] Bits */\r
-#define FPB_FP_COMP4_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP4_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP4[FPB_FP_COMP4_REPLACE] Bits */\r
-#define FPB_FP_COMP4_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP4_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP4_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP4_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP4_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP4_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP4_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP4_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP5[FPB_FP_COMP5_ENABLE] Bits */\r
-#define FPB_FP_COMP5_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP5_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP5[FPB_FP_COMP5_COMP] Bits */\r
-#define FPB_FP_COMP5_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP5_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP5[FPB_FP_COMP5_REPLACE] Bits */\r
-#define FPB_FP_COMP5_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP5_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP5_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP5_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP5_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP5_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP5_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP5_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP6[FPB_FP_COMP6_ENABLE] Bits */\r
-#define FPB_FP_COMP6_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP6_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP6[FPB_FP_COMP6_COMP] Bits */\r
-#define FPB_FP_COMP6_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP6_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP6[FPB_FP_COMP6_REPLACE] Bits */\r
-#define FPB_FP_COMP6_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP6_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP6_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP6_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP6_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP6_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP6_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP6_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP7[FPB_FP_COMP7_ENABLE] Bits */\r
-#define FPB_FP_COMP7_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP7_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP7[FPB_FP_COMP7_COMP] Bits */\r
-#define FPB_FP_COMP7_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP7_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP7[FPB_FP_COMP7_REPLACE] Bits */\r
-#define FPB_FP_COMP7_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP7_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP7_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP7_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP7_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP7_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP7_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP7_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-\r
-\r
-//*****************************************************************************\r
-// FPU Bits\r
-//*****************************************************************************\r
-/* FPU_FPCCR[FPU_FPCCR_ASPEN] Bits */\r
-#define FPU_FPCCR_ASPEN_OFS (31) /* ASPEN Offset */\r
-#define FPU_FPCCR_ASPEN (0x80000000) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_LSPEN] Bits */\r
-#define FPU_FPCCR_LSPEN_OFS (30) /* LSPEN Offset */\r
-#define FPU_FPCCR_LSPEN (0x40000000) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_MONRDY] Bits */\r
-#define FPU_FPCCR_MONRDY_OFS ( 8) /* MONRDY Offset */\r
-#define FPU_FPCCR_MONRDY (0x00000100) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_BFRDY] Bits */\r
-#define FPU_FPCCR_BFRDY_OFS ( 6) /* BFRDY Offset */\r
-#define FPU_FPCCR_BFRDY (0x00000040) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_MMRDY] Bits */\r
-#define FPU_FPCCR_MMRDY_OFS ( 5) /* MMRDY Offset */\r
-#define FPU_FPCCR_MMRDY (0x00000020) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_HFRDY] Bits */\r
-#define FPU_FPCCR_HFRDY_OFS ( 4) /* HFRDY Offset */\r
-#define FPU_FPCCR_HFRDY (0x00000010) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_THREAD] Bits */\r
-#define FPU_FPCCR_THREAD_OFS ( 3) /* THREAD Offset */\r
-#define FPU_FPCCR_THREAD (0x00000008) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_USER] Bits */\r
-#define FPU_FPCCR_USER_OFS ( 1) /* USER Offset */\r
-#define FPU_FPCCR_USER (0x00000002) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_LSPACT] Bits */\r
-#define FPU_FPCCR_LSPACT_OFS ( 0) /* LSPACT Offset */\r
-#define FPU_FPCCR_LSPACT (0x00000001) /* */\r
-/* FPU_FPCAR[FPU_FPCAR_ADDRESS] Bits */\r
-#define FPU_FPCAR_ADDRESS_OFS ( 2) /* ADDRESS Offset */\r
-#define FPU_FPCAR_ADDRESS_M (0x7ffffffc) /* */\r
-/* FPU_FPDSCR[FPU_FPDSCR_AHP] Bits */\r
-#define FPU_FPDSCR_AHP_OFS (26) /* AHP Offset */\r
-#define FPU_FPDSCR_AHP (0x04000000) /* */\r
-/* FPU_FPDSCR[FPU_FPDSCR_DN] Bits */\r
-#define FPU_FPDSCR_DN_OFS (25) /* DN Offset */\r
-#define FPU_FPDSCR_DN (0x02000000) /* */\r
-/* FPU_FPDSCR[FPU_FPDSCR_FZ] Bits */\r
-#define FPU_FPDSCR_FZ_OFS (24) /* FZ Offset */\r
-#define FPU_FPDSCR_FZ (0x01000000) /* */\r
-/* FPU_FPDSCR[FPU_FPDSCR_RMODE] Bits */\r
-#define FPU_FPDSCR_RMODE_OFS (22) /* RMODE Offset */\r
-#define FPU_FPDSCR_RMODE_M (0x00c00000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_FP_ROUNDING_MODES] Bits */\r
-#define FPU_MVFR0_FP_ROUNDING_MODES_OFS (28) /* FP_ROUNDING_MODES Offset */\r
-#define FPU_MVFR0_FP_ROUNDING_MODES_M (0xf0000000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_SHORT_VECTORS] Bits */\r
-#define FPU_MVFR0_SHORT_VECTORS_OFS (24) /* SHORT_VECTORS Offset */\r
-#define FPU_MVFR0_SHORT_VECTORS_M (0x0f000000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_SQUARE_ROOT] Bits */\r
-#define FPU_MVFR0_SQUARE_ROOT_OFS (20) /* SQUARE_ROOT Offset */\r
-#define FPU_MVFR0_SQUARE_ROOT_M (0x00f00000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_DIVIDE] Bits */\r
-#define FPU_MVFR0_DIVIDE_OFS (16) /* DIVIDE Offset */\r
-#define FPU_MVFR0_DIVIDE_M (0x000f0000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_FP_ECEPTION_TRAPPING] Bits */\r
-#define FPU_MVFR0_FP_ECEPTION_TRAPPING_OFS (12) /* FP_EXCEPTION_TRAPPING Offset */\r
-#define FPU_MVFR0_FP_ECEPTION_TRAPPING_M (0x0000f000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_DOUBLE_PRECISION] Bits */\r
-#define FPU_MVFR0_DOUBLE_PRECISION_OFS ( 8) /* DOUBLE_PRECISION Offset */\r
-#define FPU_MVFR0_DOUBLE_PRECISION_M (0x00000f00) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_SINGLE_PRECISION] Bits */\r
-#define FPU_MVFR0_SINGLE_PRECISION_OFS ( 4) /* SINGLE_PRECISION Offset */\r
-#define FPU_MVFR0_SINGLE_PRECISION_M (0x000000f0) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_A_SIMD_REGISTERS] Bits */\r
-#define FPU_MVFR0_A_SIMD_REGISTERS_OFS ( 0) /* A_SIMD_REGISTERS Offset */\r
-#define FPU_MVFR0_A_SIMD_REGISTERS_M (0x0000000f) /* */\r
-/* FPU_MVFR1[FPU_MVFR1_FP_FUSED_MAC] Bits */\r
-#define FPU_MVFR1_FP_FUSED_MAC_OFS (28) /* FP_FUSED_MAC Offset */\r
-#define FPU_MVFR1_FP_FUSED_MAC_M (0xf0000000) /* */\r
-/* FPU_MVFR1[FPU_MVFR1_FP_HPFP] Bits */\r
-#define FPU_MVFR1_FP_HPFP_OFS (24) /* FP_HPFP Offset */\r
-#define FPU_MVFR1_FP_HPFP_M (0x0f000000) /* */\r
-/* FPU_MVFR1[FPU_MVFR1_D_NAN_MODE] Bits */\r
-#define FPU_MVFR1_D_NAN_MODE_OFS ( 4) /* D_NAN_MODE Offset */\r
-#define FPU_MVFR1_D_NAN_MODE_M (0x000000f0) /* */\r
-/* FPU_MVFR1[FPU_MVFR1_FTZ_MODE] Bits */\r
-#define FPU_MVFR1_FTZ_MODE_OFS ( 0) /* FTZ_MODE Offset */\r
-#define FPU_MVFR1_FTZ_MODE_M (0x0000000f) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// ITM Bits\r
-//*****************************************************************************\r
-/* ITM_TPR[ITM_TPR_PRIVMASK] Bits */\r
-#define ITM_TPR_PRIVMASK_OFS ( 0) /* PRIVMASK Offset */\r
-#define ITM_TPR_PRIVMASK_M (0x0000000f) /* */\r
-/* ITM_TCR[ITM_TCR_ITMENA] Bits */\r
-#define ITM_TCR_ITMENA_OFS ( 0) /* ITMENA Offset */\r
-#define ITM_TCR_ITMENA (0x00000001) /* */\r
-/* ITM_TCR[ITM_TCR_TSENA] Bits */\r
-#define ITM_TCR_TSENA_OFS ( 1) /* TSENA Offset */\r
-#define ITM_TCR_TSENA (0x00000002) /* */\r
-/* ITM_TCR[ITM_TCR_SYNCENA] Bits */\r
-#define ITM_TCR_SYNCENA_OFS ( 2) /* SYNCENA Offset */\r
-#define ITM_TCR_SYNCENA (0x00000004) /* */\r
-/* ITM_TCR[ITM_TCR_DWTENA] Bits */\r
-#define ITM_TCR_DWTENA_OFS ( 3) /* DWTENA Offset */\r
-#define ITM_TCR_DWTENA (0x00000008) /* */\r
-/* ITM_TCR[ITM_TCR_SWOENA] Bits */\r
-#define ITM_TCR_SWOENA_OFS ( 4) /* SWOENA Offset */\r
-#define ITM_TCR_SWOENA (0x00000010) /* */\r
-/* ITM_TCR[ITM_TCR_TSPRESCALE] Bits */\r
-#define ITM_TCR_TSPRESCALE_OFS ( 8) /* TSPRESCALE Offset */\r
-#define ITM_TCR_TSPRESCALE_M (0x00000300) /* */\r
-#define ITM_TCR_TSPRESCALE0 (0x00000100) /* */\r
-#define ITM_TCR_TSPRESCALE1 (0x00000200) /* */\r
-#define ITM_TCR_TSPRESCALE_0 (0x00000000) /* no prescaling */\r
-#define ITM_TCR_TSPRESCALE_1 (0x00000100) /* divide by 4 */\r
-#define ITM_TCR_TSPRESCALE_2 (0x00000200) /* divide by 16 */\r
-#define ITM_TCR_TSPRESCALE_3 (0x00000300) /* divide by 64 */\r
-/* ITM_TCR[ITM_TCR_ATBID] Bits */\r
-#define ITM_TCR_ATBID_OFS (16) /* ATBID Offset */\r
-#define ITM_TCR_ATBID_M (0x007f0000) /* */\r
-/* ITM_TCR[ITM_TCR_BUSY] Bits */\r
-#define ITM_TCR_BUSY_OFS (23) /* BUSY Offset */\r
-#define ITM_TCR_BUSY (0x00800000) /* */\r
-/* ITM_IWR[ITM_IWR_ATVALIDM] Bits */\r
-#define ITM_IWR_ATVALIDM_OFS ( 0) /* ATVALIDM Offset */\r
-#define ITM_IWR_ATVALIDM (0x00000001) /* */\r
-/* ITM_IMCR[ITM_IMCR_INTEGRATION] Bits */\r
-#define ITM_IMCR_INTEGRATION_OFS ( 0) /* INTEGRATION Offset */\r
-#define ITM_IMCR_INTEGRATION (0x00000001) /* */\r
-/* ITM_LSR[ITM_LSR_PRESENT] Bits */\r
-#define ITM_LSR_PRESENT_OFS ( 0) /* PRESENT Offset */\r
-#define ITM_LSR_PRESENT (0x00000001) /* */\r
-/* ITM_LSR[ITM_LSR_ACCESS] Bits */\r
-#define ITM_LSR_ACCESS_OFS ( 1) /* ACCESS Offset */\r
-#define ITM_LSR_ACCESS (0x00000002) /* */\r
-/* ITM_LSR[ITM_LSR_BYTEACC] Bits */\r
-#define ITM_LSR_BYTEACC_OFS ( 2) /* BYTEACC Offset */\r
-#define ITM_LSR_BYTEACC (0x00000004) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// MPU Bits\r
-//*****************************************************************************\r
-/* MPU_TYPE[MPU_TYPE_SEPARATE] Bits */\r
-#define MPU_TYPE_SEPARATE_OFS ( 0) /* SEPARATE Offset */\r
-#define MPU_TYPE_SEPARATE (0x00000001) /* */\r
-/* MPU_TYPE[MPU_TYPE_DREGION] Bits */\r
-#define MPU_TYPE_DREGION_OFS ( 8) /* DREGION Offset */\r
-#define MPU_TYPE_DREGION_M (0x0000ff00) /* */\r
-/* MPU_TYPE[MPU_TYPE_IREGION] Bits */\r
-#define MPU_TYPE_IREGION_OFS (16) /* IREGION Offset */\r
-#define MPU_TYPE_IREGION_M (0x00ff0000) /* */\r
-/* MPU_CTRL[MPU_CTRL_ENABLE] Bits */\r
-#define MPU_CTRL_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define MPU_CTRL_ENABLE (0x00000001) /* */\r
-/* MPU_CTRL[MPU_CTRL_HFNMIENA] Bits */\r
-#define MPU_CTRL_HFNMIENA_OFS ( 1) /* HFNMIENA Offset */\r
-#define MPU_CTRL_HFNMIENA (0x00000002) /* */\r
-/* MPU_CTRL[MPU_CTRL_PRIVDEFENA] Bits */\r
-#define MPU_CTRL_PRIVDEFENA_OFS ( 2) /* PRIVDEFENA Offset */\r
-#define MPU_CTRL_PRIVDEFENA (0x00000004) /* */\r
-/* MPU_RNR[MPU_RNR_REGION] Bits */\r
-#define MPU_RNR_REGION_OFS ( 0) /* REGION Offset */\r
-#define MPU_RNR_REGION_M (0x000000ff) /* */\r
-/* MPU_RBAR[MPU_RBAR_REGION] Bits */\r
-#define MPU_RBAR_REGION_OFS ( 0) /* REGION Offset */\r
-#define MPU_RBAR_REGION_M (0x0000000f) /* */\r
-/* MPU_RBAR[MPU_RBAR_VALID] Bits */\r
-#define MPU_RBAR_VALID_OFS ( 4) /* VALID Offset */\r
-#define MPU_RBAR_VALID (0x00000010) /* */\r
-/* MPU_RBAR[MPU_RBAR_ADDR] Bits */\r
-#define MPU_RBAR_ADDR_OFS ( 5) /* ADDR Offset */\r
-#define MPU_RBAR_ADDR_M (0xffffffe0) /* */\r
-/* MPU_RASR[MPU_RASR_ENABLE] Bits */\r
-#define MPU_RASR_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define MPU_RASR_ENABLE (0x00000001) /* */\r
-/* MPU_RASR[MPU_RASR_SIZE] Bits */\r
-#define MPU_RASR_SIZE_OFS ( 1) /* SIZE Offset */\r
-#define MPU_RASR_SIZE_M (0x0000003e) /* */\r
-#define MPU_RASR_SIZE0 (0x00000002) /* */\r
-#define MPU_RASR_SIZE1 (0x00000004) /* */\r
-#define MPU_RASR_SIZE2 (0x00000008) /* */\r
-#define MPU_RASR_SIZE3 (0x00000010) /* */\r
-#define MPU_RASR_SIZE4 (0x00000020) /* */\r
-#define MPU_RASR_SIZE_0 (0x00000000) /* 4KB */\r
-#define MPU_RASR_SIZE_1 (0x00000002) /* 256MB */\r
-#define MPU_RASR_SIZE_4 (0x00000008) /* 32B */\r
-#define MPU_RASR_SIZE_5 (0x0000000a) /* 64B */\r
-#define MPU_RASR_SIZE_6 (0x0000000c) /* 128B */\r
-#define MPU_RASR_SIZE_7 (0x0000000e) /* 256B */\r
-#define MPU_RASR_SIZE_8 (0x00000010) /* 512B */\r
-#define MPU_RASR_SIZE_9 (0x00000012) /* 1KB */\r
-#define MPU_RASR_SIZE_10 (0x00000014) /* 2KB */\r
-#define MPU_RASR_SIZE_12 (0x00000018) /* 8KB */\r
-#define MPU_RASR_SIZE_13 (0x0000001a) /* 16KB */\r
-#define MPU_RASR_SIZE_14 (0x0000001c) /* 32KB */\r
-#define MPU_RASR_SIZE_15 (0x0000001e) /* 64KB */\r
-#define MPU_RASR_SIZE_16 (0x00000020) /* 128KB */\r
-#define MPU_RASR_SIZE_17 (0x00000022) /* 256KB */\r
-#define MPU_RASR_SIZE_18 (0x00000024) /* 512KB */\r
-#define MPU_RASR_SIZE_19 (0x00000026) /* 1MB */\r
-#define MPU_RASR_SIZE_20 (0x00000028) /* 2MB */\r
-#define MPU_RASR_SIZE_21 (0x0000002a) /* 4MB */\r
-#define MPU_RASR_SIZE_22 (0x0000002c) /* 8MB */\r
-#define MPU_RASR_SIZE_23 (0x0000002e) /* 16MB */\r
-#define MPU_RASR_SIZE_24 (0x00000030) /* 32MB */\r
-#define MPU_RASR_SIZE_25 (0x00000032) /* 64MB */\r
-#define MPU_RASR_SIZE_26 (0x00000034) /* 128MB */\r
-#define MPU_RASR_SIZE_28 (0x00000038) /* 512MB */\r
-#define MPU_RASR_SIZE_29 (0x0000003a) /* 1GB */\r
-#define MPU_RASR_SIZE_30 (0x0000003c) /* 2GB */\r
-#define MPU_RASR_SIZE_31 (0x0000003e) /* 4GB */\r
-/* MPU_RASR[MPU_RASR_SRD] Bits */\r
-#define MPU_RASR_SRD_OFS ( 8) /* SRD Offset */\r
-#define MPU_RASR_SRD_M (0x0000ff00) /* */\r
-/* MPU_RASR[MPU_RASR_B] Bits */\r
-#define MPU_RASR_B_OFS (16) /* B Offset */\r
-#define MPU_RASR_B (0x00010000) /* */\r
-/* MPU_RASR[MPU_RASR_C] Bits */\r
-#define MPU_RASR_C_OFS (17) /* C Offset */\r
-#define MPU_RASR_C (0x00020000) /* */\r
-/* MPU_RASR[MPU_RASR_S] Bits */\r
-#define MPU_RASR_S_OFS (18) /* S Offset */\r
-#define MPU_RASR_S (0x00040000) /* */\r
-/* MPU_RASR[MPU_RASR_TEX] Bits */\r
-#define MPU_RASR_TEX_OFS (19) /* TEX Offset */\r
-#define MPU_RASR_TEX_M (0x00380000) /* */\r
-/* MPU_RASR[MPU_RASR_AP] Bits */\r
-#define MPU_RASR_AP_OFS (24) /* AP Offset */\r
-#define MPU_RASR_AP_M (0x07000000) /* */\r
-#define MPU_RASR_AP0 (0x01000000) /* */\r
-#define MPU_RASR_AP1 (0x02000000) /* */\r
-#define MPU_RASR_AP2 (0x04000000) /* */\r
-#define MPU_RASR_AP_0 (0x00000000) /* Priviliged permissions: No access. User permissions: No access. */\r
-#define MPU_RASR_AP_1 (0x01000000) /* Priviliged permissions: Read-write. User permissions: No access. */\r
-#define MPU_RASR_AP_2 (0x02000000) /* Priviliged permissions: Read-write. User permissions: Read-only. */\r
-#define MPU_RASR_AP_3 (0x03000000) /* Priviliged permissions: Read-write. User permissions: Read-write. */\r
-#define MPU_RASR_AP_5 (0x05000000) /* Priviliged permissions: Read-only. User permissions: No access. */\r
-#define MPU_RASR_AP_6 (0x06000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */\r
-#define MPU_RASR_AP_7 (0x07000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */\r
-/* MPU_RASR[MPU_RASR_XN] Bits */\r
-#define MPU_RASR_XN_OFS (28) /* XN Offset */\r
-#define MPU_RASR_XN (0x10000000) /* */\r
+#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /* Destination Address Increment */\r
+#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /* Byte */\r
+#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /* Half-word */\r
+#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /* Word */\r
+#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /* No increment */\r
+#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /* Destination Data Size */\r
+#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /* Byte */\r
+#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /* Half-word */\r
+#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /* Word */\r
+#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /* Source Address Increment */\r
+#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /* Byte */\r
+#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /* Half-word */\r
+#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /* Word */\r
+#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /* No increment */\r
+#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /* Source Data Size */\r
+#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /* Byte */\r
+#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /* Half-word */\r
+#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /* Word */\r
+#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /* Arbitration Size */\r
+#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /* 1 Transfer */\r
+#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /* 2 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /* 4 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /* 8 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /* 16 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /* 32 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /* 64 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /* 128 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /* 256 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /* 512 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /* 1024 Transfers */\r
+#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /* Transfer Size (minus 1) */\r
+#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /* Next Useburst */\r
+#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /* uDMA Transfer Mode */\r
+#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /* Stop */\r
+#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /* Basic */\r
+#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /* Auto-Request */\r
+#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /* Ping-Pong */\r
+#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /* Memory Scatter-Gather */\r
+#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /* Alternate Memory Scatter-Gather */\r
+#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /* Peripheral Scatter-Gather */\r
+#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /* Alternate Peripheral Scatter-Gather */\r
+\r
+#define UDMA_CHCTL_XFERSIZE_S ( 4)\r
+\r
+\r
+/******************************************************************************\r
+* DWT Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* EUSCI_A Bits\r
+******************************************************************************/\r
+/* EUSCI_A_CTLW0[SWRST] Bits */\r
+#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /**< UCSWRST Bit Offset */\r
+#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /**< Software reset enable */\r
+/* EUSCI_A_CTLW0[TXBRK] Bits */\r
+#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /**< UCTXBRK Bit Offset */\r
+#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /**< Transmit break */\r
+/* EUSCI_A_CTLW0[TXADDR] Bits */\r
+#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /**< UCTXADDR Bit Offset */\r
+#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /**< Transmit address */\r
+/* EUSCI_A_CTLW0[DORM] Bits */\r
+#define EUSCI_A_CTLW0_DORM_OFS ( 3) /**< UCDORM Bit Offset */\r
+#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /**< Dormant */\r
+/* EUSCI_A_CTLW0[BRKIE] Bits */\r
+#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /**< UCBRKIE Bit Offset */\r
+#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /**< Receive break character interrupt enable */\r
+/* EUSCI_A_CTLW0[RXEIE] Bits */\r
+#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /**< UCRXEIE Bit Offset */\r
+#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /**< Receive erroneous-character interrupt enable */\r
+/* EUSCI_A_CTLW0[SSEL] Bits */\r
+#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /**< UCSSEL Bit Offset */\r
+#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /**< UCSSEL Bit Mask */\r
+#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /**< SSEL Bit 0 */\r
+#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /**< SSEL Bit 1 */\r
+#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /**< UCLK */\r
+#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /**< ACLK */\r
+#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /**< SMCLK */\r
+#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /**< UCLK */\r
+#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /**< ACLK */\r
+#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /**< SMCLK */\r
+/* EUSCI_A_CTLW0[SYNC] Bits */\r
+#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /**< UCSYNC Bit Offset */\r
+#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /**< Synchronous mode enable */\r
+/* EUSCI_A_CTLW0[MODE] Bits */\r
+#define EUSCI_A_CTLW0_MODE_OFS ( 9) /**< UCMODE Bit Offset */\r
+#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /**< UCMODE Bit Mask */\r
+#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /**< MODE Bit 0 */\r
+#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /**< MODE Bit 1 */\r
+#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /**< UART mode */\r
+#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /**< Idle-line multiprocessor mode */\r
+#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /**< Address-bit multiprocessor mode */\r
+#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /**< UART mode with automatic baud-rate detection */\r
+/* EUSCI_A_CTLW0[SPB] Bits */\r
+#define EUSCI_A_CTLW0_SPB_OFS (11) /**< UCSPB Bit Offset */\r
+#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /**< Stop bit select */\r
+/* EUSCI_A_CTLW0[SEVENBIT] Bits */\r
+#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /**< UC7BIT Bit Offset */\r
+#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /**< Character length */\r
+/* EUSCI_A_CTLW0[MSB] Bits */\r
+#define EUSCI_A_CTLW0_MSB_OFS (13) /**< UCMSB Bit Offset */\r
+#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /**< MSB first select */\r
+/* EUSCI_A_CTLW0[PAR] Bits */\r
+#define EUSCI_A_CTLW0_PAR_OFS (14) /**< UCPAR Bit Offset */\r
+#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /**< Parity select */\r
+/* EUSCI_A_CTLW0[PEN] Bits */\r
+#define EUSCI_A_CTLW0_PEN_OFS (15) /**< UCPEN Bit Offset */\r
+#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /**< Parity enable */\r
+/* EUSCI_A_CTLW0[STEM] Bits */\r
+#define EUSCI_A_CTLW0_STEM_OFS ( 1) /**< UCSTEM Bit Offset */\r
+#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /**< STE mode select in master mode. */\r
+/* EUSCI_A_CTLW0[SSEL] Bits */\r
+\r
+\r
+#define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000) /**< Reserved */\r
+\r
+\r
+/* EUSCI_A_CTLW0[MODE] Bits */\r
+\r
+\r
+\r
+/* EUSCI_A_CTLW0[MST] Bits */\r
+#define EUSCI_A_CTLW0_MST_OFS (11) /**< UCMST Bit Offset */\r
+#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /**< Master mode select */\r
+/* EUSCI_A_CTLW0[CKPL] Bits */\r
+#define EUSCI_A_CTLW0_CKPL_OFS (14) /**< UCCKPL Bit Offset */\r
+#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /**< Clock polarity select */\r
+/* EUSCI_A_CTLW0[CKPH] Bits */\r
+#define EUSCI_A_CTLW0_CKPH_OFS (15) /**< UCCKPH Bit Offset */\r
+#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /**< Clock phase select */\r
+/* EUSCI_A_CTLW1[GLIT] Bits */\r
+#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /**< UCGLIT Bit Offset */\r
+#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /**< UCGLIT Bit Mask */\r
+#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /**< GLIT Bit 0 */\r
+#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /**< GLIT Bit 1 */\r
+#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /**< Approximately 2 ns (equivalent of 1 delay element) */\r
+#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /**< Approximately 50 ns */\r
+#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /**< Approximately 100 ns */\r
+#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /**< Approximately 200 ns */\r
+/* EUSCI_A_MCTLW[OS16] Bits */\r
+#define EUSCI_A_MCTLW_OS16_OFS ( 0) /**< UCOS16 Bit Offset */\r
+#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /**< Oversampling mode enabled */\r
+/* EUSCI_A_MCTLW[BRF] Bits */\r
+#define EUSCI_A_MCTLW_BRF_OFS ( 4) /**< UCBRF Bit Offset */\r
+#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /**< UCBRF Bit Mask */\r
+/* EUSCI_A_MCTLW[BRS] Bits */\r
+#define EUSCI_A_MCTLW_BRS_OFS ( 8) /**< UCBRS Bit Offset */\r
+#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /**< UCBRS Bit Mask */\r
+/* EUSCI_A_STATW[BUSY] Bits */\r
+#define EUSCI_A_STATW_BUSY_OFS ( 0) /**< UCBUSY Bit Offset */\r
+#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /**< eUSCI_A busy */\r
+/* EUSCI_A_STATW[ADDR_IDLE] Bits */\r
+#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /**< UCADDR_UCIDLE Bit Offset */\r
+#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /**< Address received / Idle line detected */\r
+/* EUSCI_A_STATW[RXERR] Bits */\r
+#define EUSCI_A_STATW_RXERR_OFS ( 2) /**< UCRXERR Bit Offset */\r
+#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /**< Receive error flag */\r
+/* EUSCI_A_STATW[BRK] Bits */\r
+#define EUSCI_A_STATW_BRK_OFS ( 3) /**< UCBRK Bit Offset */\r
+#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /**< Break detect flag */\r
+/* EUSCI_A_STATW[PE] Bits */\r
+#define EUSCI_A_STATW_PE_OFS ( 4) /**< UCPE Bit Offset */\r
+#define EUSCI_A_STATW_PE ((uint16_t)0x0010)\r
+/* EUSCI_A_STATW[OE] Bits */\r
+#define EUSCI_A_STATW_OE_OFS ( 5) /**< UCOE Bit Offset */\r
+#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /**< Overrun error flag */\r
+/* EUSCI_A_STATW[FE] Bits */\r
+#define EUSCI_A_STATW_FE_OFS ( 6) /**< UCFE Bit Offset */\r
+#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /**< Framing error flag */\r
+/* EUSCI_A_STATW[LISTEN] Bits */\r
+#define EUSCI_A_STATW_LISTEN_OFS ( 7) /**< UCLISTEN Bit Offset */\r
+#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /**< Listen enable */\r
+/* EUSCI_A_RXBUF[RXBUF] Bits */\r
+#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /**< UCRXBUF Bit Offset */\r
+#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /**< UCRXBUF Bit Mask */\r
+/* EUSCI_A_TXBUF[TXBUF] Bits */\r
+#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /**< UCTXBUF Bit Offset */\r
+#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /**< UCTXBUF Bit Mask */\r
+/* EUSCI_A_ABCTL[ABDEN] Bits */\r
+#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /**< UCABDEN Bit Offset */\r
+#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /**< Automatic baud-rate detect enable */\r
+/* EUSCI_A_ABCTL[BTOE] Bits */\r
+#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /**< UCBTOE Bit Offset */\r
+#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /**< Break time out error */\r
+/* EUSCI_A_ABCTL[STOE] Bits */\r
+#define EUSCI_A_ABCTL_STOE_OFS ( 3) /**< UCSTOE Bit Offset */\r
+#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /**< Synch field time out error */\r
+/* EUSCI_A_ABCTL[DELIM] Bits */\r
+#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /**< UCDELIM Bit Offset */\r
+#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /**< UCDELIM Bit Mask */\r
+#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /**< DELIM Bit 0 */\r
+#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /**< DELIM Bit 1 */\r
+#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /**< 1 bit time */\r
+#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /**< 2 bit times */\r
+#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /**< 3 bit times */\r
+#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /**< 4 bit times */\r
+/* EUSCI_A_IRCTL[IREN] Bits */\r
+#define EUSCI_A_IRCTL_IREN_OFS ( 0) /**< UCIREN Bit Offset */\r
+#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /**< IrDA encoder/decoder enable */\r
+/* EUSCI_A_IRCTL[IRTXCLK] Bits */\r
+#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /**< UCIRTXCLK Bit Offset */\r
+#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /**< IrDA transmit pulse clock select */\r
+/* EUSCI_A_IRCTL[IRTXPL] Bits */\r
+#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /**< UCIRTXPL Bit Offset */\r
+#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /**< UCIRTXPL Bit Mask */\r
+/* EUSCI_A_IRCTL[IRRXFE] Bits */\r
+#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /**< UCIRRXFE Bit Offset */\r
+#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /**< IrDA receive filter enabled */\r
+/* EUSCI_A_IRCTL[IRRXPL] Bits */\r
+#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /**< UCIRRXPL Bit Offset */\r
+#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /**< IrDA receive input UCAxRXD polarity */\r
+/* EUSCI_A_IRCTL[IRRXFL] Bits */\r
+#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /**< UCIRRXFL Bit Offset */\r
+#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /**< UCIRRXFL Bit Mask */\r
+/* EUSCI_A_IE[RXIE] Bits */\r
+#define EUSCI_A_IE_RXIE_OFS ( 0) /**< UCRXIE Bit Offset */\r
+#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */\r
+/* EUSCI_A_IE[TXIE] Bits */\r
+#define EUSCI_A_IE_TXIE_OFS ( 1) /**< UCTXIE Bit Offset */\r
+#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */\r
+/* EUSCI_A_IE[STTIE] Bits */\r
+#define EUSCI_A_IE_STTIE_OFS ( 2) /**< UCSTTIE Bit Offset */\r
+#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /**< Start bit interrupt enable */\r
+/* EUSCI_A_IE[TXCPTIE] Bits */\r
+#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /**< UCTXCPTIE Bit Offset */\r
+#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /**< Transmit complete interrupt enable */\r
+/* EUSCI_A_UCAxIE_SPI[RXIE] Bits */\r
+#define EUSCI_A__RXIE_OFS ( 0) /**< UCRXIE Bit Offset */\r
+#define EUSCI_A__RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */\r
+/* EUSCI_A_UCAxIE_SPI[TXIE] Bits */\r
+#define EUSCI_A__TXIE_OFS ( 1) /**< UCTXIE Bit Offset */\r
+#define EUSCI_A__TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */\r
+/* EUSCI_A_IFG[RXIFG] Bits */\r
+#define EUSCI_A_IFG_RXIFG_OFS ( 0) /**< UCRXIFG Bit Offset */\r
+#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /**< Receive interrupt flag */\r
+/* EUSCI_A_IFG[TXIFG] Bits */\r
+#define EUSCI_A_IFG_TXIFG_OFS ( 1) /**< UCTXIFG Bit Offset */\r
+#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /**< Transmit interrupt flag */\r
+/* EUSCI_A_IFG[STTIFG] Bits */\r
+#define EUSCI_A_IFG_STTIFG_OFS ( 2) /**< UCSTTIFG Bit Offset */\r
+#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /**< Start bit interrupt flag */\r
+/* EUSCI_A_IFG[TXCPTIFG] Bits */\r
+#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /**< UCTXCPTIFG Bit Offset */\r
+#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /**< Transmit ready interrupt enable */\r
+\r
+\r
+/******************************************************************************\r
+* EUSCI_B Bits\r
+******************************************************************************/\r
+/* EUSCI_B_CTLW0[SWRST] Bits */\r
+#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /**< UCSWRST Bit Offset */\r
+#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /**< Software reset enable */\r
+/* EUSCI_B_CTLW0[TXSTT] Bits */\r
+#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /**< UCTXSTT Bit Offset */\r
+#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /**< Transmit START condition in master mode */\r
+/* EUSCI_B_CTLW0[TXSTP] Bits */\r
+#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /**< UCTXSTP Bit Offset */\r
+#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /**< Transmit STOP condition in master mode */\r
+/* EUSCI_B_CTLW0[TXNACK] Bits */\r
+#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /**< UCTXNACK Bit Offset */\r
+#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /**< Transmit a NACK */\r
+/* EUSCI_B_CTLW0[TR] Bits */\r
+#define EUSCI_B_CTLW0_TR_OFS ( 4) /**< UCTR Bit Offset */\r
+#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /**< Transmitter/receiver */\r
+/* EUSCI_B_CTLW0[TXACK] Bits */\r
+#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /**< UCTXACK Bit Offset */\r
+#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /**< Transmit ACK condition in slave mode */\r
+/* EUSCI_B_CTLW0[SSEL] Bits */\r
+#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /**< UCSSEL Bit Offset */\r
+#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /**< UCSSEL Bit Mask */\r
+#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /**< SSEL Bit 0 */\r
+#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /**< SSEL Bit 1 */\r
+#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /**< UCLKI */\r
+#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /**< ACLK */\r
+#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /**< SMCLK */\r
+#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /**< UCLKI */\r
+#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /**< ACLK */\r
+#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /**< SMCLK */\r
+#define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0) /**< SMCLK */\r
+/* EUSCI_B_CTLW0[SYNC] Bits */\r
+#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /**< UCSYNC Bit Offset */\r
+#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /**< Synchronous mode enable */\r
+/* EUSCI_B_CTLW0[MODE] Bits */\r
+#define EUSCI_B_CTLW0_MODE_OFS ( 9) /**< UCMODE Bit Offset */\r
+#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /**< UCMODE Bit Mask */\r
+#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /**< MODE Bit 0 */\r
+#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /**< MODE Bit 1 */\r
+#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /**< 3-pin SPI */\r
+#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /**< 4-pin SPI (master or slave enabled if STE = 1) */\r
+#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /**< 4-pin SPI (master or slave enabled if STE = 0) */\r
+#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /**< I2C mode */\r
+/* EUSCI_B_CTLW0[MST] Bits */\r
+#define EUSCI_B_CTLW0_MST_OFS (11) /**< UCMST Bit Offset */\r
+#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /**< Master mode select */\r
+/* EUSCI_B_CTLW0[MM] Bits */\r
+#define EUSCI_B_CTLW0_MM_OFS (13) /**< UCMM Bit Offset */\r
+#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /**< Multi-master environment select */\r
+/* EUSCI_B_CTLW0[SLA10] Bits */\r
+#define EUSCI_B_CTLW0_SLA10_OFS (14) /**< UCSLA10 Bit Offset */\r
+#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /**< Slave addressing mode select */\r
+/* EUSCI_B_CTLW0[A10] Bits */\r
+#define EUSCI_B_CTLW0_A10_OFS (15) /**< UCA10 Bit Offset */\r
+#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /**< Own addressing mode select */\r
+/* EUSCI_B_CTLW0[STEM] Bits */\r
+#define EUSCI_B_CTLW0_STEM_OFS ( 1) /**< UCSTEM Bit Offset */\r
+#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /**< STE mode select in master mode. */\r
+/* EUSCI_B_CTLW0[SSEL] Bits */\r
+\r
+\r
+#define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000) /**< Reserved */\r
+\r
+\r
+\r
+/* EUSCI_B_CTLW0[MODE] Bits */\r
+\r
+\r
+\r
+\r
+/* EUSCI_B_CTLW0[SEVENBIT] Bits */\r
+#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /**< UC7BIT Bit Offset */\r
+#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /**< Character length */\r
+/* EUSCI_B_CTLW0[MSB] Bits */\r
+#define EUSCI_B_CTLW0_MSB_OFS (13) /**< UCMSB Bit Offset */\r
+#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /**< MSB first select */\r
+/* EUSCI_B_CTLW0[CKPL] Bits */\r
+#define EUSCI_B_CTLW0_CKPL_OFS (14) /**< UCCKPL Bit Offset */\r
+#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /**< Clock polarity select */\r
+/* EUSCI_B_CTLW0[CKPH] Bits */\r
+#define EUSCI_B_CTLW0_CKPH_OFS (15) /**< UCCKPH Bit Offset */\r
+#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /**< Clock phase select */\r
+/* EUSCI_B_CTLW1[GLIT] Bits */\r
+#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /**< UCGLIT Bit Offset */\r
+#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /**< UCGLIT Bit Mask */\r
+#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /**< GLIT Bit 0 */\r
+#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /**< GLIT Bit 1 */\r
+#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /**< 50 ns */\r
+#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /**< 25 ns */\r
+#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /**< 12.5 ns */\r
+#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /**< 6.25 ns */\r
+/* EUSCI_B_CTLW1[ASTP] Bits */\r
+#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /**< UCASTP Bit Offset */\r
+#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /**< UCASTP Bit Mask */\r
+#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /**< ASTP Bit 0 */\r
+#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /**< ASTP Bit 1 */\r
+#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /**< No automatic STOP generation. The STOP condition is generated after the user */\r
+ /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
+#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /**< UCBCNTIFG is set with the byte counter reaches the threshold defined in */\r
+ /* UCBxTBCNT */\r
+#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /**< A STOP condition is generated automatically after the byte counter value */\r
+ /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */\r
+ /* threshold */\r
+/* EUSCI_B_CTLW1[SWACK] Bits */\r
+#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /**< UCSWACK Bit Offset */\r
+#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /**< SW or HW ACK control */\r
+/* EUSCI_B_CTLW1[STPNACK] Bits */\r
+#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /**< UCSTPNACK Bit Offset */\r
+#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /**< ACK all master bytes */\r
+/* EUSCI_B_CTLW1[CLTO] Bits */\r
+#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /**< UCCLTO Bit Offset */\r
+#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /**< UCCLTO Bit Mask */\r
+#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /**< CLTO Bit 0 */\r
+#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /**< CLTO Bit 1 */\r
+#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /**< Disable clock low timeout counter */\r
+#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /**< 135 000 SYSCLK cycles (approximately 28 ms) */\r
+#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /**< 150 000 SYSCLK cycles (approximately 31 ms) */\r
+#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /**< 165 000 SYSCLK cycles (approximately 34 ms) */\r
+/* EUSCI_B_CTLW1[ETXINT] Bits */\r
+#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /**< UCETXINT Bit Offset */\r
+#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /**< Early UCTXIFG0 */\r
+/* EUSCI_B_STATW[BBUSY] Bits */\r
+#define EUSCI_B_STATW_BBUSY_OFS ( 4) /**< UCBBUSY Bit Offset */\r
+#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /**< Bus busy */\r
+/* EUSCI_B_STATW[GC] Bits */\r
+#define EUSCI_B_STATW_GC_OFS ( 5) /**< UCGC Bit Offset */\r
+#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /**< General call address received */\r
+/* EUSCI_B_STATW[SCLLOW] Bits */\r
+#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /**< UCSCLLOW Bit Offset */\r
+#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /**< SCL low */\r
+/* EUSCI_B_STATW[BCNT] Bits */\r
+#define EUSCI_B_STATW_BCNT_OFS ( 8) /**< UCBCNT Bit Offset */\r
+#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /**< UCBCNT Bit Mask */\r
+/* EUSCI_B_STATW[BUSY] Bits */\r
+#define EUSCI_B_STATW_BUSY_OFS ( 0) /**< UCBUSY Bit Offset */\r
+#define EUSCI_B_STATW_BUSY ((uint16_t)0x0001) /**< eUSCI_B busy */\r
+/* EUSCI_B_STATW[OE] Bits */\r
+#define EUSCI_B_STATW_OE_OFS ( 5) /**< UCOE Bit Offset */\r
+#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /**< Overrun error flag */\r
+/* EUSCI_B_STATW[FE] Bits */\r
+#define EUSCI_B_STATW_FE_OFS ( 6) /**< UCFE Bit Offset */\r
+#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /**< Framing error flag */\r
+/* EUSCI_B_STATW[LISTEN] Bits */\r
+#define EUSCI_B_STATW_LISTEN_OFS ( 7) /**< UCLISTEN Bit Offset */\r
+#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /**< Listen enable */\r
+/* EUSCI_B_TBCNT[TBCNT] Bits */\r
+#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /**< UCTBCNT Bit Offset */\r
+#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /**< UCTBCNT Bit Mask */\r
+/* EUSCI_B_RXBUF[RXBUF] Bits */\r
+#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /**< UCRXBUF Bit Offset */\r
+#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /**< UCRXBUF Bit Mask */\r
+/* EUSCI_B_TXBUF[TXBUF] Bits */\r
+#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /**< UCTXBUF Bit Offset */\r
+#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /**< UCTXBUF Bit Mask */\r
+/* EUSCI_B_I2COA0[I2COA0] Bits */\r
+#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /**< I2COA0 Bit Offset */\r
+#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /**< I2COA0 Bit Mask */\r
+/* EUSCI_B_I2COA0[OAEN] Bits */\r
+#define EUSCI_B_I2COA0_OAEN_OFS (10) /**< UCOAEN Bit Offset */\r
+#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /**< Own Address enable register */\r
+/* EUSCI_B_I2COA0[GCEN] Bits */\r
+#define EUSCI_B_I2COA0_GCEN_OFS (15) /**< UCGCEN Bit Offset */\r
+#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /**< General call response enable */\r
+/* EUSCI_B_I2COA1[I2COA1] Bits */\r
+#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /**< I2COA1 Bit Offset */\r
+#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /**< I2COA1 Bit Mask */\r
+/* EUSCI_B_I2COA1[OAEN] Bits */\r
+#define EUSCI_B_I2COA1_OAEN_OFS (10) /**< UCOAEN Bit Offset */\r
+#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /**< Own Address enable register */\r
+/* EUSCI_B_I2COA2[I2COA2] Bits */\r
+#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /**< I2COA2 Bit Offset */\r
+#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /**< I2COA2 Bit Mask */\r
+/* EUSCI_B_I2COA2[OAEN] Bits */\r
+#define EUSCI_B_I2COA2_OAEN_OFS (10) /**< UCOAEN Bit Offset */\r
+#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /**< Own Address enable register */\r
+/* EUSCI_B_I2COA3[I2COA3] Bits */\r
+#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /**< I2COA3 Bit Offset */\r
+#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /**< I2COA3 Bit Mask */\r
+/* EUSCI_B_I2COA3[OAEN] Bits */\r
+#define EUSCI_B_I2COA3_OAEN_OFS (10) /**< UCOAEN Bit Offset */\r
+#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /**< Own Address enable register */\r
+/* EUSCI_B_ADDRX[ADDRX] Bits */\r
+#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /**< ADDRX Bit Offset */\r
+#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /**< ADDRX Bit Mask */\r
+/* EUSCI_B_ADDMASK[ADDMASK] Bits */\r
+#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /**< ADDMASK Bit Offset */\r
+#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /**< ADDMASK Bit Mask */\r
+/* EUSCI_B_I2CSA[I2CSA] Bits */\r
+#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /**< I2CSA Bit Offset */\r
+#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /**< I2CSA Bit Mask */\r
+/* EUSCI_B_IE[RXIE0] Bits */\r
+#define EUSCI_B_IE_RXIE0_OFS ( 0) /**< UCRXIE0 Bit Offset */\r
+#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /**< Receive interrupt enable 0 */\r
+/* EUSCI_B_IE[TXIE0] Bits */\r
+#define EUSCI_B_IE_TXIE0_OFS ( 1) /**< UCTXIE0 Bit Offset */\r
+#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /**< Transmit interrupt enable 0 */\r
+/* EUSCI_B_IE[STTIE] Bits */\r
+#define EUSCI_B_IE_STTIE_OFS ( 2) /**< UCSTTIE Bit Offset */\r
+#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /**< START condition interrupt enable */\r
+/* EUSCI_B_IE[STPIE] Bits */\r
+#define EUSCI_B_IE_STPIE_OFS ( 3) /**< UCSTPIE Bit Offset */\r
+#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /**< STOP condition interrupt enable */\r
+/* EUSCI_B_IE[ALIE] Bits */\r
+#define EUSCI_B_IE_ALIE_OFS ( 4) /**< UCALIE Bit Offset */\r
+#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /**< Arbitration lost interrupt enable */\r
+/* EUSCI_B_IE[NACKIE] Bits */\r
+#define EUSCI_B_IE_NACKIE_OFS ( 5) /**< UCNACKIE Bit Offset */\r
+#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /**< Not-acknowledge interrupt enable */\r
+/* EUSCI_B_IE[BCNTIE] Bits */\r
+#define EUSCI_B_IE_BCNTIE_OFS ( 6) /**< UCBCNTIE Bit Offset */\r
+#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /**< Byte counter interrupt enable */\r
+/* EUSCI_B_IE[CLTOIE] Bits */\r
+#define EUSCI_B_IE_CLTOIE_OFS ( 7) /**< UCCLTOIE Bit Offset */\r
+#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /**< Clock low timeout interrupt enable */\r
+/* EUSCI_B_IE[RXIE1] Bits */\r
+#define EUSCI_B_IE_RXIE1_OFS ( 8) /**< UCRXIE1 Bit Offset */\r
+#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /**< Receive interrupt enable 1 */\r
+/* EUSCI_B_IE[TXIE1] Bits */\r
+#define EUSCI_B_IE_TXIE1_OFS ( 9) /**< UCTXIE1 Bit Offset */\r
+#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /**< Transmit interrupt enable 1 */\r
+/* EUSCI_B_IE[RXIE2] Bits */\r
+#define EUSCI_B_IE_RXIE2_OFS (10) /**< UCRXIE2 Bit Offset */\r
+#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /**< Receive interrupt enable 2 */\r
+/* EUSCI_B_IE[TXIE2] Bits */\r
+#define EUSCI_B_IE_TXIE2_OFS (11) /**< UCTXIE2 Bit Offset */\r
+#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /**< Transmit interrupt enable 2 */\r
+/* EUSCI_B_IE[RXIE3] Bits */\r
+#define EUSCI_B_IE_RXIE3_OFS (12) /**< UCRXIE3 Bit Offset */\r
+#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /**< Receive interrupt enable 3 */\r
+/* EUSCI_B_IE[TXIE3] Bits */\r
+#define EUSCI_B_IE_TXIE3_OFS (13) /**< UCTXIE3 Bit Offset */\r
+#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /**< Transmit interrupt enable 3 */\r
+/* EUSCI_B_IE[BIT9IE] Bits */\r
+#define EUSCI_B_IE_BIT9IE_OFS (14) /**< UCBIT9IE Bit Offset */\r
+#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /**< Bit position 9 interrupt enable */\r
+/* EUSCI_B_UCBxIE_SPI[RXIE] Bits */\r
+#define EUSCI_B__RXIE_OFS ( 0) /**< UCRXIE Bit Offset */\r
+#define EUSCI_B__RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */\r
+/* EUSCI_B_UCBxIE_SPI[TXIE] Bits */\r
+#define EUSCI_B__TXIE_OFS ( 1) /**< UCTXIE Bit Offset */\r
+#define EUSCI_B__TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */\r
+/* EUSCI_B_IFG[RXIFG0] Bits */\r
+#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /**< UCRXIFG0 Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /**< eUSCI_B receive interrupt flag 0 */\r
+/* EUSCI_B_IFG[TXIFG0] Bits */\r
+#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /**< UCTXIFG0 Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /**< eUSCI_B transmit interrupt flag 0 */\r
+/* EUSCI_B_IFG[STTIFG] Bits */\r
+#define EUSCI_B_IFG_STTIFG_OFS ( 2) /**< UCSTTIFG Bit Offset */\r
+#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /**< START condition interrupt flag */\r
+/* EUSCI_B_IFG[STPIFG] Bits */\r
+#define EUSCI_B_IFG_STPIFG_OFS ( 3) /**< UCSTPIFG Bit Offset */\r
+#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /**< STOP condition interrupt flag */\r
+/* EUSCI_B_IFG[ALIFG] Bits */\r
+#define EUSCI_B_IFG_ALIFG_OFS ( 4) /**< UCALIFG Bit Offset */\r
+#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /**< Arbitration lost interrupt flag */\r
+/* EUSCI_B_IFG[NACKIFG] Bits */\r
+#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /**< UCNACKIFG Bit Offset */\r
+#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /**< Not-acknowledge received interrupt flag */\r
+/* EUSCI_B_IFG[BCNTIFG] Bits */\r
+#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /**< UCBCNTIFG Bit Offset */\r
+#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /**< Byte counter interrupt flag */\r
+/* EUSCI_B_IFG[CLTOIFG] Bits */\r
+#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /**< UCCLTOIFG Bit Offset */\r
+#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /**< Clock low timeout interrupt flag */\r
+/* EUSCI_B_IFG[RXIFG1] Bits */\r
+#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /**< UCRXIFG1 Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /**< eUSCI_B receive interrupt flag 1 */\r
+/* EUSCI_B_IFG[TXIFG1] Bits */\r
+#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /**< UCTXIFG1 Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /**< eUSCI_B transmit interrupt flag 1 */\r
+/* EUSCI_B_IFG[RXIFG2] Bits */\r
+#define EUSCI_B_IFG_RXIFG2_OFS (10) /**< UCRXIFG2 Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /**< eUSCI_B receive interrupt flag 2 */\r
+/* EUSCI_B_IFG[TXIFG2] Bits */\r
+#define EUSCI_B_IFG_TXIFG2_OFS (11) /**< UCTXIFG2 Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /**< eUSCI_B transmit interrupt flag 2 */\r
+/* EUSCI_B_IFG[RXIFG3] Bits */\r
+#define EUSCI_B_IFG_RXIFG3_OFS (12) /**< UCRXIFG3 Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /**< eUSCI_B receive interrupt flag 3 */\r
+/* EUSCI_B_IFG[TXIFG3] Bits */\r
+#define EUSCI_B_IFG_TXIFG3_OFS (13) /**< UCTXIFG3 Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /**< eUSCI_B transmit interrupt flag 3 */\r
+/* EUSCI_B_IFG[BIT9IFG] Bits */\r
+#define EUSCI_B_IFG_BIT9IFG_OFS (14) /**< UCBIT9IFG Bit Offset */\r
+#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /**< Bit position 9 interrupt flag */\r
+/* EUSCI_B_IFG[RXIFG] Bits */\r
+#define EUSCI_B_IFG_RXIFG_OFS ( 0) /**< UCRXIFG Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /**< Receive interrupt flag */\r
+/* EUSCI_B_IFG[TXIFG] Bits */\r
+#define EUSCI_B_IFG_TXIFG_OFS ( 1) /**< UCTXIFG Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /**< Transmit interrupt flag */\r
+\r
+\r
+/******************************************************************************\r
+* FLCTL Bits\r
+******************************************************************************/\r
+/* FLCTL_POWER_STAT[PSTAT] Bits */\r
+#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /**< PSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /**< PSTAT Bit Mask */\r
+#define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /**< PSTAT Bit 0 */\r
+#define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /**< PSTAT Bit 1 */\r
+#define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /**< PSTAT Bit 2 */\r
+#define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /**< Flash IP in power-down mode */\r
+#define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /**< Flash IP Vdd domain power-up in progress */\r
+#define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /**< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */\r
+#define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /**< Flash IP SAFE_LV check in progress */\r
+#define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /**< Flash IP Active */\r
+#define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /**< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */\r
+#define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /**< Flash IP in Standby mode */\r
+#define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /**< Flash IP in Current mirror boost state */\r
+/* FLCTL_POWER_STAT[LDOSTAT] Bits */\r
+#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /**< LDOSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /**< PSS FLDO GOOD status */\r
+/* FLCTL_POWER_STAT[VREFSTAT] Bits */\r
+#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /**< VREFSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /**< PSS VREF stable status */\r
+/* FLCTL_POWER_STAT[IREFSTAT] Bits */\r
+#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /**< IREFSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /**< PSS IREF stable status */\r
+/* FLCTL_POWER_STAT[TRIMSTAT] Bits */\r
+#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /**< TRIMSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /**< PSS trim done status */\r
+/* FLCTL_POWER_STAT[RD_2T] Bits */\r
+#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /**< RD_2T Bit Offset */\r
+#define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /**< Indicates if Flash is being accessed in 2T mode */\r
+/* FLCTL_BANK0_RDCTL[RD_MODE] Bits */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /**< RD_MODE Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /**< RD_MODE Bit Mask */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /**< RD_MODE Bit 0 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /**< RD_MODE Bit 1 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /**< RD_MODE Bit 2 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /**< RD_MODE Bit 3 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /**< Normal read mode */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /**< Read Margin 0 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /**< Read Margin 1 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /**< Program Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /**< Erase Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /**< Leakage Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /**< Read Margin 0B */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /**< Read Margin 1B */\r
+/* FLCTL_BANK0_RDCTL[BUFI] Bits */\r
+#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /**< BUFI Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /**< Enables read buffering feature for instruction fetches to this Bank */\r
+/* FLCTL_BANK0_RDCTL[BUFD] Bits */\r
+#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /**< BUFD Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /**< Enables read buffering feature for data reads to this Bank */\r
+/* FLCTL_BANK0_RDCTL[WAIT] Bits */\r
+#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /**< WAIT Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /**< WAIT Bit Mask */\r
+#define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /**< WAIT Bit 0 */\r
+#define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /**< WAIT Bit 1 */\r
+#define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /**< WAIT Bit 2 */\r
+#define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /**< WAIT Bit 3 */\r
+#define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /**< 0 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /**< 1 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /**< 2 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /**< 3 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /**< 4 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /**< 5 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /**< 6 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /**< 7 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /**< 8 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /**< 9 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /**< 10 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /**< 11 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /**< 12 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /**< 13 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /**< 14 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /**< 15 wait states */\r
+/* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /**< RD_MODE_STATUS Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /**< RD_MODE_STATUS Bit Mask */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /**< RD_MODE_STATUS Bit 0 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /**< RD_MODE_STATUS Bit 1 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /**< RD_MODE_STATUS Bit 2 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /**< RD_MODE_STATUS Bit 3 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /**< Normal read mode */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /**< Read Margin 0 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /**< Read Margin 1 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /**< Program Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /**< Erase Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /**< Leakage Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /**< Read Margin 0B */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /**< Read Margin 1B */\r
+/* FLCTL_BANK1_RDCTL[RD_MODE] Bits */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /**< RD_MODE Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /**< RD_MODE Bit Mask */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /**< RD_MODE Bit 0 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /**< RD_MODE Bit 1 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /**< RD_MODE Bit 2 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /**< RD_MODE Bit 3 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /**< Normal read mode */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /**< Read Margin 0 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /**< Read Margin 1 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /**< Program Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /**< Erase Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /**< Leakage Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /**< Read Margin 0B */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /**< Read Margin 1B */\r
+/* FLCTL_BANK1_RDCTL[BUFI] Bits */\r
+#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /**< BUFI Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /**< Enables read buffering feature for instruction fetches to this Bank */\r
+/* FLCTL_BANK1_RDCTL[BUFD] Bits */\r
+#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /**< BUFD Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /**< Enables read buffering feature for data reads to this Bank */\r
+/* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /**< RD_MODE_STATUS Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /**< RD_MODE_STATUS Bit Mask */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /**< RD_MODE_STATUS Bit 0 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /**< RD_MODE_STATUS Bit 1 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /**< RD_MODE_STATUS Bit 2 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /**< RD_MODE_STATUS Bit 3 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /**< Normal read mode */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /**< Read Margin 0 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /**< Read Margin 1 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /**< Program Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /**< Erase Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /**< Leakage Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /**< Read Margin 0B */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /**< Read Margin 1B */\r
+/* FLCTL_BANK1_RDCTL[WAIT] Bits */\r
+#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /**< WAIT Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /**< WAIT Bit Mask */\r
+#define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /**< WAIT Bit 0 */\r
+#define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /**< WAIT Bit 1 */\r
+#define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /**< WAIT Bit 2 */\r
+#define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /**< WAIT Bit 3 */\r
+#define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /**< 0 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /**< 1 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /**< 2 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /**< 3 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /**< 4 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /**< 5 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /**< 6 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /**< 7 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /**< 8 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /**< 9 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /**< 10 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /**< 11 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /**< 12 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /**< 13 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /**< 14 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /**< 15 wait states */\r
+/* FLCTL_RDBRST_CTLSTAT[START] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /**< Start of burst/compare operation */\r
+/* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /**< MEM_TYPE Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /**< MEM_TYPE Bit Mask */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /**< MEM_TYPE Bit 0 */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /**< MEM_TYPE Bit 1 */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /**< Information Memory */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /**< Reserved */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /**< Engineering Memory */\r
+/* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /**< STOP_FAIL Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /**< Terminate burst/compare operation */\r
+/* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /**< DATA_CMP Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /**< Data pattern used for comparison against memory read data */\r
+/* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /**< TEST_EN Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /**< Enable comparison against test data compare registers */\r
+/* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /**< BRST_STAT Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /**< BRST_STAT Bit Mask */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /**< BRST_STAT Bit 0 */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /**< BRST_STAT Bit 1 */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /**< Idle */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /**< Burst/Compare START bit written, but operation pending */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /**< Burst/Compare in progress */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /**< Burst complete (status of completed burst remains in this state unless */\r
+ /* explicitly cleared by SW) */\r
+/* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /**< CMP_ERR Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /**< Burst/Compare Operation encountered atleast one data */\r
+/* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /**< ADDR_ERR Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /**< Burst/Compare Operation was terminated due to access to */\r
+/* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /**< CLR_STAT Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /**< Clear status bits 19-16 of this register */\r
+/* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */\r
+#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /**< START_ADDRESS Bit Offset */\r
+#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /**< START_ADDRESS Bit Mask */\r
+/* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */\r
+#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /**< BURST_LENGTH Bit Offset */\r
+#define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /**< BURST_LENGTH Bit Mask */\r
+/* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */\r
+#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /**< FAIL_ADDRESS Bit Offset */\r
+#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /**< FAIL_ADDRESS Bit Mask */\r
+/* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */\r
+#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /**< FAIL_COUNT Bit Offset */\r
+#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /**< FAIL_COUNT Bit Mask */\r
+/* FLCTL_PRG_CTLSTAT[ENABLE] Bits */\r
+#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /**< ENABLE Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /**< Master control for all word program operations */\r
+/* FLCTL_PRG_CTLSTAT[MODE] Bits */\r
+#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /**< MODE Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /**< Write mode */\r
+/* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */\r
+#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /**< VER_PRE Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /**< Controls automatic pre program verify operations */\r
+/* FLCTL_PRG_CTLSTAT[VER_PST] Bits */\r
+#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /**< VER_PST Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /**< Controls automatic post program verify operations */\r
+/* FLCTL_PRG_CTLSTAT[STATUS] Bits */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /**< STATUS Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /**< STATUS Bit Mask */\r
+#define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /**< STATUS Bit 0 */\r
+#define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /**< STATUS Bit 1 */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /**< Idle (no program operation currently active) */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /**< Single word program operation triggered, but pending */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /**< Single word program in progress */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /**< Reserved (Idle) */\r
+/* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */\r
+#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /**< BNK_ACT Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /**< Bank active */\r
+/* FLCTL_PRGBRST_CTLSTAT[START] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /**< Trigger start of burst program operation */\r
+/* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /**< TYPE Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /**< TYPE Bit Mask */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /**< TYPE Bit 0 */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /**< TYPE Bit 1 */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /**< Information Memory */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /**< Reserved */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /**< Engineering Memory */\r
+/* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /**< LEN Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /**< LEN Bit Mask */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /**< LEN Bit 0 */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /**< LEN Bit 1 */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /**< LEN Bit 2 */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /**< No burst operation */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /**< 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR */\r
+ /* Register */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /**< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */\r
+ /* Register */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /**< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */\r
+ /* Register */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /**< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */\r
+ /* Register */\r
+/* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /**< AUTO_PRE Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /**< Auto-Verify operation before the Burst Program */\r
+/* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /**< AUTO_PST Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /**< Auto-Verify operation after the Burst Program */\r
+/* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /**< BURST_STATUS Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /**< BURST_STATUS Bit Mask */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /**< BURST_STATUS Bit 0 */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /**< BURST_STATUS Bit 1 */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /**< BURST_STATUS Bit 2 */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /**< Idle (Burst not active) */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /**< Burst program started but pending */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /**< Burst active, with 1st 128 bit word being written into Flash */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /**< Burst active, with 2nd 128 bit word being written into Flash */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /**< Burst active, with 3rd 128 bit word being written into Flash */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /**< Burst active, with 4th 128 bit word being written into Flash */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /**< Reserved (Idle) */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /**< Burst Complete (status of completed burst remains in this state unless */\r
+ /* explicitly cleared by SW) */\r
+/* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /**< PRE_ERR Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /**< Burst Operation encountered preprogram auto-verify errors */\r
+/* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /**< PST_ERR Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /**< Burst Operation encountered postprogram auto-verify errors */\r
+/* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /**< ADDR_ERR Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /**< Burst Operation was terminated due to attempted program of reserved memory */\r
+/* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /**< CLR_STAT Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /**< Clear status bits 21-16 of this register */\r
+/* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */\r
+#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /**< START_ADDRESS Bit Offset */\r
+#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /**< START_ADDRESS Bit Mask */\r
+/* FLCTL_ERASE_CTLSTAT[START] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /**< Start of Erase operation */\r
+/* FLCTL_ERASE_CTLSTAT[MODE] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /**< MODE Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /**< Erase mode selected by application */\r
+/* FLCTL_ERASE_CTLSTAT[TYPE] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /**< TYPE Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /**< TYPE Bit Mask */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /**< TYPE Bit 0 */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /**< TYPE Bit 1 */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /**< Information Memory */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /**< Reserved */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /**< Engineering Memory */\r
+/* FLCTL_ERASE_CTLSTAT[STATUS] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /**< STATUS Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /**< STATUS Bit Mask */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /**< STATUS Bit 0 */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /**< STATUS Bit 1 */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /**< Idle (no program operation currently active) */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /**< Erase operation triggered to START but pending */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /**< Erase operation in progress */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /**< Erase operation completed (status of completed erase remains in this state */\r
+ /* unless explicitly cleared by SW) */\r
+/* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /**< ADDR_ERR Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /**< Erase Operation was terminated due to attempted erase of reserved memory */\r
+ /* address */\r
+/* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /**< CLR_STAT Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /**< Clear status bits 18-16 of this register */\r
+/* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */\r
+#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /**< SECT_ADDRESS Bit Offset */\r
+#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /**< SECT_ADDRESS Bit Mask */\r
+/* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */\r
+#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */\r
+#define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase */\r
+/* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */\r
+#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */\r
+#define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /**< PROT2 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /**< Protects Sector 2 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /**< PROT3 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /**< Protects Sector 3 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /**< PROT4 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /**< Protects Sector 4 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /**< PROT5 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /**< Protects Sector 5 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /**< PROT6 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /**< Protects Sector 6 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /**< PROT7 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /**< Protects Sector 7 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /**< PROT8 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /**< Protects Sector 8 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /**< PROT9 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /**< Protects Sector 9 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /**< PROT10 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /**< Protects Sector 10 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /**< PROT11 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /**< Protects Sector 11 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /**< PROT12 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /**< Protects Sector 12 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /**< PROT13 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /**< Protects Sector 13 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /**< PROT14 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /**< Protects Sector 14 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /**< PROT15 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /**< Protects Sector 15 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /**< PROT16 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /**< Protects Sector 16 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /**< PROT17 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /**< Protects Sector 17 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /**< PROT18 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /**< Protects Sector 18 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /**< PROT19 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /**< Protects Sector 19 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /**< PROT20 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /**< Protects Sector 20 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /**< PROT21 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /**< Protects Sector 21 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /**< PROT22 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /**< Protects Sector 22 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /**< PROT23 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /**< Protects Sector 23 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /**< PROT24 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /**< Protects Sector 24 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /**< PROT25 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /**< Protects Sector 25 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /**< PROT26 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /**< Protects Sector 26 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /**< PROT27 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /**< Protects Sector 27 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /**< PROT28 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /**< Protects Sector 28 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /**< PROT29 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /**< Protects Sector 29 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /**< PROT30 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /**< Protects Sector 30 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /**< PROT31 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /**< Protects Sector 31 from program or erase */\r
+/* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */\r
+#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */\r
+#define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase operations */\r
+/* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */\r
+#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */\r
+#define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /**< PROT2 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /**< Protects Sector 2 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /**< PROT3 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /**< Protects Sector 3 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /**< PROT4 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /**< Protects Sector 4 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /**< PROT5 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /**< Protects Sector 5 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /**< PROT6 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /**< Protects Sector 6 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /**< PROT7 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /**< Protects Sector 7 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /**< PROT8 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /**< Protects Sector 8 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /**< PROT9 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /**< Protects Sector 9 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /**< PROT10 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /**< Protects Sector 10 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /**< PROT11 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /**< Protects Sector 11 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /**< PROT12 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /**< Protects Sector 12 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /**< PROT13 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /**< Protects Sector 13 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /**< PROT14 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /**< Protects Sector 14 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /**< PROT15 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /**< Protects Sector 15 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /**< PROT16 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /**< Protects Sector 16 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /**< PROT17 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /**< Protects Sector 17 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /**< PROT18 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /**< Protects Sector 18 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /**< PROT19 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /**< Protects Sector 19 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /**< PROT20 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /**< Protects Sector 20 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /**< PROT21 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /**< Protects Sector 21 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /**< PROT22 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /**< Protects Sector 22 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /**< PROT23 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /**< Protects Sector 23 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /**< PROT24 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /**< Protects Sector 24 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /**< PROT25 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /**< Protects Sector 25 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /**< PROT26 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /**< Protects Sector 26 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /**< PROT27 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /**< Protects Sector 27 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /**< PROT28 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /**< Protects Sector 28 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /**< PROT29 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /**< Protects Sector 29 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /**< PROT30 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /**< Protects Sector 30 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /**< PROT31 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /**< Protects Sector 31 from program or erase operations */\r
+/* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */\r
+#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /**< I_BMRK Bit Offset */\r
+#define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001)\r
+/* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */\r
+#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /**< D_BMRK Bit Offset */\r
+#define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002)\r
+/* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */\r
+#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /**< CMP_EN Bit Offset */\r
+#define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004)\r
+/* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */\r
+#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /**< CMP_SEL Bit Offset */\r
+#define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008)\r
+/* FLCTL_IFG[RDBRST] Bits */\r
+#define FLCTL_IFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */\r
+#define FLCTL_IFG_RDBRST ((uint32_t)0x00000001)\r
+/* FLCTL_IFG[AVPRE] Bits */\r
+#define FLCTL_IFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */\r
+#define FLCTL_IFG_AVPRE ((uint32_t)0x00000002)\r
+/* FLCTL_IFG[AVPST] Bits */\r
+#define FLCTL_IFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */\r
+#define FLCTL_IFG_AVPST ((uint32_t)0x00000004)\r
+/* FLCTL_IFG[PRG] Bits */\r
+#define FLCTL_IFG_PRG_OFS ( 3) /**< PRG Bit Offset */\r
+#define FLCTL_IFG_PRG ((uint32_t)0x00000008)\r
+/* FLCTL_IFG[PRGB] Bits */\r
+#define FLCTL_IFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */\r
+#define FLCTL_IFG_PRGB ((uint32_t)0x00000010)\r
+/* FLCTL_IFG[ERASE] Bits */\r
+#define FLCTL_IFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */\r
+#define FLCTL_IFG_ERASE ((uint32_t)0x00000020)\r
+/* FLCTL_IFG[BMRK] Bits */\r
+#define FLCTL_IFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */\r
+#define FLCTL_IFG_BMRK ((uint32_t)0x00000100)\r
+/* FLCTL_IFG[PRG_ERR] Bits */\r
+#define FLCTL_IFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */\r
+#define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200)\r
+/* FLCTL_IE[RDBRST] Bits */\r
+#define FLCTL_IE_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */\r
+#define FLCTL_IE_RDBRST ((uint32_t)0x00000001)\r
+/* FLCTL_IE[AVPRE] Bits */\r
+#define FLCTL_IE_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */\r
+#define FLCTL_IE_AVPRE ((uint32_t)0x00000002)\r
+/* FLCTL_IE[AVPST] Bits */\r
+#define FLCTL_IE_AVPST_OFS ( 2) /**< AVPST Bit Offset */\r
+#define FLCTL_IE_AVPST ((uint32_t)0x00000004)\r
+/* FLCTL_IE[PRG] Bits */\r
+#define FLCTL_IE_PRG_OFS ( 3) /**< PRG Bit Offset */\r
+#define FLCTL_IE_PRG ((uint32_t)0x00000008)\r
+/* FLCTL_IE[PRGB] Bits */\r
+#define FLCTL_IE_PRGB_OFS ( 4) /**< PRGB Bit Offset */\r
+#define FLCTL_IE_PRGB ((uint32_t)0x00000010)\r
+/* FLCTL_IE[ERASE] Bits */\r
+#define FLCTL_IE_ERASE_OFS ( 5) /**< ERASE Bit Offset */\r
+#define FLCTL_IE_ERASE ((uint32_t)0x00000020)\r
+/* FLCTL_IE[BMRK] Bits */\r
+#define FLCTL_IE_BMRK_OFS ( 8) /**< BMRK Bit Offset */\r
+#define FLCTL_IE_BMRK ((uint32_t)0x00000100)\r
+/* FLCTL_IE[PRG_ERR] Bits */\r
+#define FLCTL_IE_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */\r
+#define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200)\r
+/* FLCTL_CLRIFG[RDBRST] Bits */\r
+#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */\r
+#define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001)\r
+/* FLCTL_CLRIFG[AVPRE] Bits */\r
+#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */\r
+#define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002)\r
+/* FLCTL_CLRIFG[AVPST] Bits */\r
+#define FLCTL_CLRIFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */\r
+#define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004)\r
+/* FLCTL_CLRIFG[PRG] Bits */\r
+#define FLCTL_CLRIFG_PRG_OFS ( 3) /**< PRG Bit Offset */\r
+#define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008)\r
+/* FLCTL_CLRIFG[PRGB] Bits */\r
+#define FLCTL_CLRIFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */\r
+#define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010)\r
+/* FLCTL_CLRIFG[ERASE] Bits */\r
+#define FLCTL_CLRIFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */\r
+#define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020)\r
+/* FLCTL_CLRIFG[BMRK] Bits */\r
+#define FLCTL_CLRIFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */\r
+#define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100)\r
+/* FLCTL_CLRIFG[PRG_ERR] Bits */\r
+#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */\r
+#define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200)\r
+/* FLCTL_SETIFG[RDBRST] Bits */\r
+#define FLCTL_SETIFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */\r
+#define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001)\r
+/* FLCTL_SETIFG[AVPRE] Bits */\r
+#define FLCTL_SETIFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */\r
+#define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002)\r
+/* FLCTL_SETIFG[AVPST] Bits */\r
+#define FLCTL_SETIFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */\r
+#define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004)\r
+/* FLCTL_SETIFG[PRG] Bits */\r
+#define FLCTL_SETIFG_PRG_OFS ( 3) /**< PRG Bit Offset */\r
+#define FLCTL_SETIFG_PRG ((uint32_t)0x00000008)\r
+/* FLCTL_SETIFG[PRGB] Bits */\r
+#define FLCTL_SETIFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */\r
+#define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010)\r
+/* FLCTL_SETIFG[ERASE] Bits */\r
+#define FLCTL_SETIFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */\r
+#define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020)\r
+/* FLCTL_SETIFG[BMRK] Bits */\r
+#define FLCTL_SETIFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */\r
+#define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100)\r
+/* FLCTL_SETIFG[PRG_ERR] Bits */\r
+#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */\r
+#define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200)\r
+/* FLCTL_READ_TIMCTL[SETUP] Bits */\r
+#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */\r
+#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /**< IREF_BOOST1 Bit Offset */\r
+#define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /**< IREF_BOOST1 Bit Mask */\r
+/* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */\r
+#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /**< SETUP_LONG Bit Offset */\r
+#define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /**< SETUP_LONG Bit Mask */\r
+/* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */\r
+#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_PRGVER_TIMCTL[SETUP] Bits */\r
+#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */\r
+#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */\r
+#define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /**< ACTIVE Bit Mask */\r
+/* FLCTL_PRGVER_TIMCTL[HOLD] Bits */\r
+#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /**< HOLD Bit Offset */\r
+#define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /**< HOLD Bit Mask */\r
+/* FLCTL_ERSVER_TIMCTL[SETUP] Bits */\r
+#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_LKGVER_TIMCTL[SETUP] Bits */\r
+#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */\r
+#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */\r
+#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */\r
+#define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */\r
+/* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */\r
+#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /**< HOLD Bit Offset */\r
+#define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /**< HOLD Bit Mask */\r
+/* FLCTL_ERASE_TIMCTL[SETUP] Bits */\r
+#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */\r
+#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */\r
+#define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */\r
+/* FLCTL_ERASE_TIMCTL[HOLD] Bits */\r
+#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /**< HOLD Bit Offset */\r
+#define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /**< HOLD Bit Mask */\r
+/* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */\r
+#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /**< BOOST_ACTIVE Bit Offset */\r
+#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /**< BOOST_ACTIVE Bit Mask */\r
+/* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */\r
+#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /**< BOOST_HOLD Bit Offset */\r
+#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /**< BOOST_HOLD Bit Mask */\r
+/* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */\r
+#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */\r
+#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */\r
+\r
+\r
+/******************************************************************************\r
+* FPB Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* FPU Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* ITM Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* MPU Bits\r
+******************************************************************************/\r
\r
/* Pre-defined bitfield values */\r
\r
/* MPU_RASR_SIZE Bitfield Bits */\r
-#define MPU_RASR_SIZE__4 (0x00000008) /* 64B */\r
-#define MPU_RASR_SIZE__32B (0x00000008) /* 32B */\r
-#define MPU_RASR_SIZE__64B (0x0000000c) /* 128B */\r
-#define MPU_RASR_SIZE__256B (0x0000000e) /* 256B */\r
-#define MPU_RASR_SIZE__512B (0x00000010) /* 512B */\r
-#define MPU_RASR_SIZE__1K (0x00000012) /* 1KB */\r
-#define MPU_RASR_SIZE__2K (0x00000014) /* 2KB */\r
-#define MPU_RASR_SIZE__4K (0x00000016) /* 4KB */\r
-#define MPU_RASR_SIZE__8K (0x00000018) /* 8KB */\r
-#define MPU_RASR_SIZE__16K (0x0000001a) /* 16KB */\r
-#define MPU_RASR_SIZE__32K (0x0000001c) /* 32KB */\r
-#define MPU_RASR_SIZE__64K (0x0000001e) /* 64KB */\r
-#define MPU_RASR_SIZE__128K (0x00000020) /* 128KB */\r
-#define MPU_RASR_SIZE__256K (0x00000022) /* 256KB */\r
-#define MPU_RASR_SIZE__512K (0x00000024) /* 512KB */\r
-#define MPU_RASR_SIZE__1M (0x00000026) /* 1MB */\r
-#define MPU_RASR_SIZE__2M (0x00000028) /* 2MB */\r
-#define MPU_RASR_SIZE__4M (0x0000002a) /* 4MB */\r
-#define MPU_RASR_SIZE__8M (0x0000002c) /* 8MB */\r
-#define MPU_RASR_SIZE__16M (0x0000002e) /* 16MB */\r
-#define MPU_RASR_SIZE__32M (0x00000030) /* 32MB */\r
-#define MPU_RASR_SIZE__64M (0x00000032) /* 64MB */\r
-#define MPU_RASR_SIZE__128M (0x00000034) /* 128MB */\r
-#define MPU_RASR_SIZE__256M (0x00000036) /* 256MB */\r
-#define MPU_RASR_SIZE__512M (0x00000038) /* 512MB */\r
-#define MPU_RASR_SIZE__1G (0x0000003a) /* 1GB */\r
-#define MPU_RASR_SIZE__2G (0x0000003c) /* 2GB */\r
-#define MPU_RASR_SIZE__4G (0x0000003e) /* 4GB */\r
+#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /* 32B */\r
+#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /* 64B */\r
+#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /* 128B */\r
+#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /* 256B */\r
+#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /* 512B */\r
+#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /* 1KB */\r
+#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /* 2KB */\r
+#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /* 4KB */\r
+#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /* 8KB */\r
+#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /* 16KB */\r
+#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /* 32KB */\r
+#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /* 64KB */\r
+#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /* 128KB */\r
+#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /* 256KB */\r
+#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /* 512KB */\r
+#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /* 1MB */\r
+#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /* 2MB */\r
+#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /* 4MB */\r
+#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /* 8MB */\r
+#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /* 16MB */\r
+#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /* 32MB */\r
+#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /* 64MB */\r
+#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /* 128MB */\r
+#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /* 256MB */\r
+#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /* 512MB */\r
+#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /* 1GB */\r
+#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /* 2GB */\r
+#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /* 4GB */\r
\r
/* MPU_RASR_AP Bitfield Bits */\r
-#define MPU_RASR_AP_PRV_NO_USR_NO (0x00000000) /* Priviliged permissions: No access. User permissions: No access. */\r
-#define MPU_RASR_AP_PRV_RW_USR_NO (0x01000000) /* Priviliged permissions: Read-write. User permissions: No access. */\r
-#define MPU_RASR_AP_PRV_RW_USR_RO (0x02000000) /* Priviliged permissions: Read-write. User permissions: Read-only. */ \r
-#define MPU_RASR_AP_PRV_RW_USR_RW (0x03000000) /* Priviliged permissions: Read-write. User permissions: Read-write. */\r
-#define MPU_RASR_AP_PRV_RO_USR_NO (0x05000000) /* Priviliged permissions: Read-only. User permissions: No access. */\r
-#define MPU_RASR_AP_PRV_RO_USR_RO (0x06000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */\r
+#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /* Privileged permissions: No access. User permissions: No access. */\r
+#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /* Privileged permissions: Read-write. User permissions: No access. */\r
+#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /* Privileged permissions: Read-write. User permissions: Read-only. */\r
+#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /* Privileged permissions: Read-write. User permissions: Read-write. */\r
+#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /* Privileged permissions: Read-only. User permissions: No access. */\r
+#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /* Privileged permissions: Read-only. User permissions: Read-only. */\r
\r
/* MPU_RASR_XN Bitfield Bits */\r
-#define MPU_RASR_AP_EXEC (0x00000000) /* Instruction access enabled */ \r
-#define MPU_RASR_AP_NOEXEC (0x10000000) /* Instruction access disabled */\r
-\r
-\r
-//*****************************************************************************\r
-// NVIC Bits\r
-//*****************************************************************************\r
-/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */\r
-#define NVIC_IPR0_PRI_0_OFS ( 0) /* PRI_0 Offset */\r
-#define NVIC_IPR0_PRI_0_M (0x000000ff) /* */\r
-/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */\r
-#define NVIC_IPR0_PRI_1_OFS ( 8) /* PRI_1 Offset */\r
-#define NVIC_IPR0_PRI_1_M (0x0000ff00) /* */\r
-/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */\r
-#define NVIC_IPR0_PRI_2_OFS (16) /* PRI_2 Offset */\r
-#define NVIC_IPR0_PRI_2_M (0x00ff0000) /* */\r
-/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */\r
-#define NVIC_IPR0_PRI_3_OFS (24) /* PRI_3 Offset */\r
-#define NVIC_IPR0_PRI_3_M (0xff000000) /* */\r
-/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */\r
-#define NVIC_IPR1_PRI_4_OFS ( 0) /* PRI_4 Offset */\r
-#define NVIC_IPR1_PRI_4_M (0x000000ff) /* */\r
-/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */\r
-#define NVIC_IPR1_PRI_5_OFS ( 8) /* PRI_5 Offset */\r
-#define NVIC_IPR1_PRI_5_M (0x0000ff00) /* */\r
-/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */\r
-#define NVIC_IPR1_PRI_6_OFS (16) /* PRI_6 Offset */\r
-#define NVIC_IPR1_PRI_6_M (0x00ff0000) /* */\r
-/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */\r
-#define NVIC_IPR1_PRI_7_OFS (24) /* PRI_7 Offset */\r
-#define NVIC_IPR1_PRI_7_M (0xff000000) /* */\r
-/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */\r
-#define NVIC_IPR2_PRI_8_OFS ( 0) /* PRI_8 Offset */\r
-#define NVIC_IPR2_PRI_8_M (0x000000ff) /* */\r
-/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */\r
-#define NVIC_IPR2_PRI_9_OFS ( 8) /* PRI_9 Offset */\r
-#define NVIC_IPR2_PRI_9_M (0x0000ff00) /* */\r
-/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */\r
-#define NVIC_IPR2_PRI_10_OFS (16) /* PRI_10 Offset */\r
-#define NVIC_IPR2_PRI_10_M (0x00ff0000) /* */\r
-/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */\r
-#define NVIC_IPR2_PRI_11_OFS (24) /* PRI_11 Offset */\r
-#define NVIC_IPR2_PRI_11_M (0xff000000) /* */\r
-/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */\r
-#define NVIC_IPR3_PRI_12_OFS ( 0) /* PRI_12 Offset */\r
-#define NVIC_IPR3_PRI_12_M (0x000000ff) /* */\r
-/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */\r
-#define NVIC_IPR3_PRI_13_OFS ( 8) /* PRI_13 Offset */\r
-#define NVIC_IPR3_PRI_13_M (0x0000ff00) /* */\r
-/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */\r
-#define NVIC_IPR3_PRI_14_OFS (16) /* PRI_14 Offset */\r
-#define NVIC_IPR3_PRI_14_M (0x00ff0000) /* */\r
-/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */\r
-#define NVIC_IPR3_PRI_15_OFS (24) /* PRI_15 Offset */\r
-#define NVIC_IPR3_PRI_15_M (0xff000000) /* */\r
-/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */\r
-#define NVIC_IPR4_PRI_16_OFS ( 0) /* PRI_16 Offset */\r
-#define NVIC_IPR4_PRI_16_M (0x000000ff) /* */\r
-/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */\r
-#define NVIC_IPR4_PRI_17_OFS ( 8) /* PRI_17 Offset */\r
-#define NVIC_IPR4_PRI_17_M (0x0000ff00) /* */\r
-/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */\r
-#define NVIC_IPR4_PRI_18_OFS (16) /* PRI_18 Offset */\r
-#define NVIC_IPR4_PRI_18_M (0x00ff0000) /* */\r
-/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */\r
-#define NVIC_IPR4_PRI_19_OFS (24) /* PRI_19 Offset */\r
-#define NVIC_IPR4_PRI_19_M (0xff000000) /* */\r
-/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */\r
-#define NVIC_IPR5_PRI_20_OFS ( 0) /* PRI_20 Offset */\r
-#define NVIC_IPR5_PRI_20_M (0x000000ff) /* */\r
-/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */\r
-#define NVIC_IPR5_PRI_21_OFS ( 8) /* PRI_21 Offset */\r
-#define NVIC_IPR5_PRI_21_M (0x0000ff00) /* */\r
-/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */\r
-#define NVIC_IPR5_PRI_22_OFS (16) /* PRI_22 Offset */\r
-#define NVIC_IPR5_PRI_22_M (0x00ff0000) /* */\r
-/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */\r
-#define NVIC_IPR5_PRI_23_OFS (24) /* PRI_23 Offset */\r
-#define NVIC_IPR5_PRI_23_M (0xff000000) /* */\r
-/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */\r
-#define NVIC_IPR6_PRI_24_OFS ( 0) /* PRI_24 Offset */\r
-#define NVIC_IPR6_PRI_24_M (0x000000ff) /* */\r
-/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */\r
-#define NVIC_IPR6_PRI_25_OFS ( 8) /* PRI_25 Offset */\r
-#define NVIC_IPR6_PRI_25_M (0x0000ff00) /* */\r
-/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */\r
-#define NVIC_IPR6_PRI_26_OFS (16) /* PRI_26 Offset */\r
-#define NVIC_IPR6_PRI_26_M (0x00ff0000) /* */\r
-/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */\r
-#define NVIC_IPR6_PRI_27_OFS (24) /* PRI_27 Offset */\r
-#define NVIC_IPR6_PRI_27_M (0xff000000) /* */\r
-/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */\r
-#define NVIC_IPR7_PRI_28_OFS ( 0) /* PRI_28 Offset */\r
-#define NVIC_IPR7_PRI_28_M (0x000000ff) /* */\r
-/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */\r
-#define NVIC_IPR7_PRI_29_OFS ( 8) /* PRI_29 Offset */\r
-#define NVIC_IPR7_PRI_29_M (0x0000ff00) /* */\r
-/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */\r
-#define NVIC_IPR7_PRI_30_OFS (16) /* PRI_30 Offset */\r
-#define NVIC_IPR7_PRI_30_M (0x00ff0000) /* */\r
-/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */\r
-#define NVIC_IPR7_PRI_31_OFS (24) /* PRI_31 Offset */\r
-#define NVIC_IPR7_PRI_31_M (0xff000000) /* */\r
-/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */\r
-#define NVIC_IPR8_PRI_32_OFS ( 0) /* PRI_32 Offset */\r
-#define NVIC_IPR8_PRI_32_M (0x000000ff) /* */\r
-/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */\r
-#define NVIC_IPR8_PRI_33_OFS ( 8) /* PRI_33 Offset */\r
-#define NVIC_IPR8_PRI_33_M (0x0000ff00) /* */\r
-/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */\r
-#define NVIC_IPR8_PRI_34_OFS (16) /* PRI_34 Offset */\r
-#define NVIC_IPR8_PRI_34_M (0x00ff0000) /* */\r
-/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */\r
-#define NVIC_IPR8_PRI_35_OFS (24) /* PRI_35 Offset */\r
-#define NVIC_IPR8_PRI_35_M (0xff000000) /* */\r
-/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */\r
-#define NVIC_IPR9_PRI_36_OFS ( 0) /* PRI_36 Offset */\r
-#define NVIC_IPR9_PRI_36_M (0x000000ff) /* */\r
-/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */\r
-#define NVIC_IPR9_PRI_37_OFS ( 8) /* PRI_37 Offset */\r
-#define NVIC_IPR9_PRI_37_M (0x0000ff00) /* */\r
-/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */\r
-#define NVIC_IPR9_PRI_38_OFS (16) /* PRI_38 Offset */\r
-#define NVIC_IPR9_PRI_38_M (0x00ff0000) /* */\r
-/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */\r
-#define NVIC_IPR9_PRI_39_OFS (24) /* PRI_39 Offset */\r
-#define NVIC_IPR9_PRI_39_M (0xff000000) /* */\r
-/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */\r
-#define NVIC_IPR10_PRI_40_OFS ( 0) /* PRI_40 Offset */\r
-#define NVIC_IPR10_PRI_40_M (0x000000ff) /* */\r
-/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */\r
-#define NVIC_IPR10_PRI_41_OFS ( 8) /* PRI_41 Offset */\r
-#define NVIC_IPR10_PRI_41_M (0x0000ff00) /* */\r
-/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */\r
-#define NVIC_IPR10_PRI_42_OFS (16) /* PRI_42 Offset */\r
-#define NVIC_IPR10_PRI_42_M (0x00ff0000) /* */\r
-/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */\r
-#define NVIC_IPR10_PRI_43_OFS (24) /* PRI_43 Offset */\r
-#define NVIC_IPR10_PRI_43_M (0xff000000) /* */\r
-/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */\r
-#define NVIC_IPR11_PRI_44_OFS ( 0) /* PRI_44 Offset */\r
-#define NVIC_IPR11_PRI_44_M (0x000000ff) /* */\r
-/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */\r
-#define NVIC_IPR11_PRI_45_OFS ( 8) /* PRI_45 Offset */\r
-#define NVIC_IPR11_PRI_45_M (0x0000ff00) /* */\r
-/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */\r
-#define NVIC_IPR11_PRI_46_OFS (16) /* PRI_46 Offset */\r
-#define NVIC_IPR11_PRI_46_M (0x00ff0000) /* */\r
-/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */\r
-#define NVIC_IPR11_PRI_47_OFS (24) /* PRI_47 Offset */\r
-#define NVIC_IPR11_PRI_47_M (0xff000000) /* */\r
-/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */\r
-#define NVIC_IPR12_PRI_48_OFS ( 0) /* PRI_48 Offset */\r
-#define NVIC_IPR12_PRI_48_M (0x000000ff) /* */\r
-/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */\r
-#define NVIC_IPR12_PRI_49_OFS ( 8) /* PRI_49 Offset */\r
-#define NVIC_IPR12_PRI_49_M (0x0000ff00) /* */\r
-/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */\r
-#define NVIC_IPR12_PRI_50_OFS (16) /* PRI_50 Offset */\r
-#define NVIC_IPR12_PRI_50_M (0x00ff0000) /* */\r
-/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */\r
-#define NVIC_IPR12_PRI_51_OFS (24) /* PRI_51 Offset */\r
-#define NVIC_IPR12_PRI_51_M (0xff000000) /* */\r
-/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */\r
-#define NVIC_IPR13_PRI_52_OFS ( 0) /* PRI_52 Offset */\r
-#define NVIC_IPR13_PRI_52_M (0x000000ff) /* */\r
-/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */\r
-#define NVIC_IPR13_PRI_53_OFS ( 8) /* PRI_53 Offset */\r
-#define NVIC_IPR13_PRI_53_M (0x0000ff00) /* */\r
-/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */\r
-#define NVIC_IPR13_PRI_54_OFS (16) /* PRI_54 Offset */\r
-#define NVIC_IPR13_PRI_54_M (0x00ff0000) /* */\r
-/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */\r
-#define NVIC_IPR13_PRI_55_OFS (24) /* PRI_55 Offset */\r
-#define NVIC_IPR13_PRI_55_M (0xff000000) /* */\r
-/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */\r
-#define NVIC_IPR14_PRI_56_OFS ( 0) /* PRI_56 Offset */\r
-#define NVIC_IPR14_PRI_56_M (0x000000ff) /* */\r
-/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */\r
-#define NVIC_IPR14_PRI_57_OFS ( 8) /* PRI_57 Offset */\r
-#define NVIC_IPR14_PRI_57_M (0x0000ff00) /* */\r
-/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */\r
-#define NVIC_IPR14_PRI_58_OFS (16) /* PRI_58 Offset */\r
-#define NVIC_IPR14_PRI_58_M (0x00ff0000) /* */\r
-/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */\r
-#define NVIC_IPR14_PRI_59_OFS (24) /* PRI_59 Offset */\r
-#define NVIC_IPR14_PRI_59_M (0xff000000) /* */\r
-/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */\r
-#define NVIC_IPR15_PRI_60_OFS ( 0) /* PRI_60 Offset */\r
-#define NVIC_IPR15_PRI_60_M (0x000000ff) /* */\r
-/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */\r
-#define NVIC_IPR15_PRI_61_OFS ( 8) /* PRI_61 Offset */\r
-#define NVIC_IPR15_PRI_61_M (0x0000ff00) /* */\r
-/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */\r
-#define NVIC_IPR15_PRI_62_OFS (16) /* PRI_62 Offset */\r
-#define NVIC_IPR15_PRI_62_M (0x00ff0000) /* */\r
-/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */\r
-#define NVIC_IPR15_PRI_63_OFS (24) /* PRI_63 Offset */\r
-#define NVIC_IPR15_PRI_63_M (0xff000000) /* */\r
-/* NVIC_STIR[NVIC_STIR_INTID] Bits */\r
-#define NVIC_STIR_INTID_OFS ( 0) /* INTID Offset */\r
-#define NVIC_STIR_INTID_M (0x000001ff) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// PCM Bits\r
-//*****************************************************************************\r
-/* PCMCTL0[AMR] Bits */\r
-#define AMR_OFS ( 0) /* AMR Offset */\r
-#define AMR_M (0x0000000f) /* Active Mode Request */\r
-#define AMR0 (0x00000001) /* Active Mode Request */\r
-#define AMR1 (0x00000002) /* Active Mode Request */\r
-#define AMR2 (0x00000004) /* Active Mode Request */\r
-#define AMR3 (0x00000008) /* Active Mode Request */\r
-#define AMR_0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */\r
-#define AMR_1 (0x00000001) /* LDO based Active Mode at Core voltage setting 1. */\r
-#define AMR_4 (0x00000004) /* DC-DC based Active Mode at Core voltage setting 0. */\r
-#define AMR_5 (0x00000005) /* DC-DC based Active Mode at Core voltage setting 1. */\r
-#define AMR_8 (0x00000008) /* Low-Frequency Active Mode at Core voltage setting 0. */\r
-#define AMR_9 (0x00000009) /* Low-Frequency Active Mode at Core voltage setting 1. */\r
-#define AMR__AM_LDO_VCORE0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */\r
-#define AMR__AM_LDO_VCORE1 (0x00000001) /* LDO based Active Mode at Core voltage setting 1. */\r
-#define AMR__AM_DCDC_VCORE0 (0x00000004) /* DC-DC based Active Mode at Core voltage setting 0. */\r
-#define AMR__AM_DCDC_VCORE1 (0x00000005) /* DC-DC based Active Mode at Core voltage setting 1. */\r
-#define AMR__AM_LF_VCORE0 (0x00000008) /* Low-Frequency Active Mode at Core voltage setting 0. */\r
-#define AMR__AM_LF_VCORE1 (0x00000009) /* Low-Frequency Active Mode at Core voltage setting 1. */\r
-/* PCMCTL0[LPMR] Bits */\r
-#define LPMR_OFS ( 4) /* LPMR Offset */\r
-#define LPMR_M (0x000000f0) /* Low Power Mode Request */\r
-#define LPMR0 (0x00000010) /* Low Power Mode Request */\r
-#define LPMR1 (0x00000020) /* Low Power Mode Request */\r
-#define LPMR2 (0x00000040) /* Low Power Mode Request */\r
-#define LPMR3 (0x00000080) /* Low Power Mode Request */\r
-#define LPMR_0 (0x00000000) /* LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */\r
-#define LPMR_10 (0x000000a0) /* LPM3.5. Core voltage setting 0. */\r
-#define LPMR_12 (0x000000c0) /* LPM4.5 */\r
-#define LPMR__LPM3 (0x00000000) /* LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */\r
-#define LPMR__LPM35 (0x000000a0) /* LPM3.5. Core voltage setting 0. */\r
-#define LPMR__LPM45 (0x000000c0) /* LPM4.5 */\r
-/* PCMCTL0[CPM] Bits */\r
-#define CPM_OFS ( 8) /* CPM Offset */\r
-#define CPM_M (0x00003f00) /* Current Power Mode */\r
-#define CPM0 (0x00000100) /* Current Power Mode */\r
-#define CPM1 (0x00000200) /* Current Power Mode */\r
-#define CPM2 (0x00000400) /* Current Power Mode */\r
-#define CPM3 (0x00000800) /* Current Power Mode */\r
-#define CPM4 (0x00001000) /* Current Power Mode */\r
-#define CPM5 (0x00002000) /* Current Power Mode */\r
-#define CPM_0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */\r
-#define CPM_1 (0x00000100) /* LDO based Active Mode at Core voltage setting 1. */\r
-#define CPM_4 (0x00000400) /* DC-DC based Active Mode at Core voltage setting 0. */\r
-#define CPM_5 (0x00000500) /* DC-DC based Active Mode at Core voltage setting 1. */\r
-#define CPM_8 (0x00000800) /* Low-Frequency Active Mode at Core voltage setting 0. */\r
-#define CPM_9 (0x00000900) /* Low-Frequency Active Mode at Core voltage setting 1. */\r
-#define CPM_16 (0x00001000) /* LDO based LPM0 at Core voltage setting 0. */\r
-#define CPM_17 (0x00001100) /* LDO based LPM0 at Core voltage setting 1. */\r
-#define CPM_20 (0x00001400) /* DC-DC based LPM0 at Core voltage setting 0. */\r
-#define CPM_21 (0x00001500) /* DC-DC based LPM0 at Core voltage setting 1. */\r
-#define CPM_24 (0x00001800) /* Low-Frequency LPM0 at Core voltage setting 0. */\r
-#define CPM_25 (0x00001900) /* Low-Frequency LPM0 at Core voltage setting 1. */\r
-#define CPM_32 (0x00002000) /* LPM3 */\r
-#define CPM__AM_LDO_VCORE0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */\r
-#define CPM__AM_LDO_VCORE1 (0x00000100) /* LDO based Active Mode at Core voltage setting 1. */\r
-#define CPM__AM_DCDC_VCORE0 (0x00000400) /* DC-DC based Active Mode at Core voltage setting 0. */\r
-#define CPM__AM_DCDC_VCORE1 (0x00000500) /* DC-DC based Active Mode at Core voltage setting 1. */\r
-#define CPM__AM_LF_VCORE0 (0x00000800) /* Low-Frequency Active Mode at Core voltage setting 0. */\r
-#define CPM__AM_LF_VCORE1 (0x00000900) /* Low-Frequency Active Mode at Core voltage setting 1. */\r
-#define CPM__LPM0_LDO_VCORE0 (0x00001000) /* LDO based LPM0 at Core voltage setting 0. */\r
-#define CPM__LPM0_LDO_VCORE1 (0x00001100) /* LDO based LPM0 at Core voltage setting 1. */\r
-#define CPM__LPM0_DCDC_VCORE0 (0x00001400) /* DC-DC based LPM0 at Core voltage setting 0. */\r
-#define CPM__LPM0_DCDC_VCORE1 (0x00001500) /* DC-DC based LPM0 at Core voltage setting 1. */\r
-#define CPM__LPM0_LF_VCORE0 (0x00001800) /* Low-Frequency LPM0 at Core voltage setting 0. */\r
-#define CPM__LPM0_LF_VCORE1 (0x00001900) /* Low-Frequency LPM0 at Core voltage setting 1. */\r
-#define CPM__LPM3 (0x00002000) /* LPM3 */\r
-/* PCMCTL0[PCMKEY] Bits */\r
-#define PCMKEY_OFS (16) /* PCMKEY Offset */\r
-#define PCMKEY_M (0xffff0000) /* PCM key */\r
-/* PCMCTL1[LOCKLPM5] Bits */\r
-#define LOCKLPM5_OFS ( 0) /* LOCKLPM5 Offset */\r
-#define LOCKLPM5 (0x00000001) /* Lock LPM5 */\r
-/* PCMCTL1[LOCKBKUP] Bits */\r
-#define LOCKBKUP_OFS ( 1) /* LOCKBKUP Offset */\r
-#define LOCKBKUP (0x00000002) /* Lock Backup */\r
-/* PCMCTL1[FORCE_LPM_ENTRY] Bits */\r
-#define FORCE_LPM_ENTRY_OFS ( 2) /* FORCE_LPM_ENTRY Offset */\r
-#define FORCE_LPM_ENTRY (0x00000004) /* Force LPM entry */\r
-/* PCMCTL1[PMR_BUSY] Bits */\r
-#define PMR_BUSY_OFS ( 8) /* PMR_BUSY Offset */\r
-#define PMR_BUSY (0x00000100) /* Power mode request busy flag */\r
-/* PCMCTL1[PCMKEY] Bits */\r
-//#define PCMKEY_OFS (16) /* PCMKEY Offset */\r
-//#define PCMKEY_M (0xffff0000) /* PCM key */\r
-/* PCMIE[LPM_INVALID_TR_IE] Bits */\r
-#define LPM_INVALID_TR_IE_OFS ( 0) /* LPM_INVALID_TR_IE Offset */\r
-#define LPM_INVALID_TR_IE (0x00000001) /* LPM invalid transition interrupt enable */\r
-/* PCMIE[LPM_INVALID_CLK_IE] Bits */\r
-#define LPM_INVALID_CLK_IE_OFS ( 1) /* LPM_INVALID_CLK_IE Offset */\r
-#define LPM_INVALID_CLK_IE (0x00000002) /* LPM invalid clock interrupt enable */\r
-/* PCMIE[AM_INVALID_TR_IE] Bits */\r
-#define AM_INVALID_TR_IE_OFS ( 2) /* AM_INVALID_TR_IE Offset */\r
-#define AM_INVALID_TR_IE (0x00000004) /* Active mode invalid transition interrupt enable */\r
-/* PCMIE[DCDC_ERROR_IE] Bits */\r
-#define DCDC_ERROR_IE_OFS ( 6) /* DCDC_ERROR_IE Offset */\r
-#define DCDC_ERROR_IE (0x00000040) /* DC-DC error interrupt enable */\r
-/* PCMIFG[LPM_INVALID_TR_IFG] Bits */\r
-#define LPM_INVALID_TR_IFG_OFS ( 0) /* LPM_INVALID_TR_IFG Offset */\r
-#define LPM_INVALID_TR_IFG (0x00000001) /* LPM invalid transition flag */\r
-/* PCMIFG[LPM_INVALID_CLK_IFG] Bits */\r
-#define LPM_INVALID_CLK_IFG_OFS ( 1) /* LPM_INVALID_CLK_IFG Offset */\r
-#define LPM_INVALID_CLK_IFG (0x00000002) /* LPM invalid clock flag */\r
-/* PCMIFG[AM_INVALID_TR_IFG] Bits */\r
-#define AM_INVALID_TR_IFG_OFS ( 2) /* AM_INVALID_TR_IFG Offset */\r
-#define AM_INVALID_TR_IFG (0x00000004) /* Active mode invalid transition flag */\r
-/* PCMIFG[DCDC_ERROR_IFG] Bits */\r
-#define DCDC_ERROR_IFG_OFS ( 6) /* DCDC_ERROR_IFG Offset */\r
-#define DCDC_ERROR_IFG (0x00000040) /* DC-DC error flag */\r
-/* PCMCLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */\r
-#define CLR_LPM_INVALID_TR_IFG_OFS ( 0) /* CLR_LPM_INVALID_TR_IFG Offset */\r
-#define CLR_LPM_INVALID_TR_IFG (0x00000001) /* Clear LPM invalid transition flag */\r
-/* PCMCLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */\r
-#define CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /* CLR_LPM_INVALID_CLK_IFG Offset */\r
-#define CLR_LPM_INVALID_CLK_IFG (0x00000002) /* Clear LPM invalid clock flag */\r
-/* PCMCLRIFG[CLR_AM_INVALID_TR_IFG] Bits */\r
-#define CLR_AM_INVALID_TR_IFG_OFS ( 2) /* CLR_AM_INVALID_TR_IFG Offset */\r
-#define CLR_AM_INVALID_TR_IFG (0x00000004) /* Clear active mode invalid transition flag */\r
-/* PCMCLRIFG[CLR_DCDC_ERROR_IFG] Bits */\r
-#define CLR_DCDC_ERROR_IFG_OFS ( 6) /* CLR_DCDC_ERROR_IFG Offset */\r
-#define CLR_DCDC_ERROR_IFG (0x00000040) /* Clear DC-DC error flag */\r
+#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /* Instruction access enabled */\r
+#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /* Instruction access disabled */\r
+\r
+\r
+/******************************************************************************\r
+* NVIC Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* PCM Bits\r
+******************************************************************************/\r
+/* PCM_CTL0[AMR] Bits */\r
+#define PCM_CTL0_AMR_OFS ( 0) /**< AMR Bit Offset */\r
+#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /**< AMR Bit Mask */\r
+#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /**< AMR Bit 0 */\r
+#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /**< AMR Bit 1 */\r
+#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /**< AMR Bit 2 */\r
+#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /**< AMR Bit 3 */\r
+#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /**< LDO based Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /**< DC-DC based Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /**< DC-DC based Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /**< Low-Frequency Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /**< Low-Frequency Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /**< LDO based Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /**< DC-DC based Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /**< DC-DC based Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /**< Low-Frequency Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /**< Low-Frequency Active Mode at Core voltage setting 1. */\r
+/* PCM_CTL0[LPMR] Bits */\r
+#define PCM_CTL0_LPMR_OFS ( 4) /**< LPMR Bit Offset */\r
+#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /**< LPMR Bit Mask */\r
+#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /**< LPMR Bit 0 */\r
+#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /**< LPMR Bit 1 */\r
+#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /**< LPMR Bit 2 */\r
+#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /**< LPMR Bit 3 */\r
+#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /**< LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */\r
+#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /**< LPM3.5. Core voltage setting 0. */\r
+#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /**< LPM4.5 */\r
+#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /**< LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */\r
+#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /**< LPM3.5. Core voltage setting 0. */\r
+#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /**< LPM4.5 */\r
+/* PCM_CTL0[CPM] Bits */\r
+#define PCM_CTL0_CPM_OFS ( 8) /**< CPM Bit Offset */\r
+#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /**< CPM Bit Mask */\r
+#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /**< CPM Bit 0 */\r
+#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /**< CPM Bit 1 */\r
+#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /**< CPM Bit 2 */\r
+#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /**< CPM Bit 3 */\r
+#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /**< CPM Bit 4 */\r
+#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /**< CPM Bit 5 */\r
+#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /**< LDO based Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /**< DC-DC based Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /**< DC-DC based Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /**< Low-Frequency Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /**< Low-Frequency Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /**< LDO based LPM0 at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /**< LDO based LPM0 at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /**< DC-DC based LPM0 at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /**< DC-DC based LPM0 at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /**< Low-Frequency LPM0 at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /**< Low-Frequency LPM0 at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /**< LPM3 */\r
+#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /**< LDO based Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /**< DC-DC based Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /**< DC-DC based Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /**< Low-Frequency Active Mode at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /**< Low-Frequency Active Mode at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /**< LDO based LPM0 at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /**< LDO based LPM0 at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /**< DC-DC based LPM0 at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /**< DC-DC based LPM0 at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /**< Low-Frequency LPM0 at Core voltage setting 0. */\r
+#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /**< Low-Frequency LPM0 at Core voltage setting 1. */\r
+#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /**< LPM3 */\r
+/* PCM_CTL0[KEY] Bits */\r
+#define PCM_CTL0_KEY_OFS (16) /**< PCMKEY Bit Offset */\r
+#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /**< PCMKEY Bit Mask */\r
+/* PCM_CTL1[LOCKLPM5] Bits */\r
+#define PCM_CTL1_LOCKLPM5_OFS ( 0) /**< LOCKLPM5 Bit Offset */\r
+#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /**< Lock LPM5 */\r
+/* PCM_CTL1[LOCKBKUP] Bits */\r
+#define PCM_CTL1_LOCKBKUP_OFS ( 1) /**< LOCKBKUP Bit Offset */\r
+#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /**< Lock Backup */\r
+/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */\r
+#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /**< FORCE_LPM_ENTRY Bit Offset */\r
+#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /**< Force LPM entry */\r
+/* PCM_CTL1[PMR_BUSY] Bits */\r
+#define PCM_CTL1_PMR_BUSY_OFS ( 8) /**< PMR_BUSY Bit Offset */\r
+#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /**< Power mode request busy flag */\r
+/* PCM_CTL1[KEY] Bits */\r
+#define PCM_CTL1_KEY_OFS (16) /**< PCMKEY Bit Offset */\r
+#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /**< PCMKEY Bit Mask */\r
+/* PCM_IE[LPM_INVALID_TR_IE] Bits */\r
+#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /**< LPM_INVALID_TR_IE Bit Offset */\r
+#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /**< LPM invalid transition interrupt enable */\r
+/* PCM_IE[LPM_INVALID_CLK_IE] Bits */\r
+#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /**< LPM_INVALID_CLK_IE Bit Offset */\r
+#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /**< LPM invalid clock interrupt enable */\r
+/* PCM_IE[AM_INVALID_TR_IE] Bits */\r
+#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /**< AM_INVALID_TR_IE Bit Offset */\r
+#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /**< Active mode invalid transition interrupt enable */\r
+/* PCM_IE[DCDC_ERROR_IE] Bits */\r
+#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /**< DCDC_ERROR_IE Bit Offset */\r
+#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /**< DC-DC error interrupt enable */\r
+/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */\r
+#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /**< LPM_INVALID_TR_IFG Bit Offset */\r
+#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /**< LPM invalid transition flag */\r
+/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */\r
+#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /**< LPM_INVALID_CLK_IFG Bit Offset */\r
+#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /**< LPM invalid clock flag */\r
+/* PCM_IFG[AM_INVALID_TR_IFG] Bits */\r
+#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /**< AM_INVALID_TR_IFG Bit Offset */\r
+#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /**< Active mode invalid transition flag */\r
+/* PCM_IFG[DCDC_ERROR_IFG] Bits */\r
+#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /**< DCDC_ERROR_IFG Bit Offset */\r
+#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /**< DC-DC error flag */\r
+/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */\r
+#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /**< CLR_LPM_INVALID_TR_IFG Bit Offset */\r
+#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /**< Clear LPM invalid transition flag */\r
+/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */\r
+#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /**< CLR_LPM_INVALID_CLK_IFG Bit Offset */\r
+#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /**< Clear LPM invalid clock flag */\r
+/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */\r
+#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /**< CLR_AM_INVALID_TR_IFG Bit Offset */\r
+#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /**< Clear active mode invalid transition flag */\r
+/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */\r
+#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /**< CLR_DCDC_ERROR_IFG Bit Offset */\r
+#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /**< Clear DC-DC error flag */\r
\r
/* Pre-defined bitfield values */\r
-#define PCM_PMR_KEY_VAL (0x695A0000) /* PCM key value */\r
-#define PCM_CTL_KEY_VAL (0x695A0000) /* PCM key value */\r
+#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /* PCM key value */\r
+#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /* PCM key value */\r
\r
\r
-//*****************************************************************************\r
-// PMAP Bits\r
-//*****************************************************************************\r
-/* PMAPCTL[PMAPLOCKED] Bits */\r
-#define PMAPLOCKED_OFS ( 0) /* PMAPLOCKED Offset */\r
-#define PMAPLOCKED (0x0001) /* Port mapping lock bit */\r
-/* PMAPCTL[PMAPRECFG] Bits */\r
-#define PMAPRECFG_OFS ( 1) /* PMAPRECFG Offset */\r
-#define PMAPRECFG (0x0002) /* Port mapping reconfiguration control bit */\r
+/******************************************************************************\r
+* PMAP Bits\r
+******************************************************************************/\r
+/* PMAP_CTL[LOCKED] Bits */\r
+#define PMAP_CTL_LOCKED_OFS ( 0) /**< PMAPLOCKED Bit Offset */\r
+#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /**< Port mapping lock bit */\r
+/* PMAP_CTL[PRECFG] Bits */\r
+#define PMAP_CTL_PRECFG_OFS ( 1) /**< PMAPRECFG Bit Offset */\r
+#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /**< Port mapping reconfiguration control bit */\r
\r
/* Pre-defined bitfield values */\r
-#define PM_NONE 0\r
-#define PM_UCA0CLK 1\r
-#define PM_UCA0RXD 2\r
-#define PM_UCA0SOMI 2\r
-#define PM_UCA0TXD 3\r
-#define PM_UCA0SIMO 3\r
-#define PM_UCB0CLK 4\r
-#define PM_UCB0SDA 5\r
-#define PM_UCB0SIMO 5\r
-#define PM_UCB0SCL 6\r
-#define PM_UCB0SOMI 6\r
-#define PM_UCA1STE 7 \r
-#define PM_UCA1CLK 8\r
-#define PM_UCA1RXD 9\r
-#define PM_UCA1SOMI 9\r
-#define PM_UCA1TXD 10\r
-#define PM_UCA1SIMO 10\r
-#define PM_UCA2STE 11\r
-#define PM_UCA2CLK 12\r
-#define PM_UCA2RXD 13\r
-#define PM_UCA2SOMI 13\r
-#define PM_UCA2TXD 14\r
-#define PM_UCA2SIMO 14\r
-#define PM_UCB2STE 15\r
-#define PM_UCB2CLK 16\r
-#define PM_UCB2SDA 17\r
-#define PM_UCB2SIMO 17\r
-#define PM_UCB2SCL 18\r
-#define PM_UCB2SOMI 18\r
-#define PM_TA0CCR0A 19\r
-#define PM_TA0CCR1A 20\r
-#define PM_TA0CCR2A 21\r
-#define PM_TA0CCR3A 22\r
-#define PM_TA0CCR4A 23\r
-#define PM_TA1CCR1A 24\r
-#define PM_TA1CCR2A 25\r
-#define PM_TA1CCR3A 26\r
-#define PM_TA1CCR4A 27\r
-#define PM_TA0CLK 28\r
-#define PM_CE0OUT 28\r
-#define PM_TA1CLK 29\r
-#define PM_CE1OUT 29\r
-#define PM_DMAE0 30\r
-#define PM_SMCLK 30\r
-#define PM_ANALOG 31\r
-\r
-#define PMAP_KEYID_VAL (0x2D52) /* Port mapping controller write access key */\r
- \r
-\r
-//*****************************************************************************\r
-// PSS Bits\r
-//*****************************************************************************\r
-/* PSSKEY[PSSKEY] Bits */\r
-#define PSSKEY_OFS ( 0) /* PSSKEY Offset */\r
-#define PSSKEY_M (0x0000ffff) /* PSS control key */\r
-/* PSSCTL0[SVSMHOFF] Bits */\r
-#define SVSMHOFF_OFS ( 0) /* SVSMHOFF Offset */\r
-#define SVSMHOFF (0x00000001) /* SVSM high-side off */\r
-/* PSSCTL0[SVSMHLP] Bits */\r
-#define SVSMHLP_OFS ( 1) /* SVSMHLP Offset */\r
-#define SVSMHLP (0x00000002) /* SVSM high-side low power normal performance mode */\r
-/* PSSCTL0[SVSMHS] Bits */\r
-#define SVSMHS_OFS ( 2) /* SVSMHS Offset */\r
-#define SVSMHS (0x00000004) /* Supply supervisor or monitor selection for the high-side */\r
-/* PSSCTL0[SVSMHTH] Bits */\r
-#define SVSMHTH_OFS ( 3) /* SVSMHTH Offset */\r
-#define SVSMHTH_M (0x00000038) /* SVSM high-side reset voltage level */\r
-/* PSSCTL0[SVMHOE] Bits */\r
-#define SVMHOE_OFS ( 6) /* SVMHOE Offset */\r
-#define SVMHOE (0x00000040) /* SVSM high-side output enable */\r
-/* PSSCTL0[SVMHOUTPOLAL] Bits */\r
-#define SVMHOUTPOLAL_OFS ( 7) /* SVMHOUTPOLAL Offset */\r
-#define SVMHOUTPOLAL (0x00000080) /* SVMHOUT pin polarity active low */\r
-/* PSSCTL0[SVSLOFF] Bits */\r
-#define SVSLOFF_OFS ( 8) /* SVSLOFF Offset */\r
-#define SVSLOFF (0x00000100) /* SVS low-side off */\r
-/* PSSCTL0[SVSLLP] Bits */\r
-#define SVSLLP_OFS ( 9) /* SVSLLP Offset */\r
-#define SVSLLP (0x00000200) /* SVS low-side low power normal performance mode */\r
-/* PSSCTL0[DCDC_FORCE] Bits */\r
-#define DCDC_FORCE_OFS (10) /* DCDC_FORCE Offset */\r
-#define DCDC_FORCE (0x00000400) /* Disables automatic supply voltage detection */\r
-/* PSSCTL0[VCORETRAN] Bits */\r
-#define VCORETRAN_OFS (12) /* VCORETRAN Offset */\r
-#define VCORETRAN_M (0x00003000) /* Controls VCORE Level Transition time */\r
-#define VCORETRAN0 (0x00001000) /* Controls VCORE Level Transition time */\r
-#define VCORETRAN1 (0x00002000) /* Controls VCORE Level Transition time */\r
-#define VCORETRAN_0 (0x00000000) /* 32 ?s / 100 mV */\r
-#define VCORETRAN_1 (0x00001000) /* 64 ?s / 100 mV */\r
-#define VCORETRAN_2 (0x00002000) /* 128 ?s / 100 mV (default) */\r
-#define VCORETRAN_3 (0x00003000) /* 256 ?s / 100 mV */\r
-#define VCORETRAN__32 (0x00000000) /* 32 ?s / 100 mV */\r
-#define VCORETRAN__64 (0x00001000) /* 64 ?s / 100 mV */\r
-#define VCORETRAN__128 (0x00002000) /* 128 ?s / 100 mV (default) */\r
-#define VCORETRAN__256 (0x00003000) /* 256 ?s / 100 mV */\r
-/* PSSIE[SVSMHIE] Bits */\r
-#define SVSMHIE_OFS ( 1) /* SVSMHIE Offset */\r
-#define SVSMHIE (0x00000002) /* High-side SVSM interrupt enable */\r
-/* PSSIFG[SVSMHIFG] Bits */\r
-#define SVSMHIFG_OFS ( 1) /* SVSMHIFG Offset */\r
-#define SVSMHIFG (0x00000002) /* High-side SVSM interrupt flag */\r
-/* PSSCLRIFG[CLRSVSMHIFG] Bits */\r
-#define CLRSVSMHIFG_OFS ( 1) /* CLRSVSMHIFG Offset */\r
-#define CLRSVSMHIFG (0x00000002) /* SVSMH clear interrupt flag */\r
+#define PMAP_NONE 0\r
+#define PMAP_UCA0CLK 1\r
+#define PMAP_UCA0RXD 2\r
+#define PMAP_UCA0SOMI 2\r
+#define PMAP_UCA0TXD 3\r
+#define PMAP_UCA0SIMO 3\r
+#define PMAP_UCB0CLK 4\r
+#define PMAP_UCB0SDA 5\r
+#define PMAP_UCB0SIMO 5\r
+#define PMAP_UCB0SCL 6\r
+#define PMAP_UCB0SOMI 6\r
+#define PMAP_UCA1STE 7\r
+#define PMAP_UCA1CLK 8\r
+#define PMAP_UCA1RXD 9\r
+#define PMAP_UCA1SOMI 9\r
+#define PMAP_UCA1TXD 10\r
+#define PMAP_UCA1SIMO 10\r
+#define PMAP_UCA2STE 11\r
+#define PMAP_UCA2CLK 12\r
+#define PMAP_UCA2RXD 13\r
+#define PMAP_UCA2SOMI 13\r
+#define PMAP_UCA2TXD 14\r
+#define PMAP_UCA2SIMO 14\r
+#define PMAP_UCB2STE 15\r
+#define PMAP_UCB2CLK 16\r
+#define PMAP_UCB2SDA 17\r
+#define PMAP_UCB2SIMO 17\r
+#define PMAP_UCB2SCL 18\r
+#define PMAP_UCB2SOMI 18\r
+#define PMAP_TA0CCR0A 19\r
+#define PMAP_TA0CCR1A 20\r
+#define PMAP_TA0CCR2A 21\r
+#define PMAP_TA0CCR3A 22\r
+#define PMAP_TA0CCR4A 23\r
+#define PMAP_TA1CCR1A 24\r
+#define PMAP_TA1CCR2A 25\r
+#define PMAP_TA1CCR3A 26\r
+#define PMAP_TA1CCR4A 27\r
+#define PMAP_TA0CLK 28\r
+#define PMAP_CE0OUT 28\r
+#define PMAP_TA1CLK 29\r
+#define PMAP_CE1OUT 29\r
+#define PMAP_DMAE0 30\r
+#define PMAP_SMCLK 30\r
+#define PMAP_ANALOG 31\r
+\r
+#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /**< Port Mapping Key */\r
+\r
+\r
+/******************************************************************************\r
+* PSS Bits\r
+******************************************************************************/\r
+/* PSS_KEY[KEY] Bits */\r
+#define PSS_KEY_KEY_OFS ( 0) /**< PSSKEY Bit Offset */\r
+#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /**< PSSKEY Bit Mask */\r
+/* PSS_CTL0[SVSMHOFF] Bits */\r
+#define PSS_CTL0_SVSMHOFF_OFS ( 0) /**< SVSMHOFF Bit Offset */\r
+#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /**< SVSM high-side off */\r
+/* PSS_CTL0[SVSMHLP] Bits */\r
+#define PSS_CTL0_SVSMHLP_OFS ( 1) /**< SVSMHLP Bit Offset */\r
+#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /**< SVSM high-side low power normal performance mode */\r
+/* PSS_CTL0[SVSMHS] Bits */\r
+#define PSS_CTL0_SVSMHS_OFS ( 2) /**< SVSMHS Bit Offset */\r
+#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /**< Supply supervisor or monitor selection for the high-side */\r
+/* PSS_CTL0[SVSMHTH] Bits */\r
+#define PSS_CTL0_SVSMHTH_OFS ( 3) /**< SVSMHTH Bit Offset */\r
+#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /**< SVSMHTH Bit Mask */\r
+/* PSS_CTL0[SVMHOE] Bits */\r
+#define PSS_CTL0_SVMHOE_OFS ( 6) /**< SVMHOE Bit Offset */\r
+#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /**< SVSM high-side output enable */\r
+/* PSS_CTL0[SVMHOUTPOLAL] Bits */\r
+#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /**< SVMHOUTPOLAL Bit Offset */\r
+#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /**< SVMHOUT pin polarity active low */\r
+/* PSS_CTL0[DCDC_FORCE] Bits */\r
+#define PSS_CTL0_DCDC_FORCE_OFS (10) /**< DCDC_FORCE Bit Offset */\r
+#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /**< Force DC-DC regulator operation */\r
+/* PSS_CTL0[VCORETRAN] Bits */\r
+#define PSS_CTL0_VCORETRAN_OFS (12) /**< VCORETRAN Bit Offset */\r
+#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /**< VCORETRAN Bit Mask */\r
+#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /**< VCORETRAN Bit 0 */\r
+#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /**< VCORETRAN Bit 1 */\r
+#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /**< 32 ?s / 100 mV */\r
+#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /**< 64 ?s / 100 mV */\r
+#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /**< 128 ?s / 100 mV (default) */\r
+#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /**< 256 ?s / 100 mV */\r
+#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /**< 32 ?s / 100 mV */\r
+#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /**< 64 ?s / 100 mV */\r
+#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /**< 128 ?s / 100 mV (default) */\r
+#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /**< 256 ?s / 100 mV */\r
+/* PSS_IE[SVSMHIE] Bits */\r
+#define PSS_IE_SVSMHIE_OFS ( 1) /**< SVSMHIE Bit Offset */\r
+#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /**< High-side SVSM interrupt enable */\r
+/* PSS_IFG[SVSMHIFG] Bits */\r
+#define PSS_IFG_SVSMHIFG_OFS ( 1) /**< SVSMHIFG Bit Offset */\r
+#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /**< High-side SVSM interrupt flag */\r
+/* PSS_CLRIFG[CLRSVSMHIFG] Bits */\r
+#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /**< CLRSVSMHIFG Bit Offset */\r
+#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /**< SVSMH clear interrupt flag */\r
\r
/* Pre-defined bitfield values */\r
-#define PSS_KEY_KEY_VAL (0x0000695A) /* PSS control key value */\r
-\r
-\r
-//*****************************************************************************\r
-// REF_A Bits\r
-//*****************************************************************************\r
-/* REFCTL0[REFON] Bits */\r
-#define REFON_OFS ( 0) /* REFON Offset */\r
-#define REFON (0x0001) /* Reference enable */\r
-/* REFCTL0[REFOUT] Bits */\r
-#define REFOUT_OFS ( 1) /* REFOUT Offset */\r
-#define REFOUT (0x0002) /* Reference output buffer */\r
-/* REFCTL0[REFTCOFF] Bits */\r
-#define REFTCOFF_OFS ( 3) /* REFTCOFF Offset */\r
-#define REFTCOFF (0x0008) /* Temperature sensor disabled */\r
-/* REFCTL0[REFVSEL] Bits */\r
-#define REFVSEL_OFS ( 4) /* REFVSEL Offset */\r
-#define REFVSEL_M (0x0030) /* Reference voltage level select */\r
-#define REFVSEL0 (0x0010) /* Reference voltage level select */\r
-#define REFVSEL1 (0x0020) /* Reference voltage level select */\r
-#define REFVSEL_0 (0x0000) /* 1.2 V available when reference requested or REFON = 1 */\r
-#define REFVSEL_1 (0x0010) /* 1.45 V available when reference requested or REFON = 1 */\r
-#define REFVSEL_3 (0x0030) /* 2.5 V available when reference requested or REFON = 1 */\r
-/* REFCTL0[REFGENOT] Bits */\r
-#define REFGENOT_OFS ( 6) /* REFGENOT Offset */\r
-#define REFGENOT (0x0040) /* Reference generator one-time trigger */\r
-/* REFCTL0[REFBGOT] Bits */\r
-#define REFBGOT_OFS ( 7) /* REFBGOT Offset */\r
-#define REFBGOT (0x0080) /* Bandgap and bandgap buffer one-time trigger */\r
-/* REFCTL0[REFGENACT] Bits */\r
-#define REFGENACT_OFS ( 8) /* REFGENACT Offset */\r
-#define REFGENACT (0x0100) /* Reference generator active */\r
-/* REFCTL0[REFBGACT] Bits */\r
-#define REFBGACT_OFS ( 9) /* REFBGACT Offset */\r
-#define REFBGACT (0x0200) /* Reference bandgap active */\r
-/* REFCTL0[REFGENBUSY] Bits */\r
-#define REFGENBUSY_OFS (10) /* REFGENBUSY Offset */\r
-#define REFGENBUSY (0x0400) /* Reference generator busy */\r
-/* REFCTL0[BGMODE] Bits */\r
-#define BGMODE_OFS (11) /* BGMODE Offset */\r
-#define BGMODE (0x0800) /* Bandgap mode */\r
-/* REFCTL0[REFGENRDY] Bits */\r
-#define REFGENRDY_OFS (12) /* REFGENRDY Offset */\r
-#define REFGENRDY (0x1000) /* Variable reference voltage ready status */\r
-/* REFCTL0[REFBGRDY] Bits */\r
-#define REFBGRDY_OFS (13) /* REFBGRDY Offset */\r
-#define REFBGRDY (0x2000) /* Buffered bandgap voltage ready status */\r
-\r
-\r
-//*****************************************************************************\r
-// RSTCTL Bits\r
-//*****************************************************************************\r
-/* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_SOFT_REQ] Bits */\r
-#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /* SOFT_REQ Offset */\r
-#define RSTCTL_RESET_REQ_SOFT_REQ (0x00000001) /* Soft Reset request */\r
-/* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_HARD_REQ] Bits */\r
-#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /* HARD_REQ Offset */\r
-#define RSTCTL_RESET_REQ_HARD_REQ (0x00000002) /* Hard Reset request */\r
-/* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_RSTKEY] Bits */\r
-#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /* RSTKEY Offset */\r
-#define RSTCTL_RESET_REQ_RSTKEY_M (0x0000ff00) /* Write key to unlock reset request bits */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC0] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /* SRC0 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC0 (0x00000001) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC1] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /* SRC1 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC1 (0x00000002) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC2] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /* SRC2 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC2 (0x00000004) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC3] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /* SRC3 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC3 (0x00000008) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC4] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /* SRC4 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC4 (0x00000010) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC5] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /* SRC5 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC5 (0x00000020) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC6] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /* SRC6 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC6 (0x00000040) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC7] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /* SRC7 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC7 (0x00000080) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC8] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /* SRC8 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC8 (0x00000100) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC9] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /* SRC9 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC9 (0x00000200) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC10] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /* SRC10 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC10 (0x00000400) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC11] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /* SRC11 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC11 (0x00000800) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC12] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /* SRC12 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC12 (0x00001000) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC13] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /* SRC13 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC13 (0x00002000) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC14] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /* SRC14 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC14 (0x00004000) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC15] Bits */\r
-#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /* SRC15 Offset */\r
-#define RSTCTL_HARDRESET_CLR_SRC15 (0x00008000) /* Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC0] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /* SRC0 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC0 (0x00000001) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC1] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /* SRC1 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC1 (0x00000002) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC2] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /* SRC2 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC2 (0x00000004) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC3] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /* SRC3 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC3 (0x00000008) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC4] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /* SRC4 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC4 (0x00000010) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC5] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /* SRC5 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC5 (0x00000020) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC6] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /* SRC6 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC6 (0x00000040) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC7] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /* SRC7 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC7 (0x00000080) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC8] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /* SRC8 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC8 (0x00000100) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC9] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /* SRC9 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC9 (0x00000200) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC10] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /* SRC10 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC10 (0x00000400) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC11] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /* SRC11 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC11 (0x00000800) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC12] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /* SRC12 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC12 (0x00001000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC13] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /* SRC13 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC13 (0x00002000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC14] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /* SRC14 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC14 (0x00004000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC15] Bits */\r
-#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /* SRC15 Offset */\r
-#define RSTCTL_HARDRESET_SET_SRC15 (0x00008000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC0] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /* SRC0 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC0 (0x00000001) /* If 1, indicates that SRC0 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC1] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /* SRC1 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC1 (0x00000002) /* If 1, indicates that SRC1 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC2] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /* SRC2 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC2 (0x00000004) /* If 1, indicates that SRC2 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC3] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /* SRC3 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC3 (0x00000008) /* If 1, indicates that SRC3 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC4] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /* SRC4 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC4 (0x00000010) /* If 1, indicates that SRC4 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC5] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /* SRC5 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC5 (0x00000020) /* If 1, indicates that SRC5 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC6] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /* SRC6 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC6 (0x00000040) /* If 1, indicates that SRC6 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC7] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /* SRC7 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC7 (0x00000080) /* If 1, indicates that SRC7 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC8] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /* SRC8 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC8 (0x00000100) /* If 1, indicates that SRC8 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC9] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /* SRC9 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC9 (0x00000200) /* If 1, indicates that SRC9 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC10] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /* SRC10 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC10 (0x00000400) /* If 1, indicates that SRC10 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC11] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /* SRC11 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC11 (0x00000800) /* If 1, indicates that SRC11 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC12] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /* SRC12 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC12 (0x00001000) /* If 1, indicates that SRC12 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC13] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /* SRC13 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC13 (0x00002000) /* If 1, indicates that SRC13 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC14] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /* SRC14 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC14 (0x00004000) /* If 1, indicates that SRC14 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC15] Bits */\r
-#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /* SRC15 Offset */\r
-#define RSTCTL_SOFTRESET_STAT_SRC15 (0x00008000) /* If 1, indicates that SRC15 was the source of the Soft Reset */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC0] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /* SRC0 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC0 (0x00000001) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC1] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /* SRC1 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC1 (0x00000002) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC2] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /* SRC2 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC2 (0x00000004) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC3] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /* SRC3 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC3 (0x00000008) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC4] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /* SRC4 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC4 (0x00000010) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC5] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /* SRC5 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC5 (0x00000020) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC6] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /* SRC6 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC6 (0x00000040) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC7] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /* SRC7 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC7 (0x00000080) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC8] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /* SRC8 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC8 (0x00000100) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC9] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /* SRC9 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC9 (0x00000200) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC10] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /* SRC10 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC10 (0x00000400) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC11] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /* SRC11 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC11 (0x00000800) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC12] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /* SRC12 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC12 (0x00001000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC13] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /* SRC13 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC13 (0x00002000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC14] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /* SRC14 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC14 (0x00004000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC15] Bits */\r
-#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /* SRC15 Offset */\r
-#define RSTCTL_SOFTRESET_CLR_SRC15 (0x00008000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC0] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /* SRC0 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC0 (0x00000001) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC1] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /* SRC1 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC1 (0x00000002) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC2] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /* SRC2 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC2 (0x00000004) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC3] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /* SRC3 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC3 (0x00000008) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC4] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /* SRC4 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC4 (0x00000010) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC5] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /* SRC5 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC5 (0x00000020) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC6] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /* SRC6 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC6 (0x00000040) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC7] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /* SRC7 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC7 (0x00000080) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC8] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /* SRC8 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC8 (0x00000100) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC9] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /* SRC9 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC9 (0x00000200) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC10] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /* SRC10 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC10 (0x00000400) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC11] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /* SRC11 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC11 (0x00000800) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC12] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /* SRC12 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC12 (0x00001000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC13] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /* SRC13 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC13 (0x00002000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC14] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /* SRC14 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC14 (0x00004000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC15] Bits */\r
-#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /* SRC15 Offset */\r
-#define RSTCTL_SOFTRESET_SET_SRC15 (0x00008000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */\r
-/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_SVSL] Bits */\r
-#define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /* SVSL Offset */\r
-#define RSTCTL_PSSRESET_STAT_SVSL (0x00000001) /* Indicates if POR was caused by an SVSL trip condition in the PSS */\r
-/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_SVSMH] Bits */\r
-#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /* SVSMH Offset */\r
-#define RSTCTL_PSSRESET_STAT_SVSMH (0x00000002) /* Indicates if POR was caused by an SVSMH trip condition int the PSS */\r
-/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_BGREF] Bits */\r
-#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /* BGREF Offset */\r
-#define RSTCTL_PSSRESET_STAT_BGREF (0x00000004) /* Indicates if POR was caused by a BGREF not okay condition in the PSS */\r
-/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_VCCDET] Bits */\r
-#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /* VCCDET Offset */\r
-#define RSTCTL_PSSRESET_STAT_VCCDET (0x00000008) /* Indicates if POR was caused by a VCCDET trip condition in the PSS */\r
-/* RSTCTL_PSSRESET_CLR[RSTCTL_PSSRESET_CLR_CLR] Bits */\r
-#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /* CLR Offset */\r
-#define RSTCTL_PSSRESET_CLR_CLR (0x00000001) /* Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */\r
-/* RSTCTL_PCMRESET_STAT[RSTCTL_PCMRESET_STAT_LPM35] Bits */\r
-#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /* LPM35 Offset */\r
-#define RSTCTL_PCMRESET_STAT_LPM35 (0x00000001) /* Indicates if POR was caused by PCM due to an exit from LPM3.5 */\r
-/* RSTCTL_PCMRESET_STAT[RSTCTL_PCMRESET_STAT_LPM45] Bits */\r
-#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /* LPM45 Offset */\r
-#define RSTCTL_PCMRESET_STAT_LPM45 (0x00000002) /* Indicates if POR was caused by PCM due to an exit from LPM4.5 */\r
-/* RSTCTL_PCMRESET_CLR[RSTCTL_PCMRESET_CLR_CLR] Bits */\r
-#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /* CLR Offset */\r
-#define RSTCTL_PCMRESET_CLR_CLR (0x00000001) /* Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */\r
-/* RSTCTL_PINRESET_STAT[RSTCTL_PINRESET_STAT_RSTNMI] Bits */\r
-#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /* RSTNMI Offset */\r
-#define RSTCTL_PINRESET_STAT_RSTNMI (0x00000001) /* POR was caused by RSTn/NMI pin based reset event */\r
-/* RSTCTL_PINRESET_CLR[RSTCTL_PINRESET_CLR_CLR] Bits */\r
-#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /* CLR Offset */\r
-#define RSTCTL_PINRESET_CLR_CLR (0x00000001) /* Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */\r
-/* RSTCTL_REBOOTRESET_STAT[RSTCTL_REBOOTRESET_STAT_REBOOT] Bits */\r
-#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /* REBOOT Offset */\r
-#define RSTCTL_REBOOTRESET_STAT_REBOOT (0x00000001) /* Indicates if Reboot reset was caused by the SYSCTL module. */\r
-/* RSTCTL_REBOOTRESET_CLR[RSTCTL_REBOOTRESET_CLR_CLR] Bits */\r
-#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /* CLR Offset */\r
-#define RSTCTL_REBOOTRESET_CLR_CLR (0x00000001) /* Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */\r
+#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /* PSS control key value */\r
+\r
+\r
+/******************************************************************************\r
+* REF_A Bits\r
+******************************************************************************/\r
+/* REF_A_CTL0[ON] Bits */\r
+#define REF_A_CTL0_ON_OFS ( 0) /**< REFON Bit Offset */\r
+#define REF_A_CTL0_ON ((uint16_t)0x0001) /**< Reference enable */\r
+/* REF_A_CTL0[OUT] Bits */\r
+#define REF_A_CTL0_OUT_OFS ( 1) /**< REFOUT Bit Offset */\r
+#define REF_A_CTL0_OUT ((uint16_t)0x0002) /**< Reference output buffer */\r
+/* REF_A_CTL0[TCOFF] Bits */\r
+#define REF_A_CTL0_TCOFF_OFS ( 3) /**< REFTCOFF Bit Offset */\r
+#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /**< Temperature sensor disabled */\r
+/* REF_A_CTL0[VSEL] Bits */\r
+#define REF_A_CTL0_VSEL_OFS ( 4) /**< REFVSEL Bit Offset */\r
+#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /**< REFVSEL Bit Mask */\r
+#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /**< VSEL Bit 0 */\r
+#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /**< VSEL Bit 1 */\r
+#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /**< 1.2 V available when reference requested or REFON = 1 */\r
+#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /**< 1.45 V available when reference requested or REFON = 1 */\r
+#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /**< 2.5 V available when reference requested or REFON = 1 */\r
+/* REF_A_CTL0[GENOT] Bits */\r
+#define REF_A_CTL0_GENOT_OFS ( 6) /**< REFGENOT Bit Offset */\r
+#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /**< Reference generator one-time trigger */\r
+/* REF_A_CTL0[BGOT] Bits */\r
+#define REF_A_CTL0_BGOT_OFS ( 7) /**< REFBGOT Bit Offset */\r
+#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /**< Bandgap and bandgap buffer one-time trigger */\r
+/* REF_A_CTL0[GENACT] Bits */\r
+#define REF_A_CTL0_GENACT_OFS ( 8) /**< REFGENACT Bit Offset */\r
+#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /**< Reference generator active */\r
+/* REF_A_CTL0[BGACT] Bits */\r
+#define REF_A_CTL0_BGACT_OFS ( 9) /**< REFBGACT Bit Offset */\r
+#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /**< Reference bandgap active */\r
+/* REF_A_CTL0[GENBUSY] Bits */\r
+#define REF_A_CTL0_GENBUSY_OFS (10) /**< REFGENBUSY Bit Offset */\r
+#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /**< Reference generator busy */\r
+/* REF_A_CTL0[BGMODE] Bits */\r
+#define REF_A_CTL0_BGMODE_OFS (11) /**< BGMODE Bit Offset */\r
+#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /**< Bandgap mode */\r
+/* REF_A_CTL0[GENRDY] Bits */\r
+#define REF_A_CTL0_GENRDY_OFS (12) /**< REFGENRDY Bit Offset */\r
+#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /**< Variable reference voltage ready status */\r
+/* REF_A_CTL0[BGRDY] Bits */\r
+#define REF_A_CTL0_BGRDY_OFS (13) /**< REFBGRDY Bit Offset */\r
+#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /**< Buffered bandgap voltage ready status */\r
+\r
+\r
+/******************************************************************************\r
+* RSTCTL Bits\r
+******************************************************************************/\r
+/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */\r
+#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /**< SOFT_REQ Bit Offset */\r
+#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /**< Soft Reset request */\r
+/* RSTCTL_RESET_REQ[HARD_REQ] Bits */\r
+#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /**< HARD_REQ Bit Offset */\r
+#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /**< Hard Reset request */\r
+/* RSTCTL_RESET_REQ[RSTKEY] Bits */\r
+#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /**< RSTKEY Bit Offset */\r
+#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /**< RSTKEY Bit Mask */\r
+/* RSTCTL_HARDRESET_STAT[SRC0] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /**< SRC0 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /**< Indicates that SRC0 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC1] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /**< SRC1 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /**< Indicates that SRC1 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC2] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /**< SRC2 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /**< Indicates that SRC2 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC3] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /**< SRC3 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /**< Indicates that SRC3 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC4] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /**< SRC4 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /**< Indicates that SRC4 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC5] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /**< SRC5 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /**< Indicates that SRC5 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC6] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /**< SRC6 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /**< Indicates that SRC6 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC7] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /**< SRC7 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /**< Indicates that SRC7 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC8] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /**< SRC8 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /**< Indicates that SRC8 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC9] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /**< SRC9 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /**< Indicates that SRC9 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC10] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /**< SRC10 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /**< Indicates that SRC10 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC11] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /**< SRC11 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /**< Indicates that SRC11 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC12] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /**< SRC12 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /**< Indicates that SRC12 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC13] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /**< SRC13 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /**< Indicates that SRC13 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC14] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /**< SRC14 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /**< Indicates that SRC14 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_STAT[SRC15] Bits */\r
+#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /**< SRC15 Bit Offset */\r
+#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /**< Indicates that SRC15 was the source of the Hard Reset */\r
+/* RSTCTL_HARDRESET_CLR[SRC0] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /**< SRC0 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC1] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /**< SRC1 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC2] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /**< SRC2 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC3] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /**< SRC3 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC4] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /**< SRC4 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC5] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /**< SRC5 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC6] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /**< SRC6 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC7] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /**< SRC7 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC8] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /**< SRC8 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC9] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /**< SRC9 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC10] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /**< SRC10 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC11] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /**< SRC11 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC12] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /**< SRC12 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC13] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /**< SRC13 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC14] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /**< SRC14 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */\r
+/* RSTCTL_HARDRESET_CLR[SRC15] Bits */\r
+#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /**< SRC15 Bit Offset */\r
+#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /**< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */\r
+/* RSTCTL_HARDRESET_SET[SRC0] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /**< SRC0 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC1] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /**< SRC1 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC2] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /**< SRC2 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC3] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /**< SRC3 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC4] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /**< SRC4 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC5] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /**< SRC5 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC6] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /**< SRC6 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC7] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /**< SRC7 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC8] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /**< SRC8 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC9] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /**< SRC9 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC10] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /**< SRC10 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC11] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /**< SRC11 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC12] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /**< SRC12 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC13] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /**< SRC13 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC14] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /**< SRC14 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_HARDRESET_SET[SRC15] Bits */\r
+#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /**< SRC15 Bit Offset */\r
+#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */\r
+ /* a Hard Reset) */\r
+/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /**< SRC0 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /**< If 1, indicates that SRC0 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /**< SRC1 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /**< If 1, indicates that SRC1 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /**< SRC2 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /**< If 1, indicates that SRC2 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /**< SRC3 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /**< If 1, indicates that SRC3 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /**< SRC4 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /**< If 1, indicates that SRC4 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /**< SRC5 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /**< If 1, indicates that SRC5 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /**< SRC6 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /**< If 1, indicates that SRC6 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /**< SRC7 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /**< If 1, indicates that SRC7 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /**< SRC8 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /**< If 1, indicates that SRC8 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /**< SRC9 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /**< If 1, indicates that SRC9 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /**< SRC10 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /**< If 1, indicates that SRC10 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /**< SRC11 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /**< If 1, indicates that SRC11 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /**< SRC12 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /**< If 1, indicates that SRC12 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /**< SRC13 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /**< If 1, indicates that SRC13 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /**< SRC14 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /**< If 1, indicates that SRC14 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */\r
+#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /**< SRC15 Bit Offset */\r
+#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /**< If 1, indicates that SRC15 was the source of the Soft Reset */\r
+/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /**< SRC0 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /**< SRC1 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /**< SRC2 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /**< SRC3 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /**< SRC4 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /**< SRC5 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /**< SRC6 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /**< SRC7 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /**< SRC8 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /**< SRC9 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /**< SRC10 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /**< SRC11 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /**< SRC12 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /**< SRC13 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /**< SRC14 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */\r
+#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /**< SRC15 Bit Offset */\r
+#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */\r
+/* RSTCTL_SOFTRESET_SET[SRC0] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /**< SRC0 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC1] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /**< SRC1 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC2] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /**< SRC2 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC3] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /**< SRC3 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC4] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /**< SRC4 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC5] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /**< SRC5 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC6] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /**< SRC6 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC7] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /**< SRC7 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC8] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /**< SRC8 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC9] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /**< SRC9 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC10] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /**< SRC10 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC11] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /**< SRC11 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC12] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /**< SRC12 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC13] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /**< SRC13 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC14] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /**< SRC14 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_SOFTRESET_SET[SRC15] Bits */\r
+#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /**< SRC15 Bit Offset */\r
+#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */\r
+ /* a Soft Reset) */\r
+/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */\r
+#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /**< SVSMH Bit Offset */\r
+#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /**< Indicates if POR was caused by an SVSMH trip condition int the PSS */\r
+/* RSTCTL_PSSRESET_STAT[BGREF] Bits */\r
+#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /**< BGREF Bit Offset */\r
+#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /**< Indicates if POR was caused by a BGREF not okay condition in the PSS */\r
+/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */\r
+#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /**< VCCDET Bit Offset */\r
+#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /**< Indicates if POR was caused by a VCCDET trip condition in the PSS */\r
+/* RSTCTL_PSSRESET_STAT[SVSL] Bits */\r
+#define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /**< SVSL Bit Offset */\r
+#define RSTCTL_PSSRESET_STAT_SVSL ((uint32_t)0x00000001) /**< Indicates if POR was caused by an SVSL trip condition in the PSS */\r
+/* RSTCTL_PSSRESET_CLR[CLR] Bits */\r
+#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */\r
+#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */\r
+/* RSTCTL_PCMRESET_STAT[LPM35] Bits */\r
+#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /**< LPM35 Bit Offset */\r
+#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /**< Indicates if POR was caused by PCM due to an exit from LPM3.5 */\r
+/* RSTCTL_PCMRESET_STAT[LPM45] Bits */\r
+#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /**< LPM45 Bit Offset */\r
+#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /**< Indicates if POR was caused by PCM due to an exit from LPM4.5 */\r
+/* RSTCTL_PCMRESET_CLR[CLR] Bits */\r
+#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */\r
+#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */\r
+/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */\r
+#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /**< RSTNMI Bit Offset */\r
+#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /**< POR was caused by RSTn/NMI pin based reset event */\r
+/* RSTCTL_PINRESET_CLR[CLR] Bits */\r
+#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */\r
+#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */\r
+/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */\r
+#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /**< REBOOT Bit Offset */\r
+#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /**< Indicates if Reboot reset was caused by the SYSCTL module. */\r
+/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */\r
+#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */\r
+#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */\r
+/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */\r
+#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /**< DCOR_SHT Bit Offset */\r
+#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /**< Indicates if POR was caused by DCO short circuit fault in the external */\r
+ /* resistor mode */\r
+/* RSTCTL_CSRESET_CLR[CLR] Bits */\r
+#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */\r
+#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as DCOR_SHTIFG */\r
+ /* flag in CSIFG register of clock system */\r
\r
/* Pre-defined bitfield values */\r
-#define RSTCTL_RESETREQ_RSTKEY_VAL (0x00006900) /* Key value to enable writes to bits 1-0 */\r
-\r
-\r
-//*****************************************************************************\r
-// RTC_C Bits\r
-//*****************************************************************************\r
-/* RTCCTL0[RTCRDYIFG] Bits */\r
-#define RTCRDYIFG_OFS ( 0) /* RTCRDYIFG Offset */\r
-#define RTCRDYIFG (0x0001) /* Real-time clock ready interrupt flag */\r
-/* RTCCTL0[RTCAIFG] Bits */\r
-#define RTCAIFG_OFS ( 1) /* RTCAIFG Offset */\r
-#define RTCAIFG (0x0002) /* Real-time clock alarm interrupt flag */\r
-/* RTCCTL0[RTCTEVIFG] Bits */\r
-#define RTCTEVIFG_OFS ( 2) /* RTCTEVIFG Offset */\r
-#define RTCTEVIFG (0x0004) /* Real-time clock time event interrupt flag */\r
-/* RTCCTL0[RTCOFIFG] Bits */\r
-#define RTCOFIFG_OFS ( 3) /* RTCOFIFG Offset */\r
-#define RTCOFIFG (0x0008) /* 32-kHz crystal oscillator fault interrupt flag */\r
-/* RTCCTL0[RTCRDYIE] Bits */\r
-#define RTCRDYIE_OFS ( 4) /* RTCRDYIE Offset */\r
-#define RTCRDYIE (0x0010) /* Real-time clock ready interrupt enable */\r
-/* RTCCTL0[RTCAIE] Bits */\r
-#define RTCAIE_OFS ( 5) /* RTCAIE Offset */\r
-#define RTCAIE (0x0020) /* Real-time clock alarm interrupt enable */\r
-/* RTCCTL0[RTCTEVIE] Bits */\r
-#define RTCTEVIE_OFS ( 6) /* RTCTEVIE Offset */\r
-#define RTCTEVIE (0x0040) /* Real-time clock time event interrupt enable */\r
-/* RTCCTL0[RTCOFIE] Bits */\r
-#define RTCOFIE_OFS ( 7) /* RTCOFIE Offset */\r
-#define RTCOFIE (0x0080) /* 32-kHz crystal oscillator fault interrupt enable */\r
-/* RTCCTL0[RTCKEY] Bits */\r
-#define RTCKEY_OFS ( 8) /* RTCKEY Offset */\r
-#define RTCKEY_M (0xff00) /* Real-time clock key */\r
-/* RTCCTL13[RTCTEV] Bits */\r
-#define RTCTEV_OFS ( 0) /* RTCTEV Offset */\r
-#define RTCTEV_M (0x0003) /* Real-time clock time event */\r
-#define RTCTEV0 (0x0001) /* Real-time clock time event */\r
-#define RTCTEV1 (0x0002) /* Real-time clock time event */\r
-#define RTCTEV_0 (0x0000) /* Minute changed */\r
-#define RTCTEV_1 (0x0001) /* Hour changed */\r
-#define RTCTEV_2 (0x0002) /* Every day at midnight (00:00) */\r
-#define RTCTEV_3 (0x0003) /* Every day at noon (12:00) */\r
-/* RTCCTL13[RTCSSEL] Bits */\r
-#define RTCSSEL_OFS ( 2) /* RTCSSEL Offset */\r
-#define RTCSSEL_M (0x000c) /* Real-time clock source select */\r
-#define RTCSSEL0 (0x0004) /* Real-time clock source select */\r
-#define RTCSSEL1 (0x0008) /* Real-time clock source select */\r
-#define RTCSSEL_0 (0x0000) /* BCLK */\r
-#define RTCSSEL__BCLK (0x0000) /* BCLK */\r
-/* RTCCTL13[RTCRDY] Bits */\r
-#define RTCRDY_OFS ( 4) /* RTCRDY Offset */\r
-#define RTCRDY (0x0010) /* Real-time clock ready */\r
-/* RTCCTL13[RTCMODE] Bits */\r
-#define RTCMODE_OFS ( 5) /* RTCMODE Offset */\r
-#define RTCMODE (0x0020) /* */\r
-/* RTCCTL13[RTCHOLD] Bits */\r
-#define RTCHOLD_OFS ( 6) /* RTCHOLD Offset */\r
-#define RTCHOLD (0x0040) /* Real-time clock hold */\r
-/* RTCCTL13[RTCBCD] Bits */\r
-#define RTCBCD_OFS ( 7) /* RTCBCD Offset */\r
-#define RTCBCD (0x0080) /* Real-time clock BCD select */\r
-/* RTCCTL13[RTCCALF] Bits */\r
-#define RTCCALF_OFS ( 8) /* RTCCALF Offset */\r
-#define RTCCALF_M (0x0300) /* Real-time clock calibration frequency */\r
-#define RTCCALF0 (0x0100) /* Real-time clock calibration frequency */\r
-#define RTCCALF1 (0x0200) /* Real-time clock calibration frequency */\r
-#define RTCCALF_0 (0x0000) /* No frequency output to RTCCLK pin */\r
-#define RTCCALF_1 (0x0100) /* 512 Hz */\r
-#define RTCCALF_2 (0x0200) /* 256 Hz */\r
-#define RTCCALF_3 (0x0300) /* 1 Hz */\r
-#define RTCCALF__NONE (0x0000) /* No frequency output to RTCCLK pin */\r
-#define RTCCALF__512 (0x0100) /* 512 Hz */\r
-#define RTCCALF__256 (0x0200) /* 256 Hz */\r
-#define RTCCALF__1 (0x0300) /* 1 Hz */\r
-/* RTCOCAL[RTCOCAL] Bits */\r
-#define RTCOCAL_OFS ( 0) /* RTCOCAL Offset */\r
-#define RTCOCAL_M (0x00ff) /* Real-time clock offset error calibration */\r
-/* RTCOCAL[RTCOCALS] Bits */\r
-#define RTCOCALS_OFS (15) /* RTCOCALS Offset */\r
-#define RTCOCALS (0x8000) /* Real-time clock offset error calibration sign */\r
-/* RTCTCMP[RTCTCMP] Bits */\r
-#define RTCTCMP_OFS ( 0) /* RTCTCMP Offset */\r
-#define RTCTCMP_M (0x00ff) /* Real-time clock temperature compensation */\r
-/* RTCTCMP[RTCTCOK] Bits */\r
-#define RTCTCOK_OFS (13) /* RTCTCOK Offset */\r
-#define RTCTCOK (0x2000) /* Real-time clock temperature compensation write OK */\r
-/* RTCTCMP[RTCTCRDY] Bits */\r
-#define RTCTCRDY_OFS (14) /* RTCTCRDY Offset */\r
-#define RTCTCRDY (0x4000) /* Real-time clock temperature compensation ready */\r
-/* RTCTCMP[RTCTCMPS] Bits */\r
-#define RTCTCMPS_OFS (15) /* RTCTCMPS Offset */\r
-#define RTCTCMPS (0x8000) /* Real-time clock temperature compensation sign */\r
-/* RTCPS0CTL[RT0PSIFG] Bits */\r
-#define RT0PSIFG_OFS ( 0) /* RT0PSIFG Offset */\r
-#define RT0PSIFG (0x0001) /* Prescale timer 0 interrupt flag */\r
-/* RTCPS0CTL[RT0PSIE] Bits */\r
-#define RT0PSIE_OFS ( 1) /* RT0PSIE Offset */\r
-#define RT0PSIE (0x0002) /* Prescale timer 0 interrupt enable */\r
-/* RTCPS0CTL[RT0IP] Bits */\r
-#define RT0IP_OFS ( 2) /* RT0IP Offset */\r
-#define RT0IP_M (0x001c) /* Prescale timer 0 interrupt interval */\r
-#define RT0IP0 (0x0004) /* Prescale timer 0 interrupt interval */\r
-#define RT0IP1 (0x0008) /* Prescale timer 0 interrupt interval */\r
-#define RT0IP2 (0x0010) /* Prescale timer 0 interrupt interval */\r
-#define RT0IP_0 (0x0000) /* Divide by 2 */\r
-#define RT0IP_1 (0x0004) /* Divide by 4 */\r
-#define RT0IP_2 (0x0008) /* Divide by 8 */\r
-#define RT0IP_3 (0x000c) /* Divide by 16 */\r
-#define RT0IP_4 (0x0010) /* Divide by 32 */\r
-#define RT0IP_5 (0x0014) /* Divide by 64 */\r
-#define RT0IP_6 (0x0018) /* Divide by 128 */\r
-#define RT0IP_7 (0x001c) /* Divide by 256 */\r
-#define RT0IP__2 (0x0000) /* Divide by 2 */\r
-#define RT0IP__4 (0x0004) /* Divide by 4 */\r
-#define RT0IP__8 (0x0008) /* Divide by 8 */\r
-#define RT0IP__16 (0x000c) /* Divide by 16 */\r
-#define RT0IP__32 (0x0010) /* Divide by 32 */\r
-#define RT0IP__64 (0x0014) /* Divide by 64 */\r
-#define RT0IP__128 (0x0018) /* Divide by 128 */\r
-#define RT0IP__256 (0x001c) /* Divide by 256 */\r
-/* RTCPS1CTL[RT1PSIFG] Bits */\r
-#define RT1PSIFG_OFS ( 0) /* RT1PSIFG Offset */\r
-#define RT1PSIFG (0x0001) /* Prescale timer 1 interrupt flag */\r
-/* RTCPS1CTL[RT1PSIE] Bits */\r
-#define RT1PSIE_OFS ( 1) /* RT1PSIE Offset */\r
-#define RT1PSIE (0x0002) /* Prescale timer 1 interrupt enable */\r
-/* RTCPS1CTL[RT1IP] Bits */\r
-#define RT1IP_OFS ( 2) /* RT1IP Offset */\r
-#define RT1IP_M (0x001c) /* Prescale timer 1 interrupt interval */\r
-#define RT1IP0 (0x0004) /* Prescale timer 1 interrupt interval */\r
-#define RT1IP1 (0x0008) /* Prescale timer 1 interrupt interval */\r
-#define RT1IP2 (0x0010) /* Prescale timer 1 interrupt interval */\r
-#define RT1IP_0 (0x0000) /* Divide by 2 */\r
-#define RT1IP_1 (0x0004) /* Divide by 4 */\r
-#define RT1IP_2 (0x0008) /* Divide by 8 */\r
-#define RT1IP_3 (0x000c) /* Divide by 16 */\r
-#define RT1IP_4 (0x0010) /* Divide by 32 */\r
-#define RT1IP_5 (0x0014) /* Divide by 64 */\r
-#define RT1IP_6 (0x0018) /* Divide by 128 */\r
-#define RT1IP_7 (0x001c) /* Divide by 256 */\r
-#define RT1IP__2 (0x0000) /* Divide by 2 */\r
-#define RT1IP__4 (0x0004) /* Divide by 4 */\r
-#define RT1IP__8 (0x0008) /* Divide by 8 */\r
-#define RT1IP__16 (0x000c) /* Divide by 16 */\r
-#define RT1IP__32 (0x0010) /* Divide by 32 */\r
-#define RT1IP__64 (0x0014) /* Divide by 64 */\r
-#define RT1IP__128 (0x0018) /* Divide by 128 */\r
-#define RT1IP__256 (0x001c) /* Divide by 256 */\r
-/* RTCPS[RT0PS] Bits */\r
-#define RT0PS_OFS ( 0) /* RT0PS Offset */\r
-#define RT0PS_M (0x00ff) /* Prescale timer 0 counter value */\r
-/* RTCPS[RT1PS] Bits */\r
-#define RT1PS_OFS ( 8) /* RT1PS Offset */\r
-#define RT1PS_M (0xff00) /* Prescale timer 1 counter value */\r
-/* RTCTIM0[SECONDS] Bits */\r
-#define SECONDS_OFS ( 0) /* Seconds Offset */\r
-#define SECONDS_M (0x003f) /* Seconds (0 to 59) */\r
-/* RTCTIM0[MINUTES] Bits */\r
-#define MINUTES_OFS ( 8) /* Minutes Offset */\r
-#define MINUTES_M (0x3f00) /* Minutes (0 to 59) */\r
-/* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */\r
-#define SECONDSLOWDIGIT_OFS ( 0) /* SecondsLowDigit Offset */\r
-#define SECONDSLOWDIGIT_M (0x000f) /* Seconds ? low digit (0 to 9) */\r
-/* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */\r
-#define SECONDSHIGHDIGIT_OFS ( 4) /* SecondsHighDigit Offset */\r
-#define SECONDSHIGHDIGIT_M (0x0070) /* Seconds ? high digit (0 to 5) */\r
-/* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */\r
-#define MINUTESLOWDIGIT_OFS ( 8) /* MinutesLowDigit Offset */\r
-#define MINUTESLOWDIGIT_M (0x0f00) /* Minutes ? low digit (0 to 9) */\r
-/* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */\r
-#define MINUTESHIGHDIGIT_OFS (12) /* MinutesHighDigit Offset */\r
-#define MINUTESHIGHDIGIT_M (0x7000) /* Minutes ? high digit (0 to 5) */\r
-/* RTCTIM1[HOURS] Bits */\r
-#define HOURS_OFS ( 0) /* Hours Offset */\r
-#define HOURS_M (0x001f) /* Hours (0 to 23) */\r
-/* RTCTIM1[DAYOFWEEK] Bits */\r
-#define DAYOFWEEK_OFS ( 8) /* DayofWeek Offset */\r
-#define DAYOFWEEK_M (0x0700) /* Day of week (0 to 6) */\r
-/* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */\r
-#define HOURSLOWDIGIT_OFS ( 0) /* HoursLowDigit Offset */\r
-#define HOURSLOWDIGIT_M (0x000f) /* Hours ? low digit (0 to 9) */\r
-/* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */\r
-#define HOURSHIGHDIGIT_OFS ( 4) /* HoursHighDigit Offset */\r
-#define HOURSHIGHDIGIT_M (0x0030) /* Hours ? high digit (0 to 2) */\r
-/* RTCTIM1_BCD[DAYOFWEEK] Bits */\r
-//#define DAYOFWEEK_OFS ( 8) /* DayofWeek Offset */\r
-//#define DAYOFWEEK_M (0x0700) /* Day of week (0 to 6) */\r
-/* RTCDATE[DAY] Bits */\r
-#define DAY_OFS ( 0) /* Day Offset */\r
-#define DAY_M (0x001f) /* Day of month (1 to 28, 29, 30, 31) */\r
-/* RTCDATE[MONTH] Bits */\r
-#define MONTH_OFS ( 8) /* Month Offset */\r
-#define MONTH_M (0x0f00) /* Month (1 to 12) */\r
-/* RTCDATE_BCD[DAYLOWDIGIT] Bits */\r
-#define DAYLOWDIGIT_OFS ( 0) /* DayLowDigit Offset */\r
-#define DAYLOWDIGIT_M (0x000f) /* Day of month ? low digit (0 to 9) */\r
-/* RTCDATE_BCD[DAYHIGHDIGIT] Bits */\r
-#define DAYHIGHDIGIT_OFS ( 4) /* DayHighDigit Offset */\r
-#define DAYHIGHDIGIT_M (0x0030) /* Day of month ? high digit (0 to 3) */\r
-/* RTCDATE_BCD[MONTHLOWDIGIT] Bits */\r
-#define MONTHLOWDIGIT_OFS ( 8) /* MonthLowDigit Offset */\r
-#define MONTHLOWDIGIT_M (0x0f00) /* Month ? low digit (0 to 9) */\r
-/* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */\r
-#define MONTHHIGHDIGIT_OFS (12) /* MonthHighDigit Offset */\r
-#define MONTHHIGHDIGIT (0x1000) /* Month ? high digit (0 or 1) */\r
-/* RTCYEAR[YEARLOWBYTE] Bits */\r
-#define YEARLOWBYTE_OFS ( 0) /* YearLowByte Offset */\r
-#define YEARLOWBYTE_M (0x00ff) /* Year ? low byte. Valid values for Year are 0 to 4095. */\r
-/* RTCYEAR[YEARHIGHBYTE] Bits */\r
-#define YEARHIGHBYTE_OFS ( 8) /* YearHighByte Offset */\r
-#define YEARHIGHBYTE_M (0x0f00) /* Year ? high byte. Valid values for Year are 0 to 4095. */\r
-/* RTCYEAR_BCD[YEAR] Bits */\r
-#define YEAR_OFS ( 0) /* Year Offset */\r
-#define YEAR_M (0x000f) /* Year ? lowest digit (0 to 9) */\r
-/* RTCYEAR_BCD[DECADE] Bits */\r
-#define DECADE_OFS ( 4) /* Decade Offset */\r
-#define DECADE_M (0x00f0) /* Decade (0 to 9) */\r
-/* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */\r
-#define CENTURYLOWDIGIT_OFS ( 8) /* CenturyLowDigit Offset */\r
-#define CENTURYLOWDIGIT_M (0x0f00) /* Century ? low digit (0 to 9) */\r
-/* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */\r
-#define CENTURYHIGHDIGIT_OFS (12) /* CenturyHighDigit Offset */\r
-#define CENTURYHIGHDIGIT_M (0x7000) /* Century ? high digit (0 to 4) */\r
-/* RTCAMINHR[MINUTES] Bits */\r
-//#define MINUTES_OFS ( 0) /* Minutes Offset */\r
-//#define MINUTES_M (0x003f) /* Minutes (0 to 59) */\r
-/* RTCAMINHR[MINAE] Bits */\r
-#define MINAE_OFS ( 7) /* MINAE Offset */\r
-#define MINAE (0x0080) /* Alarm enable */\r
-/* RTCAMINHR[HOURS] Bits */\r
-//#define HOURS_OFS ( 8) /* Hours Offset */\r
-//#define HOURS_M (0x1f00) /* Hours (0 to 23) */\r
-/* RTCAMINHR[HOURAE] Bits */\r
-#define HOURAE_OFS (15) /* HOURAE Offset */\r
-#define HOURAE (0x8000) /* Alarm enable */\r
-/* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */\r
-//#define MINUTESLOWDIGIT_OFS ( 0) /* MinutesLowDigit Offset */\r
-//#define MINUTESLOWDIGIT_M (0x000f) /* Minutes ? low digit (0 to 9) */\r
-/* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */\r
-//#define MINUTESHIGHDIGIT_OFS ( 4) /* MinutesHighDigit Offset */\r
-//#define MINUTESHIGHDIGIT_M (0x0070) /* Minutes ? high digit (0 to 5) */\r
-/* RTCAMINHR_BCD[MINAE] Bits */\r
-//#define MINAE_OFS ( 7) /* MINAE Offset */\r
-//#define MINAE (0x0080) /* Alarm enable */\r
-/* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */\r
-//#define HOURSLOWDIGIT_OFS ( 8) /* HoursLowDigit Offset */\r
-//#define HOURSLOWDIGIT_M (0x0f00) /* Hours ? low digit (0 to 9) */\r
-/* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */\r
-//#define HOURSHIGHDIGIT_OFS (12) /* HoursHighDigit Offset */\r
-//#define HOURSHIGHDIGIT_M (0x3000) /* Hours ? high digit (0 to 2) */\r
-/* RTCAMINHR_BCD[HOURAE] Bits */\r
-//#define HOURAE_OFS (15) /* HOURAE Offset */\r
-//#define HOURAE (0x8000) /* Alarm enable */\r
-/* RTCADOWDAY[DAYOFWEEK] Bits */\r
-//#define DAYOFWEEK_OFS ( 0) /* DayofWeek Offset */\r
-//#define DAYOFWEEK_M (0x0007) /* Day of week (0 to 6) */\r
-/* RTCADOWDAY[DOWAE] Bits */\r
-#define DOWAE_OFS ( 7) /* DOWAE Offset */\r
-#define DOWAE (0x0080) /* Alarm enable */\r
-/* RTCADOWDAY[DAYOFMONTH] Bits */\r
-#define DAYOFMONTH_OFS ( 8) /* DayofMonth Offset */\r
-#define DAYOFMONTH_M (0x1f00) /* Day of month (1 to 28, 29, 30, 31) */\r
-/* RTCADOWDAY[DAYAE] Bits */\r
-#define DAYAE_OFS (15) /* DAYAE Offset */\r
-#define DAYAE (0x8000) /* Alarm enable */\r
-/* RTCADOWDAY_BCD[DAYOFWEEK] Bits */\r
-//#define DAYOFWEEK_OFS ( 0) /* DayofWeek Offset */\r
-//#define DAYOFWEEK_M (0x0007) /* Day of week (0 to 6) */\r
-/* RTCADOWDAY_BCD[DOWAE] Bits */\r
-//#define DOWAE_OFS ( 7) /* DOWAE Offset */\r
-//#define DOWAE (0x0080) /* Alarm enable */\r
-/* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */\r
-//#define DAYLOWDIGIT_OFS ( 8) /* DayLowDigit Offset */\r
-//#define DAYLOWDIGIT_M (0x0f00) /* Day of month ? low digit (0 to 9) */\r
-/* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */\r
-//#define DAYHIGHDIGIT_OFS (12) /* DayHighDigit Offset */\r
-//#define DAYHIGHDIGIT_M (0x3000) /* Day of month ? high digit (0 to 3) */\r
-/* RTCADOWDAY_BCD[DAYAE] Bits */\r
-//#define DAYAE_OFS (15) /* DAYAE Offset */\r
-//#define DAYAE (0x8000) /* Alarm enable */\r
+#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /* Key value to enable writes to bits 1-0 */\r
+\r
+\r
+/******************************************************************************\r
+* RTC_C Bits\r
+******************************************************************************/\r
+/* RTC_C_CTL0[RDYIFG] Bits */\r
+#define RTC_C_CTL0_RDYIFG_OFS ( 0) /**< RTCRDYIFG Bit Offset */\r
+#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /**< Real-time clock ready interrupt flag */\r
+/* RTC_C_CTL0[AIFG] Bits */\r
+#define RTC_C_CTL0_AIFG_OFS ( 1) /**< RTCAIFG Bit Offset */\r
+#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /**< Real-time clock alarm interrupt flag */\r
+/* RTC_C_CTL0[TEVIFG] Bits */\r
+#define RTC_C_CTL0_TEVIFG_OFS ( 2) /**< RTCTEVIFG Bit Offset */\r
+#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /**< Real-time clock time event interrupt flag */\r
+/* RTC_C_CTL0[OFIFG] Bits */\r
+#define RTC_C_CTL0_OFIFG_OFS ( 3) /**< RTCOFIFG Bit Offset */\r
+#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /**< 32-kHz crystal oscillator fault interrupt flag */\r
+/* RTC_C_CTL0[RDYIE] Bits */\r
+#define RTC_C_CTL0_RDYIE_OFS ( 4) /**< RTCRDYIE Bit Offset */\r
+#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /**< Real-time clock ready interrupt enable */\r
+/* RTC_C_CTL0[AIE] Bits */\r
+#define RTC_C_CTL0_AIE_OFS ( 5) /**< RTCAIE Bit Offset */\r
+#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /**< Real-time clock alarm interrupt enable */\r
+/* RTC_C_CTL0[TEVIE] Bits */\r
+#define RTC_C_CTL0_TEVIE_OFS ( 6) /**< RTCTEVIE Bit Offset */\r
+#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /**< Real-time clock time event interrupt enable */\r
+/* RTC_C_CTL0[OFIE] Bits */\r
+#define RTC_C_CTL0_OFIE_OFS ( 7) /**< RTCOFIE Bit Offset */\r
+#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /**< 32-kHz crystal oscillator fault interrupt enable */\r
+/* RTC_C_CTL0[KEY] Bits */\r
+#define RTC_C_CTL0_KEY_OFS ( 8) /**< RTCKEY Bit Offset */\r
+#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /**< RTCKEY Bit Mask */\r
+/* RTC_C_CTL13[TEV] Bits */\r
+#define RTC_C_CTL13_TEV_OFS ( 0) /**< RTCTEV Bit Offset */\r
+#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /**< RTCTEV Bit Mask */\r
+#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /**< TEV Bit 0 */\r
+#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /**< TEV Bit 1 */\r
+#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /**< Minute changed */\r
+#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /**< Hour changed */\r
+#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /**< Every day at midnight (00:00) */\r
+#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /**< Every day at noon (12:00) */\r
+/* RTC_C_CTL13[SSEL] Bits */\r
+#define RTC_C_CTL13_SSEL_OFS ( 2) /**< RTCSSEL Bit Offset */\r
+#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /**< RTCSSEL Bit Mask */\r
+#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /**< SSEL Bit 0 */\r
+#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /**< SSEL Bit 1 */\r
+#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /**< BCLK */\r
+#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /**< BCLK */\r
+/* RTC_C_CTL13[RDY] Bits */\r
+#define RTC_C_CTL13_RDY_OFS ( 4) /**< RTCRDY Bit Offset */\r
+#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /**< Real-time clock ready */\r
+/* RTC_C_CTL13[MODE] Bits */\r
+#define RTC_C_CTL13_MODE_OFS ( 5) /**< RTCMODE Bit Offset */\r
+#define RTC_C_CTL13_MODE ((uint16_t)0x0020)\r
+/* RTC_C_CTL13[HOLD] Bits */\r
+#define RTC_C_CTL13_HOLD_OFS ( 6) /**< RTCHOLD Bit Offset */\r
+#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /**< Real-time clock hold */\r
+/* RTC_C_CTL13[BCD] Bits */\r
+#define RTC_C_CTL13_BCD_OFS ( 7) /**< RTCBCD Bit Offset */\r
+#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /**< Real-time clock BCD select */\r
+/* RTC_C_CTL13[CALF] Bits */\r
+#define RTC_C_CTL13_CALF_OFS ( 8) /**< RTCCALF Bit Offset */\r
+#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /**< RTCCALF Bit Mask */\r
+#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /**< CALF Bit 0 */\r
+#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /**< CALF Bit 1 */\r
+#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /**< No frequency output to RTCCLK pin */\r
+#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /**< 512 Hz */\r
+#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /**< 256 Hz */\r
+#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /**< 1 Hz */\r
+#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /**< No frequency output to RTCCLK pin */\r
+#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /**< 512 Hz */\r
+#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /**< 256 Hz */\r
+#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /**< 1 Hz */\r
+/* RTC_C_OCAL[OCAL] Bits */\r
+#define RTC_C_OCAL_OCAL_OFS ( 0) /**< RTCOCAL Bit Offset */\r
+#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /**< RTCOCAL Bit Mask */\r
+/* RTC_C_OCAL[OCALS] Bits */\r
+#define RTC_C_OCAL_OCALS_OFS (15) /**< RTCOCALS Bit Offset */\r
+#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /**< Real-time clock offset error calibration sign */\r
+/* RTC_C_TCMP[TCMPX] Bits */\r
+#define RTC_C_TCMP_TCMPX_OFS ( 0) /**< RTCTCMP Bit Offset */\r
+#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /**< RTCTCMP Bit Mask */\r
+/* RTC_C_TCMP[TCOK] Bits */\r
+#define RTC_C_TCMP_TCOK_OFS (13) /**< RTCTCOK Bit Offset */\r
+#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /**< Real-time clock temperature compensation write OK */\r
+/* RTC_C_TCMP[TCRDY] Bits */\r
+#define RTC_C_TCMP_TCRDY_OFS (14) /**< RTCTCRDY Bit Offset */\r
+#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /**< Real-time clock temperature compensation ready */\r
+/* RTC_C_TCMP[TCMPS] Bits */\r
+#define RTC_C_TCMP_TCMPS_OFS (15) /**< RTCTCMPS Bit Offset */\r
+#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /**< Real-time clock temperature compensation sign */\r
+/* RTC_C_PS0CTL[RT0PSIFG] Bits */\r
+#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /**< RT0PSIFG Bit Offset */\r
+#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /**< Prescale timer 0 interrupt flag */\r
+/* RTC_C_PS0CTL[RT0PSIE] Bits */\r
+#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /**< RT0PSIE Bit Offset */\r
+#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /**< Prescale timer 0 interrupt enable */\r
+/* RTC_C_PS0CTL[RT0IP] Bits */\r
+#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /**< RT0IP Bit Offset */\r
+#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /**< RT0IP Bit Mask */\r
+#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /**< RT0IP Bit 0 */\r
+#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /**< RT0IP Bit 1 */\r
+#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /**< RT0IP Bit 2 */\r
+#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /**< Divide by 2 */\r
+#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /**< Divide by 4 */\r
+#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /**< Divide by 8 */\r
+#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /**< Divide by 16 */\r
+#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /**< Divide by 32 */\r
+#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /**< Divide by 64 */\r
+#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /**< Divide by 128 */\r
+#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /**< Divide by 256 */\r
+#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /**< Divide by 2 */\r
+#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /**< Divide by 4 */\r
+#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /**< Divide by 8 */\r
+#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /**< Divide by 16 */\r
+#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /**< Divide by 32 */\r
+#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /**< Divide by 64 */\r
+#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /**< Divide by 128 */\r
+#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /**< Divide by 256 */\r
+/* RTC_C_PS1CTL[RT1PSIFG] Bits */\r
+#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /**< RT1PSIFG Bit Offset */\r
+#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /**< Prescale timer 1 interrupt flag */\r
+/* RTC_C_PS1CTL[RT1PSIE] Bits */\r
+#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /**< RT1PSIE Bit Offset */\r
+#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /**< Prescale timer 1 interrupt enable */\r
+/* RTC_C_PS1CTL[RT1IP] Bits */\r
+#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /**< RT1IP Bit Offset */\r
+#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /**< RT1IP Bit Mask */\r
+#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /**< RT1IP Bit 0 */\r
+#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /**< RT1IP Bit 1 */\r
+#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /**< RT1IP Bit 2 */\r
+#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /**< Divide by 2 */\r
+#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /**< Divide by 4 */\r
+#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /**< Divide by 8 */\r
+#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /**< Divide by 16 */\r
+#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /**< Divide by 32 */\r
+#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /**< Divide by 64 */\r
+#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /**< Divide by 128 */\r
+#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /**< Divide by 256 */\r
+#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /**< Divide by 2 */\r
+#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /**< Divide by 4 */\r
+#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /**< Divide by 8 */\r
+#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /**< Divide by 16 */\r
+#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /**< Divide by 32 */\r
+#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /**< Divide by 64 */\r
+#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /**< Divide by 128 */\r
+#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /**< Divide by 256 */\r
+/* RTC_C_PS[RT0PS] Bits */\r
+#define RTC_C_PS_RT0PS_OFS ( 0) /**< RT0PS Bit Offset */\r
+#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /**< RT0PS Bit Mask */\r
+/* RTC_C_PS[RT1PS] Bits */\r
+#define RTC_C_PS_RT1PS_OFS ( 8) /**< RT1PS Bit Offset */\r
+#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /**< RT1PS Bit Mask */\r
+/* RTC_C_TIM0[SEC] Bits */\r
+#define RTC_C_TIM0_SEC_OFS ( 0) /**< Seconds Bit Offset */\r
+#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /**< Seconds Bit Mask */\r
+/* RTC_C_TIM0[MIN] Bits */\r
+#define RTC_C_TIM0_MIN_OFS ( 8) /**< Minutes Bit Offset */\r
+#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /**< Minutes Bit Mask */\r
+/* RTC_C_TIM0[SEC_LD] Bits */\r
+#define RTC_C_TIM0_SEC_LD_OFS ( 0) /**< SecondsLowDigit Bit Offset */\r
+#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /**< SecondsLowDigit Bit Mask */\r
+/* RTC_C_TIM0[SEC_HD] Bits */\r
+#define RTC_C_TIM0_SEC_HD_OFS ( 4) /**< SecondsHighDigit Bit Offset */\r
+#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /**< SecondsHighDigit Bit Mask */\r
+/* RTC_C_TIM0[MIN_LD] Bits */\r
+#define RTC_C_TIM0_MIN_LD_OFS ( 8) /**< MinutesLowDigit Bit Offset */\r
+#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /**< MinutesLowDigit Bit Mask */\r
+/* RTC_C_TIM0[MIN_HD] Bits */\r
+#define RTC_C_TIM0_MIN_HD_OFS (12) /**< MinutesHighDigit Bit Offset */\r
+#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /**< MinutesHighDigit Bit Mask */\r
+/* RTC_C_TIM1[HOUR] Bits */\r
+#define RTC_C_TIM1_HOUR_OFS ( 0) /**< Hours Bit Offset */\r
+#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /**< Hours Bit Mask */\r
+/* RTC_C_TIM1[DOW] Bits */\r
+#define RTC_C_TIM1_DOW_OFS ( 8) /**< DayofWeek Bit Offset */\r
+#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /**< DayofWeek Bit Mask */\r
+/* RTC_C_TIM1[HOUR_LD] Bits */\r
+#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /**< HoursLowDigit Bit Offset */\r
+#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /**< HoursLowDigit Bit Mask */\r
+/* RTC_C_TIM1[HOUR_HD] Bits */\r
+#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /**< HoursHighDigit Bit Offset */\r
+#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /**< HoursHighDigit Bit Mask */\r
+/* RTC_C_DATE[DAY] Bits */\r
+#define RTC_C_DATE_DAY_OFS ( 0) /**< Day Bit Offset */\r
+#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /**< Day Bit Mask */\r
+/* RTC_C_DATE[MON] Bits */\r
+#define RTC_C_DATE_MON_OFS ( 8) /**< Month Bit Offset */\r
+#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /**< Month Bit Mask */\r
+/* RTC_C_DATE[DAY_LD] Bits */\r
+#define RTC_C_DATE_DAY_LD_OFS ( 0) /**< DayLowDigit Bit Offset */\r
+#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /**< DayLowDigit Bit Mask */\r
+/* RTC_C_DATE[DAY_HD] Bits */\r
+#define RTC_C_DATE_DAY_HD_OFS ( 4) /**< DayHighDigit Bit Offset */\r
+#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /**< DayHighDigit Bit Mask */\r
+/* RTC_C_DATE[MON_LD] Bits */\r
+#define RTC_C_DATE_MON_LD_OFS ( 8) /**< MonthLowDigit Bit Offset */\r
+#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /**< MonthLowDigit Bit Mask */\r
+/* RTC_C_DATE[MON_HD] Bits */\r
+#define RTC_C_DATE_MON_HD_OFS (12) /**< MonthHighDigit Bit Offset */\r
+#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /**< Month ? high digit (0 or 1) */\r
+/* RTC_C_YEAR[YEAR_LB] Bits */\r
+#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /**< YearLowByte Bit Offset */\r
+#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /**< YearLowByte Bit Mask */\r
+/* RTC_C_YEAR[YEAR_HB] Bits */\r
+#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /**< YearHighByte Bit Offset */\r
+#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /**< YearHighByte Bit Mask */\r
+/* RTC_C_YEAR[YEAR] Bits */\r
+#define RTC_C_YEAR_YEAR_OFS ( 0) /**< Year Bit Offset */\r
+#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /**< Year Bit Mask */\r
+/* RTC_C_YEAR[DEC] Bits */\r
+#define RTC_C_YEAR_DEC_OFS ( 4) /**< Decade Bit Offset */\r
+#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /**< Decade Bit Mask */\r
+/* RTC_C_YEAR[CENT_LD] Bits */\r
+#define RTC_C_YEAR_CENT_LD_OFS ( 8) /**< CenturyLowDigit Bit Offset */\r
+#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /**< CenturyLowDigit Bit Mask */\r
+/* RTC_C_YEAR[CENT_HD] Bits */\r
+#define RTC_C_YEAR_CENT_HD_OFS (12) /**< CenturyHighDigit Bit Offset */\r
+#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /**< CenturyHighDigit Bit Mask */\r
+/* RTC_C_AMINHR[MIN] Bits */\r
+#define RTC_C_AMINHR_MIN_OFS ( 0) /**< Minutes Bit Offset */\r
+#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /**< Minutes Bit Mask */\r
+/* RTC_C_AMINHR[MINAE] Bits */\r
+#define RTC_C_AMINHR_MINAE_OFS ( 7) /**< MINAE Bit Offset */\r
+#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /**< Alarm enable */\r
+/* RTC_C_AMINHR[HOUR] Bits */\r
+#define RTC_C_AMINHR_HOUR_OFS ( 8) /**< Hours Bit Offset */\r
+#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /**< Hours Bit Mask */\r
+/* RTC_C_AMINHR[HOURAE] Bits */\r
+#define RTC_C_AMINHR_HOURAE_OFS (15) /**< HOURAE Bit Offset */\r
+#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /**< Alarm enable */\r
+/* RTC_C_AMINHR[MIN_LD] Bits */\r
+#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /**< MinutesLowDigit Bit Offset */\r
+#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /**< MinutesLowDigit Bit Mask */\r
+/* RTC_C_AMINHR[MIN_HD] Bits */\r
+#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /**< MinutesHighDigit Bit Offset */\r
+#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /**< MinutesHighDigit Bit Mask */\r
+/* RTC_C_AMINHR[HOUR_LD] Bits */\r
+#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /**< HoursLowDigit Bit Offset */\r
+#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /**< HoursLowDigit Bit Mask */\r
+/* RTC_C_AMINHR[HOUR_HD] Bits */\r
+#define RTC_C_AMINHR_HOUR_HD_OFS (12) /**< HoursHighDigit Bit Offset */\r
+#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /**< HoursHighDigit Bit Mask */\r
+/* RTC_C_ADOWDAY[DOW] Bits */\r
+#define RTC_C_ADOWDAY_DOW_OFS ( 0) /**< DayofWeek Bit Offset */\r
+#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /**< DayofWeek Bit Mask */\r
+/* RTC_C_ADOWDAY[DOWAE] Bits */\r
+#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /**< DOWAE Bit Offset */\r
+#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /**< Alarm enable */\r
+/* RTC_C_ADOWDAY[DAY] Bits */\r
+#define RTC_C_ADOWDAY_DAY_OFS ( 8) /**< DayofMonth Bit Offset */\r
+#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /**< DayofMonth Bit Mask */\r
+/* RTC_C_ADOWDAY[DAYAE] Bits */\r
+#define RTC_C_ADOWDAY_DAYAE_OFS (15) /**< DAYAE Bit Offset */\r
+#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /**< Alarm enable */\r
+/* RTC_C_ADOWDAY[DAY_LD] Bits */\r
+#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /**< DayLowDigit Bit Offset */\r
+#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /**< DayLowDigit Bit Mask */\r
+/* RTC_C_ADOWDAY[DAY_HD] Bits */\r
+#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /**< DayHighDigit Bit Offset */\r
+#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /**< DayHighDigit Bit Mask */\r
\r
/* Pre-defined bitfield values */\r
-#define RTCKEY (0xA500) /* RTC_C Key Value for RTC_C write access */\r
-#define RTCKEY_H (0x00A5) /* RTC_C Key Value for RTC_C write access */\r
-#define RTCKEY_VAL (0xA500) /* RTC_C Key Value for RTC_C write access */\r
-\r
-\r
-//*****************************************************************************\r
-// SCB Bits\r
-//*****************************************************************************\r
-/* SCB_CPUID[SCB_CPUID_REVISION] Bits */\r
-#define SCB_CPUID_REVISION_OFS ( 0) /* REVISION Offset */\r
-#define SCB_CPUID_REVISION_M (0x0000000f) /* */\r
-/* SCB_CPUID[SCB_CPUID_PARTNO] Bits */\r
-#define SCB_CPUID_PARTNO_OFS ( 4) /* PARTNO Offset */\r
-#define SCB_CPUID_PARTNO_M (0x0000fff0) /* */\r
-/* SCB_CPUID[SCB_CPUID_CONSTANT] Bits */\r
-#define SCB_CPUID_CONSTANT_OFS (16) /* CONSTANT Offset */\r
-#define SCB_CPUID_CONSTANT_M (0x000f0000) /* */\r
-/* SCB_CPUID[SCB_CPUID_VARIANT] Bits */\r
-#define SCB_CPUID_VARIANT_OFS (20) /* VARIANT Offset */\r
-#define SCB_CPUID_VARIANT_M (0x00f00000) /* */\r
-/* SCB_CPUID[SCB_CPUID_IMPLEMENTER] Bits */\r
-#define SCB_CPUID_IMPLEMENTER_OFS (24) /* IMPLEMENTER Offset */\r
-#define SCB_CPUID_IMPLEMENTER_M (0xff000000) /* */\r
-/* SCB_ICSR[SCB_ICSR_VECTACTIVE] Bits */\r
-#define SCB_ICSR_VECTACTIVE_OFS ( 0) /* VECTACTIVE Offset */\r
-#define SCB_ICSR_VECTACTIVE_M (0x000001ff) /* */\r
-/* SCB_ICSR[SCB_ICSR_RETTOBASE] Bits */\r
-#define SCB_ICSR_RETTOBASE_OFS (11) /* RETTOBASE Offset */\r
-#define SCB_ICSR_RETTOBASE (0x00000800) /* */\r
-/* SCB_ICSR[SCB_ICSR_VECTPENDING] Bits */\r
-#define SCB_ICSR_VECTPENDING_OFS (12) /* VECTPENDING Offset */\r
-#define SCB_ICSR_VECTPENDING_M (0x0003f000) /* */\r
-/* SCB_ICSR[SCB_ICSR_ISRPENDING] Bits */\r
-#define SCB_ICSR_ISRPENDING_OFS (22) /* ISRPENDING Offset */\r
-#define SCB_ICSR_ISRPENDING (0x00400000) /* */\r
-/* SCB_ICSR[SCB_ICSR_ISRPREEMPT] Bits */\r
-#define SCB_ICSR_ISRPREEMPT_OFS (23) /* ISRPREEMPT Offset */\r
-#define SCB_ICSR_ISRPREEMPT (0x00800000) /* */\r
-/* SCB_ICSR[SCB_ICSR_PENDSTCLR] Bits */\r
-#define SCB_ICSR_PENDSTCLR_OFS (25) /* PENDSTCLR Offset */\r
-#define SCB_ICSR_PENDSTCLR (0x02000000) /* */\r
-/* SCB_ICSR[SCB_ICSR_PENDSTSET] Bits */\r
-#define SCB_ICSR_PENDSTSET_OFS (26) /* PENDSTSET Offset */\r
-#define SCB_ICSR_PENDSTSET (0x04000000) /* */\r
-/* SCB_ICSR[SCB_ICSR_PENDSVCLR] Bits */\r
-#define SCB_ICSR_PENDSVCLR_OFS (27) /* PENDSVCLR Offset */\r
-#define SCB_ICSR_PENDSVCLR (0x08000000) /* */\r
-/* SCB_ICSR[SCB_ICSR_PENDSVSET] Bits */\r
-#define SCB_ICSR_PENDSVSET_OFS (28) /* PENDSVSET Offset */\r
-#define SCB_ICSR_PENDSVSET (0x10000000) /* */\r
-/* SCB_ICSR[SCB_ICSR_NMIPENDSET] Bits */\r
-#define SCB_ICSR_NMIPENDSET_OFS (31) /* NMIPENDSET Offset */\r
-#define SCB_ICSR_NMIPENDSET (0x80000000) /* */\r
-/* SCB_VTOR[SCB_VTOR_TBLOFF] Bits */\r
-#define SCB_VTOR_TBLOFF_OFS ( 7) /* TBLOFF Offset */\r
-#define SCB_VTOR_TBLOFF_M (0x1fffff80) /* */\r
-/* SCB_VTOR[SCB_VTOR_TBLBASE] Bits */\r
-#define SCB_VTOR_TBLBASE_OFS (29) /* TBLBASE Offset */\r
-#define SCB_VTOR_TBLBASE (0x20000000) /* */\r
-/* SCB_AIRCR[SCB_AIRCR_VECTRESET] Bits */\r
-#define SCB_AIRCR_VECTRESET_OFS ( 0) /* VECTRESET Offset */\r
-#define SCB_AIRCR_VECTRESET (0x00000001) /* */\r
-/* SCB_AIRCR[SCB_AIRCR_VECTCLRACTIVE] Bits */\r
-#define SCB_AIRCR_VECTCLRACTIVE_OFS ( 1) /* VECTCLRACTIVE Offset */\r
-#define SCB_AIRCR_VECTCLRACTIVE (0x00000002) /* */\r
-/* SCB_AIRCR[SCB_AIRCR_SYSRESETREQ] Bits */\r
-#define SCB_AIRCR_SYSRESETREQ_OFS ( 2) /* SYSRESETREQ Offset */\r
-#define SCB_AIRCR_SYSRESETREQ (0x00000004) /* */\r
-/* SCB_AIRCR[SCB_AIRCR_PRIGROUP] Bits */\r
-#define SCB_AIRCR_PRIGROUP_OFS ( 8) /* PRIGROUP Offset */\r
-#define SCB_AIRCR_PRIGROUP_M (0x00000700) /* */\r
-/* SCB_AIRCR[SCB_AIRCR_ENDIANESS] Bits */\r
-#define SCB_AIRCR_ENDIANESS_OFS (15) /* ENDIANESS Offset */\r
-#define SCB_AIRCR_ENDIANESS (0x00008000) /* */\r
-/* SCB_AIRCR[SCB_AIRCR_VECTKEY] Bits */\r
-#define SCB_AIRCR_VECTKEY_OFS (16) /* VECTKEY Offset */\r
-#define SCB_AIRCR_VECTKEY_M (0xffff0000) /* */\r
-/* SCB_SCR[SCB_SCR_SLEEPONEXIT] Bits */\r
-#define SCB_SCR_SLEEPONEXIT_OFS ( 1) /* SLEEPONEXIT Offset */\r
-#define SCB_SCR_SLEEPONEXIT (0x00000002) /* */\r
-/* SCB_SCR[SCB_SCR_SLEEPDEEP] Bits */\r
-#define SCB_SCR_SLEEPDEEP_OFS ( 2) /* SLEEPDEEP Offset */\r
-#define SCB_SCR_SLEEPDEEP (0x00000004) /* */\r
-/* SCB_SCR[SCB_SCR_SEVONPEND] Bits */\r
-#define SCB_SCR_SEVONPEND_OFS ( 4) /* SEVONPEND Offset */\r
-#define SCB_SCR_SEVONPEND (0x00000010) /* */\r
-/* SCB_CCR[SCB_CCR_NONBASETHREDENA] Bits */\r
-#define SCB_CCR_NONBASETHREDENA_OFS ( 0) /* NONBASETHREDENA Offset */\r
-#define SCB_CCR_NONBASETHREDENA (0x00000001) /* */\r
-/* SCB_CCR[SCB_CCR_USERSETMPEND] Bits */\r
-#define SCB_CCR_USERSETMPEND_OFS ( 1) /* USERSETMPEND Offset */\r
-#define SCB_CCR_USERSETMPEND (0x00000002) /* */\r
-/* SCB_CCR[SCB_CCR_UNALIGN_TRP] Bits */\r
-#define SCB_CCR_UNALIGN_TRP_OFS ( 3) /* UNALIGN_TRP Offset */\r
-#define SCB_CCR_UNALIGN_TRP (0x00000008) /* */\r
-/* SCB_CCR[SCB_CCR_DIV_0_TRP] Bits */\r
-#define SCB_CCR_DIV_0_TRP_OFS ( 4) /* DIV_0_TRP Offset */\r
-#define SCB_CCR_DIV_0_TRP (0x00000010) /* */\r
-/* SCB_CCR[SCB_CCR_BFHFNMIGN] Bits */\r
-#define SCB_CCR_BFHFNMIGN_OFS ( 8) /* BFHFNMIGN Offset */\r
-#define SCB_CCR_BFHFNMIGN (0x00000100) /* */\r
-/* SCB_CCR[SCB_CCR_STKALIGN] Bits */\r
-#define SCB_CCR_STKALIGN_OFS ( 9) /* STKALIGN Offset */\r
-#define SCB_CCR_STKALIGN (0x00000200) /* */\r
-/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */\r
-#define SCB_SHPR1_PRI_4_OFS ( 0) /* PRI_4 Offset */\r
-#define SCB_SHPR1_PRI_4_M (0x000000ff) /* */\r
-/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */\r
-#define SCB_SHPR1_PRI_5_OFS ( 8) /* PRI_5 Offset */\r
-#define SCB_SHPR1_PRI_5_M (0x0000ff00) /* */\r
-/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */\r
-#define SCB_SHPR1_PRI_6_OFS (16) /* PRI_6 Offset */\r
-#define SCB_SHPR1_PRI_6_M (0x00ff0000) /* */\r
-/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */\r
-#define SCB_SHPR1_PRI_7_OFS (24) /* PRI_7 Offset */\r
-#define SCB_SHPR1_PRI_7_M (0xff000000) /* */\r
-/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */\r
-#define SCB_SHPR2_PRI_8_OFS ( 0) /* PRI_8 Offset */\r
-#define SCB_SHPR2_PRI_8_M (0x000000ff) /* */\r
-/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */\r
-#define SCB_SHPR2_PRI_9_OFS ( 8) /* PRI_9 Offset */\r
-#define SCB_SHPR2_PRI_9_M (0x0000ff00) /* */\r
-/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */\r
-#define SCB_SHPR2_PRI_10_OFS (16) /* PRI_10 Offset */\r
-#define SCB_SHPR2_PRI_10_M (0x00ff0000) /* */\r
-/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */\r
-#define SCB_SHPR2_PRI_11_OFS (24) /* PRI_11 Offset */\r
-#define SCB_SHPR2_PRI_11_M (0xff000000) /* */\r
-/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */\r
-#define SCB_SHPR3_PRI_12_OFS ( 0) /* PRI_12 Offset */\r
-#define SCB_SHPR3_PRI_12_M (0x000000ff) /* */\r
-/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */\r
-#define SCB_SHPR3_PRI_13_OFS ( 8) /* PRI_13 Offset */\r
-#define SCB_SHPR3_PRI_13_M (0x0000ff00) /* */\r
-/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */\r
-#define SCB_SHPR3_PRI_14_OFS (16) /* PRI_14 Offset */\r
-#define SCB_SHPR3_PRI_14_M (0x00ff0000) /* */\r
-/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */\r
-#define SCB_SHPR3_PRI_15_OFS (24) /* PRI_15 Offset */\r
-#define SCB_SHPR3_PRI_15_M (0xff000000) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_MEMFAULTACT] Bits */\r
-#define SCB_SHCSR_MEMFAULTACT_OFS ( 0) /* MEMFAULTACT Offset */\r
-#define SCB_SHCSR_MEMFAULTACT (0x00000001) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_BUSFAULTACT] Bits */\r
-#define SCB_SHCSR_BUSFAULTACT_OFS ( 1) /* BUSFAULTACT Offset */\r
-#define SCB_SHCSR_BUSFAULTACT (0x00000002) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_USGFAULTACT] Bits */\r
-#define SCB_SHCSR_USGFAULTACT_OFS ( 3) /* USGFAULTACT Offset */\r
-#define SCB_SHCSR_USGFAULTACT (0x00000008) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_SVCALLACT] Bits */\r
-#define SCB_SHCSR_SVCALLACT_OFS ( 7) /* SVCALLACT Offset */\r
-#define SCB_SHCSR_SVCALLACT (0x00000080) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_MONITORACT] Bits */\r
-#define SCB_SHCSR_MONITORACT_OFS ( 8) /* MONITORACT Offset */\r
-#define SCB_SHCSR_MONITORACT (0x00000100) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_PENDSVACT] Bits */\r
-#define SCB_SHCSR_PENDSVACT_OFS (10) /* PENDSVACT Offset */\r
-#define SCB_SHCSR_PENDSVACT (0x00000400) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_SYSTICKACT] Bits */\r
-#define SCB_SHCSR_SYSTICKACT_OFS (11) /* SYSTICKACT Offset */\r
-#define SCB_SHCSR_SYSTICKACT (0x00000800) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_USGFAULTPENDED] Bits */\r
-#define SCB_SHCSR_USGFAULTPENDED_OFS (12) /* USGFAULTPENDED Offset */\r
-#define SCB_SHCSR_USGFAULTPENDED (0x00001000) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_MEMFAULTPENDED] Bits */\r
-#define SCB_SHCSR_MEMFAULTPENDED_OFS (13) /* MEMFAULTPENDED Offset */\r
-#define SCB_SHCSR_MEMFAULTPENDED (0x00002000) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_BUSFAULTPENDED] Bits */\r
-#define SCB_SHCSR_BUSFAULTPENDED_OFS (14) /* BUSFAULTPENDED Offset */\r
-#define SCB_SHCSR_BUSFAULTPENDED (0x00004000) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_SVCALLPENDED] Bits */\r
-#define SCB_SHCSR_SVCALLPENDED_OFS (15) /* SVCALLPENDED Offset */\r
-#define SCB_SHCSR_SVCALLPENDED (0x00008000) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_MEMFAULTENA] Bits */\r
-#define SCB_SHCSR_MEMFAULTENA_OFS (16) /* MEMFAULTENA Offset */\r
-#define SCB_SHCSR_MEMFAULTENA (0x00010000) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_BUSFAULTENA] Bits */\r
-#define SCB_SHCSR_BUSFAULTENA_OFS (17) /* BUSFAULTENA Offset */\r
-#define SCB_SHCSR_BUSFAULTENA (0x00020000) /* */\r
-/* SCB_SHCSR[SCB_SHCSR_USGFAULTENA] Bits */\r
-#define SCB_SHCSR_USGFAULTENA_OFS (18) /* USGFAULTENA Offset */\r
-#define SCB_SHCSR_USGFAULTENA (0x00040000) /* */\r
-/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */\r
-#define SCB_CFSR_IACCVIOL_OFS ( 0) /* IACCVIOL Offset */\r
-#define SCB_CFSR_IACCVIOL (0x00000001) /* */\r
-/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */\r
-#define SCB_CFSR_DACCVIOL_OFS ( 1) /* DACCVIOL Offset */\r
-#define SCB_CFSR_DACCVIOL (0x00000002) /* */\r
-/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */\r
-#define SCB_CFSR_MUNSTKERR_OFS ( 3) /* MUNSTKERR Offset */\r
-#define SCB_CFSR_MUNSTKERR (0x00000008) /* */\r
-/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */\r
-#define SCB_CFSR_MSTKERR_OFS ( 4) /* MSTKERR Offset */\r
-#define SCB_CFSR_MSTKERR (0x00000010) /* */\r
-/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */\r
-#define SCB_CFSR_MMARVALID_OFS ( 7) /* MMARVALID Offset */\r
-#define SCB_CFSR_MMARVALID (0x00000080) /* */\r
-/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */\r
-#define SCB_CFSR_IBUSERR_OFS ( 8) /* IBUSERR Offset */\r
-#define SCB_CFSR_IBUSERR (0x00000100) /* */\r
-/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */\r
-#define SCB_CFSR_PRECISERR_OFS ( 9) /* PRECISERR Offset */\r
-#define SCB_CFSR_PRECISERR (0x00000200) /* */\r
-/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */\r
-#define SCB_CFSR_IMPRECISERR_OFS (10) /* IMPRECISERR Offset */\r
-#define SCB_CFSR_IMPRECISERR (0x00000400) /* */\r
-/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */\r
-#define SCB_CFSR_UNSTKERR_OFS (11) /* UNSTKERR Offset */\r
-#define SCB_CFSR_UNSTKERR (0x00000800) /* */\r
-/* SCB_CFSR[SCB_CFSR_STKERR] Bits */\r
-#define SCB_CFSR_STKERR_OFS (12) /* STKERR Offset */\r
-#define SCB_CFSR_STKERR (0x00001000) /* */\r
-/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */\r
-#define SCB_CFSR_BFARVALID_OFS (15) /* BFARVALID Offset */\r
-#define SCB_CFSR_BFARVALID (0x00008000) /* */\r
-/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */\r
-#define SCB_CFSR_UNDEFINSTR_OFS (16) /* UNDEFINSTR Offset */\r
-#define SCB_CFSR_UNDEFINSTR (0x00010000) /* */\r
-/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */\r
-#define SCB_CFSR_INVSTATE_OFS (17) /* INVSTATE Offset */\r
-#define SCB_CFSR_INVSTATE (0x00020000) /* */\r
-/* SCB_CFSR[SCB_CFSR_INVPC] Bits */\r
-#define SCB_CFSR_INVPC_OFS (18) /* INVPC Offset */\r
-#define SCB_CFSR_INVPC (0x00040000) /* */\r
-/* SCB_CFSR[SCB_CFSR_NOCP] Bits */\r
-#define SCB_CFSR_NOCP_OFS (19) /* NOCP Offset */\r
-#define SCB_CFSR_NOCP (0x00080000) /* */\r
-/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */\r
-#define SCB_CFSR_UNALIGNED_OFS (24) /* UNALIGNED Offset */\r
-#define SCB_CFSR_UNALIGNED (0x01000000) /* */\r
-/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */\r
-#define SCB_CFSR_DIVBYZERO_OFS (25) /* DIVBYZERO Offset */\r
-#define SCB_CFSR_DIVBYZERO (0x02000000) /* */\r
-/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */\r
-#define SCB_CFSR_MLSPERR_OFS ( 5) /* MLSPERR Offset */\r
-#define SCB_CFSR_MLSPERR (0x00000020) /* */\r
-/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */\r
-#define SCB_CFSR_LSPERR_OFS (13) /* LSPERR Offset */\r
-#define SCB_CFSR_LSPERR (0x00002000) /* */\r
-/* SCB_HFSR[SCB_HFSR_VECTTBL] Bits */\r
-#define SCB_HFSR_VECTTBL_OFS ( 1) /* VECTTBL Offset */\r
-#define SCB_HFSR_VECTTBL (0x00000002) /* */\r
-/* SCB_HFSR[SCB_HFSR_FORCED] Bits */\r
-#define SCB_HFSR_FORCED_OFS (30) /* FORCED Offset */\r
-#define SCB_HFSR_FORCED (0x40000000) /* */\r
-/* SCB_HFSR[SCB_HFSR_DEBUGEVT] Bits */\r
-#define SCB_HFSR_DEBUGEVT_OFS (31) /* DEBUGEVT Offset */\r
-#define SCB_HFSR_DEBUGEVT (0x80000000) /* */\r
-/* SCB_DFSR[SCB_DFSR_HALTED] Bits */\r
-#define SCB_DFSR_HALTED_OFS ( 0) /* HALTED Offset */\r
-#define SCB_DFSR_HALTED (0x00000001) /* */\r
-/* SCB_DFSR[SCB_DFSR_BKPT] Bits */\r
-#define SCB_DFSR_BKPT_OFS ( 1) /* BKPT Offset */\r
-#define SCB_DFSR_BKPT (0x00000002) /* */\r
-/* SCB_DFSR[SCB_DFSR_DWTTRAP] Bits */\r
-#define SCB_DFSR_DWTTRAP_OFS ( 2) /* DWTTRAP Offset */\r
-#define SCB_DFSR_DWTTRAP (0x00000004) /* */\r
-/* SCB_DFSR[SCB_DFSR_VCATCH] Bits */\r
-#define SCB_DFSR_VCATCH_OFS ( 3) /* VCATCH Offset */\r
-#define SCB_DFSR_VCATCH (0x00000008) /* */\r
-/* SCB_DFSR[SCB_DFSR_EXTERNAL] Bits */\r
-#define SCB_DFSR_EXTERNAL_OFS ( 4) /* EXTERNAL Offset */\r
-#define SCB_DFSR_EXTERNAL (0x00000010) /* */\r
-/* SCB_PFR0[SCB_PFR0_STATE0] Bits */\r
-#define SCB_PFR0_STATE0_OFS ( 0) /* STATE0 Offset */\r
-#define SCB_PFR0_STATE0_M (0x0000000f) /* */\r
-#define SCB_PFR0_STATE00 (0x00000001) /* */\r
-#define SCB_PFR0_STATE01 (0x00000002) /* */\r
-#define SCB_PFR0_STATE02 (0x00000004) /* */\r
-#define SCB_PFR0_STATE03 (0x00000008) /* */\r
-#define SCB_PFR0_STATE0_0 (0x00000000) /* no ARM encoding */\r
-#define SCB_PFR0_STATE0_1 (0x00000001) /* N/A */\r
-/* SCB_PFR0[SCB_PFR0_STATE1] Bits */\r
-#define SCB_PFR0_STATE1_OFS ( 4) /* STATE1 Offset */\r
-#define SCB_PFR0_STATE1_M (0x000000f0) /* */\r
-#define SCB_PFR0_STATE10 (0x00000010) /* */\r
-#define SCB_PFR0_STATE11 (0x00000020) /* */\r
-#define SCB_PFR0_STATE12 (0x00000040) /* */\r
-#define SCB_PFR0_STATE13 (0x00000080) /* */\r
-#define SCB_PFR0_STATE1_0 (0x00000000) /* N/A */\r
-#define SCB_PFR0_STATE1_1 (0x00000010) /* N/A */\r
-#define SCB_PFR0_STATE1_2 (0x00000020) /* Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) */\r
-#define SCB_PFR0_STATE1_3 (0x00000030) /* Thumb-2 encoding with all Thumb-2 basic instructions */\r
-/* SCB_PFR1[SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */\r
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /* MICROCONTROLLER_PROGRAMMERS_MODEL Offset */\r
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M (0x00000f00) /* */\r
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 (0x00000100) /* */\r
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 (0x00000200) /* */\r
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 (0x00000400) /* */\r
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 (0x00000800) /* */\r
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 (0x00000000) /* not supported */\r
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 (0x00000200) /* two-stack support */\r
-/* SCB_DFR0[SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL] Bits */\r
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /* MICROCONTROLLER_DEBUG_MODEL Offset */\r
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_M (0x00f00000) /* */\r
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 (0x00100000) /* */\r
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 (0x00200000) /* */\r
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 (0x00400000) /* */\r
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 (0x00800000) /* */\r
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 (0x00000000) /* not supported */\r
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 (0x00100000) /* Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */\r
-/* SCB_MMFR0[SCB_MMFR0_PMSA_SUPPORT] Bits */\r
-#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /* PMSA_SUPPORT Offset */\r
-#define SCB_MMFR0_PMSA_SUPPORT_M (0x000000f0) /* */\r
-#define SCB_MMFR0_PMSA_SUPPORT0 (0x00000010) /* */\r
-#define SCB_MMFR0_PMSA_SUPPORT1 (0x00000020) /* */\r
-#define SCB_MMFR0_PMSA_SUPPORT2 (0x00000040) /* */\r
-#define SCB_MMFR0_PMSA_SUPPORT3 (0x00000080) /* */\r
-#define SCB_MMFR0_PMSA_SUPPORT_0 (0x00000000) /* not supported */\r
-#define SCB_MMFR0_PMSA_SUPPORT_1 (0x00000010) /* IMPLEMENTATION DEFINED (N/A) */\r
-#define SCB_MMFR0_PMSA_SUPPORT_2 (0x00000020) /* PMSA base (features as defined for ARMv6) (N/A) */\r
-#define SCB_MMFR0_PMSA_SUPPORT_3 (0x00000030) /* PMSAv7 (base plus subregion support) */\r
-/* SCB_MMFR0[SCB_MMFR0_CACHE_COHERENCE_SUPPORT] Bits */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /* CACHE_COHERENCE_SUPPORT Offset */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_M (0x00000f00) /* */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 (0x00000100) /* */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 (0x00000200) /* */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 (0x00000400) /* */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 (0x00000800) /* */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 (0x00000000) /* no shared support */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 (0x00000100) /* partial-inner-shared coherency (coherency amongst some - but not all - of the entities within an inner-coherent domain) */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 (0x00000200) /* full-inner-shared coherency (coherency amongst all of the entities within an inner-coherent domain) */\r
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 (0x00000300) /* full coherency (coherency amongst all of the entities) */\r
-/* SCB_MMFR0[SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT] Bits */\r
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /* OUTER_NON_SHARABLE_SUPPORT Offset */\r
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_M (0x0000f000) /* */\r
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 (0x00001000) /* */\r
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 (0x00002000) /* */\r
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 (0x00004000) /* */\r
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 (0x00008000) /* */\r
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 (0x00000000) /* Outer non-sharable not supported */\r
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 (0x00001000) /* Outer sharable supported */\r
-/* SCB_MMFR0[SCB_MMFR0_AUILIARY_REGISTER_SUPPORT] Bits */\r
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /* AUXILIARY_REGISTER_SUPPORT Offset */\r
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_M (0x00f00000) /* */\r
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 (0x00100000) /* */\r
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 (0x00200000) /* */\r
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 (0x00400000) /* */\r
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 (0x00800000) /* */\r
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 (0x00000000) /* not supported */\r
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 (0x00100000) /* Auxiliary control register */\r
-/* SCB_MMFR2[SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING] Bits */\r
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /* WAIT_FOR_INTERRUPT_STALLING Offset */\r
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M (0x0f000000) /* */\r
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 (0x01000000) /* */\r
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 (0x02000000) /* */\r
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 (0x04000000) /* */\r
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 (0x08000000) /* */\r
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 (0x00000000) /* not supported */\r
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 (0x01000000) /* wait for interrupt supported */\r
-/* SCB_ISAR0[SCB_ISAR0_BITCOUNT_INSTRS] Bits */\r
-#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /* BITCOUNT_INSTRS Offset */\r
-#define SCB_ISAR0_BITCOUNT_INSTRS_M (0x000000f0) /* */\r
-#define SCB_ISAR0_BITCOUNT_INSTRS0 (0x00000010) /* */\r
-#define SCB_ISAR0_BITCOUNT_INSTRS1 (0x00000020) /* */\r
-#define SCB_ISAR0_BITCOUNT_INSTRS2 (0x00000040) /* */\r
-#define SCB_ISAR0_BITCOUNT_INSTRS3 (0x00000080) /* */\r
-#define SCB_ISAR0_BITCOUNT_INSTRS_0 (0x00000000) /* no bit-counting instructions present */\r
-#define SCB_ISAR0_BITCOUNT_INSTRS_1 (0x00000010) /* adds CLZ */\r
-/* SCB_ISAR0[SCB_ISAR0_BITFIELD_INSTRS] Bits */\r
-#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /* BITFIELD_INSTRS Offset */\r
-#define SCB_ISAR0_BITFIELD_INSTRS_M (0x00000f00) /* */\r
-#define SCB_ISAR0_BITFIELD_INSTRS0 (0x00000100) /* */\r
-#define SCB_ISAR0_BITFIELD_INSTRS1 (0x00000200) /* */\r
-#define SCB_ISAR0_BITFIELD_INSTRS2 (0x00000400) /* */\r
-#define SCB_ISAR0_BITFIELD_INSTRS3 (0x00000800) /* */\r
-#define SCB_ISAR0_BITFIELD_INSTRS_0 (0x00000000) /* no bitfield instructions present */\r
-#define SCB_ISAR0_BITFIELD_INSTRS_1 (0x00000100) /* adds BFC, BFI, SBFX, UBFX */\r
-/* SCB_ISAR0[SCB_ISAR0_CMPBRANCH_INSTRS] Bits */\r
-#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /* CMPBRANCH_INSTRS Offset */\r
-#define SCB_ISAR0_CMPBRANCH_INSTRS_M (0x0000f000) /* */\r
-#define SCB_ISAR0_CMPBRANCH_INSTRS0 (0x00001000) /* */\r
-#define SCB_ISAR0_CMPBRANCH_INSTRS1 (0x00002000) /* */\r
-#define SCB_ISAR0_CMPBRANCH_INSTRS2 (0x00004000) /* */\r
-#define SCB_ISAR0_CMPBRANCH_INSTRS3 (0x00008000) /* */\r
-#define SCB_ISAR0_CMPBRANCH_INSTRS_0 (0x00000000) /* no combined compare-and-branch instructions present */\r
-#define SCB_ISAR0_CMPBRANCH_INSTRS_1 (0x00001000) /* adds CB{N}Z */\r
-/* SCB_ISAR0[SCB_ISAR0_COPROC_INSTRS] Bits */\r
-#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /* COPROC_INSTRS Offset */\r
-#define SCB_ISAR0_COPROC_INSTRS_M (0x000f0000) /* */\r
-#define SCB_ISAR0_COPROC_INSTRS0 (0x00010000) /* */\r
-#define SCB_ISAR0_COPROC_INSTRS1 (0x00020000) /* */\r
-#define SCB_ISAR0_COPROC_INSTRS2 (0x00040000) /* */\r
-#define SCB_ISAR0_COPROC_INSTRS3 (0x00080000) /* */\r
-#define SCB_ISAR0_COPROC_INSTRS_0 (0x00000000) /* no coprocessor support, other than for separately attributed architectures such as CP15 or VFP */\r
-#define SCB_ISAR0_COPROC_INSTRS_1 (0x00010000) /* adds generic CDP, LDC, MCR, MRC, STC */\r
-#define SCB_ISAR0_COPROC_INSTRS_2 (0x00020000) /* adds generic CDP2, LDC2, MCR2, MRC2, STC2 */\r
-#define SCB_ISAR0_COPROC_INSTRS_3 (0x00030000) /* adds generic MCRR, MRRC */\r
-#define SCB_ISAR0_COPROC_INSTRS_4 (0x00040000) /* adds generic MCRR2, MRRC2 */\r
-/* SCB_ISAR0[SCB_ISAR0_DEBUG_INSTRS] Bits */\r
-#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /* DEBUG_INSTRS Offset */\r
-#define SCB_ISAR0_DEBUG_INSTRS_M (0x00f00000) /* */\r
-#define SCB_ISAR0_DEBUG_INSTRS0 (0x00100000) /* */\r
-#define SCB_ISAR0_DEBUG_INSTRS1 (0x00200000) /* */\r
-#define SCB_ISAR0_DEBUG_INSTRS2 (0x00400000) /* */\r
-#define SCB_ISAR0_DEBUG_INSTRS3 (0x00800000) /* */\r
-#define SCB_ISAR0_DEBUG_INSTRS_0 (0x00000000) /* no debug instructions present */\r
-#define SCB_ISAR0_DEBUG_INSTRS_1 (0x00100000) /* adds BKPT */\r
-/* SCB_ISAR0[SCB_ISAR0_DIVIDE_INSTRS] Bits */\r
-#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /* DIVIDE_INSTRS Offset */\r
-#define SCB_ISAR0_DIVIDE_INSTRS_M (0x0f000000) /* */\r
-#define SCB_ISAR0_DIVIDE_INSTRS0 (0x01000000) /* */\r
-#define SCB_ISAR0_DIVIDE_INSTRS1 (0x02000000) /* */\r
-#define SCB_ISAR0_DIVIDE_INSTRS2 (0x04000000) /* */\r
-#define SCB_ISAR0_DIVIDE_INSTRS3 (0x08000000) /* */\r
-#define SCB_ISAR0_DIVIDE_INSTRS_0 (0x00000000) /* no divide instructions present */\r
-#define SCB_ISAR0_DIVIDE_INSTRS_1 (0x01000000) /* adds SDIV, UDIV (v1 quotient only result) */\r
-/* SCB_ISAR1[SCB_ISAR1_ETEND_INSRS] Bits */\r
-#define SCB_ISAR1_ETEND_INSRS_OFS (12) /* EXTEND_INSRS Offset */\r
-#define SCB_ISAR1_ETEND_INSRS_M (0x0000f000) /* */\r
-#define SCB_ISAR1_ETEND_INSRS0 (0x00001000) /* */\r
-#define SCB_ISAR1_ETEND_INSRS1 (0x00002000) /* */\r
-#define SCB_ISAR1_ETEND_INSRS2 (0x00004000) /* */\r
-#define SCB_ISAR1_ETEND_INSRS3 (0x00008000) /* */\r
-#define SCB_ISAR1_ETEND_INSRS_0 (0x00000000) /* no scalar (i.e. non-SIMD) sign/zero-extend instructions present */\r
-#define SCB_ISAR1_ETEND_INSRS_1 (0x00001000) /* adds SXTB, SXTH, UXTB, UXTH */\r
-#define SCB_ISAR1_ETEND_INSRS_2 (0x00002000) /* N/A */\r
-/* SCB_ISAR1[SCB_ISAR1_IFTHEN_INSTRS] Bits */\r
-#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /* IFTHEN_INSTRS Offset */\r
-#define SCB_ISAR1_IFTHEN_INSTRS_M (0x000f0000) /* */\r
-#define SCB_ISAR1_IFTHEN_INSTRS0 (0x00010000) /* */\r
-#define SCB_ISAR1_IFTHEN_INSTRS1 (0x00020000) /* */\r
-#define SCB_ISAR1_IFTHEN_INSTRS2 (0x00040000) /* */\r
-#define SCB_ISAR1_IFTHEN_INSTRS3 (0x00080000) /* */\r
-#define SCB_ISAR1_IFTHEN_INSTRS_0 (0x00000000) /* IT instructions not present */\r
-#define SCB_ISAR1_IFTHEN_INSTRS_1 (0x00010000) /* adds IT instructions (and IT bits in PSRs) */\r
-/* SCB_ISAR1[SCB_ISAR1_IMMEDIATE_INSTRS] Bits */\r
-#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /* IMMEDIATE_INSTRS Offset */\r
-#define SCB_ISAR1_IMMEDIATE_INSTRS_M (0x00f00000) /* */\r
-#define SCB_ISAR1_IMMEDIATE_INSTRS0 (0x00100000) /* */\r
-#define SCB_ISAR1_IMMEDIATE_INSTRS1 (0x00200000) /* */\r
-#define SCB_ISAR1_IMMEDIATE_INSTRS2 (0x00400000) /* */\r
-#define SCB_ISAR1_IMMEDIATE_INSTRS3 (0x00800000) /* */\r
-#define SCB_ISAR1_IMMEDIATE_INSTRS_0 (0x00000000) /* no special immediate-generating instructions present */\r
-#define SCB_ISAR1_IMMEDIATE_INSTRS_1 (0x00100000) /* adds ADDW, MOVW, MOVT, SUBW */\r
-/* SCB_ISAR1[SCB_ISAR1_INTERWORK_INSTRS] Bits */\r
-#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /* INTERWORK_INSTRS Offset */\r
-#define SCB_ISAR1_INTERWORK_INSTRS_M (0x0f000000) /* */\r
-#define SCB_ISAR1_INTERWORK_INSTRS0 (0x01000000) /* */\r
-#define SCB_ISAR1_INTERWORK_INSTRS1 (0x02000000) /* */\r
-#define SCB_ISAR1_INTERWORK_INSTRS2 (0x04000000) /* */\r
-#define SCB_ISAR1_INTERWORK_INSTRS3 (0x08000000) /* */\r
-#define SCB_ISAR1_INTERWORK_INSTRS_0 (0x00000000) /* no interworking instructions supported */\r
-#define SCB_ISAR1_INTERWORK_INSTRS_1 (0x01000000) /* adds BX (and T bit in PSRs) */\r
-#define SCB_ISAR1_INTERWORK_INSTRS_2 (0x02000000) /* adds BLX, and PC loads have BX-like behavior */\r
-#define SCB_ISAR1_INTERWORK_INSTRS_3 (0x03000000) /* N/A */\r
-/* SCB_ISAR2[SCB_ISAR2_LOADSTORE_INSTRS] Bits */\r
-#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /* LOADSTORE_INSTRS Offset */\r
-#define SCB_ISAR2_LOADSTORE_INSTRS_M (0x0000000f) /* */\r
-#define SCB_ISAR2_LOADSTORE_INSTRS0 (0x00000001) /* */\r
-#define SCB_ISAR2_LOADSTORE_INSTRS1 (0x00000002) /* */\r
-#define SCB_ISAR2_LOADSTORE_INSTRS2 (0x00000004) /* */\r
-#define SCB_ISAR2_LOADSTORE_INSTRS3 (0x00000008) /* */\r
-#define SCB_ISAR2_LOADSTORE_INSTRS_0 (0x00000000) /* no additional normal load/store instructions present */\r
-#define SCB_ISAR2_LOADSTORE_INSTRS_1 (0x00000001) /* adds LDRD/STRD */\r
-/* SCB_ISAR2[SCB_ISAR2_MEMHINT_INSTRS] Bits */\r
-#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /* MEMHINT_INSTRS Offset */\r
-#define SCB_ISAR2_MEMHINT_INSTRS_M (0x000000f0) /* */\r
-#define SCB_ISAR2_MEMHINT_INSTRS0 (0x00000010) /* */\r
-#define SCB_ISAR2_MEMHINT_INSTRS1 (0x00000020) /* */\r
-#define SCB_ISAR2_MEMHINT_INSTRS2 (0x00000040) /* */\r
-#define SCB_ISAR2_MEMHINT_INSTRS3 (0x00000080) /* */\r
-#define SCB_ISAR2_MEMHINT_INSTRS_0 (0x00000000) /* no memory hint instructions presen */\r
-#define SCB_ISAR2_MEMHINT_INSTRS_1 (0x00000010) /* adds PLD */\r
-#define SCB_ISAR2_MEMHINT_INSTRS_2 (0x00000020) /* adds PLD (ie a repeat on value 1) */\r
-#define SCB_ISAR2_MEMHINT_INSTRS_3 (0x00000030) /* adds PLI */\r
-/* SCB_ISAR2[SCB_ISAR2_MULTIACCESSINT_INSTRS] Bits */\r
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /* MULTIACCESSINT_INSTRS Offset */\r
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_M (0x00000f00) /* */\r
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 (0x00000100) /* */\r
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 (0x00000200) /* */\r
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 (0x00000400) /* */\r
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 (0x00000800) /* */\r
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 (0x00000000) /* the (LDM/STM) instructions are non-interruptible */\r
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 (0x00000100) /* the (LDM/STM) instructions are restartable */\r
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 (0x00000200) /* the (LDM/STM) instructions are continuable */\r
-/* SCB_ISAR2[SCB_ISAR2_MULT_INSTRS] Bits */\r
-#define SCB_ISAR2_MULT_INSTRS_OFS (12) /* MULT_INSTRS Offset */\r
-#define SCB_ISAR2_MULT_INSTRS_M (0x0000f000) /* */\r
-#define SCB_ISAR2_MULT_INSTRS0 (0x00001000) /* */\r
-#define SCB_ISAR2_MULT_INSTRS1 (0x00002000) /* */\r
-#define SCB_ISAR2_MULT_INSTRS2 (0x00004000) /* */\r
-#define SCB_ISAR2_MULT_INSTRS3 (0x00008000) /* */\r
-#define SCB_ISAR2_MULT_INSTRS_0 (0x00000000) /* only MUL present */\r
-#define SCB_ISAR2_MULT_INSTRS_1 (0x00001000) /* adds MLA */\r
-#define SCB_ISAR2_MULT_INSTRS_2 (0x00002000) /* adds MLS */\r
-/* SCB_ISAR2[SCB_ISAR2_MULTS_INSTRS] Bits */\r
-#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /* MULTS_INSTRS Offset */\r
-#define SCB_ISAR2_MULTS_INSTRS_M (0x000f0000) /* */\r
-#define SCB_ISAR2_MULTS_INSTRS0 (0x00010000) /* */\r
-#define SCB_ISAR2_MULTS_INSTRS1 (0x00020000) /* */\r
-#define SCB_ISAR2_MULTS_INSTRS2 (0x00040000) /* */\r
-#define SCB_ISAR2_MULTS_INSTRS3 (0x00080000) /* */\r
-#define SCB_ISAR2_MULTS_INSTRS_0 (0x00000000) /* no signed multiply instructions present */\r
-#define SCB_ISAR2_MULTS_INSTRS_1 (0x00010000) /* adds SMULL, SMLAL */\r
-#define SCB_ISAR2_MULTS_INSTRS_2 (0x00020000) /* N/A */\r
-#define SCB_ISAR2_MULTS_INSTRS_3 (0x00030000) /* N/A */\r
-/* SCB_ISAR2[SCB_ISAR2_MULTU_INSTRS] Bits */\r
-#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /* MULTU_INSTRS Offset */\r
-#define SCB_ISAR2_MULTU_INSTRS_M (0x00f00000) /* */\r
-#define SCB_ISAR2_MULTU_INSTRS0 (0x00100000) /* */\r
-#define SCB_ISAR2_MULTU_INSTRS1 (0x00200000) /* */\r
-#define SCB_ISAR2_MULTU_INSTRS2 (0x00400000) /* */\r
-#define SCB_ISAR2_MULTU_INSTRS3 (0x00800000) /* */\r
-#define SCB_ISAR2_MULTU_INSTRS_0 (0x00000000) /* no unsigned multiply instructions present */\r
-#define SCB_ISAR2_MULTU_INSTRS_1 (0x00100000) /* adds UMULL, UMLAL */\r
-#define SCB_ISAR2_MULTU_INSTRS_2 (0x00200000) /* N/A */\r
-/* SCB_ISAR2[SCB_ISAR2_REVERSAL_INSTRS] Bits */\r
-#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /* REVERSAL_INSTRS Offset */\r
-#define SCB_ISAR2_REVERSAL_INSTRS_M (0xf0000000) /* */\r
-#define SCB_ISAR2_REVERSAL_INSTRS0 (0x10000000) /* */\r
-#define SCB_ISAR2_REVERSAL_INSTRS1 (0x20000000) /* */\r
-#define SCB_ISAR2_REVERSAL_INSTRS2 (0x40000000) /* */\r
-#define SCB_ISAR2_REVERSAL_INSTRS3 (0x80000000) /* */\r
-#define SCB_ISAR2_REVERSAL_INSTRS_0 (0x00000000) /* no reversal instructions present */\r
-#define SCB_ISAR2_REVERSAL_INSTRS_1 (0x10000000) /* adds REV, REV16, REVSH */\r
-#define SCB_ISAR2_REVERSAL_INSTRS_2 (0x20000000) /* adds RBIT */\r
-/* SCB_ISAR3[SCB_ISAR3_SATRUATE_INSTRS] Bits */\r
-#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /* SATRUATE_INSTRS Offset */\r
-#define SCB_ISAR3_SATRUATE_INSTRS_M (0x0000000f) /* */\r
-#define SCB_ISAR3_SATRUATE_INSTRS0 (0x00000001) /* */\r
-#define SCB_ISAR3_SATRUATE_INSTRS1 (0x00000002) /* */\r
-#define SCB_ISAR3_SATRUATE_INSTRS2 (0x00000004) /* */\r
-#define SCB_ISAR3_SATRUATE_INSTRS3 (0x00000008) /* */\r
-#define SCB_ISAR3_SATRUATE_INSTRS_0 (0x00000000) /* no non-SIMD saturate instructions present */\r
-#define SCB_ISAR3_SATRUATE_INSTRS_1 (0x00000001) /* N/A */\r
-/* SCB_ISAR3[SCB_ISAR3_SIMD_INSTRS] Bits */\r
-#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /* SIMD_INSTRS Offset */\r
-#define SCB_ISAR3_SIMD_INSTRS_M (0x000000f0) /* */\r
-#define SCB_ISAR3_SIMD_INSTRS0 (0x00000010) /* */\r
-#define SCB_ISAR3_SIMD_INSTRS1 (0x00000020) /* */\r
-#define SCB_ISAR3_SIMD_INSTRS2 (0x00000040) /* */\r
-#define SCB_ISAR3_SIMD_INSTRS3 (0x00000080) /* */\r
-#define SCB_ISAR3_SIMD_INSTRS_0 (0x00000000) /* no SIMD instructions present */\r
-#define SCB_ISAR3_SIMD_INSTRS_1 (0x00000010) /* adds SSAT, USAT (and the Q flag in the PSRs) */\r
-#define SCB_ISAR3_SIMD_INSTRS_3 (0x00000030) /* N/A */\r
-/* SCB_ISAR3[SCB_ISAR3_SVC_INSTRS] Bits */\r
-#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /* SVC_INSTRS Offset */\r
-#define SCB_ISAR3_SVC_INSTRS_M (0x00000f00) /* */\r
-#define SCB_ISAR3_SVC_INSTRS0 (0x00000100) /* */\r
-#define SCB_ISAR3_SVC_INSTRS1 (0x00000200) /* */\r
-#define SCB_ISAR3_SVC_INSTRS2 (0x00000400) /* */\r
-#define SCB_ISAR3_SVC_INSTRS3 (0x00000800) /* */\r
-#define SCB_ISAR3_SVC_INSTRS_0 (0x00000000) /* no SVC (SWI) instructions present */\r
-#define SCB_ISAR3_SVC_INSTRS_1 (0x00000100) /* adds SVC (SWI) */\r
-/* SCB_ISAR3[SCB_ISAR3_SYNCPRIM_INSTRS] Bits */\r
-#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /* SYNCPRIM_INSTRS Offset */\r
-#define SCB_ISAR3_SYNCPRIM_INSTRS_M (0x0000f000) /* */\r
-#define SCB_ISAR3_SYNCPRIM_INSTRS0 (0x00001000) /* */\r
-#define SCB_ISAR3_SYNCPRIM_INSTRS1 (0x00002000) /* */\r
-#define SCB_ISAR3_SYNCPRIM_INSTRS2 (0x00004000) /* */\r
-#define SCB_ISAR3_SYNCPRIM_INSTRS3 (0x00008000) /* */\r
-#define SCB_ISAR3_SYNCPRIM_INSTRS_0 (0x00000000) /* no synchronization primitives present */\r
-#define SCB_ISAR3_SYNCPRIM_INSTRS_1 (0x00001000) /* adds LDREX, STREX */\r
-#define SCB_ISAR3_SYNCPRIM_INSTRS_2 (0x00002000) /* adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */\r
-/* SCB_ISAR3[SCB_ISAR3_TABBRANCH_INSTRS] Bits */\r
-#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /* TABBRANCH_INSTRS Offset */\r
-#define SCB_ISAR3_TABBRANCH_INSTRS_M (0x000f0000) /* */\r
-#define SCB_ISAR3_TABBRANCH_INSTRS0 (0x00010000) /* */\r
-#define SCB_ISAR3_TABBRANCH_INSTRS1 (0x00020000) /* */\r
-#define SCB_ISAR3_TABBRANCH_INSTRS2 (0x00040000) /* */\r
-#define SCB_ISAR3_TABBRANCH_INSTRS3 (0x00080000) /* */\r
-#define SCB_ISAR3_TABBRANCH_INSTRS_0 (0x00000000) /* no table-branch instructions present */\r
-#define SCB_ISAR3_TABBRANCH_INSTRS_1 (0x00010000) /* adds TBB, TBH */\r
-/* SCB_ISAR3[SCB_ISAR3_THUMBCOPY_INSTRS] Bits */\r
-#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /* THUMBCOPY_INSTRS Offset */\r
-#define SCB_ISAR3_THUMBCOPY_INSTRS_M (0x00f00000) /* */\r
-#define SCB_ISAR3_THUMBCOPY_INSTRS0 (0x00100000) /* */\r
-#define SCB_ISAR3_THUMBCOPY_INSTRS1 (0x00200000) /* */\r
-#define SCB_ISAR3_THUMBCOPY_INSTRS2 (0x00400000) /* */\r
-#define SCB_ISAR3_THUMBCOPY_INSTRS3 (0x00800000) /* */\r
-#define SCB_ISAR3_THUMBCOPY_INSTRS_0 (0x00000000) /* Thumb MOV(register) instruction does not allow low reg -> low reg */\r
-#define SCB_ISAR3_THUMBCOPY_INSTRS_1 (0x00100000) /* adds Thumb MOV(register) low reg -> low reg and the CPY alias */\r
-/* SCB_ISAR3[SCB_ISAR3_TRUENOP_INSTRS] Bits */\r
-#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /* TRUENOP_INSTRS Offset */\r
-#define SCB_ISAR3_TRUENOP_INSTRS_M (0x0f000000) /* */\r
-#define SCB_ISAR3_TRUENOP_INSTRS0 (0x01000000) /* */\r
-#define SCB_ISAR3_TRUENOP_INSTRS1 (0x02000000) /* */\r
-#define SCB_ISAR3_TRUENOP_INSTRS2 (0x04000000) /* */\r
-#define SCB_ISAR3_TRUENOP_INSTRS3 (0x08000000) /* */\r
-#define SCB_ISAR3_TRUENOP_INSTRS_0 (0x00000000) /* true NOP instructions not present - that is, NOP instructions with no register dependencies */\r
-#define SCB_ISAR3_TRUENOP_INSTRS_1 (0x01000000) /* adds "true NOP", and the capability of additional "NOP compatible hints" */\r
-/* SCB_ISAR4[SCB_ISAR4_UNPRIV_INSTRS] Bits */\r
-#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /* UNPRIV_INSTRS Offset */\r
-#define SCB_ISAR4_UNPRIV_INSTRS_M (0x0000000f) /* */\r
-#define SCB_ISAR4_UNPRIV_INSTRS0 (0x00000001) /* */\r
-#define SCB_ISAR4_UNPRIV_INSTRS1 (0x00000002) /* */\r
-#define SCB_ISAR4_UNPRIV_INSTRS2 (0x00000004) /* */\r
-#define SCB_ISAR4_UNPRIV_INSTRS3 (0x00000008) /* */\r
-#define SCB_ISAR4_UNPRIV_INSTRS_0 (0x00000000) /* no "T variant" instructions exist */\r
-#define SCB_ISAR4_UNPRIV_INSTRS_1 (0x00000001) /* adds LDRBT, LDRT, STRBT, STRT */\r
-#define SCB_ISAR4_UNPRIV_INSTRS_2 (0x00000002) /* adds LDRHT, LDRSBT, LDRSHT, STRHT */\r
-/* SCB_ISAR4[SCB_ISAR4_WITHSHIFTS_INSTRS] Bits */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /* WITHSHIFTS_INSTRS Offset */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_M (0x000000f0) /* */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS0 (0x00000010) /* */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS1 (0x00000020) /* */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS2 (0x00000040) /* */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS3 (0x00000080) /* */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 (0x00000000) /* non-zero shifts only support MOV and shift instructions (see notes) */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 (0x00000010) /* shifts of loads/stores over the range LSL 0-3 */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 (0x00000030) /* adds other constant shift options. */\r
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 (0x00000040) /* adds register-controlled shift options. */\r
-/* SCB_ISAR4[SCB_ISAR4_WRITEBACK_INSTRS] Bits */\r
-#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /* WRITEBACK_INSTRS Offset */\r
-#define SCB_ISAR4_WRITEBACK_INSTRS_M (0x00000f00) /* */\r
-#define SCB_ISAR4_WRITEBACK_INSTRS0 (0x00000100) /* */\r
-#define SCB_ISAR4_WRITEBACK_INSTRS1 (0x00000200) /* */\r
-#define SCB_ISAR4_WRITEBACK_INSTRS2 (0x00000400) /* */\r
-#define SCB_ISAR4_WRITEBACK_INSTRS3 (0x00000800) /* */\r
-#define SCB_ISAR4_WRITEBACK_INSTRS_0 (0x00000000) /* only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */\r
-#define SCB_ISAR4_WRITEBACK_INSTRS_1 (0x00000100) /* adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */\r
-/* SCB_ISAR4[SCB_ISAR4_BARRIER_INSTRS] Bits */\r
-#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /* BARRIER_INSTRS Offset */\r
-#define SCB_ISAR4_BARRIER_INSTRS_M (0x000f0000) /* */\r
-#define SCB_ISAR4_BARRIER_INSTRS0 (0x00010000) /* */\r
-#define SCB_ISAR4_BARRIER_INSTRS1 (0x00020000) /* */\r
-#define SCB_ISAR4_BARRIER_INSTRS2 (0x00040000) /* */\r
-#define SCB_ISAR4_BARRIER_INSTRS3 (0x00080000) /* */\r
-#define SCB_ISAR4_BARRIER_INSTRS_0 (0x00000000) /* no barrier instructions supported */\r
-#define SCB_ISAR4_BARRIER_INSTRS_1 (0x00010000) /* adds DMB, DSB, ISB barrier instructions */\r
-/* SCB_ISAR4[SCB_ISAR4_SYNCPRIM_INSTRS_FRAC] Bits */\r
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /* SYNCPRIM_INSTRS_FRAC Offset */\r
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_M (0x00f00000) /* */\r
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 (0x00100000) /* */\r
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 (0x00200000) /* */\r
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 (0x00400000) /* */\r
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 (0x00800000) /* */\r
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 (0x00000000) /* no additional support */\r
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 (0x00300000) /* adds CLREX, LDREXB, STREXB, LDREXH, STREXH */\r
-/* SCB_ISAR4[SCB_ISAR4_PSR_M_INSTRS] Bits */\r
-#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /* PSR_M_INSTRS Offset */\r
-#define SCB_ISAR4_PSR_M_INSTRS_M (0x0f000000) /* */\r
-#define SCB_ISAR4_PSR_M_INSTRS0 (0x01000000) /* */\r
-#define SCB_ISAR4_PSR_M_INSTRS1 (0x02000000) /* */\r
-#define SCB_ISAR4_PSR_M_INSTRS2 (0x04000000) /* */\r
-#define SCB_ISAR4_PSR_M_INSTRS3 (0x08000000) /* */\r
-#define SCB_ISAR4_PSR_M_INSTRS_0 (0x00000000) /* instructions not present */\r
-#define SCB_ISAR4_PSR_M_INSTRS_1 (0x01000000) /* adds CPS, MRS, and MSR instructions (M-profile forms) */\r
-/* SCB_CPACR[SCB_CPACR_CP11] Bits */\r
-#define SCB_CPACR_CP11_OFS (22) /* CP11 Offset */\r
-#define SCB_CPACR_CP11_M (0x00c00000) /* */\r
-/* SCB_CPACR[SCB_CPACR_CP10] Bits */\r
-#define SCB_CPACR_CP10_OFS (20) /* CP10 Offset */\r
-#define SCB_CPACR_CP10_M (0x00300000) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// SCnSCB Bits\r
-//*****************************************************************************\r
-/* SCSCB_ICTR[SCNSCB_ICTR_INTLINESNUM] Bits */\r
-#define SCNSCB_ICTR_INTLINESNUM_OFS ( 0) /* INTLINESNUM Offset */\r
-#define SCNSCB_ICTR_INTLINESNUM_M (0x0000001f) /* */\r
-/* SCSCB_ACTLR[SCNSCB_ACTLR_DISMCYCINT] Bits */\r
-#define SCNSCB_ACTLR_DISMCYCINT_OFS ( 0) /* DISMCYCINT Offset */\r
-#define SCNSCB_ACTLR_DISMCYCINT (0x00000001) /* */\r
-/* SCSCB_ACTLR[SCNSCB_ACTLR_DISDEFWBUF] Bits */\r
-#define SCNSCB_ACTLR_DISDEFWBUF_OFS ( 1) /* DISDEFWBUF Offset */\r
-#define SCNSCB_ACTLR_DISDEFWBUF (0x00000002) /* */\r
-/* SCSCB_ACTLR[SCNSCB_ACTLR_DISFOLD] Bits */\r
-#define SCNSCB_ACTLR_DISFOLD_OFS ( 2) /* DISFOLD Offset */\r
-#define SCNSCB_ACTLR_DISFOLD (0x00000004) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// SYSCTL Bits\r
-//*****************************************************************************\r
-/* SYSCTL_REBOOT_CTL[SYSCTL_REBOOT_CTL_REBOOT] Bits */\r
-#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /* REBOOT Offset */\r
-#define SYSCTL_REBOOT_CTL_REBOOT (0x00000001) /* Write 1 initiates a Reboot of the device */\r
-/* SYSCTL_REBOOT_CTL[SYSCTL_REBOOT_CTL_WKEY] Bits */\r
-#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /* WKEY Offset */\r
-#define SYSCTL_REBOOT_CTL_WKEY_M (0x0000ff00) /* Key to enable writes to bit 0 */\r
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_CS_SRC] Bits */\r
-#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /* CS_SRC Offset */\r
-#define SYSCTL_NMI_CTLSTAT_CS_SRC (0x00000001) /* CS interrupt as a source of NMI */\r
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PSS_SRC] Bits */\r
-#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /* PSS_SRC Offset */\r
-#define SYSCTL_NMI_CTLSTAT_PSS_SRC (0x00000002) /* PSS interrupt as a source of NMI */\r
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PCM_SRC] Bits */\r
-#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /* PCM_SRC Offset */\r
-#define SYSCTL_NMI_CTLSTAT_PCM_SRC (0x00000004) /* PCM interrupt as a source of NMI */\r
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PIN_SRC] Bits */\r
-#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /* PIN_SRC Offset */\r
-#define SYSCTL_NMI_CTLSTAT_PIN_SRC (0x00000008) /* */\r
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_CS_FLG] Bits */\r
-#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /* CS_FLG Offset */\r
-#define SYSCTL_NMI_CTLSTAT_CS_FLG (0x00010000) /* CS interrupt was the source of NMI */\r
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PSS_FLG] Bits */\r
-#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /* PSS_FLG Offset */\r
-#define SYSCTL_NMI_CTLSTAT_PSS_FLG (0x00020000) /* PSS interrupt was the source of NMI */\r
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PCM_FLG] Bits */\r
-#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /* PCM_FLG Offset */\r
-#define SYSCTL_NMI_CTLSTAT_PCM_FLG (0x00040000) /* PCM interrupt was the source of NMI */\r
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PIN_FLG] Bits */\r
-#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /* PIN_FLG Offset */\r
-#define SYSCTL_NMI_CTLSTAT_PIN_FLG (0x00080000) /* RSTn/NMI pin was the source of NMI */\r
-/* SYSCTL_WDTRESET_CTL[SYSCTL_WDTRESET_CTL_TIMEOUT] Bits */\r
-#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /* TIMEOUT Offset */\r
-#define SYSCTL_WDTRESET_CTL_TIMEOUT (0x00000001) /* WDT timeout reset type */\r
-/* SYSCTL_WDTRESET_CTL[SYSCTL_WDTRESET_CTL_VIOLATION] Bits */\r
-#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /* VIOLATION Offset */\r
-#define SYSCTL_WDTRESET_CTL_VIOLATION (0x00000002) /* WDT password violation reset type */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_0] Bits */\r
-#define SYSCTL_PERIHALT_CTL_T16_0_OFS ( 0) /* T16_0 Offset */\r
-#define SYSCTL_PERIHALT_CTL_T16_0 (0x00000001) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_1] Bits */\r
-#define SYSCTL_PERIHALT_CTL_T16_1_OFS ( 1) /* T16_1 Offset */\r
-#define SYSCTL_PERIHALT_CTL_T16_1 (0x00000002) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_2] Bits */\r
-#define SYSCTL_PERIHALT_CTL_T16_2_OFS ( 2) /* T16_2 Offset */\r
-#define SYSCTL_PERIHALT_CTL_T16_2 (0x00000004) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_3] Bits */\r
-#define SYSCTL_PERIHALT_CTL_T16_3_OFS ( 3) /* T16_3 Offset */\r
-#define SYSCTL_PERIHALT_CTL_T16_3 (0x00000008) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T32_0] Bits */\r
-#define SYSCTL_PERIHALT_CTL_T32_0_OFS ( 4) /* T32_0 Offset */\r
-#define SYSCTL_PERIHALT_CTL_T32_0 (0x00000010) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA0] Bits */\r
-#define SYSCTL_PERIHALT_CTL_EUA0_OFS ( 5) /* eUA0 Offset */\r
-#define SYSCTL_PERIHALT_CTL_EUA0 (0x00000020) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA1] Bits */\r
-#define SYSCTL_PERIHALT_CTL_EUA1_OFS ( 6) /* eUA1 Offset */\r
-#define SYSCTL_PERIHALT_CTL_EUA1 (0x00000040) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA2] Bits */\r
-#define SYSCTL_PERIHALT_CTL_EUA2_OFS ( 7) /* eUA2 Offset */\r
-#define SYSCTL_PERIHALT_CTL_EUA2 (0x00000080) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA3] Bits */\r
-#define SYSCTL_PERIHALT_CTL_EUA3_OFS ( 8) /* eUA3 Offset */\r
-#define SYSCTL_PERIHALT_CTL_EUA3 (0x00000100) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB0] Bits */\r
-#define SYSCTL_PERIHALT_CTL_EUB0_OFS ( 9) /* eUB0 Offset */\r
-#define SYSCTL_PERIHALT_CTL_EUB0 (0x00000200) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB1] Bits */\r
-#define SYSCTL_PERIHALT_CTL_EUB1_OFS (10) /* eUB1 Offset */\r
-#define SYSCTL_PERIHALT_CTL_EUB1 (0x00000400) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB2] Bits */\r
-#define SYSCTL_PERIHALT_CTL_EUB2_OFS (11) /* eUB2 Offset */\r
-#define SYSCTL_PERIHALT_CTL_EUB2 (0x00000800) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB3] Bits */\r
-#define SYSCTL_PERIHALT_CTL_EUB3_OFS (12) /* eUB3 Offset */\r
-#define SYSCTL_PERIHALT_CTL_EUB3 (0x00001000) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_ADC] Bits */\r
-#define SYSCTL_PERIHALT_CTL_ADC_OFS (13) /* ADC Offset */\r
-#define SYSCTL_PERIHALT_CTL_ADC (0x00002000) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_WDT] Bits */\r
-#define SYSCTL_PERIHALT_CTL_WDT_OFS (14) /* WDT Offset */\r
-#define SYSCTL_PERIHALT_CTL_WDT (0x00004000) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_DMA] Bits */\r
-#define SYSCTL_PERIHALT_CTL_DMA_OFS (15) /* DMA Offset */\r
-#define SYSCTL_PERIHALT_CTL_DMA (0x00008000) /* Freezes IP operation when CPU is halted */\r
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK0_EN] Bits */\r
-#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /* BNK0_EN Offset */\r
-#define SYSCTL_SRAM_BANKEN_BNK0_EN (0x00000001) /* SRAM Bank0 enable */\r
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK1_EN] Bits */\r
-#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /* BNK1_EN Offset */\r
-#define SYSCTL_SRAM_BANKEN_BNK1_EN (0x00000002) /* SRAM Bank1 enable */\r
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK2_EN] Bits */\r
-#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /* BNK2_EN Offset */\r
-#define SYSCTL_SRAM_BANKEN_BNK2_EN (0x00000004) /* SRAM Bank1 enable */\r
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK3_EN] Bits */\r
-#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /* BNK3_EN Offset */\r
-#define SYSCTL_SRAM_BANKEN_BNK3_EN (0x00000008) /* SRAM Bank1 enable */\r
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK4_EN] Bits */\r
-#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /* BNK4_EN Offset */\r
-#define SYSCTL_SRAM_BANKEN_BNK4_EN (0x00000010) /* SRAM Bank1 enable */\r
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK5_EN] Bits */\r
-#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /* BNK5_EN Offset */\r
-#define SYSCTL_SRAM_BANKEN_BNK5_EN (0x00000020) /* SRAM Bank1 enable */\r
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK6_EN] Bits */\r
-#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /* BNK6_EN Offset */\r
-#define SYSCTL_SRAM_BANKEN_BNK6_EN (0x00000040) /* SRAM Bank1 enable */\r
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK7_EN] Bits */\r
-#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /* BNK7_EN Offset */\r
-#define SYSCTL_SRAM_BANKEN_BNK7_EN (0x00000080) /* SRAM Bank1 enable */\r
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_SRAM_RDY] Bits */\r
-#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /* SRAM_RDY Offset */\r
-#define SYSCTL_SRAM_BANKEN_SRAM_RDY (0x00010000) /* SRAM ready */\r
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK0_RET] Bits */\r
-#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /* BNK0_RET Offset */\r
-#define SYSCTL_SRAM_BANKRET_BNK0_RET (0x00000001) /* Bank0 retention */\r
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK1_RET] Bits */\r
-#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /* BNK1_RET Offset */\r
-#define SYSCTL_SRAM_BANKRET_BNK1_RET (0x00000002) /* Bank1 retention */\r
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK2_RET] Bits */\r
-#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /* BNK2_RET Offset */\r
-#define SYSCTL_SRAM_BANKRET_BNK2_RET (0x00000004) /* Bank2 retention */\r
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK3_RET] Bits */\r
-#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /* BNK3_RET Offset */\r
-#define SYSCTL_SRAM_BANKRET_BNK3_RET (0x00000008) /* Bank3 retention */\r
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK4_RET] Bits */\r
-#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /* BNK4_RET Offset */\r
-#define SYSCTL_SRAM_BANKRET_BNK4_RET (0x00000010) /* Bank4 retention */\r
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK5_RET] Bits */\r
-#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /* BNK5_RET Offset */\r
-#define SYSCTL_SRAM_BANKRET_BNK5_RET (0x00000020) /* Bank5 retention */\r
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK6_RET] Bits */\r
-#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /* BNK6_RET Offset */\r
-#define SYSCTL_SRAM_BANKRET_BNK6_RET (0x00000040) /* Bank6 retention */\r
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK7_RET] Bits */\r
-#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /* BNK7_RET Offset */\r
-#define SYSCTL_SRAM_BANKRET_BNK7_RET (0x00000080) /* Bank7 retention */\r
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_SRAM_RDY] Bits */\r
-#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /* SRAM_RDY Offset */\r
-#define SYSCTL_SRAM_BANKRET_SRAM_RDY (0x00010000) /* SRAM ready */\r
-/* SYSCTL_DIO_GLTFLT_CTL[SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN] Bits */\r
-#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /* GLTCH_EN Offset */\r
-#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN (0x00000001) /* Glitch filter enable */\r
-/* SYSCTL_SECDATA_UNLOCK[SYSCTL_SECDATA_UNLOCK_UNLKEY] Bits */\r
-#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /* UNLKEY Offset */\r
-#define SYSCTL_SECDATA_UNLOCK_UNLKEY_M (0x0000ffff) /* Unlock key */\r
-/* SYSCTL_MASTER_UNLOCK[SYSCTL_MASTER_UNLOCK_UNLKEY] Bits */\r
-#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /* UNLKEY Offset */\r
-#define SYSCTL_MASTER_UNLOCK_UNLKEY_M (0x0000ffff) /* Unlock Key */\r
-/* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_POR] Bits */\r
-#define SYSCTL_RESET_REQ_POR_OFS ( 0) /* POR Offset */\r
-#define SYSCTL_RESET_REQ_POR (0x00000001) /* Generate POR */\r
-/* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_REBOOT] Bits */\r
-#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /* REBOOT Offset */\r
-#define SYSCTL_RESET_REQ_REBOOT (0x00000002) /* Generate Reboot_Reset */\r
-/* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_WKEY] Bits */\r
-#define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /* WKEY Offset */\r
-#define SYSCTL_RESET_REQ_WKEY_M (0x0000ff00) /* Write key */\r
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_SOFT] Bits */\r
-#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /* SOFT Offset */\r
-#define SYSCTL_RESET_STATOVER_SOFT (0x00000001) /* Indicates if SOFT Reset is active */\r
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_HARD] Bits */\r
-#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /* HARD Offset */\r
-#define SYSCTL_RESET_STATOVER_HARD (0x00000002) /* Indicates if HARD Reset is active */\r
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_REBOOT] Bits */\r
-#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /* REBOOT Offset */\r
-#define SYSCTL_RESET_STATOVER_REBOOT (0x00000004) /* Indicates if Reboot Reset is active */\r
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_SOFT_OVER] Bits */\r
-#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /* SOFT_OVER Offset */\r
-#define SYSCTL_RESET_STATOVER_SOFT_OVER (0x00000100) /* SOFT_Reset overwrite request */\r
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_HARD_OVER] Bits */\r
-#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /* HARD_OVER Offset */\r
-#define SYSCTL_RESET_STATOVER_HARD_OVER (0x00000200) /* HARD_Reset overwrite request */\r
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_RBT_OVER] Bits */\r
-#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /* RBT_OVER Offset */\r
-#define SYSCTL_RESET_STATOVER_RBT_OVER (0x00000400) /* Reboot Reset overwrite request */\r
-/* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_DBG_SEC_ACT] Bits */\r
-#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /* DBG_SEC_ACT Offset */\r
-#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT (0x00000008) /* Debug Security active */\r
-/* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT] Bits */\r
-#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /* JTAG_SWD_LOCK_ACT Offset */\r
-#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT (0x00000010) /* Indicates if JTAG and SWD Lock is active */\r
-/* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_IP_PROT_ACT] Bits */\r
-#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /* IP_PROT_ACT Offset */\r
-#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT (0x00000020) /* Indicates if IP protection is active */\r
+#define RTC_C_KEY ((uint16_t)0xA500) /* RTC_C Key Value for RTC_C write access */\r
+#define RTC_C_KEY_H ((uint16_t)0x00A5) /* RTC_C Key Value for RTC_C write access */\r
+#define RTC_C_KEY_VAL ((uint16_t)0xA500) /* RTC_C Key Value for RTC_C write access */\r
+\r
+\r
+/******************************************************************************\r
+* SCB Bits\r
+******************************************************************************/\r
+/* SCB_PFR0[STATE0] Bits */\r
+#define SCB_PFR0_STATE0_OFS ( 0) /**< STATE0 Bit Offset */\r
+#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /**< STATE0 Bit Mask */\r
+#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /**< STATE0 Bit 0 */\r
+#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /**< STATE0 Bit 1 */\r
+#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /**< STATE0 Bit 2 */\r
+#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /**< STATE0 Bit 3 */\r
+#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /**< no ARM encoding */\r
+#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /**< N/A */\r
+/* SCB_PFR0[STATE1] Bits */\r
+#define SCB_PFR0_STATE1_OFS ( 4) /**< STATE1 Bit Offset */\r
+#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /**< STATE1 Bit Mask */\r
+#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /**< STATE1 Bit 0 */\r
+#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /**< STATE1 Bit 1 */\r
+#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /**< STATE1 Bit 2 */\r
+#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /**< STATE1 Bit 3 */\r
+#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /**< N/A */\r
+#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /**< N/A */\r
+#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /**< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but */\r
+ /* no other 32-bit basic instructions (Note non-basic 32-bit instructions can be */\r
+ /* added using the appropriate instruction attribute, but other 32-bit basic */\r
+ /* instructions cannot.) */\r
+#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /**< Thumb-2 encoding with all Thumb-2 basic instructions */\r
+/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */\r
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */\r
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */\r
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */\r
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */\r
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */\r
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */\r
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /**< not supported */\r
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /**< two-stack support */\r
+/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */\r
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /**< MICROCONTROLLER_DEBUG_MODEL Bit Offset */\r
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /**< MICROCONTROLLER_DEBUG_MODEL Bit Mask */\r
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 0 */\r
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 1 */\r
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 2 */\r
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 3 */\r
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /**< not supported */\r
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /**< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */\r
+/* SCB_MMFR0[PMSA_SUPPORT] Bits */\r
+#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /**< PMSA_SUPPORT Bit Offset */\r
+#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /**< PMSA_SUPPORT Bit Mask */\r
+#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /**< PMSA_SUPPORT Bit 0 */\r
+#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /**< PMSA_SUPPORT Bit 1 */\r
+#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /**< PMSA_SUPPORT Bit 2 */\r
+#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /**< PMSA_SUPPORT Bit 3 */\r
+#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /**< not supported */\r
+#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /**< IMPLEMENTATION DEFINED (N/A) */\r
+#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /**< PMSA base (features as defined for ARMv6) (N/A) */\r
+#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /**< PMSAv7 (base plus subregion support) */\r
+/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /**< CACHE_COHERENCE_SUPPORT Bit Offset */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /**< CACHE_COHERENCE_SUPPORT Bit Mask */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /**< CACHE_COHERENCE_SUPPORT Bit 0 */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /**< CACHE_COHERENCE_SUPPORT Bit 1 */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /**< CACHE_COHERENCE_SUPPORT Bit 2 */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /**< CACHE_COHERENCE_SUPPORT Bit 3 */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /**< no shared support */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /**< partial-inner-shared coherency (coherency amongst some - but not all - of the */\r
+ /* entities within an inner-coherent domain) */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /**< full-inner-shared coherency (coherency amongst all of the entities within an */\r
+ /* inner-coherent domain) */\r
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /**< full coherency (coherency amongst all of the entities) */\r
+/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */\r
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /**< OUTER_NON_SHARABLE_SUPPORT Bit Offset */\r
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /**< OUTER_NON_SHARABLE_SUPPORT Bit Mask */\r
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 0 */\r
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 1 */\r
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 2 */\r
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 3 */\r
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /**< Outer non-sharable not supported */\r
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /**< Outer sharable supported */\r
+/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */\r
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /**< AUXILIARY_REGISTER_SUPPORT Bit Offset */\r
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /**< AUXILIARY_REGISTER_SUPPORT Bit Mask */\r
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /**< AUILIARY_REGISTER_SUPPORT Bit 0 */\r
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /**< AUILIARY_REGISTER_SUPPORT Bit 1 */\r
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /**< AUILIARY_REGISTER_SUPPORT Bit 2 */\r
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /**< AUILIARY_REGISTER_SUPPORT Bit 3 */\r
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /**< not supported */\r
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /**< Auxiliary control register */\r
+/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */\r
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /**< WAIT_FOR_INTERRUPT_STALLING Bit Offset */\r
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit Mask */\r
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 0 */\r
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 1 */\r
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 2 */\r
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 3 */\r
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /**< not supported */\r
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /**< wait for interrupt supported */\r
+/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */\r
+#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /**< BITCOUNT_INSTRS Bit Offset */\r
+#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /**< BITCOUNT_INSTRS Bit Mask */\r
+#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /**< BITCOUNT_INSTRS Bit 0 */\r
+#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /**< BITCOUNT_INSTRS Bit 1 */\r
+#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /**< BITCOUNT_INSTRS Bit 2 */\r
+#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /**< BITCOUNT_INSTRS Bit 3 */\r
+#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /**< no bit-counting instructions present */\r
+#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /**< adds CLZ */\r
+/* SCB_ISAR0[BITFIELD_INSTRS] Bits */\r
+#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /**< BITFIELD_INSTRS Bit Offset */\r
+#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /**< BITFIELD_INSTRS Bit Mask */\r
+#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /**< BITFIELD_INSTRS Bit 0 */\r
+#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /**< BITFIELD_INSTRS Bit 1 */\r
+#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /**< BITFIELD_INSTRS Bit 2 */\r
+#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /**< BITFIELD_INSTRS Bit 3 */\r
+#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /**< no bitfield instructions present */\r
+#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /**< adds BFC, BFI, SBFX, UBFX */\r
+/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */\r
+#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /**< CMPBRANCH_INSTRS Bit Offset */\r
+#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /**< CMPBRANCH_INSTRS Bit Mask */\r
+#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /**< CMPBRANCH_INSTRS Bit 0 */\r
+#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /**< CMPBRANCH_INSTRS Bit 1 */\r
+#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /**< CMPBRANCH_INSTRS Bit 2 */\r
+#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /**< CMPBRANCH_INSTRS Bit 3 */\r
+#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /**< no combined compare-and-branch instructions present */\r
+#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /**< adds CB{N}Z */\r
+/* SCB_ISAR0[COPROC_INSTRS] Bits */\r
+#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /**< COPROC_INSTRS Bit Offset */\r
+#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /**< COPROC_INSTRS Bit Mask */\r
+#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /**< COPROC_INSTRS Bit 0 */\r
+#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /**< COPROC_INSTRS Bit 1 */\r
+#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /**< COPROC_INSTRS Bit 2 */\r
+#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /**< COPROC_INSTRS Bit 3 */\r
+#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /**< no coprocessor support, other than for separately attributed architectures */\r
+ /* such as CP15 or VFP */\r
+#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /**< adds generic CDP, LDC, MCR, MRC, STC */\r
+#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /**< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */\r
+#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /**< adds generic MCRR, MRRC */\r
+#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /**< adds generic MCRR2, MRRC2 */\r
+/* SCB_ISAR0[DEBUG_INSTRS] Bits */\r
+#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /**< DEBUG_INSTRS Bit Offset */\r
+#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /**< DEBUG_INSTRS Bit Mask */\r
+#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /**< DEBUG_INSTRS Bit 0 */\r
+#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /**< DEBUG_INSTRS Bit 1 */\r
+#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /**< DEBUG_INSTRS Bit 2 */\r
+#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /**< DEBUG_INSTRS Bit 3 */\r
+#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /**< no debug instructions present */\r
+#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /**< adds BKPT */\r
+/* SCB_ISAR0[DIVIDE_INSTRS] Bits */\r
+#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /**< DIVIDE_INSTRS Bit Offset */\r
+#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /**< DIVIDE_INSTRS Bit Mask */\r
+#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /**< DIVIDE_INSTRS Bit 0 */\r
+#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /**< DIVIDE_INSTRS Bit 1 */\r
+#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /**< DIVIDE_INSTRS Bit 2 */\r
+#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /**< DIVIDE_INSTRS Bit 3 */\r
+#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /**< no divide instructions present */\r
+#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /**< adds SDIV, UDIV (v1 quotient only result) */\r
+/* SCB_ISAR1[ETEND_INSRS] Bits */\r
+#define SCB_ISAR1_ETEND_INSRS_OFS (12) /**< EXTEND_INSRS Bit Offset */\r
+#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /**< EXTEND_INSRS Bit Mask */\r
+#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /**< ETEND_INSRS Bit 0 */\r
+#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /**< ETEND_INSRS Bit 1 */\r
+#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /**< ETEND_INSRS Bit 2 */\r
+#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /**< ETEND_INSRS Bit 3 */\r
+#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /**< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */\r
+#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /**< adds SXTB, SXTH, UXTB, UXTH */\r
+#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /**< N/A */\r
+/* SCB_ISAR1[IFTHEN_INSTRS] Bits */\r
+#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /**< IFTHEN_INSTRS Bit Offset */\r
+#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /**< IFTHEN_INSTRS Bit Mask */\r
+#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /**< IFTHEN_INSTRS Bit 0 */\r
+#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /**< IFTHEN_INSTRS Bit 1 */\r
+#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /**< IFTHEN_INSTRS Bit 2 */\r
+#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /**< IFTHEN_INSTRS Bit 3 */\r
+#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /**< IT instructions not present */\r
+#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /**< adds IT instructions (and IT bits in PSRs) */\r
+/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */\r
+#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /**< IMMEDIATE_INSTRS Bit Offset */\r
+#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /**< IMMEDIATE_INSTRS Bit Mask */\r
+#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /**< IMMEDIATE_INSTRS Bit 0 */\r
+#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /**< IMMEDIATE_INSTRS Bit 1 */\r
+#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /**< IMMEDIATE_INSTRS Bit 2 */\r
+#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /**< IMMEDIATE_INSTRS Bit 3 */\r
+#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /**< no special immediate-generating instructions present */\r
+#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /**< adds ADDW, MOVW, MOVT, SUBW */\r
+/* SCB_ISAR1[INTERWORK_INSTRS] Bits */\r
+#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /**< INTERWORK_INSTRS Bit Offset */\r
+#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /**< INTERWORK_INSTRS Bit Mask */\r
+#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /**< INTERWORK_INSTRS Bit 0 */\r
+#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /**< INTERWORK_INSTRS Bit 1 */\r
+#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /**< INTERWORK_INSTRS Bit 2 */\r
+#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /**< INTERWORK_INSTRS Bit 3 */\r
+#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /**< no interworking instructions supported */\r
+#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /**< adds BX (and T bit in PSRs) */\r
+#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /**< adds BLX, and PC loads have BX-like behavior */\r
+#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /**< N/A */\r
+/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */\r
+#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /**< LOADSTORE_INSTRS Bit Offset */\r
+#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /**< LOADSTORE_INSTRS Bit Mask */\r
+#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /**< LOADSTORE_INSTRS Bit 0 */\r
+#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /**< LOADSTORE_INSTRS Bit 1 */\r
+#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /**< LOADSTORE_INSTRS Bit 2 */\r
+#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /**< LOADSTORE_INSTRS Bit 3 */\r
+#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /**< no additional normal load/store instructions present */\r
+#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /**< adds LDRD/STRD */\r
+/* SCB_ISAR2[MEMHINT_INSTRS] Bits */\r
+#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /**< MEMHINT_INSTRS Bit Offset */\r
+#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /**< MEMHINT_INSTRS Bit Mask */\r
+#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /**< MEMHINT_INSTRS Bit 0 */\r
+#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /**< MEMHINT_INSTRS Bit 1 */\r
+#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /**< MEMHINT_INSTRS Bit 2 */\r
+#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /**< MEMHINT_INSTRS Bit 3 */\r
+#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /**< no memory hint instructions presen */\r
+#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /**< adds PLD */\r
+#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /**< adds PLD (ie a repeat on value 1) */\r
+#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /**< adds PLI */\r
+/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */\r
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /**< MULTIACCESSINT_INSTRS Bit Offset */\r
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /**< MULTIACCESSINT_INSTRS Bit Mask */\r
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /**< MULTIACCESSINT_INSTRS Bit 0 */\r
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /**< MULTIACCESSINT_INSTRS Bit 1 */\r
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /**< MULTIACCESSINT_INSTRS Bit 2 */\r
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /**< MULTIACCESSINT_INSTRS Bit 3 */\r
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /**< the (LDM/STM) instructions are non-interruptible */\r
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /**< the (LDM/STM) instructions are restartable */\r
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /**< the (LDM/STM) instructions are continuable */\r
+/* SCB_ISAR2[MULT_INSTRS] Bits */\r
+#define SCB_ISAR2_MULT_INSTRS_OFS (12) /**< MULT_INSTRS Bit Offset */\r
+#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /**< MULT_INSTRS Bit Mask */\r
+#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /**< MULT_INSTRS Bit 0 */\r
+#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /**< MULT_INSTRS Bit 1 */\r
+#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /**< MULT_INSTRS Bit 2 */\r
+#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /**< MULT_INSTRS Bit 3 */\r
+#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /**< only MUL present */\r
+#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /**< adds MLA */\r
+#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /**< adds MLS */\r
+/* SCB_ISAR2[MULTS_INSTRS] Bits */\r
+#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /**< MULTS_INSTRS Bit Offset */\r
+#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /**< MULTS_INSTRS Bit Mask */\r
+#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /**< MULTS_INSTRS Bit 0 */\r
+#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /**< MULTS_INSTRS Bit 1 */\r
+#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /**< MULTS_INSTRS Bit 2 */\r
+#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /**< MULTS_INSTRS Bit 3 */\r
+#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /**< no signed multiply instructions present */\r
+#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /**< adds SMULL, SMLAL */\r
+#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /**< N/A */\r
+#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /**< N/A */\r
+/* SCB_ISAR2[MULTU_INSTRS] Bits */\r
+#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /**< MULTU_INSTRS Bit Offset */\r
+#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /**< MULTU_INSTRS Bit Mask */\r
+#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /**< MULTU_INSTRS Bit 0 */\r
+#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /**< MULTU_INSTRS Bit 1 */\r
+#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /**< MULTU_INSTRS Bit 2 */\r
+#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /**< MULTU_INSTRS Bit 3 */\r
+#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /**< no unsigned multiply instructions present */\r
+#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /**< adds UMULL, UMLAL */\r
+#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /**< N/A */\r
+/* SCB_ISAR2[REVERSAL_INSTRS] Bits */\r
+#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /**< REVERSAL_INSTRS Bit Offset */\r
+#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /**< REVERSAL_INSTRS Bit Mask */\r
+#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /**< REVERSAL_INSTRS Bit 0 */\r
+#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /**< REVERSAL_INSTRS Bit 1 */\r
+#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /**< REVERSAL_INSTRS Bit 2 */\r
+#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /**< REVERSAL_INSTRS Bit 3 */\r
+#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /**< no reversal instructions present */\r
+#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /**< adds REV, REV16, REVSH */\r
+#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /**< adds RBIT */\r
+/* SCB_ISAR3[SATRUATE_INSTRS] Bits */\r
+#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /**< SATRUATE_INSTRS Bit Offset */\r
+#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /**< SATRUATE_INSTRS Bit Mask */\r
+#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /**< SATRUATE_INSTRS Bit 0 */\r
+#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /**< SATRUATE_INSTRS Bit 1 */\r
+#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /**< SATRUATE_INSTRS Bit 2 */\r
+#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /**< SATRUATE_INSTRS Bit 3 */\r
+#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /**< no non-SIMD saturate instructions present */\r
+#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /**< N/A */\r
+/* SCB_ISAR3[SIMD_INSTRS] Bits */\r
+#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /**< SIMD_INSTRS Bit Offset */\r
+#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /**< SIMD_INSTRS Bit Mask */\r
+#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /**< SIMD_INSTRS Bit 0 */\r
+#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /**< SIMD_INSTRS Bit 1 */\r
+#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /**< SIMD_INSTRS Bit 2 */\r
+#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /**< SIMD_INSTRS Bit 3 */\r
+#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /**< no SIMD instructions present */\r
+#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /**< adds SSAT, USAT (and the Q flag in the PSRs) */\r
+#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /**< N/A */\r
+/* SCB_ISAR3[SVC_INSTRS] Bits */\r
+#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /**< SVC_INSTRS Bit Offset */\r
+#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /**< SVC_INSTRS Bit Mask */\r
+#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /**< SVC_INSTRS Bit 0 */\r
+#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /**< SVC_INSTRS Bit 1 */\r
+#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /**< SVC_INSTRS Bit 2 */\r
+#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /**< SVC_INSTRS Bit 3 */\r
+#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /**< no SVC (SWI) instructions present */\r
+#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /**< adds SVC (SWI) */\r
+/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */\r
+#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /**< SYNCPRIM_INSTRS Bit Offset */\r
+#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /**< SYNCPRIM_INSTRS Bit Mask */\r
+#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /**< SYNCPRIM_INSTRS Bit 0 */\r
+#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /**< SYNCPRIM_INSTRS Bit 1 */\r
+#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /**< SYNCPRIM_INSTRS Bit 2 */\r
+#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /**< SYNCPRIM_INSTRS Bit 3 */\r
+#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /**< no synchronization primitives present */\r
+#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /**< adds LDREX, STREX */\r
+#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /**< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */\r
+/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */\r
+#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /**< TABBRANCH_INSTRS Bit Offset */\r
+#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /**< TABBRANCH_INSTRS Bit Mask */\r
+#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /**< TABBRANCH_INSTRS Bit 0 */\r
+#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /**< TABBRANCH_INSTRS Bit 1 */\r
+#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /**< TABBRANCH_INSTRS Bit 2 */\r
+#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /**< TABBRANCH_INSTRS Bit 3 */\r
+#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /**< no table-branch instructions present */\r
+#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /**< adds TBB, TBH */\r
+/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */\r
+#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /**< THUMBCOPY_INSTRS Bit Offset */\r
+#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /**< THUMBCOPY_INSTRS Bit Mask */\r
+#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /**< THUMBCOPY_INSTRS Bit 0 */\r
+#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /**< THUMBCOPY_INSTRS Bit 1 */\r
+#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /**< THUMBCOPY_INSTRS Bit 2 */\r
+#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /**< THUMBCOPY_INSTRS Bit 3 */\r
+#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /**< Thumb MOV(register) instruction does not allow low reg -> low reg */\r
+#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /**< adds Thumb MOV(register) low reg -> low reg and the CPY alias */\r
+/* SCB_ISAR3[TRUENOP_INSTRS] Bits */\r
+#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /**< TRUENOP_INSTRS Bit Offset */\r
+#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /**< TRUENOP_INSTRS Bit Mask */\r
+#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /**< TRUENOP_INSTRS Bit 0 */\r
+#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /**< TRUENOP_INSTRS Bit 1 */\r
+#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /**< TRUENOP_INSTRS Bit 2 */\r
+#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /**< TRUENOP_INSTRS Bit 3 */\r
+#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /**< true NOP instructions not present - that is, NOP instructions with no register */\r
+ /* dependencies */\r
+#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /**< adds "true NOP", and the capability of additional "NOP compatible hints" */\r
+/* SCB_ISAR4[UNPRIV_INSTRS] Bits */\r
+#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /**< UNPRIV_INSTRS Bit Offset */\r
+#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /**< UNPRIV_INSTRS Bit Mask */\r
+#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /**< UNPRIV_INSTRS Bit 0 */\r
+#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /**< UNPRIV_INSTRS Bit 1 */\r
+#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /**< UNPRIV_INSTRS Bit 2 */\r
+#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /**< UNPRIV_INSTRS Bit 3 */\r
+#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /**< no "T variant" instructions exist */\r
+#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /**< adds LDRBT, LDRT, STRBT, STRT */\r
+#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /**< adds LDRHT, LDRSBT, LDRSHT, STRHT */\r
+/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /**< WITHSHIFTS_INSTRS Bit Offset */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /**< WITHSHIFTS_INSTRS Bit Mask */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /**< WITHSHIFTS_INSTRS Bit 0 */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /**< WITHSHIFTS_INSTRS Bit 1 */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /**< WITHSHIFTS_INSTRS Bit 2 */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /**< WITHSHIFTS_INSTRS Bit 3 */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /**< non-zero shifts only support MOV and shift instructions (see notes) */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /**< shifts of loads/stores over the range LSL 0-3 */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /**< adds other constant shift options. */\r
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /**< adds register-controlled shift options. */\r
+/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */\r
+#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /**< WRITEBACK_INSTRS Bit Offset */\r
+#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /**< WRITEBACK_INSTRS Bit Mask */\r
+#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /**< WRITEBACK_INSTRS Bit 0 */\r
+#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /**< WRITEBACK_INSTRS Bit 1 */\r
+#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /**< WRITEBACK_INSTRS Bit 2 */\r
+#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /**< WRITEBACK_INSTRS Bit 3 */\r
+#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /**< only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP */\r
+ /* instructions support writeback addressing. */\r
+#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /**< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */\r
+/* SCB_ISAR4[BARRIER_INSTRS] Bits */\r
+#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /**< BARRIER_INSTRS Bit Offset */\r
+#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /**< BARRIER_INSTRS Bit Mask */\r
+#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /**< BARRIER_INSTRS Bit 0 */\r
+#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /**< BARRIER_INSTRS Bit 1 */\r
+#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /**< BARRIER_INSTRS Bit 2 */\r
+#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /**< BARRIER_INSTRS Bit 3 */\r
+#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /**< no barrier instructions supported */\r
+#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /**< adds DMB, DSB, ISB barrier instructions */\r
+/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */\r
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /**< SYNCPRIM_INSTRS_FRAC Bit Offset */\r
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /**< SYNCPRIM_INSTRS_FRAC Bit Mask */\r
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /**< SYNCPRIM_INSTRS_FRAC Bit 0 */\r
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /**< SYNCPRIM_INSTRS_FRAC Bit 1 */\r
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /**< SYNCPRIM_INSTRS_FRAC Bit 2 */\r
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /**< SYNCPRIM_INSTRS_FRAC Bit 3 */\r
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /**< no additional support */\r
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /**< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */\r
+/* SCB_ISAR4[PSR_M_INSTRS] Bits */\r
+#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /**< PSR_M_INSTRS Bit Offset */\r
+#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /**< PSR_M_INSTRS Bit Mask */\r
+#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /**< PSR_M_INSTRS Bit 0 */\r
+#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /**< PSR_M_INSTRS Bit 1 */\r
+#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /**< PSR_M_INSTRS Bit 2 */\r
+#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /**< PSR_M_INSTRS Bit 3 */\r
+#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /**< instructions not present */\r
+#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /**< adds CPS, MRS, and MSR instructions (M-profile forms) */\r
+/* SCB_CPACR[CP11] Bits */\r
+#define SCB_CPACR_CP11_OFS (22) /**< CP11 Bit Offset */\r
+#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /**< CP11 Bit Mask */\r
+/* SCB_CPACR[CP10] Bits */\r
+#define SCB_CPACR_CP10_OFS (20) /**< CP10 Bit Offset */\r
+#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /**< CP10 Bit Mask */\r
+\r
+\r
+/******************************************************************************\r
+* SCnSCB Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* SYSCTL Bits\r
+******************************************************************************/\r
+/* SYSCTL_REBOOT_CTL[REBOOT] Bits */\r
+#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /**< REBOOT Bit Offset */\r
+#define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /**< Write 1 initiates a Reboot of the device */\r
+/* SYSCTL_REBOOT_CTL[WKEY] Bits */\r
+#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /**< WKEY Bit Offset */\r
+#define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */\r
+/* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */\r
+#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /**< CS_SRC Bit Offset */\r
+#define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /**< CS interrupt as a source of NMI */\r
+/* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */\r
+#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /**< PSS_SRC Bit Offset */\r
+#define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /**< PSS interrupt as a source of NMI */\r
+/* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */\r
+#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /**< PCM_SRC Bit Offset */\r
+#define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /**< PCM interrupt as a source of NMI */\r
+/* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */\r
+#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /**< PIN_SRC Bit Offset */\r
+#define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008)\r
+/* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */\r
+#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /**< CS_FLG Bit Offset */\r
+#define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /**< CS interrupt was the source of NMI */\r
+/* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */\r
+#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /**< PSS_FLG Bit Offset */\r
+#define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /**< PSS interrupt was the source of NMI */\r
+/* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */\r
+#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /**< PCM_FLG Bit Offset */\r
+#define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /**< PCM interrupt was the source of NMI */\r
+/* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */\r
+#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /**< PIN_FLG Bit Offset */\r
+#define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /**< RSTn/NMI pin was the source of NMI */\r
+/* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */\r
+#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /**< TIMEOUT Bit Offset */\r
+#define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /**< WDT timeout reset type */\r
+/* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */\r
+#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /**< VIOLATION Bit Offset */\r
+#define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /**< WDT password violation reset type */\r
+/* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /**< HALT_T16_0 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /**< HALT_T16_1 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /**< HALT_T16_2 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /**< HALT_T16_3 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /**< HALT_T32_0 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_EUA0] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /**< HALT_eUA0 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_EUA1] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /**< HALT_eUA1 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_EUA2] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /**< HALT_eUA2 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_EUA3] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /**< HALT_eUA3 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_EUB0] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /**< HALT_eUB0 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_EUB1] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /**< HALT_eUB1 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_EUB2] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /**< HALT_eUB2 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_EUB3] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /**< HALT_eUB3 Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /**< HALT_ADC Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /**< HALT_WDT Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */\r
+#define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /**< HALT_DMA Bit Offset */\r
+#define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /**< Freezes IP operation when CPU is halted */\r
+/* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */\r
+#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /**< BNK0_EN Bit Offset */\r
+#define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /**< SRAM Bank0 enable */\r
+/* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */\r
+#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /**< BNK1_EN Bit Offset */\r
+#define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /**< SRAM Bank1 enable */\r
+/* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */\r
+#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /**< BNK2_EN Bit Offset */\r
+#define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /**< SRAM Bank1 enable */\r
+/* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */\r
+#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /**< BNK3_EN Bit Offset */\r
+#define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /**< SRAM Bank1 enable */\r
+/* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */\r
+#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /**< BNK4_EN Bit Offset */\r
+#define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /**< SRAM Bank1 enable */\r
+/* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */\r
+#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /**< BNK5_EN Bit Offset */\r
+#define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /**< SRAM Bank1 enable */\r
+/* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */\r
+#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /**< BNK6_EN Bit Offset */\r
+#define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /**< SRAM Bank1 enable */\r
+/* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */\r
+#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /**< BNK7_EN Bit Offset */\r
+#define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /**< SRAM Bank1 enable */\r
+/* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */\r
+#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /**< SRAM_RDY Bit Offset */\r
+#define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /**< SRAM ready */\r
+/* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */\r
+#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /**< BNK0_RET Bit Offset */\r
+#define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /**< Bank0 retention */\r
+/* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */\r
+#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /**< BNK1_RET Bit Offset */\r
+#define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /**< Bank1 retention */\r
+/* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */\r
+#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /**< BNK2_RET Bit Offset */\r
+#define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /**< Bank2 retention */\r
+/* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */\r
+#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /**< BNK3_RET Bit Offset */\r
+#define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /**< Bank3 retention */\r
+/* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */\r
+#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /**< BNK4_RET Bit Offset */\r
+#define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /**< Bank4 retention */\r
+/* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */\r
+#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /**< BNK5_RET Bit Offset */\r
+#define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /**< Bank5 retention */\r
+/* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */\r
+#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /**< BNK6_RET Bit Offset */\r
+#define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /**< Bank6 retention */\r
+/* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */\r
+#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /**< BNK7_RET Bit Offset */\r
+#define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /**< Bank7 retention */\r
+/* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */\r
+#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /**< SRAM_RDY Bit Offset */\r
+#define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /**< SRAM ready */\r
+/* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */\r
+#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /**< GLTCH_EN Bit Offset */\r
+#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /**< Glitch filter enable */\r
+/* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */\r
+#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /**< UNLKEY Bit Offset */\r
+#define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /**< UNLKEY Bit Mask */\r
+/* SYSCTL_CSYS_MASTER_UNLOCK[UNLKEY] Bits */\r
+#define SYSCTL_CSYS_MASTER_UNLOCK_UNLKEY_OFS ( 0) /**< UNLKEY Bit Offset */\r
+#define SYSCTL_CSYS_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /**< UNLKEY Bit Mask */\r
+/* SYSCTL_BOOT_CTL[BOOT_SECEN] Bits */\r
+#define SYSCTL_BOOT_CTL_BOOT_SECEN_OFS ( 0) /**< BOOT_SECEN Bit Offset */\r
+#define SYSCTL_BOOT_CTL_BOOT_SECEN ((uint32_t)0x00000001)\r
+/* SYSCTL_BOOT_CTL[BOOTACT] Bits */\r
+#define SYSCTL_BOOT_CTL_BOOTACT_OFS ( 1) /**< BOOTACT Bit Offset */\r
+#define SYSCTL_BOOT_CTL_BOOTACT ((uint32_t)0x00000002)\r
+/* SYSCTL_BOOT_CTL[BOOTCMPL] Bits */\r
+#define SYSCTL_BOOT_CTL_BOOTCMPL_OFS ( 2) /**< BOOTCMPL Bit Offset */\r
+#define SYSCTL_BOOT_CTL_BOOTCMPL ((uint32_t)0x00000004)\r
+/* SYSCTL_BOOT_CTL[BOOT_REMAPEN] Bits */\r
+#define SYSCTL_BOOT_CTL_BOOT_REMAPEN_OFS ( 3) /**< BOOT_REMAPEN Bit Offset */\r
+#define SYSCTL_BOOT_CTL_BOOT_REMAPEN ((uint32_t)0x00000008)\r
+/* SYSCTL_BOOT_CTL[ENGR_DIS] Bits */\r
+#define SYSCTL_BOOT_CTL_ENGR_DIS_OFS ( 4) /**< ENGR_DIS Bit Offset */\r
+#define SYSCTL_BOOT_CTL_ENGR_DIS ((uint32_t)0x00000010)\r
+/* SYSCTL_BOOT_CTL[WKEY] Bits */\r
+#define SYSCTL_BOOT_CTL_WKEY_OFS ( 8) /**< WKEY Bit Offset */\r
+#define SYSCTL_BOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */\r
+/* SYSCTL_SEC_CTL[JTAG_SWD_LOCK_EN] Bits */\r
+#define SYSCTL_SEC_CTL_JTAG_SWD_LOCK_EN_OFS ( 0) /**< JTAG_SWD_LOCK_EN Bit Offset */\r
+#define SYSCTL_SEC_CTL_JTAG_SWD_LOCK_EN ((uint32_t)0x00000001)\r
+/* SYSCTL_SEC_CTL[IP_PROT_EN] Bits */\r
+#define SYSCTL_SEC_CTL_IP_PROT_EN_OFS ( 1) /**< IP_PROT_EN Bit Offset */\r
+#define SYSCTL_SEC_CTL_IP_PROT_EN ((uint32_t)0x00000002)\r
+/* SYSCTL_SEC_CTL[DLOCK_EN] Bits */\r
+#define SYSCTL_SEC_CTL_DLOCK_EN_OFS ( 2) /**< DLOCK_EN Bit Offset */\r
+#define SYSCTL_SEC_CTL_DLOCK_EN ((uint32_t)0x00000004)\r
+/* SYSCTL_SEC_CTL[SBUS_IF_DIS] Bits */\r
+#define SYSCTL_SEC_CTL_SBUS_IF_DIS_OFS ( 3) /**< SBUS_IF_DIS Bit Offset */\r
+#define SYSCTL_SEC_CTL_SBUS_IF_DIS ((uint32_t)0x00000008)\r
+/* SYSCTL_SEC_CTL[SEC_ZONE0_EN] Bits */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE0_EN_OFS ( 8) /**< SEC_ZONE0_EN Bit Offset */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE0_EN ((uint32_t)0x00000100)\r
+/* SYSCTL_SEC_CTL[SEC_ZONE1_EN] Bits */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE1_EN_OFS ( 9) /**< SEC_ZONE1_EN Bit Offset */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE1_EN ((uint32_t)0x00000200)\r
+/* SYSCTL_SEC_CTL[SEC_ZONE2_EN] Bits */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE2_EN_OFS (10) /**< SEC_ZONE2_EN Bit Offset */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE2_EN ((uint32_t)0x00000400)\r
+/* SYSCTL_SEC_CTL[SEC_ZONE3_EN] Bits */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE3_EN_OFS (11) /**< SEC_ZONE3_EN Bit Offset */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE3_EN ((uint32_t)0x00000800)\r
+/* SYSCTL_SEC_CTL[SEC_ZONE0_DATAEN] Bits */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE0_DATAEN_OFS (16) /**< SEC_ZONE0_DATAEN Bit Offset */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE0_DATAEN ((uint32_t)0x00010000)\r
+/* SYSCTL_SEC_CTL[SEC_ZONE1_DATAEN] Bits */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE1_DATAEN_OFS (17) /**< SEC_ZONE1_DATAEN Bit Offset */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE1_DATAEN ((uint32_t)0x00020000)\r
+/* SYSCTL_SEC_CTL[SEC_ZONE2_DATAEN] Bits */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE2_DATAEN_OFS (18) /**< SEC_ZONE2_DATAEN Bit Offset */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE2_DATAEN ((uint32_t)0x00040000)\r
+/* SYSCTL_SEC_CTL[SEC_ZONE3_DATAEN] Bits */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE3_DATAEN_OFS (19) /**< SEC_ZONE3_DATAEN Bit Offset */\r
+#define SYSCTL_SEC_CTL_SEC_ZONE3_DATAEN ((uint32_t)0x00080000)\r
+/* SYSCTL_SEC_STARTADDR0[START_ADDR] Bits */\r
+#define SYSCTL_SEC_STARTADDR0_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */\r
+#define SYSCTL_SEC_STARTADDR0_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */\r
+/* SYSCTL_SEC_STARTADDR1[START_ADDR] Bits */\r
+#define SYSCTL_SEC_STARTADDR1_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */\r
+#define SYSCTL_SEC_STARTADDR1_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */\r
+/* SYSCTL_SEC_STARTADDR2[START_ADDR] Bits */\r
+#define SYSCTL_SEC_STARTADDR2_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */\r
+#define SYSCTL_SEC_STARTADDR2_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */\r
+/* SYSCTL_SEC_STARTADDR3[START_ADDR] Bits */\r
+#define SYSCTL_SEC_STARTADDR3_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */\r
+#define SYSCTL_SEC_STARTADDR3_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */\r
+/* SYSCTL_SEC_SIZE0[SIZE] Bits */\r
+#define SYSCTL_SEC_SIZE0_SIZE_OFS ( 0) /**< SIZE Bit Offset */\r
+#define SYSCTL_SEC_SIZE0_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */\r
+/* SYSCTL_SEC_SIZE1[SIZE] Bits */\r
+#define SYSCTL_SEC_SIZE1_SIZE_OFS ( 0) /**< SIZE Bit Offset */\r
+#define SYSCTL_SEC_SIZE1_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */\r
+/* SYSCTL_SEC_SIZE2[SIZE] Bits */\r
+#define SYSCTL_SEC_SIZE2_SIZE_OFS ( 0) /**< SIZE Bit Offset */\r
+#define SYSCTL_SEC_SIZE2_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */\r
+/* SYSCTL_SEC_SIZE3[SIZE] Bits */\r
+#define SYSCTL_SEC_SIZE3_SIZE_OFS ( 0) /**< SIZE Bit Offset */\r
+#define SYSCTL_SEC_SIZE3_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */\r
+/* SYSCTL_ETW_CTL[ETSEL] Bits */\r
+#define SYSCTL_ETW_CTL_ETSEL_OFS ( 0) /**< ETSEL Bit Offset */\r
+#define SYSCTL_ETW_CTL_ETSEL ((uint32_t)0x00000001)\r
+/* SYSCTL_ETW_CTL[DBGEN] Bits */\r
+#define SYSCTL_ETW_CTL_DBGEN_OFS ( 1) /**< DBGEN Bit Offset */\r
+#define SYSCTL_ETW_CTL_DBGEN ((uint32_t)0x00000002)\r
+/* SYSCTL_ETW_CTL[WKEY] Bits */\r
+#define SYSCTL_ETW_CTL_WKEY_OFS ( 8) /**< WKEY Bit Offset */\r
+#define SYSCTL_ETW_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */\r
+/* SYSCTL_FLASH_SIZECFG[SIZE] Bits */\r
+#define SYSCTL_FLASH_SIZECFG_SIZE_OFS ( 0) /**< SIZE Bit Offset */\r
+#define SYSCTL_FLASH_SIZECFG_SIZE_MASK ((uint32_t)0x0007FFFF) /**< SIZE Bit Mask */\r
+/* SYSCTL_SRAM_SIZECFG[SIZE] Bits */\r
+#define SYSCTL_SRAM_SIZECFG_SIZE_OFS ( 0) /**< SIZE Bit Offset */\r
+#define SYSCTL_SRAM_SIZECFG_SIZE_MASK ((uint32_t)0x0001FFFF) /**< SIZE Bit Mask */\r
+/* SYSCTL_SRAM_NUMBANK[NUM_BANK] Bits */\r
+#define SYSCTL_SRAM_NUMBANK_NUM_BANK_OFS ( 0) /**< NUM_BANK Bit Offset */\r
+#define SYSCTL_SRAM_NUMBANK_NUM_BANK_MASK ((uint32_t)0x0000001F) /**< NUM_BANK Bit Mask */\r
+/* SYSCTL_TIMER_CFG[T0_EN] Bits */\r
+#define SYSCTL_TIMER_CFG_T0_EN_OFS ( 0) /**< T0_EN Bit Offset */\r
+#define SYSCTL_TIMER_CFG_T0_EN ((uint32_t)0x00000001) /**< Enable bit for Timer0 */\r
+/* SYSCTL_TIMER_CFG[T1_EN] Bits */\r
+#define SYSCTL_TIMER_CFG_T1_EN_OFS ( 1) /**< T1_EN Bit Offset */\r
+#define SYSCTL_TIMER_CFG_T1_EN ((uint32_t)0x00000002) /**< Enable bit for Timer1 */\r
+/* SYSCTL_TIMER_CFG[T2_EN] Bits */\r
+#define SYSCTL_TIMER_CFG_T2_EN_OFS ( 2) /**< T2_EN Bit Offset */\r
+#define SYSCTL_TIMER_CFG_T2_EN ((uint32_t)0x00000004) /**< Enable bit for Timer2 */\r
+/* SYSCTL_TIMER_CFG[T3_EN] Bits */\r
+#define SYSCTL_TIMER_CFG_T3_EN_OFS ( 3) /**< T3_EN Bit Offset */\r
+#define SYSCTL_TIMER_CFG_T3_EN ((uint32_t)0x00000008) /**< Enable bit for Timer3 */\r
+/* SYSCTL_TIMER_CFG[T32_EN] Bits */\r
+#define SYSCTL_TIMER_CFG_T32_EN_OFS (16) /**< T32_EN Bit Offset */\r
+#define SYSCTL_TIMER_CFG_T32_EN ((uint32_t)0x00010000) /**< Enable bit for Timer32 */\r
+/* SYSCTL_EUSCI_CFG[EUA0_EN] Bits */\r
+#define SYSCTL_EUSCI_CFG_EUA0_EN_OFS ( 0) /**< eUA0_EN Bit Offset */\r
+#define SYSCTL_EUSCI_CFG_EUA0_EN ((uint32_t)0x00000001) /**< Enable bit for eUSCI_A0 */\r
+/* SYSCTL_EUSCI_CFG[EUA1_EN] Bits */\r
+#define SYSCTL_EUSCI_CFG_EUA1_EN_OFS ( 1) /**< eUA1_EN Bit Offset */\r
+#define SYSCTL_EUSCI_CFG_EUA1_EN ((uint32_t)0x00000002) /**< Enable bit for eUSCI_A1 */\r
+/* SYSCTL_EUSCI_CFG[EUA2_EN] Bits */\r
+#define SYSCTL_EUSCI_CFG_EUA2_EN_OFS ( 2) /**< eUA2_EN Bit Offset */\r
+#define SYSCTL_EUSCI_CFG_EUA2_EN ((uint32_t)0x00000004) /**< Enable bit for eUSCI_A2 */\r
+/* SYSCTL_EUSCI_CFG[EUA3_EN] Bits */\r
+#define SYSCTL_EUSCI_CFG_EUA3_EN_OFS ( 3) /**< eUA3_EN Bit Offset */\r
+#define SYSCTL_EUSCI_CFG_EUA3_EN ((uint32_t)0x00000008) /**< Enable bit for eUSCI_A3 */\r
+/* SYSCTL_EUSCI_CFG[EUB0_EN] Bits */\r
+#define SYSCTL_EUSCI_CFG_EUB0_EN_OFS (16) /**< eUB0_EN Bit Offset */\r
+#define SYSCTL_EUSCI_CFG_EUB0_EN ((uint32_t)0x00010000) /**< Enable bit for eUSCI_B0 */\r
+/* SYSCTL_EUSCI_CFG[EUB1_EN] Bits */\r
+#define SYSCTL_EUSCI_CFG_EUB1_EN_OFS (17) /**< eUB1_EN Bit Offset */\r
+#define SYSCTL_EUSCI_CFG_EUB1_EN ((uint32_t)0x00020000) /**< Enable bit for eUSCI_B1 */\r
+/* SYSCTL_EUSCI_CFG[EUB2_EN] Bits */\r
+#define SYSCTL_EUSCI_CFG_EUB2_EN_OFS (18) /**< eUB2_EN Bit Offset */\r
+#define SYSCTL_EUSCI_CFG_EUB2_EN ((uint32_t)0x00040000) /**< Enable bit for eUSCI_B2 */\r
+/* SYSCTL_EUSCI_CFG[EUB3_EN] Bits */\r
+#define SYSCTL_EUSCI_CFG_EUB3_EN_OFS (19) /**< eUB3_EN Bit Offset */\r
+#define SYSCTL_EUSCI_CFG_EUB3_EN ((uint32_t)0x00080000) /**< Enable bit for eUSCI_B3 */\r
+/* SYSCTL_ADC_CFG[ADC_EN] Bits */\r
+#define SYSCTL_ADC_CFG_ADC_EN_OFS ( 0) /**< ADC_EN Bit Offset */\r
+#define SYSCTL_ADC_CFG_ADC_EN ((uint32_t)0x00000001) /**< Enable bit for ADC */\r
+/* SYSCTL_XTAL_CFG[LFXT_EN] Bits */\r
+#define SYSCTL_XTAL_CFG_LFXT_EN_OFS ( 0) /**< LFXT_EN Bit Offset */\r
+#define SYSCTL_XTAL_CFG_LFXT_EN ((uint32_t)0x00000001) /**< Enable bit for LFXT */\r
+/* SYSCTL_XTAL_CFG[HFXT_EN] Bits */\r
+#define SYSCTL_XTAL_CFG_HFXT_EN_OFS ( 1) /**< HFXT_EN Bit Offset */\r
+#define SYSCTL_XTAL_CFG_HFXT_EN ((uint32_t)0x00000002) /**< Enable bit for HFXT */\r
+/* SYSCTL_XTAL_CFG[HFXT2_EN] Bits */\r
+#define SYSCTL_XTAL_CFG_HFXT2_EN_OFS ( 2) /**< HFXT2_EN Bit Offset */\r
+#define SYSCTL_XTAL_CFG_HFXT2_EN ((uint32_t)0x00000004) /**< Enable bit for HFXT2 */\r
+/* SYSCTL_BOC_CFG[BOC_CTL] Bits */\r
+#define SYSCTL_BOC_CFG_BOC_CTL_OFS ( 0) /**< BOC_CTL Bit Offset */\r
+#define SYSCTL_BOC_CFG_BOC_CTL_MASK ((uint32_t)0x00000007) /**< BOC_CTL Bit Mask */\r
+#define SYSCTL_BOC_CFG_BOC_CTL0 ((uint32_t)0x00000001) /**< BOC_CTL Bit 0 */\r
+#define SYSCTL_BOC_CFG_BOC_CTL1 ((uint32_t)0x00000002) /**< BOC_CTL Bit 1 */\r
+#define SYSCTL_BOC_CFG_BOC_CTL2 ((uint32_t)0x00000004) /**< BOC_CTL Bit 2 */\r
+#define SYSCTL_BOC_CFG_BOC_CTL_0 ((uint32_t)0x00000000) /**< 100pin package */\r
+#define SYSCTL_BOC_CFG_BOC_CTL_1 ((uint32_t)0x00000001) /**< 80pin package */\r
+#define SYSCTL_BOC_CFG_BOC_CTL_2 ((uint32_t)0x00000002) /**< 64pin package */\r
+#define SYSCTL_BOC_CFG_BOC_CTL_3 ((uint32_t)0x00000003) /**< 64pin package */\r
+#define SYSCTL_BOC_CFG_BOC_CTL__PIN_100 ((uint32_t)0x00000000) /**< 100pin package */\r
+#define SYSCTL_BOC_CFG_BOC_CTL__PIN_80 ((uint32_t)0x00000001) /**< 80pin package */\r
+#define SYSCTL_BOC_CFG_BOC_CTL__PIN_64 ((uint32_t)0x00000002) /**< 64pin package */\r
+\r
+#define SYSCTL_BOC_CFG_BOC_CTL_4 ((uint32_t)0x00000004) /**< Reserved for future use */\r
+#define SYSCTL_BOC_CFG_BOC_CTL_5 ((uint32_t)0x00000005) /**< Reserved for future use */\r
+#define SYSCTL_BOC_CFG_BOC_CTL_6 ((uint32_t)0x00000006) /**< Reserved for future use */\r
+#define SYSCTL_BOC_CFG_BOC_CTL_7 ((uint32_t)0x00000007) /**< Reserved for future use */\r
+/* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */\r
+#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /**< UNLKEY Bit Offset */\r
+#define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /**< UNLKEY Bit Mask */\r
+/* SYSCTL_RESET_REQ[POR] Bits */\r
+#define SYSCTL_RESET_REQ_POR_OFS ( 0) /**< POR Bit Offset */\r
+#define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /**< Generate POR */\r
+/* SYSCTL_RESET_REQ[REBOOT] Bits */\r
+#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /**< REBOOT Bit Offset */\r
+#define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /**< Generate Reboot_Reset */\r
+/* SYSCTL_RESET_REQ[WKEY] Bits */\r
+#define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /**< WKEY Bit Offset */\r
+#define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */\r
+/* SYSCTL_RESET_STATOVER[SOFT] Bits */\r
+#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /**< SOFT Bit Offset */\r
+#define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /**< Indicates if SOFT Reset is active */\r
+/* SYSCTL_RESET_STATOVER[HARD] Bits */\r
+#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /**< HARD Bit Offset */\r
+#define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /**< Indicates if HARD Reset is active */\r
+/* SYSCTL_RESET_STATOVER[REBOOT] Bits */\r
+#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /**< REBOOT Bit Offset */\r
+#define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /**< Indicates if Reboot Reset is active */\r
+/* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */\r
+#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /**< SOFT_OVER Bit Offset */\r
+#define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /**< SOFT_Reset overwrite request */\r
+/* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */\r
+#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /**< HARD_OVER Bit Offset */\r
+#define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /**< HARD_Reset overwrite request */\r
+/* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */\r
+#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /**< RBT_OVER Bit Offset */\r
+#define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /**< Reboot Reset overwrite request */\r
+/* SYSCTL_SYSTEM_STAT[DBG_SEC_ACT] Bits */\r
+#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /**< DBG_SEC_ACT Bit Offset */\r
+#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT ((uint32_t)0x00000008) /**< Debug Security active */\r
+/* SYSCTL_SYSTEM_STAT[JTAG_SWD_LOCK_ACT] Bits */\r
+#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /**< JTAG_SWD_LOCK_ACT Bit Offset */\r
+#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT ((uint32_t)0x00000010) /**< Indicates if JTAG and SWD Lock is active */\r
+/* SYSCTL_SYSTEM_STAT[IP_PROT_ACT] Bits */\r
+#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /**< IP_PROT_ACT Bit Offset */\r
+#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT ((uint32_t)0x00000020) /**< Indicates if IP protection is active */\r
\r
/* Pre-defined bitfield values */\r
-#define SYSCTL_REBOOT_CTL_WKEY_VAL (0x00006900) /* Key value to enable writes to bit 0 */\r
+#define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /* Key value to enable writes to bit 0 */\r
/* cleared */\r
\r
-//*****************************************************************************\r
-// SYSTICK Bits\r
-//*****************************************************************************\r
-/* SYSTICK_STCSR[SYSTICK_STCSR_ENABLE] Bits */\r
-#define SYSTICK_STCSR_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define SYSTICK_STCSR_ENABLE (0x00000001) /* */\r
-/* SYSTICK_STCSR[SYSTICK_STCSR_TICKINT] Bits */\r
-#define SYSTICK_STCSR_TICKINT_OFS ( 1) /* TICKINT Offset */\r
-#define SYSTICK_STCSR_TICKINT (0x00000002) /* */\r
-/* SYSTICK_STCSR[SYSTICK_STCSR_CLKSOURCE] Bits */\r
-#define SYSTICK_STCSR_CLKSOURCE_OFS ( 2) /* CLKSOURCE Offset */\r
-#define SYSTICK_STCSR_CLKSOURCE (0x00000004) /* */\r
-/* SYSTICK_STCSR[SYSTICK_STCSR_COUNTFLAG] Bits */\r
-#define SYSTICK_STCSR_COUNTFLAG_OFS (16) /* COUNTFLAG Offset */\r
-#define SYSTICK_STCSR_COUNTFLAG (0x00010000) /* */\r
-/* SYSTICK_STRVR[SYSTICK_STRVR_RELOAD] Bits */\r
-#define SYSTICK_STRVR_RELOAD_OFS ( 0) /* RELOAD Offset */\r
-#define SYSTICK_STRVR_RELOAD_M (0x00ffffff) /* */\r
-/* SYSTICK_STCVR[SYSTICK_STCVR_CURRENT] Bits */\r
-#define SYSTICK_STCVR_CURRENT_OFS ( 0) /* CURRENT Offset */\r
-#define SYSTICK_STCVR_CURRENT_M (0x00ffffff) /* */\r
-/* SYSTICK_STCR[SYSTICK_STCR_TENMS] Bits */\r
-#define SYSTICK_STCR_TENMS_OFS ( 0) /* TENMS Offset */\r
-#define SYSTICK_STCR_TENMS_M (0x00ffffff) /* */\r
-/* SYSTICK_STCR[SYSTICK_STCR_SKEW] Bits */\r
-#define SYSTICK_STCR_SKEW_OFS (30) /* SKEW Offset */\r
-#define SYSTICK_STCR_SKEW (0x40000000) /* */\r
-/* SYSTICK_STCR[SYSTICK_STCR_NOREF] Bits */\r
-#define SYSTICK_STCR_NOREF_OFS (31) /* NOREF Offset */\r
-#define SYSTICK_STCR_NOREF (0x80000000) /* */\r
-\r
\r
-//*****************************************************************************\r
-// TIMER32 Bits\r
-//*****************************************************************************\r
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_ONESHOT] Bits */\r
-#define TIMER32_CONTROL1_ONESHOT_OFS ( 0) /* ONESHOT Offset */\r
-#define TIMER32_CONTROL1_ONESHOT (0x00000001) /* Selects one-shot or wrapping counter mode */\r
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_SIZE] Bits */\r
-#define TIMER32_CONTROL1_SIZE_OFS ( 1) /* SIZE Offset */\r
-#define TIMER32_CONTROL1_SIZE (0x00000002) /* Selects 16 or 32 bit counter operation */\r
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_PRESCALE] Bits */\r
-#define TIMER32_CONTROL1_PRESCALE_OFS ( 2) /* PRESCALE Offset */\r
-#define TIMER32_CONTROL1_PRESCALE_M (0x0000000c) /* Prescale bits */\r
-#define TIMER32_CONTROL1_PRESCALE0 (0x00000004) /* Prescale bits */\r
-#define TIMER32_CONTROL1_PRESCALE1 (0x00000008) /* Prescale bits */\r
-#define TIMER32_CONTROL1_PRESCALE_0 (0x00000000) /* 0 stages of prescale, clock is divided by 1 */\r
-#define TIMER32_CONTROL1_PRESCALE_1 (0x00000004) /* 4 stages of prescale, clock is divided by 16 */\r
-#define TIMER32_CONTROL1_PRESCALE_2 (0x00000008) /* 8 stages of prescale, clock is divided by 256 */\r
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_IE] Bits */\r
-#define TIMER32_CONTROL1_IE_OFS ( 5) /* IE Offset */\r
-#define TIMER32_CONTROL1_IE (0x00000020) /* Interrupt enable bit */\r
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_MODE] Bits */\r
-#define TIMER32_CONTROL1_MODE_OFS ( 6) /* MODE Offset */\r
-#define TIMER32_CONTROL1_MODE (0x00000040) /* Mode bit */\r
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_ENABLE] Bits */\r
-#define TIMER32_CONTROL1_ENABLE_OFS ( 7) /* ENABLE Offset */\r
-#define TIMER32_CONTROL1_ENABLE (0x00000080) /* */\r
-/* TIMER32_RIS1[TIMER32_RIS1_RAW_IFG] Bits */\r
-#define TIMER32_RIS1_RAW_IFG_OFS ( 0) /* RAW_IFG Offset */\r
-#define TIMER32_RIS1_RAW_IFG (0x00000001) /* Raw interrupt status */\r
-/* TIMER32_MIS1[TIMER32_MIS1_] Bits */\r
-#define TIMER32_MIS1__OFS ( 0) /* IFG Offset */\r
-#define TIMER32_MIS1_ (0x00000001) /* Enabled interrupt status */\r
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_ONESHOT] Bits */\r
-#define TIMER32_CONTROL2_ONESHOT_OFS ( 0) /* ONESHOT Offset */\r
-#define TIMER32_CONTROL2_ONESHOT (0x00000001) /* Selects one-shot or wrapping counter mode */\r
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_SIZE] Bits */\r
-#define TIMER32_CONTROL2_SIZE_OFS ( 1) /* SIZE Offset */\r
-#define TIMER32_CONTROL2_SIZE (0x00000002) /* Selects 16 or 32 bit counter operation */\r
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_PRESCALE] Bits */\r
-#define TIMER32_CONTROL2_PRESCALE_OFS ( 2) /* PRESCALE Offset */\r
-#define TIMER32_CONTROL2_PRESCALE_M (0x0000000c) /* Prescale bits */\r
-#define TIMER32_CONTROL2_PRESCALE0 (0x00000004) /* Prescale bits */\r
-#define TIMER32_CONTROL2_PRESCALE1 (0x00000008) /* Prescale bits */\r
-#define TIMER32_CONTROL2_PRESCALE_0 (0x00000000) /* 0 stages of prescale, clock is divided by 1 */\r
-#define TIMER32_CONTROL2_PRESCALE_1 (0x00000004) /* 4 stages of prescale, clock is divided by 16 */\r
-#define TIMER32_CONTROL2_PRESCALE_2 (0x00000008) /* 8 stages of prescale, clock is divided by 256 */\r
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_IE] Bits */\r
-#define TIMER32_CONTROL2_IE_OFS ( 5) /* IE Offset */\r
-#define TIMER32_CONTROL2_IE (0x00000020) /* Interrupt enable bit */\r
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_MODE] Bits */\r
-#define TIMER32_CONTROL2_MODE_OFS ( 6) /* MODE Offset */\r
-#define TIMER32_CONTROL2_MODE (0x00000040) /* Mode bit */\r
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_ENABLE] Bits */\r
-#define TIMER32_CONTROL2_ENABLE_OFS ( 7) /* ENABLE Offset */\r
-#define TIMER32_CONTROL2_ENABLE (0x00000080) /* */\r
-/* TIMER32_RIS2[TIMER32_RIS2_RAW_IFG] Bits */\r
-#define TIMER32_RIS2_RAW_IFG_OFS ( 0) /* RAW_IFG Offset */\r
-#define TIMER32_RIS2_RAW_IFG (0x00000001) /* Raw interrupt status */\r
-/* TIMER32_MIS2[TIMER32_MIS2_IFG] Bits */\r
-#define TIMER32_MIS2_IFG_OFS ( 0) /* IFG Offset */\r
-#define TIMER32_MIS2_IFG (0x00000001) /* Enabled interrupt status */\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A0 Bits\r
-//*****************************************************************************\r
-/* TA0CTL[TAIFG] Bits */\r
-#define TAIFG_OFS ( 0) /* TAIFG Offset */\r
-#define TAIFG (0x0001) /* TimerA interrupt flag */\r
-/* TA0CTL[TAIE] Bits */\r
-#define TAIE_OFS ( 1) /* TAIE Offset */\r
-#define TAIE (0x0002) /* TimerA interrupt enable */\r
-/* TA0CTL[TACLR] Bits */\r
-#define TACLR_OFS ( 2) /* TACLR Offset */\r
-#define TACLR (0x0004) /* TimerA clear */\r
-/* TA0CTL[MC] Bits */\r
-#define MC_OFS ( 4) /* MC Offset */\r
-#define MC_M (0x0030) /* Mode control */\r
-#define MC0 (0x0010) /* Mode control */\r
-#define MC1 (0x0020) /* Mode control */\r
-#define MC_0 (0x0000) /* Stop mode: Timer is halted */\r
-#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
-#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
-#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
-#define MC__STOP (0x0000) /* Stop mode: Timer is halted */\r
-#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
-#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
-#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
-/* TA0CTL[ID] Bits */\r
-#define ID_OFS ( 6) /* ID Offset */\r
-#define ID_M (0x00c0) /* Input divider */\r
-#define ID0 (0x0040) /* Input divider */\r
-#define ID1 (0x0080) /* Input divider */\r
-#define ID_0 (0x0000) /* /1 */\r
-#define ID_1 (0x0040) /* /2 */\r
-#define ID_2 (0x0080) /* /4 */\r
-#define ID_3 (0x00c0) /* /8 */\r
-#define ID__1 (0x0000) /* /1 */\r
-#define ID__2 (0x0040) /* /2 */\r
-#define ID__4 (0x0080) /* /4 */\r
-#define ID__8 (0x00c0) /* /8 */\r
-/* TA0CTL[TASSEL] Bits */\r
-#define TASSEL_OFS ( 8) /* TASSEL Offset */\r
-#define TASSEL_M (0x0300) /* TimerA clock source select */\r
-#define TASSEL0 (0x0100) /* TimerA clock source select */\r
-#define TASSEL1 (0x0200) /* TimerA clock source select */\r
-#define TASSEL_0 (0x0000) /* TAxCLK */\r
-#define TASSEL_1 (0x0100) /* ACLK */\r
-#define TASSEL_2 (0x0200) /* SMCLK */\r
-#define TASSEL_3 (0x0300) /* INCLK */\r
-#define TASSEL__TACLK (0x0000) /* TAxCLK */\r
-#define TASSEL__ACLK (0x0100) /* ACLK */\r
-#define TASSEL__SMCLK (0x0200) /* SMCLK */\r
-#define TASSEL__INCLK (0x0300) /* INCLK */\r
-/* TA0CCTL[CCIFG] Bits */\r
-#define CCIFG_OFS ( 0) /* CCIFG Offset */\r
-#define CCIFG (0x0001) /* Capture/compare interrupt flag */\r
-/* TA0CCTL[COV] Bits */\r
-#define COV_OFS ( 1) /* COV Offset */\r
-#define COV (0x0002) /* Capture overflow */\r
-/* TA0CCTL[OUT] Bits */\r
-#define OUT_OFS ( 2) /* OUT Offset */\r
-#define OUT (0x0004) /* Output */\r
-/* TA0CCTL[CCI] Bits */\r
-#define CCI_OFS ( 3) /* CCI Offset */\r
-#define CCI (0x0008) /* Capture/compare input */\r
-/* TA0CCTL[CCIE] Bits */\r
-#define CCIE_OFS ( 4) /* CCIE Offset */\r
-#define CCIE (0x0010) /* Capture/compare interrupt enable */\r
-/* TA0CCTL[OUTMOD] Bits */\r
-#define OUTMOD_OFS ( 5) /* OUTMOD Offset */\r
-#define OUTMOD_M (0x00e0) /* Output mode */\r
-#define OUTMOD0 (0x0020) /* Output mode */\r
-#define OUTMOD1 (0x0040) /* Output mode */\r
-#define OUTMOD2 (0x0080) /* Output mode */\r
-#define OUTMOD_0 (0x0000) /* OUT bit value */\r
-#define OUTMOD_1 (0x0020) /* Set */\r
-#define OUTMOD_2 (0x0040) /* Toggle/reset */\r
-#define OUTMOD_3 (0x0060) /* Set/reset */\r
-#define OUTMOD_4 (0x0080) /* Toggle */\r
-#define OUTMOD_5 (0x00a0) /* Reset */\r
-#define OUTMOD_6 (0x00c0) /* Toggle/set */\r
-#define OUTMOD_7 (0x00e0) /* Reset/set */\r
-/* TA0CCTL[CAP] Bits */\r
-#define CAP_OFS ( 8) /* CAP Offset */\r
-#define CAP (0x0100) /* Capture mode */\r
-/* TA0CCTL[SCCI] Bits */\r
-#define SCCI_OFS (10) /* SCCI Offset */\r
-#define SCCI (0x0400) /* Synchronized capture/compare input */\r
-/* TA0CCTL[SCS] Bits */\r
-#define SCS_OFS (11) /* SCS Offset */\r
-#define SCS (0x0800) /* Synchronize capture source */\r
-/* TA0CCTL[CCIS] Bits */\r
-#define CCIS_OFS (12) /* CCIS Offset */\r
-#define CCIS_M (0x3000) /* Capture/compare input select */\r
-#define CCIS0 (0x1000) /* Capture/compare input select */\r
-#define CCIS1 (0x2000) /* Capture/compare input select */\r
-#define CCIS_0 (0x0000) /* CCIxA */\r
-#define CCIS_1 (0x1000) /* CCIxB */\r
-#define CCIS_2 (0x2000) /* GND */\r
-#define CCIS_3 (0x3000) /* VCC */\r
-#define CCIS__CCIA (0x0000) /* CCIxA */\r
-#define CCIS__CCIB (0x1000) /* CCIxB */\r
-#define CCIS__GND (0x2000) /* GND */\r
-#define CCIS__VCC (0x3000) /* VCC */\r
-/* TA0CCTL[CM] Bits */\r
-#define CM_OFS (14) /* CM Offset */\r
-#define CM_M (0xc000) /* Capture mode */\r
-#define CM0 (0x4000) /* Capture mode */\r
-#define CM1 (0x8000) /* Capture mode */\r
-#define CM_0 (0x0000) /* No capture */\r
-#define CM_1 (0x4000) /* Capture on rising edge */\r
-#define CM_2 (0x8000) /* Capture on falling edge */\r
-#define CM_3 (0xc000) /* Capture on both rising and falling edges */\r
-#define CM__NONE (0x0000) /* No capture */\r
-#define CM__RISING (0x4000) /* Capture on rising edge */\r
-#define CM__FALLING (0x8000) /* Capture on falling edge */\r
-#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */\r
-/* TA0EX0[TAIDEX] Bits */\r
-#define TAIDEX_OFS ( 0) /* TAIDEX Offset */\r
-#define TAIDEX_M (0x0007) /* Input divider expansion */\r
-#define TAIDEX0 (0x0001) /* Input divider expansion */\r
-#define TAIDEX1 (0x0002) /* Input divider expansion */\r
-#define TAIDEX2 (0x0004) /* Input divider expansion */\r
-#define TAIDEX_0 (0x0000) /* Divide by 1 */\r
-#define TAIDEX_1 (0x0001) /* Divide by 2 */\r
-#define TAIDEX_2 (0x0002) /* Divide by 3 */\r
-#define TAIDEX_3 (0x0003) /* Divide by 4 */\r
-#define TAIDEX_4 (0x0004) /* Divide by 5 */\r
-#define TAIDEX_5 (0x0005) /* Divide by 6 */\r
-#define TAIDEX_6 (0x0006) /* Divide by 7 */\r
-#define TAIDEX_7 (0x0007) /* Divide by 8 */\r
-#define TAIDEX__1 (0x0000) /* Divide by 1 */\r
-#define TAIDEX__2 (0x0001) /* Divide by 2 */\r
-#define TAIDEX__3 (0x0002) /* Divide by 3 */\r
-#define TAIDEX__4 (0x0003) /* Divide by 4 */\r
-#define TAIDEX__5 (0x0004) /* Divide by 5 */\r
-#define TAIDEX__6 (0x0005) /* Divide by 6 */\r
-#define TAIDEX__7 (0x0006) /* Divide by 7 */\r
-#define TAIDEX__8 (0x0007) /* Divide by 8 */\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A1 Bits\r
-//*****************************************************************************\r
-/* TA1CTL[TAIFG] Bits */\r
-//#define TAIFG_OFS ( 0) /* TAIFG Offset */\r
-//#define TAIFG (0x0001) /* TimerA interrupt flag */\r
-/* TA1CTL[TAIE] Bits */\r
-//#define TAIE_OFS ( 1) /* TAIE Offset */\r
-//#define TAIE (0x0002) /* TimerA interrupt enable */\r
-/* TA1CTL[TACLR] Bits */\r
-//#define TACLR_OFS ( 2) /* TACLR Offset */\r
-//#define TACLR (0x0004) /* TimerA clear */\r
-/* TA1CTL[MC] Bits */\r
-//#define MC_OFS ( 4) /* MC Offset */\r
-//#define MC_M (0x0030) /* Mode control */\r
-//#define MC0 (0x0010) /* Mode control */\r
-//#define MC1 (0x0020) /* Mode control */\r
-//#define MC_0 (0x0000) /* Stop mode: Timer is halted */\r
-//#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
-//#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
-//#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
-//#define MC__STOP (0x0000) /* Stop mode: Timer is halted */\r
-//#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
-//#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
-//#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
-/* TA1CTL[ID] Bits */\r
-//#define ID_OFS ( 6) /* ID Offset */\r
-//#define ID_M (0x00c0) /* Input divider */\r
-//#define ID0 (0x0040) /* Input divider */\r
-//#define ID1 (0x0080) /* Input divider */\r
-//#define ID_0 (0x0000) /* /1 */\r
-//#define ID_1 (0x0040) /* /2 */\r
-//#define ID_2 (0x0080) /* /4 */\r
-//#define ID_3 (0x00c0) /* /8 */\r
-//#define ID__1 (0x0000) /* /1 */\r
-//#define ID__2 (0x0040) /* /2 */\r
-//#define ID__4 (0x0080) /* /4 */\r
-//#define ID__8 (0x00c0) /* /8 */\r
-/* TA1CTL[TASSEL] Bits */\r
-//#define TASSEL_OFS ( 8) /* TASSEL Offset */\r
-//#define TASSEL_M (0x0300) /* TimerA clock source select */\r
-//#define TASSEL0 (0x0100) /* TimerA clock source select */\r
-//#define TASSEL1 (0x0200) /* TimerA clock source select */\r
-//#define TASSEL_0 (0x0000) /* TAxCLK */\r
-//#define TASSEL_1 (0x0100) /* ACLK */\r
-//#define TASSEL_2 (0x0200) /* SMCLK */\r
-//#define TASSEL_3 (0x0300) /* INCLK */\r
-//#define TASSEL__TACLK (0x0000) /* TAxCLK */\r
-//#define TASSEL__ACLK (0x0100) /* ACLK */\r
-//#define TASSEL__SMCLK (0x0200) /* SMCLK */\r
-//#define TASSEL__INCLK (0x0300) /* INCLK */\r
-/* TA1CCTL[CCIFG] Bits */\r
-//#define CCIFG_OFS ( 0) /* CCIFG Offset */\r
-//#define CCIFG (0x0001) /* Capture/compare interrupt flag */\r
-/* TA1CCTL[COV] Bits */\r
-//#define COV_OFS ( 1) /* COV Offset */\r
-//#define COV (0x0002) /* Capture overflow */\r
-/* TA1CCTL[OUT] Bits */\r
-//#define OUT_OFS ( 2) /* OUT Offset */\r
-//#define OUT (0x0004) /* Output */\r
-/* TA1CCTL[CCI] Bits */\r
-//#define CCI_OFS ( 3) /* CCI Offset */\r
-//#define CCI (0x0008) /* Capture/compare input */\r
-/* TA1CCTL[CCIE] Bits */\r
-//#define CCIE_OFS ( 4) /* CCIE Offset */\r
-//#define CCIE (0x0010) /* Capture/compare interrupt enable */\r
-/* TA1CCTL[OUTMOD] Bits */\r
-//#define OUTMOD_OFS ( 5) /* OUTMOD Offset */\r
-//#define OUTMOD_M (0x00e0) /* Output mode */\r
-//#define OUTMOD0 (0x0020) /* Output mode */\r
-//#define OUTMOD1 (0x0040) /* Output mode */\r
-//#define OUTMOD2 (0x0080) /* Output mode */\r
-//#define OUTMOD_0 (0x0000) /* OUT bit value */\r
-//#define OUTMOD_1 (0x0020) /* Set */\r
-//#define OUTMOD_2 (0x0040) /* Toggle/reset */\r
-//#define OUTMOD_3 (0x0060) /* Set/reset */\r
-//#define OUTMOD_4 (0x0080) /* Toggle */\r
-//#define OUTMOD_5 (0x00a0) /* Reset */\r
-//#define OUTMOD_6 (0x00c0) /* Toggle/set */\r
-//#define OUTMOD_7 (0x00e0) /* Reset/set */\r
-/* TA1CCTL[CAP] Bits */\r
-//#define CAP_OFS ( 8) /* CAP Offset */\r
-//#define CAP (0x0100) /* Capture mode */\r
-/* TA1CCTL[SCCI] Bits */\r
-//#define SCCI_OFS (10) /* SCCI Offset */\r
-//#define SCCI (0x0400) /* Synchronized capture/compare input */\r
-/* TA1CCTL[SCS] Bits */\r
-//#define SCS_OFS (11) /* SCS Offset */\r
-//#define SCS (0x0800) /* Synchronize capture source */\r
-/* TA1CCTL[CCIS] Bits */\r
-//#define CCIS_OFS (12) /* CCIS Offset */\r
-//#define CCIS_M (0x3000) /* Capture/compare input select */\r
-//#define CCIS0 (0x1000) /* Capture/compare input select */\r
-//#define CCIS1 (0x2000) /* Capture/compare input select */\r
-//#define CCIS_0 (0x0000) /* CCIxA */\r
-//#define CCIS_1 (0x1000) /* CCIxB */\r
-//#define CCIS_2 (0x2000) /* GND */\r
-//#define CCIS_3 (0x3000) /* VCC */\r
-//#define CCIS__CCIA (0x0000) /* CCIxA */\r
-//#define CCIS__CCIB (0x1000) /* CCIxB */\r
-//#define CCIS__GND (0x2000) /* GND */\r
-//#define CCIS__VCC (0x3000) /* VCC */\r
-/* TA1CCTL[CM] Bits */\r
-//#define CM_OFS (14) /* CM Offset */\r
-//#define CM_M (0xc000) /* Capture mode */\r
-//#define CM0 (0x4000) /* Capture mode */\r
-//#define CM1 (0x8000) /* Capture mode */\r
-//#define CM_0 (0x0000) /* No capture */\r
-//#define CM_1 (0x4000) /* Capture on rising edge */\r
-//#define CM_2 (0x8000) /* Capture on falling edge */\r
-//#define CM_3 (0xc000) /* Capture on both rising and falling edges */\r
-//#define CM__NONE (0x0000) /* No capture */\r
-//#define CM__RISING (0x4000) /* Capture on rising edge */\r
-//#define CM__FALLING (0x8000) /* Capture on falling edge */\r
-//#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */\r
-/* TA1EX0[TAIDEX] Bits */\r
-//#define TAIDEX_OFS ( 0) /* TAIDEX Offset */\r
-//#define TAIDEX_M (0x0007) /* Input divider expansion */\r
-//#define TAIDEX0 (0x0001) /* Input divider expansion */\r
-//#define TAIDEX1 (0x0002) /* Input divider expansion */\r
-//#define TAIDEX2 (0x0004) /* Input divider expansion */\r
-//#define TAIDEX_0 (0x0000) /* Divide by 1 */\r
-//#define TAIDEX_1 (0x0001) /* Divide by 2 */\r
-//#define TAIDEX_2 (0x0002) /* Divide by 3 */\r
-//#define TAIDEX_3 (0x0003) /* Divide by 4 */\r
-//#define TAIDEX_4 (0x0004) /* Divide by 5 */\r
-//#define TAIDEX_5 (0x0005) /* Divide by 6 */\r
-//#define TAIDEX_6 (0x0006) /* Divide by 7 */\r
-//#define TAIDEX_7 (0x0007) /* Divide by 8 */\r
-//#define TAIDEX__1 (0x0000) /* Divide by 1 */\r
-//#define TAIDEX__2 (0x0001) /* Divide by 2 */\r
-//#define TAIDEX__3 (0x0002) /* Divide by 3 */\r
-//#define TAIDEX__4 (0x0003) /* Divide by 4 */\r
-//#define TAIDEX__5 (0x0004) /* Divide by 5 */\r
-//#define TAIDEX__6 (0x0005) /* Divide by 6 */\r
-//#define TAIDEX__7 (0x0006) /* Divide by 7 */\r
-//#define TAIDEX__8 (0x0007) /* Divide by 8 */\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A2 Bits\r
-//*****************************************************************************\r
-/* TA2CTL[TAIFG] Bits */\r
-//#define TAIFG_OFS ( 0) /* TAIFG Offset */\r
-//#define TAIFG (0x0001) /* TimerA interrupt flag */\r
-/* TA2CTL[TAIE] Bits */\r
-//#define TAIE_OFS ( 1) /* TAIE Offset */\r
-//#define TAIE (0x0002) /* TimerA interrupt enable */\r
-/* TA2CTL[TACLR] Bits */\r
-//#define TACLR_OFS ( 2) /* TACLR Offset */\r
-//#define TACLR (0x0004) /* TimerA clear */\r
-/* TA2CTL[MC] Bits */\r
-//#define MC_OFS ( 4) /* MC Offset */\r
-//#define MC_M (0x0030) /* Mode control */\r
-//#define MC0 (0x0010) /* Mode control */\r
-//#define MC1 (0x0020) /* Mode control */\r
-//#define MC_0 (0x0000) /* Stop mode: Timer is halted */\r
-//#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
-//#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
-//#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
-//#define MC__STOP (0x0000) /* Stop mode: Timer is halted */\r
-//#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
-//#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
-//#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
-/* TA2CTL[ID] Bits */\r
-//#define ID_OFS ( 6) /* ID Offset */\r
-//#define ID_M (0x00c0) /* Input divider */\r
-//#define ID0 (0x0040) /* Input divider */\r
-//#define ID1 (0x0080) /* Input divider */\r
-//#define ID_0 (0x0000) /* /1 */\r
-//#define ID_1 (0x0040) /* /2 */\r
-//#define ID_2 (0x0080) /* /4 */\r
-//#define ID_3 (0x00c0) /* /8 */\r
-//#define ID__1 (0x0000) /* /1 */\r
-//#define ID__2 (0x0040) /* /2 */\r
-//#define ID__4 (0x0080) /* /4 */\r
-//#define ID__8 (0x00c0) /* /8 */\r
-/* TA2CTL[TASSEL] Bits */\r
-//#define TASSEL_OFS ( 8) /* TASSEL Offset */\r
-//#define TASSEL_M (0x0300) /* TimerA clock source select */\r
-//#define TASSEL0 (0x0100) /* TimerA clock source select */\r
-//#define TASSEL1 (0x0200) /* TimerA clock source select */\r
-//#define TASSEL_0 (0x0000) /* TAxCLK */\r
-//#define TASSEL_1 (0x0100) /* ACLK */\r
-//#define TASSEL_2 (0x0200) /* SMCLK */\r
-//#define TASSEL_3 (0x0300) /* INCLK */\r
-//#define TASSEL__TACLK (0x0000) /* TAxCLK */\r
-//#define TASSEL__ACLK (0x0100) /* ACLK */\r
-//#define TASSEL__SMCLK (0x0200) /* SMCLK */\r
-//#define TASSEL__INCLK (0x0300) /* INCLK */\r
-/* TA2CCTL[CCIFG] Bits */\r
-//#define CCIFG_OFS ( 0) /* CCIFG Offset */\r
-//#define CCIFG (0x0001) /* Capture/compare interrupt flag */\r
-/* TA2CCTL[COV] Bits */\r
-//#define COV_OFS ( 1) /* COV Offset */\r
-//#define COV (0x0002) /* Capture overflow */\r
-/* TA2CCTL[OUT] Bits */\r
-//#define OUT_OFS ( 2) /* OUT Offset */\r
-//#define OUT (0x0004) /* Output */\r
-/* TA2CCTL[CCI] Bits */\r
-//#define CCI_OFS ( 3) /* CCI Offset */\r
-//#define CCI (0x0008) /* Capture/compare input */\r
-/* TA2CCTL[CCIE] Bits */\r
-//#define CCIE_OFS ( 4) /* CCIE Offset */\r
-//#define CCIE (0x0010) /* Capture/compare interrupt enable */\r
-/* TA2CCTL[OUTMOD] Bits */\r
-//#define OUTMOD_OFS ( 5) /* OUTMOD Offset */\r
-//#define OUTMOD_M (0x00e0) /* Output mode */\r
-//#define OUTMOD0 (0x0020) /* Output mode */\r
-//#define OUTMOD1 (0x0040) /* Output mode */\r
-//#define OUTMOD2 (0x0080) /* Output mode */\r
-//#define OUTMOD_0 (0x0000) /* OUT bit value */\r
-//#define OUTMOD_1 (0x0020) /* Set */\r
-//#define OUTMOD_2 (0x0040) /* Toggle/reset */\r
-//#define OUTMOD_3 (0x0060) /* Set/reset */\r
-//#define OUTMOD_4 (0x0080) /* Toggle */\r
-//#define OUTMOD_5 (0x00a0) /* Reset */\r
-//#define OUTMOD_6 (0x00c0) /* Toggle/set */\r
-//#define OUTMOD_7 (0x00e0) /* Reset/set */\r
-/* TA2CCTL[CAP] Bits */\r
-//#define CAP_OFS ( 8) /* CAP Offset */\r
-//#define CAP (0x0100) /* Capture mode */\r
-/* TA2CCTL[SCCI] Bits */\r
-//#define SCCI_OFS (10) /* SCCI Offset */\r
-//#define SCCI (0x0400) /* Synchronized capture/compare input */\r
-/* TA2CCTL[SCS] Bits */\r
-//#define SCS_OFS (11) /* SCS Offset */\r
-//#define SCS (0x0800) /* Synchronize capture source */\r
-/* TA2CCTL[CCIS] Bits */\r
-//#define CCIS_OFS (12) /* CCIS Offset */\r
-//#define CCIS_M (0x3000) /* Capture/compare input select */\r
-//#define CCIS0 (0x1000) /* Capture/compare input select */\r
-//#define CCIS1 (0x2000) /* Capture/compare input select */\r
-//#define CCIS_0 (0x0000) /* CCIxA */\r
-//#define CCIS_1 (0x1000) /* CCIxB */\r
-//#define CCIS_2 (0x2000) /* GND */\r
-//#define CCIS_3 (0x3000) /* VCC */\r
-//#define CCIS__CCIA (0x0000) /* CCIxA */\r
-//#define CCIS__CCIB (0x1000) /* CCIxB */\r
-//#define CCIS__GND (0x2000) /* GND */\r
-//#define CCIS__VCC (0x3000) /* VCC */\r
-/* TA2CCTL[CM] Bits */\r
-//#define CM_OFS (14) /* CM Offset */\r
-//#define CM_M (0xc000) /* Capture mode */\r
-//#define CM0 (0x4000) /* Capture mode */\r
-//#define CM1 (0x8000) /* Capture mode */\r
-//#define CM_0 (0x0000) /* No capture */\r
-//#define CM_1 (0x4000) /* Capture on rising edge */\r
-//#define CM_2 (0x8000) /* Capture on falling edge */\r
-//#define CM_3 (0xc000) /* Capture on both rising and falling edges */\r
-//#define CM__NONE (0x0000) /* No capture */\r
-//#define CM__RISING (0x4000) /* Capture on rising edge */\r
-//#define CM__FALLING (0x8000) /* Capture on falling edge */\r
-//#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */\r
-/* TA2EX0[TAIDEX] Bits */\r
-//#define TAIDEX_OFS ( 0) /* TAIDEX Offset */\r
-//#define TAIDEX_M (0x0007) /* Input divider expansion */\r
-//#define TAIDEX0 (0x0001) /* Input divider expansion */\r
-//#define TAIDEX1 (0x0002) /* Input divider expansion */\r
-//#define TAIDEX2 (0x0004) /* Input divider expansion */\r
-//#define TAIDEX_0 (0x0000) /* Divide by 1 */\r
-//#define TAIDEX_1 (0x0001) /* Divide by 2 */\r
-//#define TAIDEX_2 (0x0002) /* Divide by 3 */\r
-//#define TAIDEX_3 (0x0003) /* Divide by 4 */\r
-//#define TAIDEX_4 (0x0004) /* Divide by 5 */\r
-//#define TAIDEX_5 (0x0005) /* Divide by 6 */\r
-//#define TAIDEX_6 (0x0006) /* Divide by 7 */\r
-//#define TAIDEX_7 (0x0007) /* Divide by 8 */\r
-//#define TAIDEX__1 (0x0000) /* Divide by 1 */\r
-//#define TAIDEX__2 (0x0001) /* Divide by 2 */\r
-//#define TAIDEX__3 (0x0002) /* Divide by 3 */\r
-//#define TAIDEX__4 (0x0003) /* Divide by 4 */\r
-//#define TAIDEX__5 (0x0004) /* Divide by 5 */\r
-//#define TAIDEX__6 (0x0005) /* Divide by 6 */\r
-//#define TAIDEX__7 (0x0006) /* Divide by 7 */\r
-//#define TAIDEX__8 (0x0007) /* Divide by 8 */\r
-\r
-\r
-//*****************************************************************************\r
-// TIMER_A3 Bits\r
-//*****************************************************************************\r
-/* TA3CTL[TAIFG] Bits */\r
-//#define TAIFG_OFS ( 0) /* TAIFG Offset */\r
-//#define TAIFG (0x0001) /* TimerA interrupt flag */\r
-/* TA3CTL[TAIE] Bits */\r
-//#define TAIE_OFS ( 1) /* TAIE Offset */\r
-//#define TAIE (0x0002) /* TimerA interrupt enable */\r
-/* TA3CTL[TACLR] Bits */\r
-//#define TACLR_OFS ( 2) /* TACLR Offset */\r
-//#define TACLR (0x0004) /* TimerA clear */\r
-/* TA3CTL[MC] Bits */\r
-//#define MC_OFS ( 4) /* MC Offset */\r
-//#define MC_M (0x0030) /* Mode control */\r
-//#define MC0 (0x0010) /* Mode control */\r
-//#define MC1 (0x0020) /* Mode control */\r
-//#define MC_0 (0x0000) /* Stop mode: Timer is halted */\r
-//#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
-//#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
-//#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
-//#define MC__STOP (0x0000) /* Stop mode: Timer is halted */\r
-//#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
-//#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
-//#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
-/* TA3CTL[ID] Bits */\r
-//#define ID_OFS ( 6) /* ID Offset */\r
-//#define ID_M (0x00c0) /* Input divider */\r
-//#define ID0 (0x0040) /* Input divider */\r
-//#define ID1 (0x0080) /* Input divider */\r
-//#define ID_0 (0x0000) /* /1 */\r
-//#define ID_1 (0x0040) /* /2 */\r
-//#define ID_2 (0x0080) /* /4 */\r
-//#define ID_3 (0x00c0) /* /8 */\r
-//#define ID__1 (0x0000) /* /1 */\r
-//#define ID__2 (0x0040) /* /2 */\r
-//#define ID__4 (0x0080) /* /4 */\r
-//#define ID__8 (0x00c0) /* /8 */\r
-/* TA3CTL[TASSEL] Bits */\r
-//#define TASSEL_OFS ( 8) /* TASSEL Offset */\r
-//#define TASSEL_M (0x0300) /* TimerA clock source select */\r
-//#define TASSEL0 (0x0100) /* TimerA clock source select */\r
-//#define TASSEL1 (0x0200) /* TimerA clock source select */\r
-//#define TASSEL_0 (0x0000) /* TAxCLK */\r
-//#define TASSEL_1 (0x0100) /* ACLK */\r
-//#define TASSEL_2 (0x0200) /* SMCLK */\r
-//#define TASSEL_3 (0x0300) /* INCLK */\r
-//#define TASSEL__TACLK (0x0000) /* TAxCLK */\r
-//#define TASSEL__ACLK (0x0100) /* ACLK */\r
-//#define TASSEL__SMCLK (0x0200) /* SMCLK */\r
-//#define TASSEL__INCLK (0x0300) /* INCLK */\r
-/* TA3CCTL[CCIFG] Bits */\r
-//#define CCIFG_OFS ( 0) /* CCIFG Offset */\r
-//#define CCIFG (0x0001) /* Capture/compare interrupt flag */\r
-/* TA3CCTL[COV] Bits */\r
-//#define COV_OFS ( 1) /* COV Offset */\r
-//#define COV (0x0002) /* Capture overflow */\r
-/* TA3CCTL[OUT] Bits */\r
-//#define OUT_OFS ( 2) /* OUT Offset */\r
-//#define OUT (0x0004) /* Output */\r
-/* TA3CCTL[CCI] Bits */\r
-//#define CCI_OFS ( 3) /* CCI Offset */\r
-//#define CCI (0x0008) /* Capture/compare input */\r
-/* TA3CCTL[CCIE] Bits */\r
-//#define CCIE_OFS ( 4) /* CCIE Offset */\r
-//#define CCIE (0x0010) /* Capture/compare interrupt enable */\r
-/* TA3CCTL[OUTMOD] Bits */\r
-//#define OUTMOD_OFS ( 5) /* OUTMOD Offset */\r
-//#define OUTMOD_M (0x00e0) /* Output mode */\r
-//#define OUTMOD0 (0x0020) /* Output mode */\r
-//#define OUTMOD1 (0x0040) /* Output mode */\r
-//#define OUTMOD2 (0x0080) /* Output mode */\r
-//#define OUTMOD_0 (0x0000) /* OUT bit value */\r
-//#define OUTMOD_1 (0x0020) /* Set */\r
-//#define OUTMOD_2 (0x0040) /* Toggle/reset */\r
-//#define OUTMOD_3 (0x0060) /* Set/reset */\r
-//#define OUTMOD_4 (0x0080) /* Toggle */\r
-//#define OUTMOD_5 (0x00a0) /* Reset */\r
-//#define OUTMOD_6 (0x00c0) /* Toggle/set */\r
-//#define OUTMOD_7 (0x00e0) /* Reset/set */\r
-/* TA3CCTL[CAP] Bits */\r
-//#define CAP_OFS ( 8) /* CAP Offset */\r
-//#define CAP (0x0100) /* Capture mode */\r
-/* TA3CCTL[SCCI] Bits */\r
-//#define SCCI_OFS (10) /* SCCI Offset */\r
-//#define SCCI (0x0400) /* Synchronized capture/compare input */\r
-/* TA3CCTL[SCS] Bits */\r
-//#define SCS_OFS (11) /* SCS Offset */\r
-//#define SCS (0x0800) /* Synchronize capture source */\r
-/* TA3CCTL[CCIS] Bits */\r
-//#define CCIS_OFS (12) /* CCIS Offset */\r
-//#define CCIS_M (0x3000) /* Capture/compare input select */\r
-//#define CCIS0 (0x1000) /* Capture/compare input select */\r
-//#define CCIS1 (0x2000) /* Capture/compare input select */\r
-//#define CCIS_0 (0x0000) /* CCIxA */\r
-//#define CCIS_1 (0x1000) /* CCIxB */\r
-//#define CCIS_2 (0x2000) /* GND */\r
-//#define CCIS_3 (0x3000) /* VCC */\r
-//#define CCIS__CCIA (0x0000) /* CCIxA */\r
-//#define CCIS__CCIB (0x1000) /* CCIxB */\r
-//#define CCIS__GND (0x2000) /* GND */\r
-//#define CCIS__VCC (0x3000) /* VCC */\r
-/* TA3CCTL[CM] Bits */\r
-//#define CM_OFS (14) /* CM Offset */\r
-//#define CM_M (0xc000) /* Capture mode */\r
-//#define CM0 (0x4000) /* Capture mode */\r
-//#define CM1 (0x8000) /* Capture mode */\r
-//#define CM_0 (0x0000) /* No capture */\r
-//#define CM_1 (0x4000) /* Capture on rising edge */\r
-//#define CM_2 (0x8000) /* Capture on falling edge */\r
-//#define CM_3 (0xc000) /* Capture on both rising and falling edges */\r
-//#define CM__NONE (0x0000) /* No capture */\r
-//#define CM__RISING (0x4000) /* Capture on rising edge */\r
-//#define CM__FALLING (0x8000) /* Capture on falling edge */\r
-//#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */\r
-/* TA3EX0[TAIDEX] Bits */\r
-//#define TAIDEX_OFS ( 0) /* TAIDEX Offset */\r
-//#define TAIDEX_M (0x0007) /* Input divider expansion */\r
-//#define TAIDEX0 (0x0001) /* Input divider expansion */\r
-//#define TAIDEX1 (0x0002) /* Input divider expansion */\r
-//#define TAIDEX2 (0x0004) /* Input divider expansion */\r
-//#define TAIDEX_0 (0x0000) /* Divide by 1 */\r
-//#define TAIDEX_1 (0x0001) /* Divide by 2 */\r
-//#define TAIDEX_2 (0x0002) /* Divide by 3 */\r
-//#define TAIDEX_3 (0x0003) /* Divide by 4 */\r
-//#define TAIDEX_4 (0x0004) /* Divide by 5 */\r
-//#define TAIDEX_5 (0x0005) /* Divide by 6 */\r
-//#define TAIDEX_6 (0x0006) /* Divide by 7 */\r
-//#define TAIDEX_7 (0x0007) /* Divide by 8 */\r
-//#define TAIDEX__1 (0x0000) /* Divide by 1 */\r
-//#define TAIDEX__2 (0x0001) /* Divide by 2 */\r
-//#define TAIDEX__3 (0x0002) /* Divide by 3 */\r
-//#define TAIDEX__4 (0x0003) /* Divide by 4 */\r
-//#define TAIDEX__5 (0x0004) /* Divide by 5 */\r
-//#define TAIDEX__6 (0x0005) /* Divide by 6 */\r
-//#define TAIDEX__7 (0x0006) /* Divide by 7 */\r
-//#define TAIDEX__8 (0x0007) /* Divide by 8 */\r
-\r
-\r
-//*****************************************************************************\r
-// TLV Bits\r
-//*****************************************************************************\r
-\r
-\r
-//*****************************************************************************\r
-// WDT_A Bits\r
-//*****************************************************************************\r
-/* WDTCTL[WDTIS] Bits */\r
-#define WDTIS_OFS ( 0) /* WDTIS Offset */\r
-#define WDTIS_M (0x0007) /* Watchdog timer interval select */\r
-#define WDTIS0 (0x0001) /* Watchdog timer interval select */\r
-#define WDTIS1 (0x0002) /* Watchdog timer interval select */\r
-#define WDTIS2 (0x0004) /* Watchdog timer interval select */\r
-#define WDTIS_0 (0x0000) /* Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */\r
-#define WDTIS_1 (0x0001) /* Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */\r
-#define WDTIS_2 (0x0002) /* Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */\r
-#define WDTIS_3 (0x0003) /* Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */\r
-#define WDTIS_4 (0x0004) /* Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */\r
-#define WDTIS_5 (0x0005) /* Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */\r
-#define WDTIS_6 (0x0006) /* Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */\r
-#define WDTIS_7 (0x0007) /* Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */\r
-/* WDTCTL[WDTCNTCL] Bits */\r
-#define WDTCNTCL_OFS ( 3) /* WDTCNTCL Offset */\r
-#define WDTCNTCL (0x0008) /* Watchdog timer counter clear */\r
-/* WDTCTL[WDTTMSEL] Bits */\r
-#define WDTTMSEL_OFS ( 4) /* WDTTMSEL Offset */\r
-#define WDTTMSEL (0x0010) /* Watchdog timer mode select */\r
-/* WDTCTL[WDTSSEL] Bits */\r
-#define WDTSSEL_OFS ( 5) /* WDTSSEL Offset */\r
-#define WDTSSEL_M (0x0060) /* Watchdog timer clock source select */\r
-#define WDTSSEL0 (0x0020) /* Watchdog timer clock source select */\r
-#define WDTSSEL1 (0x0040) /* Watchdog timer clock source select */\r
-#define WDTSSEL_0 (0x0000) /* SMCLK */\r
-#define WDTSSEL_1 (0x0020) /* ACLK */\r
-#define WDTSSEL_2 (0x0040) /* VLOCLK */\r
-#define WDTSSEL_3 (0x0060) /* BCLK */\r
-#define WDTSSEL__SMCLK (0x0000) /* SMCLK */\r
-#define WDTSSEL__ACLK (0x0020) /* ACLK */\r
-#define WDTSSEL__VLOCLK (0x0040) /* VLOCLK */\r
-#define WDTSSEL__BCLK (0x0060) /* BCLK */\r
-/* WDTCTL[WDTHOLD] Bits */\r
-#define WDTHOLD_OFS ( 7) /* WDTHOLD Offset */\r
-#define WDTHOLD (0x0080) /* Watchdog timer hold */\r
-/* WDTCTL[WDTPW] Bits */\r
-#define WDTPW_OFS ( 8) /* WDTPW Offset */\r
-#define WDTPW_M (0xff00) /* Watchdog timer password */\r
+/******************************************************************************\r
+* SYSTICK Bits\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+* Timer32 Bits\r
+******************************************************************************/\r
+/* TIMER32_CONTROL[ONESHOT] Bits */\r
+#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /**< ONESHOT Bit Offset */\r
+#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /**< Selects one-shot or wrapping counter mode */\r
+/* TIMER32_CONTROL[SIZE] Bits */\r
+#define TIMER32_CONTROL_SIZE_OFS ( 1) /**< SIZE Bit Offset */\r
+#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /**< Selects 16 or 32 bit counter operation */\r
+/* TIMER32_CONTROL[PRESCALE] Bits */\r
+#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /**< PRESCALE Bit Offset */\r
+#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /**< PRESCALE Bit Mask */\r
+#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /**< PRESCALE Bit 0 */\r
+#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /**< PRESCALE Bit 1 */\r
+#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /**< 0 stages of prescale, clock is divided by 1 */\r
+#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /**< 4 stages of prescale, clock is divided by 16 */\r
+#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /**< 8 stages of prescale, clock is divided by 256 */\r
+/* TIMER32_CONTROL[IE] Bits */\r
+#define TIMER32_CONTROL_IE_OFS ( 5) /**< IE Bit Offset */\r
+#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /**< Interrupt enable bit */\r
+/* TIMER32_CONTROL[MODE] Bits */\r
+#define TIMER32_CONTROL_MODE_OFS ( 6) /**< MODE Bit Offset */\r
+#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /**< Mode bit */\r
+/* TIMER32_CONTROL[ENABLE] Bits */\r
+#define TIMER32_CONTROL_ENABLE_OFS ( 7) /**< ENABLE Bit Offset */\r
+#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080)\r
+/* TIMER32_RIS[RAW_IFG] Bits */\r
+#define TIMER32_RIS_RAW_IFG_OFS ( 0) /**< RAW_IFG Bit Offset */\r
+#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /**< Raw interrupt status */\r
+/* TIMER32_MIS[IFG] Bits */\r
+#define TIMER32_MIS_IFG_OFS ( 0) /**< IFG Bit Offset */\r
+#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /**< Enabled interrupt status */\r
+\r
+\r
+\r
+/******************************************************************************\r
+* Timer_A Bits\r
+******************************************************************************/\r
+/* TIMER_A_CTL[IFG] Bits */\r
+#define TIMER_A_CTL_IFG_OFS ( 0) /**< TAIFG Bit Offset */\r
+#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /**< TimerA interrupt flag */\r
+/* TIMER_A_CTL[IE] Bits */\r
+#define TIMER_A_CTL_IE_OFS ( 1) /**< TAIE Bit Offset */\r
+#define TIMER_A_CTL_IE ((uint16_t)0x0002) /**< TimerA interrupt enable */\r
+/* TIMER_A_CTL[CLR] Bits */\r
+#define TIMER_A_CTL_CLR_OFS ( 2) /**< TACLR Bit Offset */\r
+#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /**< TimerA clear */\r
+/* TIMER_A_CTL[MC] Bits */\r
+#define TIMER_A_CTL_MC_OFS ( 4) /**< MC Bit Offset */\r
+#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /**< MC Bit Mask */\r
+#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /**< MC Bit 0 */\r
+#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /**< MC Bit 1 */\r
+#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /**< Stop mode: Timer is halted */\r
+#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /**< Up mode: Timer counts up to TAxCCR0 */\r
+#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /**< Continuous mode: Timer counts up to 0FFFFh */\r
+#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /**< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
+#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /**< Stop mode: Timer is halted */\r
+#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /**< Up mode: Timer counts up to TAxCCR0 */\r
+#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /**< Continuous mode: Timer counts up to 0FFFFh */\r
+#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /**< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
+/* TIMER_A_CTL[ID] Bits */\r
+#define TIMER_A_CTL_ID_OFS ( 6) /**< ID Bit Offset */\r
+#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /**< ID Bit Mask */\r
+#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /**< ID Bit 0 */\r
+#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /**< ID Bit 1 */\r
+#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /**< /1 */\r
+#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /**< /2 */\r
+#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /**< /4 */\r
+#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /**< /8 */\r
+#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /**< /1 */\r
+#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /**< /2 */\r
+#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /**< /4 */\r
+#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /**< /8 */\r
+/* TIMER_A_CTL[SSEL] Bits */\r
+#define TIMER_A_CTL_SSEL_OFS ( 8) /**< TASSEL Bit Offset */\r
+#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /**< TASSEL Bit Mask */\r
+#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /**< SSEL Bit 0 */\r
+#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /**< SSEL Bit 1 */\r
+#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /**< TAxCLK */\r
+#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /**< ACLK */\r
+#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /**< SMCLK */\r
+#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /**< INCLK */\r
+#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /**< TAxCLK */\r
+#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /**< ACLK */\r
+#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /**< SMCLK */\r
+#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /**< INCLK */\r
+/* TIMER_A_CCTLN[CCIFG] Bits */\r
+#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /**< CCIFG Bit Offset */\r
+#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /**< Capture/compare interrupt flag */\r
+/* TIMER_A_CCTLN[COV] Bits */\r
+#define TIMER_A_CCTLN_COV_OFS ( 1) /**< COV Bit Offset */\r
+#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /**< Capture overflow */\r
+/* TIMER_A_CCTLN[OUT] Bits */\r
+#define TIMER_A_CCTLN_OUT_OFS ( 2) /**< OUT Bit Offset */\r
+#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /**< Output */\r
+/* TIMER_A_CCTLN[CCI] Bits */\r
+#define TIMER_A_CCTLN_CCI_OFS ( 3) /**< CCI Bit Offset */\r
+#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /**< Capture/compare input */\r
+/* TIMER_A_CCTLN[CCIE] Bits */\r
+#define TIMER_A_CCTLN_CCIE_OFS ( 4) /**< CCIE Bit Offset */\r
+#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /**< Capture/compare interrupt enable */\r
+/* TIMER_A_CCTLN[OUTMOD] Bits */\r
+#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /**< OUTMOD Bit Offset */\r
+#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /**< OUTMOD Bit Mask */\r
+#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /**< OUTMOD Bit 0 */\r
+#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /**< OUTMOD Bit 1 */\r
+#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /**< OUTMOD Bit 2 */\r
+#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /**< OUT bit value */\r
+#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /**< Set */\r
+#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /**< Toggle/reset */\r
+#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /**< Set/reset */\r
+#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /**< Toggle */\r
+#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /**< Reset */\r
+#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /**< Toggle/set */\r
+#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /**< Reset/set */\r
+/* TIMER_A_CCTLN[CAP] Bits */\r
+#define TIMER_A_CCTLN_CAP_OFS ( 8) /**< CAP Bit Offset */\r
+#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /**< Capture mode */\r
+/* TIMER_A_CCTLN[SCCI] Bits */\r
+#define TIMER_A_CCTLN_SCCI_OFS (10) /**< SCCI Bit Offset */\r
+#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /**< Synchronized capture/compare input */\r
+/* TIMER_A_CCTLN[SCS] Bits */\r
+#define TIMER_A_CCTLN_SCS_OFS (11) /**< SCS Bit Offset */\r
+#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /**< Synchronize capture source */\r
+/* TIMER_A_CCTLN[CCIS] Bits */\r
+#define TIMER_A_CCTLN_CCIS_OFS (12) /**< CCIS Bit Offset */\r
+#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /**< CCIS Bit Mask */\r
+#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /**< CCIS Bit 0 */\r
+#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /**< CCIS Bit 1 */\r
+#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /**< CCIxA */\r
+#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /**< CCIxB */\r
+#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /**< GND */\r
+#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /**< VCC */\r
+#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /**< CCIxA */\r
+#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /**< CCIxB */\r
+#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /**< GND */\r
+#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /**< VCC */\r
+/* TIMER_A_CCTLN[CM] Bits */\r
+#define TIMER_A_CCTLN_CM_OFS (14) /**< CM Bit Offset */\r
+#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /**< CM Bit Mask */\r
+#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /**< CM Bit 0 */\r
+#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /**< CM Bit 1 */\r
+#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /**< No capture */\r
+#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /**< Capture on rising edge */\r
+#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /**< Capture on falling edge */\r
+#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /**< Capture on both rising and falling edges */\r
+#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /**< No capture */\r
+#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /**< Capture on rising edge */\r
+#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /**< Capture on falling edge */\r
+#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /**< Capture on both rising and falling edges */\r
+/* TIMER_A_EX0[IDEX] Bits */\r
+#define TIMER_A_EX0_IDEX_OFS ( 0) /**< TAIDEX Bit Offset */\r
+#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /**< TAIDEX Bit Mask */\r
+#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /**< IDEX Bit 0 */\r
+#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /**< IDEX Bit 1 */\r
+#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /**< IDEX Bit 2 */\r
+#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /**< Divide by 1 */\r
+#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /**< Divide by 2 */\r
+#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /**< Divide by 3 */\r
+#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /**< Divide by 4 */\r
+#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /**< Divide by 5 */\r
+#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /**< Divide by 6 */\r
+#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /**< Divide by 7 */\r
+#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /**< Divide by 8 */\r
+#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /**< Divide by 1 */\r
+#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /**< Divide by 2 */\r
+#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /**< Divide by 3 */\r
+#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /**< Divide by 4 */\r
+#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /**< Divide by 5 */\r
+#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /**< Divide by 6 */\r
+#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /**< Divide by 7 */\r
+#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /**< Divide by 8 */\r
+\r
+\r
+/******************************************************************************\r
+* TLV Bits\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+* TLV table start and TLV tags *\r
+******************************************************************************/\r
+#define TLV_START_ADDR (TLV_BASE + 0x0004) /* Start Address of the TLV structure */\r
+\r
+#define TLV_TAG_RESERVED1 1\r
+#define TLV_TAG_RESERVED2 2\r
+#define TLV_TAG_CS 3\r
+#define TLV_TAG_FLASHCTL 4\r
+#define TLV_TAG_ADC14 5\r
+#define TLV_TAG_RESERVED6 6\r
+#define TLV_TAG_RESERVED7 7\r
+#define TLV_TAG_REF 8\r
+#define TLV_TAG_RESERVED9 9\r
+#define TLV_TAG_RESERVED10 10\r
+#define TLV_TAG_DEVINFO 11\r
+#define TLV_TAG_DIEREC 12\r
+#define TLV_TAG_RANDNUM 13\r
+#define TLV_TAG_RESERVED14 14\r
+#define TLV_TAG_BSL 15\r
+#define TLV_TAG_END (0x0BD0E11D)\r
+\r
+\r
+/******************************************************************************\r
+* WDT_A Bits\r
+******************************************************************************/\r
+/* WDT_A_CTL[IS] Bits */\r
+#define WDT_A_CTL_IS_OFS ( 0) /**< WDTIS Bit Offset */\r
+#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /**< WDTIS Bit Mask */\r
+#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /**< IS Bit 0 */\r
+#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /**< IS Bit 1 */\r
+#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /**< IS Bit 2 */\r
+#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /**< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */\r
+#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /**< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */\r
+#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /**< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */\r
+#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /**< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */\r
+#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /**< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */\r
+#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /**< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */\r
+#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /**< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */\r
+#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /**< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */\r
+/* WDT_A_CTL[CNTCL] Bits */\r
+#define WDT_A_CTL_CNTCL_OFS ( 3) /**< WDTCNTCL Bit Offset */\r
+#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /**< Watchdog timer counter clear */\r
+/* WDT_A_CTL[TMSEL] Bits */\r
+#define WDT_A_CTL_TMSEL_OFS ( 4) /**< WDTTMSEL Bit Offset */\r
+#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /**< Watchdog timer mode select */\r
+/* WDT_A_CTL[SSEL] Bits */\r
+#define WDT_A_CTL_SSEL_OFS ( 5) /**< WDTSSEL Bit Offset */\r
+#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /**< WDTSSEL Bit Mask */\r
+#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /**< SSEL Bit 0 */\r
+#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /**< SSEL Bit 1 */\r
+#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /**< SMCLK */\r
+#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /**< ACLK */\r
+#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /**< VLOCLK */\r
+#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /**< BCLK */\r
+#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /**< SMCLK */\r
+#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /**< ACLK */\r
+#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /**< VLOCLK */\r
+#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /**< BCLK */\r
+/* WDT_A_CTL[HOLD] Bits */\r
+#define WDT_A_CTL_HOLD_OFS ( 7) /**< WDTHOLD Bit Offset */\r
+#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /**< Watchdog timer hold */\r
+/* WDT_A_CTL[PW] Bits */\r
+#define WDT_A_CTL_PW_OFS ( 8) /**< WDTPW Bit Offset */\r
+#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /**< WDTPW Bit Mask */\r
\r
/* Pre-defined bitfield values */\r
-#define WDTPW (0x5A00) /* WDT Key Value for WDT write access */\r
+#define WDT_A_CTL_PW ((uint16_t)0x5A00) /* WDT Key Value for WDT write access */\r
+\r
\r
-//*****************************************************************************\r
-// BSL\r
-//*****************************************************************************\r
+/******************************************************************************\r
+* BSL *\r
+******************************************************************************/\r
#define BSL_DEFAULT_PARAM (0xFC48FFFF) /* I2C slave address = 0x48, Interface selection = Auto */\r
#define BSL_API_TABLE_ADDR (0x00202000) /* Address of BSL API table */\r
#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR))\r
\r
#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /* Invoke the BSL with paramters */\r
\r
-//*****************************************************************************\r
-// ULP Advisor\r
-//*****************************************************************************\r
-#ifdef __TMS470__\r
+/******************************************************************************\r
+* ULP Advisor *\r
+******************************************************************************/\r
+#ifdef __TI_ARM__\r
#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8})\r
#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8})\r
#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8})\r
#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8})\r
#endif\r
\r
-//*****************************************************************************\r
-// NVIC interrupts\r
-//*****************************************************************************\r
-\r
-// System exceptions\r
-#define FAULT_NMI ( 2) /* NMI fault */\r
-#define FAULT_HARD ( 3) /* Hard fault */\r
-#define FAULT_MPU ( 4) /* MPU fault */\r
-#define FAULT_BUS ( 5) /* Bus fault */\r
-#define FAULT_USAGE ( 6) /* Usage fault */\r
-#define FAULT_SVCALL (11) /* SVCall */\r
-#define FAULT_DEBUG (12) /* Debug monitor */\r
-#define FAULT_PENDSV (14) /* PendSV */\r
-#define FAULT_SYSTICK (15) /* System Tick */\r
-\r
-// External interrupts\r
-#define INT_PSS (16) /* PSS IRQ */\r
-#define INT_CS (17) /* CS IRQ */\r
-#define INT_PCM (18) /* PCM IRQ */\r
-#define INT_WDT_A (19) /* WDT_A IRQ */\r
-#define INT_FPU (20) /* FPU IRQ */\r
-#define INT_FLCTL (21) /* FLCTL IRQ */\r
-#define INT_COMP_E0 (22) /* COMP_E0 IRQ */\r
-#define INT_COMP_E1 (23) /* COMP_E1 IRQ */\r
-#define INT_TA0_0 (24) /* TA0_0 IRQ */\r
-#define INT_TA0_N (25) /* TA0_N IRQ */\r
-#define INT_TA1_0 (26) /* TA1_0 IRQ */\r
-#define INT_TA1_N (27) /* TA1_N IRQ */\r
-#define INT_TA2_0 (28) /* TA2_0 IRQ */\r
-#define INT_TA2_N (29) /* TA2_N IRQ */\r
-#define INT_TA3_0 (30) /* TA3_0 IRQ */\r
-#define INT_TA3_N (31) /* TA3_N IRQ */\r
-#define INT_EUSCIA0 (32) /* EUSCIA0 IRQ */\r
-#define INT_EUSCIA1 (33) /* EUSCIA1 IRQ */\r
-#define INT_EUSCIA2 (34) /* EUSCIA2 IRQ */\r
-#define INT_EUSCIA3 (35) /* EUSCIA3 IRQ */\r
-#define INT_EUSCIB0 (36) /* EUSCIB0 IRQ */\r
-#define INT_EUSCIB1 (37) /* EUSCIB1 IRQ */\r
-#define INT_EUSCIB2 (38) /* EUSCIB2 IRQ */\r
-#define INT_EUSCIB3 (39) /* EUSCIB3 IRQ */\r
-#define INT_ADC14 (40) /* ADC14 IRQ */\r
-#define INT_T32_INT1 (41) /* T32_INT1 IRQ */\r
-#define INT_T32_INT2 (42) /* T32_INT2 IRQ */\r
-#define INT_T32_INTC (43) /* T32_INTC IRQ */\r
-#define INT_AES256 (44) /* AES256 IRQ */\r
-#define INT_RTC_C (45) /* RTC_C IRQ */\r
-#define INT_DMA_ERR (46) /* DMA_ERR IRQ */\r
-#define INT_DMA_INT3 (47) /* DMA_INT3 IRQ */\r
-#define INT_DMA_INT2 (48) /* DMA_INT2 IRQ */\r
-#define INT_DMA_INT1 (49) /* DMA_INT1 IRQ */\r
-#define INT_DMA_INT0 (50) /* DMA_INT0 IRQ */\r
-#define INT_PORT1 (51) /* PORT1 IRQ */\r
-#define INT_PORT2 (52) /* PORT2 IRQ */\r
-#define INT_PORT3 (53) /* PORT3 IRQ */\r
-#define INT_PORT4 (54) /* PORT4 IRQ */\r
-#define INT_PORT5 (55) /* PORT5 IRQ */\r
-#define INT_PORT6 (56) /* PORT6 IRQ */\r
-\r
-// Highest interrupt available\r
-#define NUM_INTERRUPTS (56)\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
\r
-#endif // __MSP432P401R_H__\r
+#endif /* __MSP432P401R_H__ */\r
\r
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