]> git.sur5r.net Git - u-boot/commitdiff
ARM: dts: rockchip: Add gmac support for rk3288-vyasa board
authorJagan Teki <jagannadh.teki@gmail.com>
Wed, 14 Feb 2018 15:56:18 +0000 (21:26 +0530)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tue, 13 Mar 2018 17:12:36 +0000 (18:12 +0100)
Sync gmac dts node from Linux.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
arch/arm/dts/rk3288-vyasa.dts

index f56e10cbada72a9bb65b494469605eca10188646..47fdd9148bfc8b3dc9056cfa3945a1caaa485c4f 100644 (file)
                regulator-boot-on;
                vin-supply = <&dc12_vbat>;
        };
+
+       ext_gmac: external-gmac-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <125000000>;
+               clock-output-names = "ext_gmac";
+       };
 };
 
 &cpu0 {
        cpu0-supply = <&vdd_cpu>;
 };
 
+&gmac {
+       assigned-clocks = <&cru SCLK_MAC>;
+       assigned-clock-parents = <&ext_gmac>;
+       clock_in_out = "input";
+       pinctrl-names = "default";
+       pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+       phy-supply = <&vcc_lan>;
+       phy-mode = "rgmii";
+       snps,reset-active-low;
+       snps,reset-delays-us = <0 10000 1000000>;
+       snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
+       tx_delay = <0x30>;
+       rx_delay = <0x10>;
+       status = "okay";
+};
+
 &gpu {
        mali-supply = <&vdd_gpu>;
        status = "okay";
 };
 
 &pinctrl {
+       pcfg_output_high: pcfg-output-high {
+               output-high;
+       };
+
+       gmac {
+               phy_int: phy-int {
+                       rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+
+               phy_pmeb: phy-pmeb {
+                       rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+
+               phy_rst: phy-rst {
+                       rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
+               };
+       };
+
        pmic {
                pmic_int: pmic-int {
                        rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;