pwm: rockchip: Add a PWM driver for Rockchip SoCs

Add a simple driver which implements the standard PWM uclass interface.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h
new file mode 100644 (file)
index 0000000..08ff945
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pwm.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2016 Google, Inc
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_PWM_H
+#define _ASM_ARCH_PWM_H
+
+struct rk3288_pwm {
+       u32 cnt;
+       u32 period_hpr;
+       u32 duty_lpr;
+       u32 ctrl;
+};
+check_member(rk3288_pwm, ctrl, 0xc);
+
+#define RK_PWM_DISABLE                  (0 << 0)
+#define RK_PWM_ENABLE                   (1 << 0)
+
+#define PWM_ONE_SHOT                    (0 << 1)
+#define PWM_CONTINUOUS                  (1 << 1)
+#define RK_PWM_CAPTURE                  (1 << 2)
+
+#define PWM_DUTY_POSTIVE                (1 << 3)
+#define PWM_DUTY_NEGATIVE               (0 << 3)
+
+#define PWM_INACTIVE_POSTIVE            (1 << 4)
+#define PWM_INACTIVE_NEGATIVE           (0 << 4)
+
+#define PWM_OUTPUT_LEFT                 (0 << 5)
+#define PWM_OUTPUT_CENTER               (1 << 5)
+
+#define PWM_LP_ENABLE                   (1 << 8)
+#define PWM_LP_DISABLE                  (0 << 8)
+
+#define PWM_SEL_SCALE_CLK              (1 << 9)
+#define PWM_SEL_SRC_CLK                        (0 << 9)
+
+#endif

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index bd47159860253ad68a47d0562d03e6668e41ce8d..cd8f3570f06df33ca21c3fb48eed123412037427 100644 (file)
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -8,3 +8,12 @@ config DM_PWM
          spends in the 'high' state, the higher the voltage. The PWM's
          frequency/period can be controlled along with the proportion of that
          time that the signal is high.
+
+config PWM_ROCKCHIP
+       bool "Enable support for the Rockchip PWM"
+       depends on DM_PWM
+       help
+         This PWM is found on RK3288 and other Rockchip SoCs. It supports a
+         programmable period and duty cycle. A 32-bit counter is used.
+         Various options provided in the hardware (such as capture mode and
+         continuous/single-shot) are not supported by the driver.

diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index d1b15e5b11e1c8f0b1ef97172a89ffea2baf09de..b6d8c166048436d666ea6af03c70bfa3d3577623 100644 (file)
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -11,4 +11,5 @@
 #ccflags-y += -DDEBUG
 
 obj-$(CONFIG_DM_PWM) += pwm-uclass.o
+obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
 obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o

diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
new file mode 100644 (file)
index 0000000..2d289a4
--- /dev/null
+++ b/drivers/pwm/rk_pwm.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <pwm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3288.h>
+#include <asm/arch/grf_rk3288.h>
+#include <asm/arch/pwm.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk_pwm_priv {
+       struct rk3288_pwm *regs;
+       struct rk3288_grf *grf;
+};
+
+static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
+                            uint duty_ns)
+{
+       struct rk_pwm_priv *priv = dev_get_priv(dev);
+       struct rk3288_pwm *regs = priv->regs;
+       unsigned long period, duty;
+
+       debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
+       writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
+               PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
+               RK_PWM_DISABLE,
+               &regs->ctrl);
+
+       period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
+       duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
+
+       writel(period, &regs->period_hpr);
+       writel(duty, &regs->duty_lpr);
+       debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
+
+       return 0;
+}
+
+static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+       struct rk_pwm_priv *priv = dev_get_priv(dev);
+       struct rk3288_pwm *regs = priv->regs;
+
+       debug("%s: Enable '%s'\n", __func__, dev->name);
+       clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
+
+       return 0;
+}
+
+static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
+{
+       struct rk_pwm_priv *priv = dev_get_priv(dev);
+       struct regmap *map;
+
+       priv->regs = (struct rk3288_pwm *)dev_get_addr(dev);
+       map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
+       if (IS_ERR(map))
+               return PTR_ERR(map);
+       priv->grf = regmap_get_range(map, 0);
+
+       return 0;
+}
+
+static int rk_pwm_probe(struct udevice *dev)
+{
+       struct rk_pwm_priv *priv = dev_get_priv(dev);
+
+       rk_setreg(&priv->grf->soc_con2, 1 << 0);
+
+       return 0;
+}
+
+static const struct pwm_ops rk_pwm_ops = {
+       .set_config     = rk_pwm_set_config,
+       .set_enable     = rk_pwm_set_enable,
+};
+
+static const struct udevice_id rk_pwm_ids[] = {
+       { .compatible = "rockchip,rk3288-pwm" },
+       { }
+};
+
+U_BOOT_DRIVER(rk_pwm) = {
+       .name   = "rk_pwm",
+       .id     = UCLASS_PWM,
+       .of_match = rk_pwm_ids,
+       .ops    = &rk_pwm_ops,
+       .ofdata_to_platdata     = rk_pwm_ofdata_to_platdata,
+       .probe          = rk_pwm_probe,
+       .priv_auto_alloc_size   = sizeof(struct rk_pwm_priv),
+};