]> git.sur5r.net Git - u-boot/commitdiff
armv7: Add workaround for USB erratum A-009007
authorRan Wang <ran.wang_1@nxp.com>
Mon, 4 Sep 2017 10:46:55 +0000 (18:46 +0800)
committerYork Sun <york.sun@nxp.com>
Mon, 11 Sep 2017 15:01:07 +0000 (08:01 -0700)
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv7/ls102xa/Kconfig
arch/arm/cpu/armv7/ls102xa/soc.c
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

index a84cda859223dff2315cfe44921c702c417910fe..20e2b1a50abf77b614a8c80fbff1297125e5a2b7 100644 (file)
@@ -3,6 +3,7 @@ config ARCH_LS1021A
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A008407
        select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
        select SYS_FSL_ERRATUM_A009008
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009798
@@ -66,6 +67,11 @@ config SYS_FSL_ERRATUM_A008997
        help
          Workaround for USB PHY erratum A008997
 
+config SYS_FSL_ERRATUM_A009007
+       bool
+       help
+         Workaround for USB PHY erratum A009007
+
 config SYS_FSL_ERRATUM_A009008
        bool
        help
index 07b525d7a3567c775e553dff4d498400dc15d8e8..e10037d71181c04a55f0972458186a4fa7da7feb 100644 (file)
@@ -92,6 +92,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+       void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
 
 void s_init(void)
 {
@@ -184,6 +195,7 @@ int arch_soc_init(void)
        erratum_a009008();
        erratum_a009798();
        erratum_a008997();
+       erratum_a009007();
 
        return 0;
 }
index 25e65cbd26ff9336ee7286785f90a65807bf77d1..fe0bbb9d93d81efb1865be9dad799d0f1b500490 100644 (file)
@@ -182,6 +182,13 @@ struct ccsr_gur {
 #define SCFG_USB_PCSTXSWINGFULL_MASK   0x0000FE00
 #define SCFG_USB_PCSTXSWINGFULL_VAL            0x00008E00
 
+#define USB_PHY_BASE                   0x08510000
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
+#define USB_PHY_RX_EQ_VAL_1            0x0000
+#define USB_PHY_RX_EQ_VAL_2            0x8000
+#define USB_PHY_RX_EQ_VAL_3            0x8004
+#define USB_PHY_RX_EQ_VAL_4            0x800C
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
        u32 dpslpcr;