spi: mxc_spi: Set master mode for all channels

The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).

Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.

Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 249d15a5053ad0cbd7b48033c2c5c7c5b4c0c44c..a71cc13e2ab498d0ea615d4dad98641786a33165 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -230,6 +230,7 @@
 #define MXC_CSPICTRL_EN                (1 << 0)
 #define MXC_CSPICTRL_MODE      (1 << 1)
 #define MXC_CSPICTRL_XCH       (1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
 #define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 12)
 #define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0xfff) << 20)
 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index eaa7439486a1f46ae78e7444f3df0985f9f79440..d79ab2f13fee81b02348565f9b5498482156d12b 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -346,6 +346,7 @@ struct cspi_regs {
 #define MXC_CSPICTRL_EN                (1 << 0)
 #define MXC_CSPICTRL_MODE      (1 << 1)
 #define MXC_CSPICTRL_XCH       (1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
 #define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 12)
 #define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0xfff) << 20)
 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 4c19e0bf18b65cdb08faab5141c79be759080dea..20419e6bc6779fcad35b2abb562e1114a7e184ba 100644 (file)
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -137,11 +137,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
                return -1;
        }
 
-       /* Reset spi */
-       reg_write(&regs->ctrl, 0);
-       reg_write(&regs->ctrl, MXC_CSPICTRL_EN);
-
-       reg_ctrl = reg_read(&regs->ctrl);
+       /*
+        * Reset SPI and set all CSs to master mode, if toggling
+        * between slave and master mode we might see a glitch
+        * on the clock line
+        */
+       reg_ctrl = MXC_CSPICTRL_MODE_MASK;
+       reg_write(&regs->ctrl, reg_ctrl);
+       reg_ctrl |=  MXC_CSPICTRL_EN;
+       reg_write(&regs->ctrl, reg_ctrl);
 
        /*
         * The following computation is taken directly from Freescale's code.
@@ -174,9 +178,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
        reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
                MXC_CSPICTRL_POSTDIV(post_div);
 
-       /* always set to master mode */
-       reg_ctrl |= 1 << (cs + 4);
-
        /* We need to disable SPI before changing registers */
        reg_ctrl &= ~MXC_CSPICTRL_EN;