]> git.sur5r.net Git - u-boot/commitdiff
ARM: mvebu: Add SoC IDs for Marvell's integrated CPUs
authorChris Packham <judge.packham@gmail.com>
Mon, 4 Sep 2017 05:38:31 +0000 (17:38 +1200)
committerStefan Roese <sr@denx.de>
Tue, 26 Sep 2017 04:51:43 +0000 (06:51 +0200)
These SoCs are network packet processors (switch chips) with integrated
ARMv7 cores. They share a great deal of commonality with the Armada-XP
CPUs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
arch/arm/mach-mvebu/cpu.c
arch/arm/mach-mvebu/include/mach/cpu.h
arch/arm/mach-mvebu/include/mach/soc.h

index 14457317ce7660c1dfda7ad05b8fb1a6322bd2ca..f7f83bfa3655975b65280d4dcb8cfededef4441d 100644 (file)
@@ -62,6 +62,11 @@ int mvebu_soc_family(void)
        case SOC_88F6820_ID:
        case SOC_88F6828_ID:
                return MVEBU_SOC_A38X;
+
+       case SOC_98DX3236_ID:
+       case SOC_98DX3336_ID:
+       case SOC_98DX4251_ID:
+               return MVEBU_SOC_MSYS;
        }
 
        return MVEBU_SOC_UNKNOWN;
@@ -208,6 +213,15 @@ int print_cpuinfo(void)
        case SOC_88F6828_ID:
                puts("MV88F6828-");
                break;
+       case SOC_98DX3236_ID:
+               puts("98DX3236-");
+               break;
+       case SOC_98DX3336_ID:
+               puts("98DX3336-");
+               break;
+       case SOC_98DX4251_ID:
+               puts("98DX4251-");
+               break;
        default:
                puts("Unknown-");
                break;
index d241eea9568d87ce2acfc80501d7c1ef75963027..b67b77ae0df424266049a5f49dc138d28f13a714 100644 (file)
@@ -65,6 +65,7 @@ enum {
        MVEBU_SOC_AXP,
        MVEBU_SOC_A375,
        MVEBU_SOC_A38X,
+       MVEBU_SOC_MSYS,
        MVEBU_SOC_UNKNOWN,
 };
 
index 0900e4008c12ec3489c0b5357c43ada791cce711..cdd64fb285271031cb1af6dd1d6a9f3dcbdce1cf 100644 (file)
@@ -18,6 +18,9 @@
 #define SOC_88F6810_ID         0x6810
 #define SOC_88F6820_ID         0x6820
 #define SOC_88F6828_ID         0x6828
+#define SOC_98DX3236_ID                0xf410
+#define SOC_98DX3336_ID                0xf400
+#define SOC_98DX4251_ID                0xfc00
 
 /* A375 revisions */
 #define MV_88F67XX_A0_ID       0x3