LIB = $(obj)lib$(BOARD).o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y += spl_minimal.o tlb.o law.o
+
+else
+
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
+endif
+
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+void sdram_init(void)
+{
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 ddr_ratio;
+ unsigned long ddr_freq_mhz;
+
+ ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+ ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+ ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
+
+ /* mask off E bit */
+ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
+
+ __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+
+ if (ddr_freq_mhz < 700) {
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
+ } else {
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
+ }
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+
+ /* P1014 and it's derivatives support max 16bit DDR width */
+ if (svr == SVR_P1014) {
+ __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
+ __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
+ /* For CS0_BNDS we divide the start and end address by 2, so we can just
+ * shift the entire register to achieve the desired result and the mask
+ * the value so we don't write reserved fields */
+ __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
+ }
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+ set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* Initialize the DDR3 */
+ sdram_init();
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
/* TLB 1 */
/* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
+ SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_8K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_SDCARD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 3, BOOKE_PAGESZ_16M, 1),
#endif
-#ifdef CONFIG_PCI
+#ifndef CONFIG_PCI
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1)
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
-#ifdef CONFIG_NAND /* NAND Boot */
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
-#else
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#endif /* CONFIG_NAND_SPL */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
+#define CONFIG_SPL_RELOC_STACK 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* High Level Configuration Options */
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* Don't relocate CCSRBAR while in NAND_SPL */
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
* IFC Definitions
*/
/* NOR Flash on IFC */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
#define CONFIG_SYS_FLASH_BASE 0xee000000
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#endif
-/* NAND boot: 8K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x2000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffb00000
#define CONFIG_SYS_CS3_FTIM3 0x0
#endif /* CONFIG_SDCARD */
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
- defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
* SPI interface will not be available in case of NAND boot SPI CS0 will be
* used for SLIC
*/
-#if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT)
+#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
/* eSPI - Enhanced SPI */
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_NAND_U_BOOT)
+#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE
+#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#else
+#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2011 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-NAND_SPL := y
-CONFIG_SYS_TEXT_BASE_SPL := 0xff800000
-PAD_TO := 0xff802000
-
-include $(TOPDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o ticks.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
-
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)cache.c:
- @rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
- @rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
- @rm -f $(obj)spl_minimal.c
- ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
- @rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
- @rm -f $(obj)law.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_ifc.c:
- @rm -f $(obj)nand_boot_fsl_ifc.c
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \
- $(obj)nand_boot_fsl_ifc.c
-
-$(obj)ns16550.c:
- @rm -f $(obj)ns16550.c
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
-
-$(obj)fixed_ivor.S:
- @rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
-
-$(obj)start.S: $(obj)fixed_ivor.S
- @rm -f $(obj)start.S
- ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
-
-$(obj)ticks.S:
- @rm -f $(obj)ticks.S
- ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
-
-$(obj)tlb.c:
- @rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
-
-$(obj)tlb_table.c:
- @rm -f $(obj)tlb_table.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-#include <common.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long ddr_freq_mhz;
-
-void sdram_init(void)
-{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
- /* mask off E bit */
- u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
-
- __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
- if (ddr_freq_mhz < 700) {
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
- } else {
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
- }
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
- /* P1014 and it's derivatives support max 16bit DDR width */
- if (svr == SVR_P1014) {
- __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
- __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
- /* For CS0_BNDS we divide the start and end address by 2, so we can just
- * shift the entire register to achieve the desired result and the mask
- * the value so we don't write reserved fields */
- __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
- }
-
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
- set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, ddr_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
- ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* Initialize the DDR3 */
- sdram_init();
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-/*
- * NAND boot for FSL Integrated Flash Controller, NAND Flash Control Machine
- *
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/fsl_ifc.h>
-#include <linux/mtd/nand.h>
-
-static inline int is_blank(uchar *addr, int page_size)
-{
- int i;
-
- for (i = 0; i < page_size; i++) {
- if (__raw_readb(&addr[i]) != 0xff)
- return 0;
- }
-
- /*
- * For the SPL, don't worry about uncorrectable errors
- * where the main area is all FFs but shouldn't be.
- */
- return 1;
-}
-
-/* returns nonzero if entire page is blank */
-static inline int check_read_ecc(uchar *buf, u32 *eccstat,
- unsigned int bufnum, int page_size)
-{
- u32 reg = eccstat[bufnum / 4];
- int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
-
- if (errors == 15) { /* uncorrectable */
- /* Blank pages fail hw ECC checks */
- if (is_blank(buf, page_size))
- return 1;
-
- puts("ecc error\n");
- for (;;)
- ;
- }
-
- return 0;
-}
-
-static inline void nand_wait(uchar *buf, int bufnum, int page_size)
-{
- struct fsl_ifc *ifc = IFC_BASE_ADDR;
- u32 status;
- u32 eccstat[4];
- int bufperpage = page_size / 512;
- int bufnum_end, i;
-
- bufnum *= bufperpage;
- bufnum_end = bufnum + bufperpage - 1;
-
- do {
- status = in_be32(&ifc->ifc_nand.nand_evter_stat);
- } while (!(status & IFC_NAND_EVTER_STAT_OPC));
-
- if (status & IFC_NAND_EVTER_STAT_FTOER) {
- puts("flash time out error\n");
- for (;;)
- ;
- }
-
- for (i = bufnum / 4; i <= bufnum_end / 4; i++)
- eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
-
- for (i = bufnum; i <= bufnum_end; i++) {
- if (check_read_ecc(buf, eccstat, i, page_size))
- break;
- }
-
- out_be32(&ifc->ifc_nand.nand_evter_stat, status);
-}
-
-static inline int bad_block(uchar *marker, int port_size)
-{
- if (port_size == 8)
- return __raw_readb(marker) != 0xff;
- else
- return __raw_readw((u16 *)marker) != 0xffff;
-}
-
-static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
-{
- struct fsl_ifc *ifc = IFC_BASE_ADDR;
- uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
- int page_size;
- int port_size;
- int pages_per_blk;
- int blk_size;
- int bad_marker = 0;
- int bufnum_mask, bufnum;
-
- int csor, cspr;
- int pos = 0;
- int j = 0;
-
- int sram_addr;
- int pg_no;
-
- /* Get NAND Flash configuration */
- csor = CONFIG_SYS_NAND_CSOR;
- cspr = CONFIG_SYS_NAND_CSPR;
-
- if (!(csor & CSOR_NAND_ECC_DEC_EN)) {
- /* soft ECC in SPL is unimplemented */
- puts("WARNING: soft ECC not checked in SPL\n");
- } else {
- u32 hwcsor;
-
- /* make sure board is configured with ECC on boot */
- hwcsor = in_be32(&ifc->csor_cs[0].csor);
- if (!(hwcsor & CSOR_NAND_ECC_DEC_EN))
- puts("WARNING: ECC not checked in SPL, "
- "check board cfg\n");
- }
-
- port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
-
- if (csor & CSOR_NAND_PGS_4K) {
- page_size = 4096;
- bufnum_mask = 1;
- } else if (csor & CSOR_NAND_PGS_2K) {
- page_size = 2048;
- bufnum_mask = 3;
- } else {
- page_size = 512;
- bufnum_mask = 15;
-
- if (port_size == 8)
- bad_marker = 5;
- }
-
- pages_per_blk =
- 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
-
- blk_size = pages_per_blk * page_size;
-
- /* Open Full SRAM mapping for spare are access */
- out_be32(&ifc->ifc_nand.ncfgr, 0x0);
-
- /* Clear Boot events */
- out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
-
- /* Program FIR/FCR for Large/Small page */
- if (page_size > 512) {
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
- (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
- (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
- out_be32(&ifc->ifc_nand.nand_fcr0,
- (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
- (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
- } else {
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
- (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
- out_be32(&ifc->ifc_nand.nand_fcr0,
- NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
- }
-
- /* Program FBCR = 0 for full page read */
- out_be32(&ifc->ifc_nand.nand_fbcr, 0);
-
- /* Read and copy u-boot on SDRAM from NAND device, In parallel
- * check for Bad block if found skip it and read continue to
- * next Block
- */
- while (pos < uboot_size) {
- int i = 0;
- do {
- pg_no = offs / page_size;
- bufnum = pg_no & bufnum_mask;
- sram_addr = bufnum * page_size * 2;
-
- out_be32(&ifc->ifc_nand.row0, pg_no);
- out_be32(&ifc->ifc_nand.col0, 0);
- /* start read */
- out_be32(&ifc->ifc_nand.nandseq_strt,
- IFC_NAND_SEQ_STRT_FIR_STRT);
-
- /* wait for read to complete */
- nand_wait(&buf[sram_addr], bufnum, page_size);
-
- /*
- * If either of the first two pages are marked bad,
- * continue to the next block.
- */
- if (i++ < 2 &&
- bad_block(&buf[sram_addr + page_size + bad_marker],
- port_size)) {
- puts("skipping\n");
- offs = (offs + blk_size) & ~(blk_size - 1);
- pos &= ~(blk_size - 1);
- break;
- }
-
- for (j = 0; j < page_size; j++)
- dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
-
- pos += page_size;
- offs += page_size;
- } while ((offs & (blk_size - 1)) && (pos < uboot_size));
- }
-}
-
-/*
- * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
- * configured and available since this code loads the main U-boot image
- * from NAND into SDRAM and starts from there.
- */
-void nand_boot(void)
-{
- __attribute__((noreturn)) void (*uboot)(void);
-
- /*
- * Load U-Boot image from NAND into RAM
- */
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
-
-#ifdef CONFIG_NAND_ENV_DST
- nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
-
-#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
-#endif
-#endif
-
- /*
- * Jump to U-Boot image
- */
- /*
- * Clean d-cache and invalidate i-cache, to
- * make sure that no stale data is executed.
- */
- flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
- uboot();
-}
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