#define CONTROL_PADCONF_STRBEN_DLY1 0x0224
#define CONTROL_PADCONF_SYS_BOOT8 0x0226
+/* AM/DM37xx specific */
+#define CONTROL_PADCONF_GPIO127 0x0A54
+#define CONTROL_PADCONF_GPIO126 0x0A56
+#define CONTROL_PADCONF_GPIO128 0x0A58
+#define CONTROL_PADCONF_GPIO129 0x0A5A
+
#define MUX_VAL(OFFSET,VALUE)\
writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
void set_muxconf_regs(void)
{
MUX_PANDORA();
+ if (get_cpu_family() == CPU_OMAP36XX) {
+ MUX_PANDORA_3730();
+ }
}
#ifdef CONFIG_GENERIC_MMC
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+#define MUX_PANDORA_3730() \
+ MUX_VAL(CP(GPIO126), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
+ MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
+ MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /*GPIO_128 - LED_MMC1*/\
+ MUX_VAL(CP(GPIO129), (IDIS | PTD | DIS | M4)) /*GPIO_129 - LED_MMC2*/
+
#endif