]> git.sur5r.net Git - u-boot/commitdiff
Kconfig: Drop CONFIG_CMD_DS4510
authorSimon Glass <sjg@chromium.org>
Wed, 17 May 2017 09:25:01 +0000 (03:25 -0600)
committerTom Rini <trini@konsulko.com>
Mon, 22 May 2017 12:37:07 +0000 (08:37 -0400)
This option enables a command in the driver. But the functions defined by
the driver are not called anywhere else in U-Boot. So it does not seem
useful to have this driver without its commands.

Drop this option, move the header file out of the common include/
directory and make all the function static.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
drivers/misc/ds4510.c
drivers/misc/ds4510.h [new file with mode: 0644]
include/configs/xpedite517x.h
include/configs/xpedite537x.h
include/ds4510.h [deleted file]
scripts/config_whitelist.txt

index c08a0bee639e131c000f21655eebc1f3f08594d6..9ffdafc9929d657e097f8e19dedc078ea61bbb60 100644 (file)
@@ -12,7 +12,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <command.h>
-#include <ds4510.h>
+#include "ds4510.h"
 
 /* Default to an address that hopefully won't corrupt other i2c devices */
 #ifndef CONFIG_SYS_I2C_DS4510_ADDR
@@ -35,7 +35,7 @@ enum {
 /*
  * Write to DS4510, taking page boundaries into account
  */
-int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
+static int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
 {
        int wrlen;
        int i = 0;
@@ -64,7 +64,7 @@ int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
 /*
  * General read from DS4510
  */
-int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
+static int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
 {
        return i2c_read(chip, offset, 1, buf, count);
 }
@@ -74,7 +74,7 @@ int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
  * nv = 0 - Writes to SEEPROM registers behave like EEPROM
  * nv = 1 - Writes to SEEPROM registers behave like SRAM
  */
-int ds4510_see_write(uint8_t chip, uint8_t nv)
+static int ds4510_see_write(uint8_t chip, uint8_t nv)
 {
        uint8_t data;
 
@@ -92,7 +92,7 @@ int ds4510_see_write(uint8_t chip, uint8_t nv)
 /*
  * Write de-assertion of reset signal delay
  */
-int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
+static int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
 {
        uint8_t data;
 
@@ -108,7 +108,7 @@ int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
 /*
  * Write pullup characteristics of IO pins
  */
-int ds4510_pullup_write(uint8_t chip, uint8_t val)
+static int ds4510_pullup_write(uint8_t chip, uint8_t val)
 {
        val &= DS4510_IO_MASK;
 
@@ -118,7 +118,7 @@ int ds4510_pullup_write(uint8_t chip, uint8_t val)
 /*
  * Read pullup characteristics of IO pins
  */
-int ds4510_pullup_read(uint8_t chip)
+static int ds4510_pullup_read(uint8_t chip)
 {
        uint8_t val;
 
@@ -131,7 +131,7 @@ int ds4510_pullup_read(uint8_t chip)
 /*
  * Write drive level of IO pins
  */
-int ds4510_gpio_write(uint8_t chip, uint8_t val)
+static int ds4510_gpio_write(uint8_t chip, uint8_t val)
 {
        uint8_t data;
        int i;
@@ -155,7 +155,7 @@ int ds4510_gpio_write(uint8_t chip, uint8_t val)
 /*
  * Read drive level of IO pins
  */
-int ds4510_gpio_read(uint8_t chip)
+static int ds4510_gpio_read(uint8_t chip)
 {
        uint8_t data;
        int val = 0;
@@ -175,7 +175,7 @@ int ds4510_gpio_read(uint8_t chip)
 /*
  * Read physical level of IO pins
  */
-int ds4510_gpio_read_val(uint8_t chip)
+static int ds4510_gpio_read_val(uint8_t chip)
 {
        uint8_t val;
 
@@ -185,7 +185,6 @@ int ds4510_gpio_read_val(uint8_t chip)
        return val & DS4510_IO_MASK;
 }
 
-#ifdef CONFIG_CMD_DS4510
 /*
  * Display DS4510 information
  */
@@ -384,4 +383,3 @@ U_BOOT_CMD(
        "ds4510 sram write addr off cnt\n"
        "       - read/write 'cnt' bytes at SRAM offset 'off'"
 );
-#endif /* CONFIG_CMD_DS4510 */
diff --git a/drivers/misc/ds4510.h b/drivers/misc/ds4510.h
new file mode 100644 (file)
index 0000000..a6c6c58
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef __DS4510_H_
+#define __DS4510_H_
+
+/* General defines */
+#define DS4510_NUM_IO                          0x04
+#define DS4510_IO_MASK                         ((1 << DS4510_NUM_IO) - 1)
+#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS      20
+
+/* EEPROM from 0x00 - 0x39 */
+#define DS4510_EEPROM                          0x00
+#define DS4510_EEPROM_SIZE                     0x40
+#define DS4510_EEPROM_PAGE_SIZE                        0x08
+#define DS4510_EEPROM_PAGE_OFFSET(x)   ((x) & (DS4510_EEPROM_PAGE_SIZE - 1))
+
+/* SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_SEEPROM                         0xf0
+#define DS4510_SEEPROM_SIZE                    0x08
+
+/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_PULLUP                          0xF0
+#define DS4510_PULLUP_DIS                      0x00
+#define DS4510_PULLUP_EN                       0x01
+#define DS4510_RSTDELAY                                0xF1
+#define DS4510_RSTDELAY_MASK                   0x03
+#define DS4510_RSTDELAY_125                    0x00
+#define DS4510_RSTDELAY_250                    0x01
+#define DS4510_RSTDELAY_500                    0x02
+#define DS4510_RSTDELAY_1000                   0x03
+#define DS4510_IO3                             0xF4
+#define DS4510_IO2                             0xF5
+#define DS4510_IO1                             0xF6
+#define DS4510_IO0                             0xF7
+
+/* Status configuration registers from 0xf8 - 0xf9*/
+#define DS4510_IO_STATUS                       0xF8
+#define DS4510_CFG                             0xF9
+#define DS4510_CFG_READY                       0x80
+#define DS4510_CFG_TRIP_POINT                  0x40
+#define DS4510_CFG_RESET                       0x20
+#define DS4510_CFG_SEE                         0x10
+#define DS4510_CFG_SWRST                       0x08
+
+/* SRAM from 0xfa - 0xff */
+#define DS4510_SRAM                            0xfa
+#define DS4510_SRAM_SIZE                       0x06
+
+#endif /* __DS4510_H_ */
index dae61b11e44502afa1eee2a77bd4d3446c6f32b3..822f70e7ac9d5ef801ded8dc29f2d8801ed45b5a 100644 (file)
@@ -502,7 +502,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Command configuration.
  */
-#define CONFIG_CMD_DS4510
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IRQ
index ce1ff86135c157e3b05c58367f317909888a13bd..a12a3f8347cb406fb495a1e1e0fe1e6e00219064 100644 (file)
@@ -354,7 +354,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 /*
  * Command configuration.
  */
-#define CONFIG_CMD_DS4510
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_JFFS2
diff --git a/include/ds4510.h b/include/ds4510.h
deleted file mode 100644 (file)
index e54db35..0000000
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0
- */
-
-#ifndef __DS4510_H_
-#define __DS4510_H_
-
-/* General defines */
-#define DS4510_NUM_IO                          0x04
-#define DS4510_IO_MASK                         ((1 << DS4510_NUM_IO) - 1)
-#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS      20
-
-/* EEPROM from 0x00 - 0x39 */
-#define DS4510_EEPROM                          0x00
-#define DS4510_EEPROM_SIZE                     0x40
-#define DS4510_EEPROM_PAGE_SIZE                        0x08
-#define DS4510_EEPROM_PAGE_OFFSET(x)   ((x) & (DS4510_EEPROM_PAGE_SIZE - 1))
-
-/* SEEPROM from 0xf0 - 0xf7 */
-#define DS4510_SEEPROM                         0xf0
-#define DS4510_SEEPROM_SIZE                    0x08
-
-/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */
-#define DS4510_PULLUP                          0xF0
-#define DS4510_PULLUP_DIS                      0x00
-#define DS4510_PULLUP_EN                       0x01
-#define DS4510_RSTDELAY                                0xF1
-#define DS4510_RSTDELAY_MASK                   0x03
-#define DS4510_RSTDELAY_125                    0x00
-#define DS4510_RSTDELAY_250                    0x01
-#define DS4510_RSTDELAY_500                    0x02
-#define DS4510_RSTDELAY_1000                   0x03
-#define DS4510_IO3                             0xF4
-#define DS4510_IO2                             0xF5
-#define DS4510_IO1                             0xF6
-#define DS4510_IO0                             0xF7
-
-/* Status configuration registers from 0xf8 - 0xf9*/
-#define DS4510_IO_STATUS                       0xF8
-#define DS4510_CFG                             0xF9
-#define DS4510_CFG_READY                       0x80
-#define DS4510_CFG_TRIP_POINT                  0x40
-#define DS4510_CFG_RESET                       0x20
-#define DS4510_CFG_SEE                         0x10
-#define DS4510_CFG_SWRST                       0x08
-
-/* SRAM from 0xfa - 0xff */
-#define DS4510_SRAM                            0xfa
-#define DS4510_SRAM_SIZE                       0x06
-
-int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count);
-int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count);
-int ds4510_see_write(uint8_t chip, uint8_t nv);
-int ds4510_rstdelay_write(uint8_t chip, uint8_t delay);
-int ds4510_pullup_write(uint8_t chip, uint8_t val);
-int ds4510_pullup_read(uint8_t chip);
-int ds4510_gpio_write(uint8_t chip, uint8_t val);
-int ds4510_gpio_read(uint8_t chip);
-int ds4510_gpio_read_val(uint8_t chip);
-
-#endif /* __DS4510_H_ */
index af253f49743808f595229e6352f32e18fad2793e..f34fd6720638fd5f901d9e9d863cb92ac669dbab 100644 (file)
@@ -383,7 +383,6 @@ CONFIG_CM922T_XA10
 CONFIG_CMDLINE_EDITING
 CONFIG_CMDLINE_PS_SUPPORT
 CONFIG_CMDLINE_TAG
-CONFIG_CMD_DS4510
 CONFIG_CMD_DTT
 CONFIG_CMD_ECCTEST
 CONFIG_CMD_EECONFIG