Guennadi Liakhovetski <g.liakhovetski@gmx.de>
mx31ads i.MX31
+ SMDK6400 S3C6400
David Müller <d.mueller@elsoft.ch>
imx31_litekit \
imx31_phycore \
mx31ads \
+ smdk6400 \
"
#########################################################################
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
+#########################################################################
+## ARM1176 Systems
+#########################################################################
+smdk6400_noUSB_config \
+smdk6400_config : unconfig
+ @mkdir -p $(obj)include $(obj)board/samsung/smdk6400
+ @mkdir -p $(obj)nand_spl/board/samsung/smdk6400
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then \
+ echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
+ $(MKCONFIG) $(@:_config=) arm arm1176 smdk6400 samsung s3c64xx; \
+ else \
+ echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
+ $(MKCONFIG) $(@:_noUSB_config=) arm arm1176 smdk6400 samsung s3c64xx; \
+ fi
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
#========================================================================
# i386
#========================================================================
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := smdk6400.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+
+# On SMDK6400 we use the 64 MB SDRAM bank at
+#
+# 0x50000000 to 0x58000000
+#
+# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
+#
+# we load ourselves to 0x57e00000 without MMU
+# with MMU, load address is changed to 0xc7e00000
+#
+# download area is 0x5000c000
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef CONFIG_NAND_SPL
+TEXT_BASE = $(RAM_TEXT)
+else
+TEXT_BASE = 0
+endif
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+#include <s3c6400.h>
+
+#ifdef CONFIG_SERIAL1
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
+#elif defined(CONFIG_SERIAL2)
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
+#else
+#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
+#endif
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r12, lr
+
+ /* LED on only #8 */
+ ldr r0, =ELFIN_GPIO_BASE
+ ldr r1, =0x55540000
+ str r1, [r0, #GPNCON_OFFSET]
+
+ ldr r1, =0x55555555
+ str r1, [r0, #GPNPUD_OFFSET]
+
+ ldr r1, =0xf000
+ str r1, [r0, #GPNDAT_OFFSET]
+
+ /* Disable Watchdog */
+ ldr r0, =0x7e000000 @0x7e004000
+ orr r0, r0, #0x4000
+ mov r1, #0
+ str r1, [r0]
+
+ /* External interrupt pending clear */
+ ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
+ ldr r1, [r0]
+ str r1, [r0]
+
+ ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
+ ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
+
+ /* Disable all interrupts (VIC0 and VIC1) */
+ mvn r3, #0x0
+ str r3, [r0, #oINTMSK]
+ str r3, [r1, #oINTMSK]
+
+ /* Set all interrupts as IRQ */
+ mov r3, #0x0
+ str r3, [r0, #oINTMOD]
+ str r3, [r1, #oINTMOD]
+
+ /* Pending Interrupt Clear */
+ mov r3, #0x0
+ str r3, [r0, #oVECTADDR]
+ str r3, [r1, #oVECTADDR]
+
+ /* init system clock */
+ bl system_clock_init
+
+#ifndef CONFIG_NAND_SPL
+ /* for UART */
+ bl uart_asm_init
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+ /* simple init for NAND */
+ bl nand_asm_init
+#endif
+
+ bl mem_ctrl_asm_init
+
+/* Wakeup support. Don't know if it's going to be used, untested. */
+ ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
+ ldr r1, [r0]
+ bic r1, r1, #0xfffffff7
+ cmp r1, #0x8
+ beq wakeup_reset
+
+1:
+ mov lr, r12
+ mov pc, lr
+
+wakeup_reset:
+
+ /* Clear wakeup status register */
+ ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
+ ldr r1, [r0]
+ str r1, [r0]
+
+ /* LED test */
+ ldr r0, =ELFIN_GPIO_BASE
+ ldr r1, =0x3000
+ str r1, [r0, #GPNDAT_OFFSET]
+
+ /* Load return address and jump to kernel */
+ ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
+ /* r1 = physical address of s3c6400_cpu_resume function */
+ ldr r1, [r0]
+ /* Jump to kernel (sleep-s3c6400.S) */
+ mov pc, r1
+ nop
+ nop
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+ ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
+
+#ifdef CONFIG_SYNC_MODE
+ ldr r1, [r0, #OTHERS_OFFSET]
+ mov r2, #0x40
+ orr r1, r1, r2
+ str r1, [r0, #OTHERS_OFFSET]
+
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ ldr r2, =0x80
+ orr r1, r1, r2
+ str r1, [r0, #OTHERS_OFFSET]
+
+check_syncack:
+ ldr r1, [r0, #OTHERS_OFFSET]
+ ldr r2, =0xf00
+ and r1, r1, r2
+ cmp r1, #0xf00
+ bne check_syncack
+#else /* ASYNC Mode */
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /*
+ * This was unconditional in original Samsung sources, but it doesn't
+ * seem to make much sense on S3C6400.
+ */
+#ifndef CONFIG_S3C6400
+ ldr r1, [r0, #OTHERS_OFFSET]
+ bic r1, r1, #0xC0
+ orr r1, r1, #0x40
+ str r1, [r0, #OTHERS_OFFSET]
+
+wait_for_async:
+ ldr r1, [r0, #OTHERS_OFFSET]
+ and r1, r1, #0xf00
+ cmp r1, #0x0
+ bne wait_for_async
+#endif
+
+ ldr r1, [r0, #OTHERS_OFFSET]
+ bic r1, r1, #0x40
+ str r1, [r0, #OTHERS_OFFSET]
+#endif
+
+ mov r1, #0xff00
+ orr r1, r1, #0xff
+ str r1, [r0, #APLL_LOCK_OFFSET]
+ str r1, [r0, #MPLL_LOCK_OFFSET]
+
+ /* Set Clock Divider */
+ ldr r1, [r0, #CLK_DIV0_OFFSET]
+ bic r1, r1, #0x30000
+ bic r1, r1, #0xff00
+ bic r1, r1, #0xff
+ ldr r2, =CLK_DIV_VAL
+ orr r1, r1, r2
+ str r1, [r0, #CLK_DIV0_OFFSET]
+
+ ldr r1, =APLL_VAL
+ str r1, [r0, #APLL_CON_OFFSET]
+ ldr r1, =MPLL_VAL
+ str r1, [r0, #MPLL_CON_OFFSET]
+
+ /* FOUT of EPLL is 96MHz */
+ ldr r1, =0x200203
+ str r1, [r0, #EPLL_CON0_OFFSET]
+ ldr r1, =0x0
+ str r1, [r0, #EPLL_CON1_OFFSET]
+
+ /* APLL, MPLL, EPLL select to Fout */
+ ldr r1, [r0, #CLK_SRC_OFFSET]
+ orr r1, r1, #0x7
+ str r1, [r0, #CLK_SRC_OFFSET]
+
+ /* wait at least 200us to stablize all clock */
+ mov r1, #0x10000
+1: subs r1, r1, #1
+ bne 1b
+
+ /* Synchronization for VIC port */
+#if defined(CONFIG_SYNC_MODE)
+ ldr r1, [r0, #OTHERS_OFFSET]
+ orr r1, r1, #0x20
+ str r1, [r0, #OTHERS_OFFSET]
+#elif !defined(CONFIG_S3C6400)
+ /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
+ ldr r1, [r0, #OTHERS_OFFSET]
+ bic r1, r1, #0x20
+ str r1, [r0, #OTHERS_OFFSET]
+#endif
+ mov pc, lr
+
+
+#ifndef CONFIG_NAND_SPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ /* set GPIO to enable UART */
+ ldr r0, =ELFIN_GPIO_BASE
+ ldr r1, =0x220022
+ str r1, [r0, #GPACON_OFFSET]
+ mov pc, lr
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+/*
+ * NAND Interface init for SMDK6400
+ */
+nand_asm_init:
+ ldr r0, =ELFIN_NAND_BASE
+ ldr r1, [r0, #NFCONF_OFFSET]
+ orr r1, r1, #0x70
+ orr r1, r1, #0x7700
+ str r1, [r0, #NFCONF_OFFSET]
+
+ ldr r1, [r0, #NFCONT_OFFSET]
+ orr r1, r1, #0x07
+ str r1, [r0, #NFCONT_OFFSET]
+
+ mov pc, lr
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+/*
+ * MMU Table for SMDK6400
+ */
+
+ /* form a first-level section entry */
+.macro FL_SECTION_ENTRY base,ap,d,c,b
+ .word (\base << 20) | (\ap << 10) | \
+ (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
+.endm
+
+.section .mmudata, "a"
+ .align 14
+ /* the following alignment creates the mmu table at address 0x4000. */
+ .globl mmu_table
+mmu_table:
+ .set __base, 0
+ /* 1:1 mapping for debugging */
+ .rept 0xA00
+ FL_SECTION_ENTRY __base, 3, 0, 0, 0
+ .set __base, __base + 1
+ .endr
+
+ /* access is not allowed. */
+ .rept 0xC00 - 0xA00
+ .word 0x00000000
+ .endr
+
+ /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
+ .set __base, 0x500
+ .rept 0xC80 - 0xC00
+ FL_SECTION_ENTRY __base, 3, 0, 1, 1
+ .set __base, __base + 1
+ .endr
+
+ /* access is not allowed. */
+ .rept 0x1000 - 0xc80
+ .word 0x00000000
+ .endr
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c6400.h>
+
+/* ------------------------------------------------------------------------- */
+#define CS8900_Tacs 0x0 /* 0clk address set-up */
+#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */
+#define CS8900_Tacc 0xE /* 14clk access cycle */
+#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */
+#define CS8900_Tah 0x4 /* 4clk address holding time */
+#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */
+#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */
+
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b"
+ : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+static void cs8900_pre_init(void)
+{
+ SROM_BW_REG &= ~(0xf << 4);
+ SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
+ SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
+ (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
+ (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
+}
+
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ cs8900_pre_init();
+
+ /* NOR-flash in SROM0 */
+
+ /* Enable WAIT */
+ SROM_BW_REG |= 4 | 8 | 1;
+
+ gd->bd->bi_arch_number = MACH_TYPE;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("Board: SMDK6400\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+ulong virt_to_phy_smdk6400(ulong addr)
+{
+ if ((0xc0000000 <= addr) && (addr < 0xc8000000))
+ return addr - 0xc0000000 + 0x50000000;
+ else
+ printf("do not support this address : %08lx\n", addr);
+
+ return addr;
+}
+#endif
+
+#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+void nand_init(void)
+{
+ nand_probe(CFG_NAND_BASE);
+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
+ print_size(nand_dev_desc[0].totlen, "\n");
+}
+#endif
+
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+ } else
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1176/start.o (.text)
+ cpu/arm1176/s3c64xx/cpu_init.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .mmudata : { *(.mmudata) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */
+#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */
+#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */
+
+#define CFG_SDRAM_BASE 0x50000000
+
+/* input clock of PLL: SMDK6400 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#define CONFIG_MEMORY_UPPER_CODE
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+/*
+ * Architecture magic and machine type
+ */
+#define MACH_TYPE 1270
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 1024 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
+#define CS8900_BASE 0x18800300
+#define CS8900_BUS16 1 /* follow the Linux driver */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#define CONFIG_CMDLINE_EDITING
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NAND
+#if defined(CONFIG_BOOT_ONENAND)
+#define CONFIG_CMD_ONENAND
+#endif
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "SMDK6400 # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE 384 /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE /* memtest works on */
+#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
+
+#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* default load address */
+
+#define CFG_HZ 1000
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */
+
+/**********************************
+ Support Clock Settings
+ **********************************
+ Setting SYNC ASYNC
+ ----------------------------------
+ 667_133_66 X O
+ 533_133_66 O O
+ 400_133_66 X O
+ 400_100_50 O O
+ **********************************/
+
+/*#define CONFIG_CLK_667_133_66*/
+#define CONFIG_CLK_533_133_66
+/*
+#define CONFIG_CLK_400_100_50
+#define CONFIG_CLK_400_133_66
+#define CONFIG_SYNC_MODE
+*/
+
+/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CFG_SDRAM_BASE /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */
+
+#define CFG_FLASH_BASE 0x10000000
+#define CFG_MONITOR_BASE 0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+/* AM29LV160B has 35 sectors, AM29LV800B - 19 */
+#define CFG_MAX_FLASH_SECT 40
+
+#define CONFIG_AMD_LV800
+#define CFG_FLASH_CFI 1 /* Use CFI parameters (needed?) */
+/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_LEGACY
+#define CFG_FLASH_LEGACY_512Kx16
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (5 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (5 * CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/*
+ * SMDK6400 board specific data
+ */
+
+#define CONFIG_IDENT_STRING " for SMDK6400"
+
+/* base address for uboot */
+#define CFG_PHY_UBOOT_BASE (CFG_SDRAM_BASE + 0x07e00000)
+/* total memory available to uboot */
+#define CFG_UBOOT_SIZE (1024 * 1024)
+
+#ifdef CONFIG_ENABLE_MMU
+#define CFG_MAPPED_RAM_BASE 0xc0000000
+#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \
+ "bootm 0xc0018000"
+#else
+#define CFG_MAPPED_RAM_BASE CFG_SDRAM_BASE
+#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \
+ "bootm 0x50018000"
+#endif
+
+/* NAND U-Boot load and start address */
+#define CFG_UBOOT_BASE (CFG_MAPPED_RAM_BASE + 0x07e00000)
+
+#define CFG_ENV_OFFSET 0x0040000
+
+/* NAND configuration */
+#define CFG_MAX_NAND_DEVICE 1
+#define CFG_NAND_BASE 0x70200010
+#define NAND_MAX_CHIPS 1
+#define CFG_S3C_NAND_HWECC
+
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_WP 1
+#define CFG_NAND_YAFFS_WRITE 1 /* support yaffs write */
+#define CFG_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */
+
+#define CFG_NAND_U_BOOT_DST CFG_PHY_UBOOT_BASE /* NUB load-addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* NUB start-addr */
+
+#define CFG_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */
+
+/* NAND chip page size */
+#define CFG_NAND_PAGE_SIZE 2048
+/* NAND chip block size */
+#define CFG_NAND_BLOCK_SIZE (128 * 1024)
+/* NAND chip page per block count */
+#define CFG_NAND_PAGE_COUNT 64
+/* Location of the bad-block label */
+#define CFG_NAND_BAD_BLOCK_POS 0
+/* Extra address cycle for > 128MiB */
+#define CFG_NAND_5_ADDR_CYCLE
+
+/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
+#define CFG_NAND_ECCSIZE CFG_NAND_PAGE_SIZE
+/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
+#define CFG_NAND_ECCBYTES 4
+/* Number of ECC-blocks per NAND page */
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+/* Size of a single OOB region */
+#define CFG_NAND_OOBSIZE 64
+/* Number of ECC bytes per page */
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+/* ECC byte positions */
+#define CFG_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63}
+
+/* Boot configuration (define only one of next 3) */
+#define CONFIG_BOOT_NAND
+/* None of these are currently implemented. Left from the original Samsung
+ * version for reference
+#define CONFIG_BOOT_NOR
+#define CONFIG_BOOT_MOVINAND
+#define CONFIG_BOOT_ONENAND
+*/
+
+#define CONFIG_NAND
+#define CONFIG_NAND_S3C64XX
+/* Unimplemented or unsupported. See comment above.
+#define CONFIG_ONENAND
+#define CONFIG_MOVINAND
+*/
+
+/* Settings as above boot configuration */
+#define CFG_ENV_IS_IN_NAND
+#define CONFIG_BOOTARGS "console=ttySAC,115200"
+#define CONFIG_EXTRA_ENV_SETTINGS "bootargs=" CONFIG_BOOTARGS
+
+#if !defined(CONFIG_ENABLE_MMU)
+#define CONFIG_CMD_USB 1
+#define CONFIG_USB_OHCI_NEW 1
+#define CFG_USB_OHCI_REGS_BASE 0x74300000
+#define CFG_USB_OHCI_SLOT_NAME "s3c6400"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
+#define CFG_USB_OHCI_CPU_INIT 1
+#define LITTLEENDIAN 1 /* used by usb_ohci.c */
+
+#define CONFIG_USB_STORAGE 1
+#endif
+#define CONFIG_DOS_PARTITION 1
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU)
+# error "usb_ohci.c is currently broken with MMU enabled."
+#endif
+
+#endif /* __CONFIG_H */
--- /dev/null
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_NAND_SPL = y
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS = start.o cpu_init.o lowlevel_init.o
+COBJS = nand_boot.o nand_ecc.o s3c64xx.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+# from cpu directory
+$(obj)start.S:
+ @rm -f $@
+ @ln -s $(TOPDIR)/cpu/arm1176/start.S $@
+
+# from SoC directory
+$(obj)cpu_init.S:
+ @rm -f $@
+ @ln -s $(TOPDIR)/cpu/arm1176/s3c64xx/cpu_init.S $@
+
+# from board directory
+$(obj)lowlevel_init.S:
+ @rm -f $@
+ @ln -s $(TOPDIR)/board/samsung/smdk6400/lowlevel_init.S $@
+
+# from nand_spl directory
+$(obj)nand_boot.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@
+
+# from drivers/mtd/nand directory
+$(obj)nand_ecc.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/drivers/mtd/nand/nand_ecc.c $@
+
+$(obj)s3c64xx.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# Samsung S3C64xx Reference Platform (smdk6400) board
+
+# TEXT_BASE for SPL:
+#
+# On S3C64xx platforms the SPL is located in SRAM at 0.
+#
+# TEXT_BASE = 0
+
+include $(TOPDIR)/board/$(BOARDDIR)/config.mk
+
+# PAD_TO used to generate a 4kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 4096
+PAD_TO := $(shell expr $$[$(TEXT_BASE) + 4096])
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ start.o (.text)
+ cpu_init.o (.text)
+ nand_boot.o (.text)
+
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
projects / u-boot / commitdiff