#define VF610_ENET_PAD_CTRL    (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
                                PAD_CTL_OBE_IBE_ENABLE)
 #define VF610_DDR_PAD_CTRL     PAD_CTL_DSE_25ohm
+#define VF610_I2C_PAD_CTRL     (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+                               PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
 
 enum {
        VF610_PAD_PTA6__RMII0_CLKIN             = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
        VF610_PAD_PTA27__ESDHC1_DAT1            = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
        VF610_PAD_PTA28__ESDHC1_DAT2            = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
        VF610_PAD_PTA29__ESDHC1_DAT3            = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+       VF610_PAD_PTB14__I2C0_SCL               = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
+       VF610_PAD_PTB15__I2C0_SDA               = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
        VF610_PAD_DDR_A15__DDR_A_15             = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A14__DDR_A_14             = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A13__DDR_A_13             = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
        imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
 }
 
+static void setup_iomux_i2c(void)
+{
+       static const iomux_v3_cfg_t i2c0_pads[] = {
+               VF610_PAD_PTB14__I2C0_SCL,
+               VF610_PAD_PTB15__I2C0_SDA,
+       };
+
+       imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
+}
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
        {ESDHC1_BASE_ADDR},
                CCM_CCGR3_ANADIG_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
                CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
-               CCM_CCGR4_GPC_CTRL_MASK);
+               CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
                CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
 
        setup_iomux_uart();
        setup_iomux_enet();
+       setup_iomux_i2c();
 
        return 0;
 }