ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines

Added some needed fines and some misc additional defines
used by p4080 initialization.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 916cc625373ce0534cd73998914fb254d91784e6..ef3a1e1c03fe3df24a1c62284e85d925d99a4028 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1,7 +1,7 @@
 /*
  * MPC85xx Internal Memory Map
  *
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
  *
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
@@ -1672,7 +1672,23 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR_I2C2       0x00000010
 #define FSL_CORENET_DEVDISR_DUART1     0x00000002
 #define FSL_CORENET_DEVDISR_DUART2     0x00000001
-       u8      res7[12];
+       u32     devdisr2;       /* Device disable control 2 */
+#define FSL_CORENET_DEVDISR2_PME       0x80000000
+#define FSL_CORENET_DEVDISR2_SEC       0x40000000
+#define FSL_CORENET_DEVDISR2_QMBM      0x08000000
+#define FSL_CORENET_DEVDISR2_FM1       0x02000000
+#define FSL_CORENET_DEVDISR2_10GEC1    0x01000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_1  0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2  0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3  0x00200000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4  0x00100000
+#define FSL_CORENET_DEVDISR2_FM2       0x00020000
+#define FSL_CORENET_DEVDISR2_10GEC2    0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1  0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2  0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3  0x00002000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4  0x00001000
+       u8      res7[8];
        u32     powmgtcsr;      /* Power management status & control */
        u8      res8[12];
        u32     coredisru;      /* uppper portion for support of 64 cores */
@@ -1699,6 +1715,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL          0xfc000000
 #define FSL_CORENET_RCWSR5_DDR_SYNC            0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT               7
+#define FSL_CORENET_RCWSR5_SRDS_EN             0x00002000
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT     0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1         0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2         0x00100000
@@ -1952,7 +1969,15 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_RST                0x80000000
 #define SRDS_RSTCTL_RSTDONE    0x40000000
 #define SRDS_RSTCTL_RSTERR     0x20000000
+#define SRDS_RSTCTL_SDPD       0x00000020
                u32     pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_RFCK_SEL_MASK      0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_100       0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125       0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25    0x20000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK     0x00030000
+#define SRDS_PLLCR0_FRATE_SEL_5                0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_6_25     0x00010000
                u32     pllcr1; /* PLL Control Register 1 */
 #define SRDS_PLLCR1_PLL_BWSEL  0x08000000
                u32     res[5];
@@ -2028,6 +2053,7 @@ enum {
 #define CONFIG_SYS_MPC85xx_USB_OFFSET          0x210000
 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET     0x318000
 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET     0x31a000
+#define CONFIG_SYS_TSEC1_OFFSET                        0x4e0000 /* FM1@DTSEC0 */
 #else
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET          0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET          0x2000