#define __packed_1_ __packed __aligned(1)
/* SGDMA Stuff */
-#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010)
+#define ALT_SGDMA_STATUS_BUSY_MSK 0x00000010
-#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020)
-#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040)
-#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000)
+#define ALT_SGDMA_CONTROL_RUN_MSK 0x00000020
+#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK 0x00000040
+#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK 0x00010000
/*
* Descriptor control bit masks & offsets
* The following bit-offsets are expressed relative to the LSB of
* the control register bitfield.
*/
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001)
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002)
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004)
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080)
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK 0x00000001
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK 0x00000002
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK 0x00000004
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK 0x00000080
/*
* Descriptor status bit masks & offsets
* The following bit-offsets are expressed relative to the LSB of
* the status register bitfield.
*/
-#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080)
+#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK 0x00000080
/*
* The SGDMA controller buffer descriptor allocates
};
/* TSE Stuff */
-#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001)
-#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002)
-#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008)
-#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400)
-#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000)
-#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000)
+#define ALTERA_TSE_CMD_TX_ENA_MSK 0x00000001
+#define ALTERA_TSE_CMD_RX_ENA_MSK 0x00000002
+#define ALTERA_TSE_CMD_ETH_SPEED_MSK 0x00000008
+#define ALTERA_TSE_CMD_HD_ENA_MSK 0x00000400
+#define ALTERA_TSE_CMD_SW_RESET_MSK 0x00002000
+#define ALTERA_TSE_CMD_ENA_10_MSK 0x02000000
#define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)