]> git.sur5r.net Git - u-boot/commitdiff
drivers/usb : Define usb control register mask for w1c bits
authorNikhil Badola <nikhil.badola@freescale.com>
Thu, 8 May 2014 11:35:26 +0000 (17:05 +0530)
committerYork Sun <yorksun@freescale.com>
Fri, 16 May 2014 21:24:27 +0000 (16:24 -0500)
Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
drivers/usb/host/ehci-fsl.c
include/usb/ehci-fsl.h

index 6cb4d986685c037757aca191dc9490e2a38c3a07..45062e699bd7c38793e9bd6a5a3142e263c16f84 100644 (file)
@@ -104,15 +104,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
        if (!strncmp(phy_type, "utmi", 4)) {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
-               setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
-               setbits_be32(&ehci->control, UTMI_PHY_EN);
+               clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+                               PHY_CLK_SEL_UTMI);
+               clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+                               UTMI_PHY_EN);
                udelay(1000); /* delay required for PHY Clk to appear */
 #endif
                out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
-               setbits_be32(&ehci->control, USB_EN);
+               clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+                               USB_EN);
        } else {
-               setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
-               clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
+               clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+                               PHY_CLK_SEL_ULPI);
+               clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
+                               CONTROL_REGISTER_W1C_MASK, USB_EN);
                udelay(1000); /* delay required for PHY Clk to appear */
                if (!usb_phy_clk_valid(ehci))
                        return -EINVAL;
index c9ee1d5bf6264b257f6042b348c20fa2f6de7606..dd77ad63254f94d03355501c9ed3a21da97826bd 100644 (file)
@@ -11,6 +11,8 @@
 
 #include <asm/processor.h>
 
+#define CONTROL_REGISTER_W1C_MASK       0x00020000  /* W1C: PHY_CLK_VALID */
+
 /* Global offsets */
 #define FSL_SKIP_PCI           0x100