ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4

This is necessary to use the USB 3.0 host controllers on PH1-Pro4.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h
index f0467bbde31fdbf10dfd2f32dc4e0a55e2c8079d..caec6c257475d2410ade3118c8a1b2bafb0793c8 100644 (file)
--- a/arch/arm/mach-uniphier/include/mach/sc-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h
@@ -1,7 +1,7 @@
 /*
  * UniPhier SC (System Control) block registers
  *
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -38,19 +38,28 @@
 #define SC_VPLL27BCTRL3                        (SC_BASE_ADDR | 0x1298)
 
 #define SC_RSTCTRL                     (SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL_NRST_USB3B0         (0x1 << 17)     /* USB3 #0 bus */
+#define SC_RSTCTRL_NRST_USB3C0         (0x1 << 16)     /* USB3 #0 core */
 #define SC_RSTCTRL_NRST_ETHER          (0x1 << 12)
 #define SC_RSTCTRL_NRST_STDMAC         (0x1 << 10)
+#define SC_RSTCTRL_NRST_GIO            (0x1 <<  6)
 #define SC_RSTCTRL_NRST_UMC1           (0x1 <<  5)
 #define SC_RSTCTRL_NRST_UMC0           (0x1 <<  4)
 #define SC_RSTCTRL_NRST_NAND           (0x1 <<  2)
 
 #define SC_RSTCTRL2                    (SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL2_NRST_USB3B1                (0x1 << 17)     /* USB3 #1 bus */
+#define SC_RSTCTRL2_NRST_USB3C1                (0x1 << 16)     /* USB3 #1 core */
+
 #define SC_RSTCTRL3                    (SC_BASE_ADDR | 0x2008)
 
 #define SC_CLKCTRL                     (SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL_CEN_USB31           (0x1 << 17)     /* USB3 #1 */
+#define SC_CLKCTRL_CEN_USB30           (0x1 << 16)     /* USB3 #0 */
 #define SC_CLKCTRL_CEN_ETHER           (0x1 << 12)
 #define SC_CLKCTRL_CEN_MIO             (0x1 << 11)
 #define SC_CLKCTRL_CEN_STDMAC          (0x1 << 10)
+#define SC_CLKCTRL_CEN_GIO             (0x1 <<  6)
 #define SC_CLKCTRL_CEN_UMC             (0x1 <<  4)
 #define SC_CLKCTRL_CEN_NAND            (0x1 <<  2)
 #define SC_CLKCTRL_CEN_SBC             (0x1 <<  1)

diff --git a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
index 4ac5411562ad5cc4dd5ef32fb915a8737090d18e..054efa653773a9249dfebb173ef820fc4459d634 100644 (file)
--- a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
+++ b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
@@ -14,6 +14,10 @@ void clkrst_init(void)
 
        /* deassert reset */
        tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+       tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
+               SC_RSTCTRL_NRST_GIO;
+#endif
 #ifdef CONFIG_UNIPHIER_ETH
        tmp |= SC_RSTCTRL_NRST_ETHER;
 #endif
@@ -26,8 +30,19 @@ void clkrst_init(void)
        writel(tmp, SC_RSTCTRL);
        readl(SC_RSTCTRL); /* dummy read */
 
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+       tmp = readl(SC_RSTCTRL2);
+       tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
+       writel(tmp, SC_RSTCTRL2);
+       readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
        /* privide clocks */
        tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+       tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+               SC_CLKCTRL_CEN_GIO;
+#endif
 #ifdef CONFIG_UNIPHIER_ETH
        tmp |= SC_CLKCTRL_CEN_ETHER;
 #endif