powerpc/mpc86xx: Disable translation for BAT setup

We really shouldn't be overwriting bat registers with translation enabled,
especially when we're executing code using one of them for translating
the current instruction stream.  Instead, disable address translation
while doing the final BAT setup.

In order to do this, setup_bats has to move back to asm code, because we
require translation to be enabled to have a stack for C code.  The yucky
thing about that is that the assembler doesn't like ULL so we have to
switch to using HIGH/LOW pairs for physical addresses that are > 32 bits
in length.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c
index 802202478aa2b296b3255e4bdde7b6fcbbc44967..0375df26f95bbd08d4e203a485db52dde1f75454 100644 (file)
--- a/arch/powerpc/cpu/mpc86xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c
@@ -35,7 +35,6 @@
 #include <asm/mp.h>
 
 extern void srio_init(void);
-void setup_bats(void);
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -91,33 +90,6 @@ int cpu_init_r(void)
        return 0;
 }
 
-/* Set up BAT registers */
-void setup_bats(void)
-{
-#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L)
-       write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
-#endif
-#if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
-       write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
-#endif
-       write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
-       write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
-       write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
-       write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L);
-       write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L);
-       write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L);
-       write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L);
-       write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L);
-       write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L);
-       write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L);
-       write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
-       write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
-       write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L);
-       write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L);
-
-       return;
-}
-
 #ifdef CONFIG_ADDR_MAP
 /* Initialize address mapping array */
 void init_addr_map(void)

diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S
index 32896d49e1a82a57715a3eca8bc61bef1a9c96b7..ef80ecf6e53801c31ecc3e31cb063925e9d2876c 100644 (file)
--- a/arch/powerpc/cpu/mpc86xx/start.S
+++ b/arch/powerpc/cpu/mpc86xx/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright 2004, 2007, 2011 Freescale Semiconductor.
  * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -322,6 +322,73 @@ invalidate_bats:
        sync
        blr
 
+#define CONFIG_BAT_PAIR(n) \
+       lis     r4, CONFIG_SYS_IBAT##n##L@h;            \
+       ori     r4, r4, CONFIG_SYS_IBAT##n##L@l;        \
+       lis     r3, CONFIG_SYS_IBAT##n##U@h;            \
+       ori     r3, r3, CONFIG_SYS_IBAT##n##U@l;        \
+       mtspr   IBAT##n##L, r4;                         \
+       mtspr   IBAT##n##U, r3;                         \
+       lis     r4, CONFIG_SYS_DBAT##n##L@h;            \
+       ori     r4, r4, CONFIG_SYS_DBAT##n##L@l;        \
+       lis     r3, CONFIG_SYS_DBAT##n##U@h;            \
+       ori     r3, r3, CONFIG_SYS_DBAT##n##U@l;        \
+       mtspr   DBAT##n##L, r4;                         \
+       mtspr   DBAT##n##U, r3;
+
+/*
+ * setup_bats:
+ *
+ * Set up the final BAT registers now that setup is done.
+ *
+ * Assumes that:
+ *     1) Address translation is enabled upon entry
+ *     2) The boot rom is still accessible via 1:1 translation
+ */
+       .globl setup_bats
+setup_bats:
+       mflr    r5
+       sync
+
+       /*
+        * When we disable address translation, we will get 1:1 (VA==PA)
+        * translation.  The only place we know for sure is safe for that is
+        * the bootrom where we originally started out.  Pop back into there.
+        */
+       lis     r4, CONFIG_SYS_MONITOR_BASE_EARLY@h
+       ori     r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l
+       addi    r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
+
+       /* disable address translation */
+       mfmsr   r3
+       rlwinm  r3, r3, 0, 28, 25
+       mtspr   SRR0, r4
+       mtspr   SRR1, r3
+       rfi
+
+trans_disabled:
+#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
+       && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
+       CONFIG_BAT_PAIR(0)
+#endif
+       CONFIG_BAT_PAIR(1)
+       CONFIG_BAT_PAIR(2)
+       CONFIG_BAT_PAIR(3)
+       CONFIG_BAT_PAIR(4)
+       CONFIG_BAT_PAIR(5)
+       CONFIG_BAT_PAIR(6)
+       CONFIG_BAT_PAIR(7)
+
+       sync
+       isync
+
+       /* Turn translation back on and return */
+       mfmsr   r3
+       ori     r3, r3, (MSR_IR | MSR_DR)
+       mtspr   SPRN_SRR0,r5
+       mtspr   SPRN_SRR1,r3
+       rfi
+
 /*
  * early_bats:
  *

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 84d95bb7c697b5669276863e962f95fce354e29a..93b360a2ba717bd1c54460bd6b47c84219659a03 100644 (file)
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -99,9 +99,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
 #else
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
 #endif
 
 /*
@@ -114,14 +114,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 /* Physical addresses */
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH   0xf
-#define CONFIG_SYS_CCSRBAR_PHYS                (CONFIG_SYS_CCSRBAR_PHYS_LOW \
-                                        | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
-#else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH   0x0
-#define CONFIG_SYS_CCSRBAR_PHYS                CONFIG_SYS_CCSRBAR_PHYS_LOW
-#endif
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH   CONFIG_SYS_PHYS_ADDR_HIGH
+#define CONFIG_SYS_CCSRBAR_PHYS \
+       PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
+                           CONFIG_SYS_CCSRBAR_PHYS_HIGH)
 
 #define CONFIG_HWCONFIG        /* use hwconfig to control memory interleaving */
 
@@ -181,8 +177,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
 #define CONFIG_SYS_FLASH_BASE          0xef800000     /* start of FLASH 8M */
-#define CONFIG_SYS_FLASH_BASE_PHYS     (CONFIG_SYS_FLASH_BASE \
-                                        | CONFIG_SYS_PHYS_ADDR_HIGH)
+#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE_PHYS \
+       PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
+                           CONFIG_SYS_PHYS_ADDR_HIGH)
 
 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 
@@ -204,12 +202,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * required for the smallest BAT mapping, so there's a 64k hole.
  */
 #define CONFIG_SYS_LBC_BASE            0xffde0000
-#define CONFIG_SYS_LBC_BASE_PHYS       (CONFIG_SYS_LBC_BASE \
-                                        | CONFIG_SYS_PHYS_ADDR_HIGH)
+#define CONFIG_SYS_LBC_BASE_PHYS_LOW   CONFIG_SYS_LBC_BASE
 
 #define CONFIG_FSL_PIXIS       1       /* use common PIXIS code */
 #define PIXIS_BASE             (CONFIG_SYS_LBC_BASE + 0x00010000)
-#define PIXIS_BASE_PHYS        (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
+#define PIXIS_BASE_PHYS_LOW    (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
+#define PIXIS_BASE_PHYS                PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
+                                                   CONFIG_SYS_PHYS_ADDR_HIGH)
 #define PIXIS_SIZE             0x00008000      /* 32k */
 #define PIXIS_ID               0x0     /* Board ID at offset 0 */
 #define PIXIS_VER              0x1     /* Board version at offset 1 */
@@ -315,10 +314,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_SRIO1_MEM_BASE      0x80000000      /* base address */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS  0x0000000c00000000ULL
+#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW  0x00000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
 #else
-#define CONFIG_SYS_SRIO1_MEM_PHYS      CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW  CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
 #endif
+#define CONFIG_SYS_SRIO1_MEM_PHYS \
+       PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
+                           CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
 #define CONFIG_SYS_SRIO1_MEM_SIZE      0x20000000      /* 128M */
 
 /*
@@ -330,16 +334,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0x0000000c00000000ULL
+#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW  0x00000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS       CONFIG_SYS_PCIE1_MEM_VIRT
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW  CONFIG_SYS_PCIE1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
 #endif
+#define CONFIG_SYS_PCIE1_MEM_PHYS \
+       PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
+                           CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_VIRT       0xffc00000
-#define CONFIG_SYS_PCIE1_IO_PHYS       (CONFIG_SYS_PCIE1_IO_VIRT \
-                                | CONFIG_SYS_PHYS_ADDR_HIGH)
+#define CONFIG_SYS_PCIE1_IO_PHYS_LOW   CONFIG_SYS_PCIE1_IO_VIRT
+#define CONFIG_SYS_PCIE1_IO_PHYS \
+       PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
+                           CONFIG_SYS_PHYS_ADDR_HIGH)
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64K */
 
 #ifdef CONFIG_PHYS_64BIT
@@ -355,12 +366,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_PCIE2_MEM_VIRT      (CONFIG_SYS_PCIE1_MEM_VIRT \
                                         + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW  (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
+                                        + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 #define CONFIG_SYS_PCIE2_MEM_PHYS      (CONFIG_SYS_PCIE1_MEM_PHYS \
                                         + CONFIG_SYS_PCIE1_MEM_SIZE)
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE2_IO_VIRT       (CONFIG_SYS_PCIE1_IO_VIRT \
                                         + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_PHYS_LOW   (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
+                                        + CONFIG_SYS_PCIE1_IO_SIZE)
 #define CONFIG_SYS_PCIE2_IO_PHYS       (CONFIG_SYS_PCIE1_IO_PHYS \
                                         + CONFIG_SYS_PCIE1_IO_SIZE)
 #define CONFIG_SYS_PCIE2_IO_SIZE       CONFIG_SYS_PCIE1_IO_SIZE
@@ -455,21 +471,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #endif /* CONFIG_TSEC_ENET */
 
-/*  Contort an addr into the format needed for BATs */
-#ifdef CONFIG_PHYS_64BIT
-#define BAT_PHYS_ADDR(x)         ((unsigned long) \
-                                 ((x & 0x00000000ffffffffULL) |        \
-                                  ((x & 0x0000000e00000000ULL) >> 24) | \
-                                  ((x & 0x0000000100000000ULL) >> 30)))
-#else
-#define BAT_PHYS_ADDR(x)        (x)
-#endif
-
 
-/* Put high physical address bits into the BAT format */
+#ifdef CONFIG_PHYS_64BIT
 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 
+/* Put physical address into the BAT format */
+#define BAT_PHYS_ADDR(low, high) \
+       (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
+/* Convert high/low pairs to actual 64-bit value */
+#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
+#else
+/* 32-bit systems just ignore the "high" bits */
+#define BAT_PHYS_ADDR(low, high)        (low)
+#define PAIRED_PHYS_TO_PHYS(low, high)  (low)
+#endif
+
 /*
  * BAT0                DDR
  */
@@ -479,12 +496,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * BAT1                LBC (PIXIS/CF)
  */
-#define CONFIG_SYS_DBAT1L      (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+#define CONFIG_SYS_DBAT1L      (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
+                                              CONFIG_SYS_PHYS_ADDR_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT | \
                                 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT1U      (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
                                 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L      (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+#define CONFIG_SYS_IBAT1L      (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
+                                              CONFIG_SYS_PHYS_ADDR_HIGH) \
                                 | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT1U      CONFIG_SYS_DBAT1U
 
@@ -494,40 +513,40 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * BAT2                Rapidio Memory
  */
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_DBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \
+#define CONFIG_SYS_DBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
+                                              CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT \
                                 | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U      (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
                                 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \
+#define CONFIG_SYS_IBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
+                                              CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U      CONFIG_SYS_DBAT2U
 #else /* CONFIG_RIO */
-#define CONFIG_SYS_DBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \
+#define CONFIG_SYS_DBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
+                                              CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT | \
                                 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U      (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
                                 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \
+#define CONFIG_SYS_IBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
+                                              CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U      CONFIG_SYS_DBAT2U
 #endif
 
 /*
  * BAT3                CCSR Space
- * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
- * instead.  The assembler chokes on ULL.
  */
-#define CONFIG_SYS_DBAT3L      (CONFIG_SYS_CCSRBAR_PHYS_LOW \
-                                | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
-                                | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+#define CONFIG_SYS_DBAT3L      (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
+                                              CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT \
                                 | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U      (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
                                 | BATU_VP)
-#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_CCSRBAR_PHYS_LOW \
-                                | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
-                                | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+#define CONFIG_SYS_IBAT3L      (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
+                                              CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT3U      CONFIG_SYS_DBAT3U
 
@@ -545,12 +564,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * BAT4                PCIE1_IO and PCIE2_IO
  */
-#define CONFIG_SYS_DBAT4L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \
+#define CONFIG_SYS_DBAT4L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
+                                              CONFIG_SYS_PHYS_ADDR_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT \
                                 | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT4U      (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
                                 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \
+#define CONFIG_SYS_IBAT4L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
+                                              CONFIG_SYS_PHYS_ADDR_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U      CONFIG_SYS_DBAT4U
 
@@ -565,12 +586,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * BAT6                FLASH
  */
-#define CONFIG_SYS_DBAT6L      (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+#define CONFIG_SYS_DBAT6L      (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
+                                              CONFIG_SYS_PHYS_ADDR_HIGH) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT \
                                 | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT6U      (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
                                 | BATU_VP)
-#define CONFIG_SYS_IBAT6L      (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+#define CONFIG_SYS_IBAT6L      (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
+                                              CONFIG_SYS_PHYS_ADDR_HIGH) \
                                 | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U      CONFIG_SYS_DBAT6U
 

diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index eb85d60cad1bfa3688d70adbaa446a44e0497b6c..31e83f2cc9213377fc55ae8473c96e9e0c40fd47 100644 (file)
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -84,6 +84,7 @@ static __inline__ unsigned long get_l2cr (void)
 }
 
 void setup_ddr_bat(phys_addr_t dram_size);
+extern void setup_bats(void);
 
 #endif  /* _ASMLANGUAGE */
 #endif /* __MPC86xx_H__ */