to give board_init_r() a larger heap then the initial heap in
SRAM which is limited to SYS_MALLOC_F_LEN bytes.
+config SPL_SEPARATE_BSS
+ depends on SPL
+ bool "BSS section is in a different memory region from text"
+ help
+ Some platforms need a large BSS region in SPL and can provide this
+ because RAM is already set up. In this case BSS can be moved to RAM.
+ This option should then be enabled so that the correct device tree
+ location is used. Normally we put the device tree at the end of BSS
+ but with this option enabled, it goes at _image_binary_end.
+
config TPL
bool
depends on SPL && SUPPORT_TPL
select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
+ select SPL_OF_CONTROL
select DM
+ select SPL_DM
select DM_SPI
+ select DM_SERIAL
select DM_SPI_FLASH
+ select SPL_SEPARATE_BSS
config ARCH_ZYNQMP
bool "Support Xilinx ZynqMP Platform"
select ARM64
+ select DM
+ select OF_CONTROL
+ select DM_SERIAL
config TEGRA
bool "NVIDIA Tegra"
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += \
+ zynqmp-ep108.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
#size-cells = <1>;
compatible = "n25q00";
reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
+ spi-max-frequency = <100000000>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
};
amba: amba {
+ u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
&qspi {
status = "okay";
};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
reg = <0 0x40000000>;
};
};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
};
&uart1 {
+ u-boot,dm-pre-reloc;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
&uart1 {
+ u-boot,dm-pre-reloc;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
&uart1 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
};
&uart1 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
};
&uart1 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
};
&uart0 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
};
&uart1 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
};
&uart1 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
--- /dev/null
+/*
+ * clock specification for Xilinx ZynqMP ep108 development board
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&amba {
+ misc_clk: misc_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ i2c_clk: i2c_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <111111111>;
+ };
+
+ sata_clk: sata_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <75000000>;
+ };
+
+ dp_aclk: clock0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-accuracy = <100>;
+ };
+
+ dp_aud_clk: clock1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <22579200>;
+ clock-accuracy = <100>;
+ };
+};
+
+&can0 {
+ clocks = <&misc_clk &misc_clk>;
+};
+
+&gem0 {
+ clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+};
+
+&gpio {
+ clocks = <&misc_clk>;
+};
+
+&i2c0 {
+ clocks = <&i2c_clk>;
+};
+
+&i2c1 {
+ clocks = <&i2c_clk>;
+};
+
+&qspi {
+ clocks = <&misc_clk &misc_clk>;
+};
+
+&sata {
+ clocks = <&sata_clk>;
+};
+
+&sdhci0 {
+ clocks = <&misc_clk>, <&misc_clk>;
+};
+
+&sdhci1 {
+ clocks = <&misc_clk>, <&misc_clk>;
+};
+
+&spi0 {
+ clocks = <&misc_clk &misc_clk>;
+};
+
+&spi1 {
+ clocks = <&misc_clk &misc_clk>;
+};
+
+&uart0 {
+ clocks = <&misc_clk &misc_clk>;
+};
+
+&usb0 {
+ clocks = <&misc_clk>, <&misc_clk>;
+};
+
+&usb1 {
+ clocks = <&misc_clk>, <&misc_clk>;
+};
+
+&watchdog0 {
+ clocks= <&misc_clk>;
+};
+
+&xilinx_drm {
+ clocks = <&misc_clk>;
+};
+
+&xlnx_dp {
+ clocks = <&dp_aclk>, <&dp_aud_clk>;
+};
+
+&xlnx_dp_snd_codec0 {
+ clocks = <&dp_aud_clk>;
+};
+
+&xlnx_dpdma {
+ clocks = <&misc_clk>;
+};
--- /dev/null
+/*
+ * dts file for Xilinx ZynqMP ep108 development board
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+/include/ "zynqmp-ep108-clk.dtsi"
+
+/ {
+ model = "ZynqMP EP108";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &qspi;
+ spi1 = &spi0;
+ spi2 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x40000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0{
+ reg = <0>;
+ max-speed = <100>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ eeprom@54 {
+ compatible = "at,24c64";
+ reg = <0x54>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ eeprom@55 {
+ compatible = "at,24c64";
+ reg = <0x55>;
+ };
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "n25q512a11";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <10000000>;
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&sata {
+ status = "okay";
+ ceva,broken-gen2;
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <1>;
+ spi0_flash0: spi0_flash0@0 {
+ compatible = "m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+
+ spi0_flash0@00000000 {
+ label = "spi0_flash0";
+ reg = <0x0 0x100000>;
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <1>;
+ spi1_flash0: spi1_flash0@0 {
+ compatible = "m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+
+ spi1_flash0@00000000 {
+ label = "spi1_flash0";
+ reg = <0x0 0x100000>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&xlnx_dp {
+ xlnx,max-pclock-frequency = <200000>;
+};
+
+&xlnx_dpdma {
+ xlnx,axi-clock-freq = <200000000>;
+};
--- /dev/null
+/*
+ * dts file for Xilinx ZynqMP
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/ {
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 143 4>,
+ <0 144 4>,
+ <0 145 4>,
+ <0 146 4>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ firmware {
+ compatible = "xlnx,zynqmp-pm";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <1 13 0xf01>,
+ <1 14 0xf01>,
+ <1 11 0xf01>,
+ <1 10 0xf01>;
+ };
+
+ amba_apu: amba_apu {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ gic: interrupt-controller@f9010000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ reg = <0x0 0xf9010000 0x10000>,
+ <0x0 0xf902f000 0x2000>,
+ <0x0 0xf9040000 0x20000>,
+ <0x0 0xf906f000 0x2000>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <1 9 0xf04>;
+ };
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ can0: can@ff060000 {
+ compatible = "xlnx,zynq-can-1.0";
+ status = "disabled";
+ clock-names = "can_clk", "pclk";
+ reg = <0x0 0xff060000 0x1000>;
+ interrupts = <0 23 4>;
+ interrupt-parent = <&gic>;
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ can1: can@ff070000 {
+ compatible = "xlnx,zynq-can-1.0";
+ status = "disabled";
+ clock-names = "can_clk", "pclk";
+ reg = <0x0 0xff070000 0x1000>;
+ interrupts = <0 24 4>;
+ interrupt-parent = <&gic>;
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ /* GDMA */
+ fpd_dma_chan1: dma@fd500000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd500000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 124 4>;
+ xlnx,id = <0>;
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan2: dma@fd510000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd510000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 125 4>;
+ xlnx,id = <1>;
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan3: dma@fd520000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd520000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 126 4>;
+ xlnx,id = <2>;
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan4: dma@fd530000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd530000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 127 4>;
+ xlnx,id = <3>;
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan5: dma@fd540000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd540000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 128 4>;
+ xlnx,id = <4>;
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan6: dma@fd550000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd550000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 129 4>;
+ xlnx,id = <5>;
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan7: dma@fd560000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd560000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 130 4>;
+ xlnx,id = <6>;
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan8: dma@fd570000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd570000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 131 4>;
+ xlnx,id = <7>;
+ xlnx,bus-width = <128>;
+ };
+
+ gpu: gpu@fd4b0000 {
+ status = "disabled";
+ compatible = "arm,mali-400", "arm,mali-utgard";
+ reg = <0x0 0xfd4b0000 0x30000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
+ interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
+ };
+
+ /* ADMA */
+ lpd_dma_chan1: dma@ffa80000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffa80000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 77 4>;
+ xlnx,id = <0>;
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan2: dma@ffa90000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffa90000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 78 4>;
+ xlnx,id = <1>;
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan3: dma@ffaa0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffaa0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 79 4>;
+ xlnx,id = <2>;
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan4: dma@ffab0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffab0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 80 4>;
+ xlnx,id = <3>;
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan5: dma@ffac0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffac0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 81 4>;
+ xlnx,id = <4>;
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan6: dma@ffad0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffad0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 82 4>;
+ xlnx,id = <5>;
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan7: dma@ffae0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffae0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 83 4>;
+ xlnx,id = <6>;
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan8: dma@ffaf0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffaf0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 84 4>;
+ xlnx,id = <7>;
+ xlnx,bus-width = <64>;
+ };
+
+ nand0: nand@ff100000 {
+ compatible = "arasan,nfc-v3p10";
+ status = "disabled";
+ reg = <0x0 0xff100000 0x1000>;
+ clock-names = "clk_sys", "clk_flash";
+ interrupt-parent = <&gic>;
+ interrupts = <0 14 4>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ gem0: ethernet@ff0b0000 {
+ compatible = "cdns,gem";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 57 4>, <0 57 4>;
+ reg = <0x0 0xff0b0000 0x1000>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ jumbo-max-len = <10240>;
+ jumbo-supported;
+ };
+
+ gem1: ethernet@ff0c0000 {
+ compatible = "cdns,gem";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 59 4>, <0 59 4>;
+ reg = <0x0 0xff0c0000 0x1000>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ jumbo-max-len = <10240>;
+ jumbo-supported;
+ };
+
+ gem2: ethernet@ff0d0000 {
+ compatible = "cdns,gem";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 61 4>, <0 61 4>;
+ reg = <0x0 0xff0d0000 0x1000>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ jumbo-max-len = <10240>;
+ jumbo-supported;
+ };
+
+ gem3: ethernet@ff0e0000 {
+ compatible = "cdns,gem";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 63 4>, <0 63 4>;
+ reg = <0x0 0xff0e0000 0x1000>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ jumbo-max-len = <10240>;
+ jumbo-supported;
+ };
+
+ gpio: gpio@ff0a0000 {
+ compatible = "xlnx,zynqmp-gpio-1.0";
+ status = "disabled";
+ #gpio-cells = <0x2>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 16 4>;
+ reg = <0x0 0xff0a0000 0x1000>;
+ };
+
+ i2c0: i2c@ff020000 {
+ compatible = "cdns,i2c-r1p10";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 17 4>;
+ reg = <0x0 0xff020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ff030000 {
+ compatible = "cdns,i2c-r1p10";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 18 4>;
+ reg = <0x0 0xff030000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcie: pcie@fd0e0000 {
+ compatible = "xlnx,nwl-pcie-2.11";
+ status = "disabled";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ interrupt-parent = <&gic>;
+ interrupts = < 0 118 4>,
+ < 0 116 4>,
+ < 0 115 4>, /* MSI_1 [63...32] */
+ < 0 114 4 >; /* MSI_0 [31...0] */
+ interrupt-names = "misc", "intx", "msi_1", "msi_0";
+ reg = <0x0 0xfd0e0000 0x1000>,
+ <0x0 0xfd480000 0x1000>,
+ <0x0 0xe0000000 0x1000000>;
+ reg-names = "breg", "pcireg", "cfg";
+ ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+ };
+
+ qspi: spi@ff0f0000 {
+ compatible = "xlnx,zynqmp-qspi-1.0";
+ status = "disabled";
+ clock-names = "ref_clk", "pclk";
+ interrupts = <0 15 4>;
+ interrupt-parent = <&gic>;
+ num-cs = <1>;
+ reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ rtc: rtc@ffa60000 {
+ compatible = "xlnx,zynqmp-rtc";
+ status = "disabled";
+ reg = <0x0 0xffa60000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 26 4>, <0 27 4>;
+ interrupt-names = "alarm", "sec";
+ };
+
+ sata: ahci@fd0c0000 {
+ compatible = "ceva,ahci-1v84";
+ status = "disabled";
+ reg = <0x0 0xfd0c0000 0x2000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 133 4>;
+ };
+
+ sdhci0: sdhci@ff160000 {
+ compatible = "arasan,sdhci-8.9a";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 48 4>;
+ reg = <0x0 0xff160000 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ };
+
+ sdhci1: sdhci@ff170000 {
+ compatible = "arasan,sdhci-8.9a";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 49 4>;
+ reg = <0x0 0xff170000 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ };
+
+ smmu: smmu@fd800000 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0xfd800000 0x20000>;
+ #global-interrupts = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 157 4>,
+ <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
+ <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
+ <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
+ <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
+ };
+
+ spi0: spi@ff040000 {
+ compatible = "cdns,spi-r1p6";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 19 4>;
+ reg = <0x0 0xff040000 0x1000>;
+ clock-names = "ref_clk", "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@ff050000 {
+ compatible = "cdns,spi-r1p6";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 20 4>;
+ reg = <0x0 0xff050000 0x1000>;
+ clock-names = "ref_clk", "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ttc0: timer@ff110000 {
+ compatible = "cdns,ttc";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
+ reg = <0x0 0xff110000 0x1000>;
+ timer-width = <32>;
+ };
+
+ ttc1: timer@ff120000 {
+ compatible = "cdns,ttc";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
+ reg = <0x0 0xff120000 0x1000>;
+ timer-width = <32>;
+ };
+
+ ttc2: timer@ff130000 {
+ compatible = "cdns,ttc";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
+ reg = <0x0 0xff130000 0x1000>;
+ timer-width = <32>;
+ };
+
+ ttc3: timer@ff140000 {
+ compatible = "cdns,ttc";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
+ reg = <0x0 0xff140000 0x1000>;
+ timer-width = <32>;
+ };
+
+ uart0: serial@ff000000 {
+ compatible = "cdns,uart-r1p8";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 21 4>;
+ reg = <0x0 0xff000000 0x1000>;
+ clock-names = "uart_clk", "pclk";
+ };
+
+ uart1: serial@ff010000 {
+ compatible = "cdns,uart-r1p8";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 22 4>;
+ reg = <0x0 0xff010000 0x1000>;
+ clock-names = "uart_clk", "pclk";
+ };
+
+ usb0: usb@fe200000 {
+ compatible = "snps,dwc3";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 65 4>;
+ reg = <0x0 0xfe200000 0x40000>;
+ clock-names = "clk_xin", "clk_ahb";
+ };
+
+ usb1: usb@fe300000 {
+ compatible = "snps,dwc3";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 70 4>;
+ reg = <0x0 0xfe300000 0x40000>;
+ clock-names = "clk_xin", "clk_ahb";
+ };
+
+ watchdog0: watchdog@fd4d0000 {
+ compatible = "cdns,wdt-r1p2";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 52 1>;
+ reg = <0x0 0xfd4d0000 0x1000>;
+ timeout-sec = <10>;
+ };
+
+ xilinx_drm: xilinx_drm {
+ compatible = "xlnx,drm";
+ status = "disabled";
+ xlnx,encoder-slave = <&xlnx_dp>;
+ xlnx,connector-type = "DisplayPort";
+ xlnx,dp-sub = <&xlnx_dp_sub>;
+ planes {
+ xlnx,pixel-format = "rgb565";
+ plane0 {
+ dmas = <&xlnx_dpdma 3>;
+ dma-names = "dma";
+ };
+ plane1 {
+ dmas = <&xlnx_dpdma 0>;
+ dma-names = "dma";
+ };
+ };
+ };
+
+ xlnx_dp: dp@43c00000 {
+ compatible = "xlnx,v-dp";
+ status = "disabled";
+ reg = <0x0 0xfd4a0000 0x1000>;
+ interrupts = <0 119 4>;
+ interrupt-parent = <&gic>;
+ clock-names = "aclk", "aud_clk";
+ xlnx,dp-version = "v1.2";
+ xlnx,max-lanes = <2>;
+ xlnx,max-link-rate = <540000>;
+ xlnx,max-bpc = <16>;
+ xlnx,enable-ycrcb;
+ xlnx,colormetry = "rgb";
+ xlnx,bpc = <8>;
+ xlnx,audio-chan = <2>;
+ xlnx,dp-sub = <&xlnx_dp_sub>;
+ };
+
+ xlnx_dp_snd_card: dp_snd_card {
+ compatible = "xlnx,dp-snd-card";
+ status = "disabled";
+ xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
+ xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
+ };
+
+ xlnx_dp_snd_codec0: dp_snd_codec0 {
+ compatible = "xlnx,dp-snd-codec";
+ status = "disabled";
+ clock-names = "aud_clk";
+ };
+
+ xlnx_dp_snd_pcm0: dp_snd_pcm0 {
+ compatible = "xlnx,dp-snd-pcm";
+ status = "disabled";
+ dmas = <&xlnx_dpdma 4>;
+ dma-names = "tx";
+ };
+
+ xlnx_dp_snd_pcm1: dp_snd_pcm1 {
+ compatible = "xlnx,dp-snd-pcm";
+ status = "disabled";
+ dmas = <&xlnx_dpdma 5>;
+ dma-names = "tx";
+ };
+
+ xlnx_dp_sub: dp_sub@43c0a000 {
+ compatible = "xlnx,dp-sub";
+ status = "disabled";
+ reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
+ reg-names = "blend", "av_buf", "aud";
+ xlnx,output-fmt = "rgb";
+ };
+
+ xlnx_dpdma: dma@fd4c0000 {
+ compatible = "xlnx,dpdma";
+ status = "disabled";
+ reg = <0x0 0xfd4c0000 0x1000>;
+ interrupts = <0 122 4>;
+ interrupt-parent = <&gic>;
+ clock-names = "axi_clk";
+ dma-channels = <6>;
+ #dma-cells = <1>;
+ dma-video0channel@43c10000 {
+ compatible = "xlnx,video0";
+ };
+ dma-video1channel@43c10000 {
+ compatible = "xlnx,video1";
+ };
+ dma-video2channel@43c10000 {
+ compatible = "xlnx,video2";
+ };
+ dma-graphicschannel@43c10000 {
+ compatible = "xlnx,graphics";
+ };
+ dma-audio0channel@43c10000 {
+ compatible = "xlnx,audio0";
+ };
+ dma-audio1channel@43c10000 {
+ compatible = "xlnx,audio1";
+ };
+ };
+ };
+};
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
+ * Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
writel(regval, &pmc->pcr);
}
+
+int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ u32 regval, status;
+ u32 timeout = 1000;
+
+ if (id > AT91_PMC_PCR_PID_MASK)
+ return -EINVAL;
+
+ if (div > 0xff)
+ return -EINVAL;
+
+ writel(id, &pmc->pcr);
+ regval = readl(&pmc->pcr);
+ regval &= ~AT91_PMC_PCR_GCKCSS;
+ regval &= ~AT91_PMC_PCR_GCKDIV;
+
+ switch (clk_source) {
+ case GCK_CSS_SLOW_CLK:
+ regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK;
+ break;
+ case GCK_CSS_MAIN_CLK:
+ regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK;
+ break;
+ case GCK_CSS_PLLA_CLK:
+ regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK;
+ break;
+ case GCK_CSS_UPLL_CLK:
+ regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK;
+ break;
+ case GCK_CSS_MCK_CLK:
+ regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK;
+ break;
+ case GCK_CSS_AUDIO_CLK:
+ regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK;
+ break;
+ default:
+ printf("Error GCK clock source selection!\n");
+ return -EINVAL;
+ }
+
+ regval |= AT91_PMC_PCR_CMD_WRITE |
+ AT91_PMC_PCR_GCKDIV_(div) |
+ AT91_PMC_PCR_GCKEN;
+
+ writel(regval, &pmc->pcr);
+
+ do {
+ udelay(1);
+ status = readl(&pmc->sr);
+ } while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY)));
+
+ if (!timeout)
+ printf("Timeout waiting for GCK ready!\n");
+
+ return 0;
+}
+
+u32 at91_get_periph_generated_clk(u32 id)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ u32 regval, clk_source, div;
+ u32 freq;
+
+ if (id > AT91_PMC_PCR_PID_MASK)
+ return 0;
+
+ writel(id, &pmc->pcr);
+ regval = readl(&pmc->pcr);
+
+ clk_source = regval & AT91_PMC_PCR_GCKCSS;
+ switch (clk_source) {
+ case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
+ freq = CONFIG_SYS_AT91_SLOW_CLOCK;
+ break;
+ case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
+ freq = gd->arch.main_clk_rate_hz;
+ break;
+ case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
+ freq = gd->arch.plla_rate_hz;
+ break;
+ default:
+ printf("Improper GCK clock source selection!\n");
+ freq = 0;
+ break;
+ }
+
+ div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET);
+ div += 1;
+
+ return freq / div;
+}
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/at91_dbu.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pit.h>
#include <asm/arch/at91_gpbr.h>
dcache_enable();
}
+#define ATMEL_CHIPID_CIDR_VERSION 0x1f
+
unsigned int get_chip_id(void)
{
- return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
+ return readl(ATMEL_CHIPID_CIDR) & ~ATMEL_CHIPID_CIDR_VERSION;
}
unsigned int get_extension_chip_id(void)
{
- return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
+ return readl(ATMEL_CHIPID_EXID);
}
#define AT91_DBU_CID_ARCH_9xx 0x01900000
#define AT91_DBU_CID_ARCH_9XExx 0x02900000
-#define AT91_DBU_CIDR_MASK 0x1f
-#define AT91_DBU_CIDR 0x40
-#define AT91_DBU_EXID 0x44
-
#endif
#define AT91_PMC_IXR_MOSCSELS 0x00010000
#define AT91_PMC_PCR_PID_MASK (0x3f)
+#define AT91_PMC_PCR_GCKCSS (0x7 << 8)
+#define AT91_PMC_PCR_GCKCSS_SLOW_CLK (0x0 << 8)
+#define AT91_PMC_PCR_GCKCSS_MAIN_CLK (0x1 << 8)
+#define AT91_PMC_PCR_GCKCSS_PLLA_CLK (0x2 << 8)
+#define AT91_PMC_PCR_GCKCSS_UPLL_CLK (0x3 << 8)
+#define AT91_PMC_PCR_GCKCSS_MCK_CLK (0x4 << 8)
+#define AT91_PMC_PCR_GCKCSS_AUDIO_CLK (0x5 << 8)
#define AT91_PMC_PCR_CMD_WRITE (0x1 << 12)
+#define AT91_PMC_PCR_DIV (0x3 << 16)
+#define AT91_PMC_PCR_GCKDIV (0xff << 20)
+#define AT91_PMC_PCR_GCKDIV_(x) ((x & 0xff) << 20)
+#define AT91_PMC_PCR_GCKDIV_OFFSET 20
#define AT91_PMC_PCR_EN (0x1 << 28)
+#define AT91_PMC_PCR_GCKEN (0x1 << 29)
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
+#define AT91_PMC_GCKRDY (1 << 24)
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
#endif
--- /dev/null
+/*
+ * Copyright (c) 2015 Atmel Corporation
+ * Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ATMEL_SDHCI_H
+#define __ATMEL_SDHCI_H
+
+int atmel_sdhci_init(void *regbase, u32 id);
+
+#endif
#include <asm/arch/at91_pmc.h>
#include <asm/global_data.h>
+#define GCK_CSS_SLOW_CLK 0
+#define GCK_CSS_MAIN_CLK 1
+#define GCK_CSS_PLLA_CLK 2
+#define GCK_CSS_UPLL_CLK 3
+#define GCK_CSS_MCK_CLK 4
+#define GCK_CSS_AUDIO_CLK 5
+
static inline unsigned long get_cpu_clk_rate(void)
{
DECLARE_GLOBAL_DATA_PTR;
int at91_clock_init(unsigned long main_clock);
void at91_periph_clk_enable(int id);
void at91_periph_clk_disable(int id);
+int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
+u32 at91_get_periph_generated_clk(u32 id);
+
#endif /* __ASM_ARM_ARCH_CLK_H__ */
#define ATMEL_BASE_RTC 0xfffffeb0
/* Reserved: 0xfffffee0 - 0xffffffff */
+#define ATMEL_CHIPID_CIDR 0xffffee40
+#define ATMEL_CHIPID_EXID 0xffffee44
+
/*
* Internal Memory.
*/
#define ATMEL_BASE_PIOE 0xfc06d000
#define ATMEL_BASE_AIC 0xfc06e000
+#define ATMEL_CHIPID_CIDR 0xfc069040
+#define ATMEL_CHIPID_EXID 0xfc069044
+
/*
* Internal Memory.
*/
#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI RSTMGR_DEFINE(0, 5)
-#define RSTMGR_SDMMC RSTMGR_DEFINE(0, 22)
-#define RSTMGR_DMA RSTMGR_DEFINE(0, 28)
+#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
/* Create a human-readable reference to SoCFPGA reset. */
config TARGET_ZYNQ_PICOZED
bool "Zynq PicoZed"
-config TARGET_ZYNQ_ZC70X
- bool "Zynq ZC702/ZC706 Board (deprecated)"
- select ZYNQ_CUSTOM_INIT
- help
- This option is deprecated. Use TARGET_ZYNQ_ZC702
- or TARGET_ZYNQ_706.
-
config TARGET_ZYNQ_ZC702
bool "Zynq ZC702 Board"
default "zynq_zed" if TARGET_ZYNQ_ZED
default "zynq_microzed" if TARGET_ZYNQ_MICROZED
default "zynq_picozed" if TARGET_ZYNQ_PICOZED
- default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 \
- || TARGET_ZYNQ_ZC70X
+ default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706
default "zynq_zc770" if TARGET_ZYNQ_ZC770
default "zynq_zybo" if TARGET_ZYNQ_ZYBO
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <debug_uart.h>
#include <spl.h>
#include <asm/io.h>
-#include <asm/arch/hardware.h>
#include <asm/spl.h>
+#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
{
ps7_init();
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
arch_cpu_init();
- board_init_r(NULL, 0);
+ /*
+ * The debug UART can be used from this point:
+ * debug_uart_init();
+ * printch('x');
+ */
}
#ifdef CONFIG_SPL_BOARD_INIT
} > .sram
. = ALIGN(4);
+#ifdef CONFIG_SPL_DM
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list_*_driver_*)));
+ KEEP(*(SORT(.u_boot_list_*_uclass_*)));
+ } > .sram
+
+ . = ALIGN(4);
+#endif
. = .;
- __image_copy_end = .;
+ _image_binary_end = .;
_end = .;
config TARGET_UCP1020
bool "Support uCP1020"
+config TARGET_CYRUS
+ bool "Support Varisys Cyrus"
+
endchoice
source "board/freescale/b4860qds/Kconfig"
source "board/keymile/kmp204x/Kconfig"
source "board/sbc8548/Kconfig"
source "board/socrates/Kconfig"
+source "board/varisys/cyrus/Kconfig"
source "board/xes/xpedite520x/Kconfig"
source "board/xes/xpedite537x/Kconfig"
source "board/xes/xpedite550x/Kconfig"
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
- * (C) Copyright 2009-2011
+ * (C) Copyright 2009-2015
* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* esd electronic system design gmbh <www.esd.eu>
*
* Miscelaneous platform dependent initialisations
*/
+#ifdef CONFIG_REVISION_TAG
static int hw_rev = -1; /* hardware revision */
int get_hw_rev(void)
return hw_rev;
}
+#endif /* CONFIG_REVISION_TAG */
#ifdef CONFIG_CMD_NAND
static void meesc_nand_hw_init(void)
int dram_init(void)
{
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
return 0;
}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+}
+
int board_eth_init(bd_t *bis)
{
int rc = 0;
return rc;
}
+#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
char str[32];
puts(", serial# ");
puts(str);
}
+#ifdef CONFIG_REVISION_TAG
printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+#endif
printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
return 0;
}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+endif
+endif
--- /dev/null
+/* EEPROM init functions for Cyrus */
+
+
+void init_eeprom(int bus_num, int addr, int addr_len);
+void mac_read_from_fixed_id(void);
+int mac_read_from_eeprom_common(void);
--- /dev/null
+/*
+ * Based on board/freescale/common/sys_eeprom.c
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ *
+ * This defines the API for storing board information in the
+ * eeprom. It has been adapted from an earlier version of the
+ * Freescale API, but has a number of key differences. Because
+ * the two APIs are independent and may diverge further, the
+ * Varisys version of the API is implemented separately here.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#include "eeprom.h"
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
+#define MAX_NUM_PORTS CONFIG_SYS_I2C_EEPROM_NXID_MAC
+#else
+#define MAX_NUM_PORTS 8
+#endif
+#define NXID_VERSION 0
+
+/**
+ * static eeprom: EEPROM layout for NXID formats
+ *
+ * See Freescale application note AN3638 for details.
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+ u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */
+ u8 sn[12]; /* 0x04 - 0x0F Serial Number */
+ u8 errata[5]; /* 0x10 - 0x14 Errata Level */
+ u8 date[6]; /* 0x15 - 0x1a Build Date */
+ u8 res_0; /* 0x1b Reserved */
+ u32 version; /* 0x1c - 0x1f NXID Version */
+ u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */
+ u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
+ u8 tempcalflags; /* 0x2a Temperature Calibration Flags */
+ u8 res_1[21]; /* 0x2b - 0x3f Reserved */
+ u8 mac_count; /* 0x40 Number of MAC addresses */
+ u8 mac_flag; /* 0x41 MAC table flags */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
+ u32 crc; /* x+1 CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/* Is this a valid NXID EEPROM? */
+#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
+ (e.id[2] == 'I') || (e.id[3] == 'D'))
+
+/** Fixed ID field in EEPROM */
+static unsigned char uid[16];
+
+static int eeprom_bus_num = -1;
+static int eeprom_addr;
+static int eeprom_addr_len;
+
+/**
+ * This must be called before any eeprom access.
+ */
+void init_eeprom(int bus_num, int addr, int addr_len)
+{
+ eeprom_bus_num = bus_num;
+ eeprom_addr = addr;
+ eeprom_addr_len = addr_len;
+}
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+void show_eeprom(void)
+{
+ int i;
+ unsigned int crc;
+
+ /* EEPROM tag ID, either CCID or NXID */
+ printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+ be32_to_cpu(e.version));
+
+ /* Serial number */
+ printf("SN: %s\n", e.sn);
+
+ printf("UID: ");
+ for (i = 0; i < 16; i++)
+ printf("%02x", uid[i]);
+ printf("\n");
+
+ /* Errata level. */
+ printf("Errata: %s\n", e.errata);
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC addresses */
+ for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
+ u8 *p = e.mac[i];
+
+ printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+ }
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n",
+ be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+int read_eeprom(void)
+{
+ int ret;
+ unsigned int bus;
+
+ if (eeprom_bus_num < 0) {
+ printf("EEPROM not configured\n");
+ return -1;
+ }
+
+ if (has_been_read)
+ return 0;
+
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(eeprom_bus_num);
+
+ ret = i2c_read(eeprom_addr, 0, eeprom_addr_len,
+ (void *)&e, sizeof(e));
+
+
+ /* Fixed address of ID field */
+ i2c_read(0x5f, 0x80, 1, uid, 16);
+
+ i2c_set_bus_num(bus);
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+ int i;
+ void *p;
+ unsigned int bus;
+
+ if (eeprom_bus_num < 0) {
+ printf("EEPROM not configured\n");
+ return -1;
+ }
+
+ /* Set the reserved values to 0xFF */
+ e.res_0 = 0xFF;
+ memset(e.res_1, 0xFF, sizeof(e.res_1));
+ update_crc();
+
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(eeprom_bus_num);
+
+ /*
+ * The AT24C02 datasheet says that data can only be written in page
+ * mode, which means 8 bytes at a time, and it takes up to 5ms to
+ * complete a given write.
+ */
+ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
+ ret = i2c_write(eeprom_addr, i, eeprom_addr_len,
+ p, min((int)(sizeof(e) - i), 8));
+ if (ret)
+ break;
+ udelay(5000); /* 5ms write cycle timing */
+ }
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+
+ ret = i2c_read(eeprom_addr, 0,
+ eeprom_addr_len, (void *)&e2, sizeof(e2));
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+ i2c_set_bus_num(bus);
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in one of the MAC address fields of the EEPROM local copy.
+ */
+static void set_mac_address(unsigned int index, const char *string)
+{
+ char *p = (char *)string;
+ unsigned int i;
+
+ if ((index >= MAX_NUM_PORTS) || !string) {
+ printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
+ return;
+ }
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[index][i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+ read_eeprom();
+ return 0;
+ }
+
+ if (cmd == 'i') {
+ memcpy(e.id, "NXID", sizeof(e.id));
+ e.version = NXID_VERSION;
+ update_crc();
+ return 0;
+ }
+
+ if (!is_valid) {
+ printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have at least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'e': /* errata */
+ memset(e.errata, 0, 5);
+ strncpy((char *)e.errata, argv[2], 4);
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'p': /* MAC table size */
+ e.mac_count = simple_strtoul(argv[2], NULL, 16);
+ update_crc();
+ break;
+ case '0' ... '9': /* "mac 0" through "mac 22" */
+ set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+int mac_read_from_generic_eeprom(const char *envvar, int chip,
+ int address, int mac_bus)
+{
+ int ret;
+ unsigned int bus;
+ unsigned char mac[6];
+ char ethaddr[18];
+
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(mac_bus);
+
+ ret = i2c_read(chip, address, 1, mac, 6);
+
+ i2c_set_bus_num(bus);
+
+ if (!ret) {
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ mac[0],
+ mac[1],
+ mac[2],
+ mac[3],
+ mac[4],
+ mac[5]);
+
+ printf("MAC: %s\n", ethaddr);
+ setenv(envvar, ethaddr);
+ }
+
+ return ret;
+}
+
+void mac_read_from_fixed_id(void)
+{
+#ifdef CONFIG_SYS_I2C_MAC1_CHIP_ADDR
+ mac_read_from_generic_eeprom("ethaddr", CONFIG_SYS_I2C_MAC1_CHIP_ADDR,
+ CONFIG_SYS_I2C_MAC1_DATA_ADDR, CONFIG_SYS_I2C_MAC1_BUS);
+#endif
+#ifdef CONFIG_SYS_I2C_MAC2_CHIP_ADDR
+ mac_read_from_generic_eeprom("eth1addr", CONFIG_SYS_I2C_MAC2_CHIP_ADDR,
+ CONFIG_SYS_I2C_MAC2_DATA_ADDR, CONFIG_SYS_I2C_MAC2_BUS);
+#endif
+}
+
+/**
+ * mac_read_from_eeprom - read the MAC addresses from EEPROM
+ *
+ * This function reads the MAC addresses from EEPROM and sets the
+ * appropriate environment variables for each one read.
+ *
+ * The environment variables are only set if they haven't been set already.
+ * This ensures that any user-saved variables are never overwritten.
+ *
+ * This function must be called after relocation.
+ *
+ * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0
+ * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is
+ * located at a different offset.
+ */
+int mac_read_from_eeprom_common(void)
+{
+ unsigned int i;
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ puts("EEPROM: ");
+
+ if (read_eeprom()) {
+ printf("Read failed.\n");
+ return 0;
+ }
+
+ if (!is_valid) {
+ printf("Invalid ID (%02x %02x %02x %02x)\n",
+ e.id[0], e.id[1], e.id[2], e.id[3]);
+ return 0;
+ }
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return 0;
+ }
+
+ /*
+ * MAC address #9 in v1 occupies the same position as the CRC in v0.
+ * Erase it so that it's not mistaken for a MAC address. We'll
+ * update the CRC later.
+ */
+ if (e.version == 0)
+ memset(e.mac[8], 0xff, 6);
+
+ for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
+ if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[18];
+ char enetvar[9];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[i][0],
+ e.mac[i][1],
+ e.mac[i][2],
+ e.mac[i][3],
+ e.mac[i][4],
+ e.mac[i][5]);
+ sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv(enetvar))
+ setenv(enetvar, ethaddr);
+ }
+ }
+
+ printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+ be32_to_cpu(e.version));
+
+ return 0;
+}
--- /dev/null
+if TARGET_CYRUS
+
+config SYS_BOARD
+ default "cyrus"
+
+config SYS_VENDOR
+ default "varisys"
+
+config SYS_CONFIG_NAME
+ default "cyrus"
+
+endif
--- /dev/null
+Cyrus BOARD
+M: Andy Fleming <afleming@gmail.com>
+S: Maintained
+F: board/varisys/cyrus/
+F: include/configs/cyrus.h
+F: configs/Cyrus_P5020_defconfig
+F: configs/Cyrus_P5040_defconfig
--- /dev/null
+#
+
+obj-y += $(BOARD).o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+obj-y += eth.o
+obj-$(CONFIG_PCI) += pci.o
--- /dev/null
+Rebuilding u-boot for Cyrus
+
+The Cyrus defconfigs are Cyrus_P5020_defconfig and Cyrus_P5040_defconfig.
+
+They currently disable size optimization in order to avoid a relocation
+bug in some versions of GCC. As the output size is a constant, the size
+optimization is not currently important.
+
+Cyrus boots off a microSD card in a slot on the motherboard. This requires
+that the u-boot is built for the Pre-Boot Loader on the P5020/P5040.
+In order to reflash u-boot, you must download u-boot.pbl, then write it
+onto the card. To do that from u-boot:
+
+> tftp 1000000 u-boot.pbl
+> mmc write 1000000 8 672
+
+If you want to do this via a card reader in linux:
+
+> dd if=u-boot.pbl of=/dev/sdX bs=512 oseek=8
--- /dev/null
+/*
+ * Based on corenet_ds.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include <pci.h>
+
+#include "cyrus.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_OPENDRAIN 0x30000000
+#define GPIO_DIR 0x3c000004
+#define GPIO_INITIAL 0x30000000
+#define GPIO_VGA_SWITCH 0x00001000
+
+int checkboard(void)
+{
+ printf("Board: CYRUS\n");
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+
+ /*
+ * Only use DDR1_MCK0/3 and DDR2_MCK0/3
+ * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
+ * the noise introduced by these unterminated and unused clock pairs.
+ */
+ setbits_be32(&gur->ddrclkdr, 0x001B001B);
+
+ /* Set GPIO reset lines to open-drain, tristate */
+ setbits_be32(&pgpio->gpdat, GPIO_INITIAL);
+ setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);
+
+ /* Set GPIO Direction */
+ setbits_be32(&pgpio->gpdir, GPIO_DIR);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ out_be32(&lbc->lbcr, 0);
+ /* 1 clock LALE cycle */
+ out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR);
+
+ set_liodns();
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+ print_lbc_regs();
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+#endif
+
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN);
+
+ return mac_read_from_eeprom_common();
+}
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CYRUS_H
+#define __CYRUS_H
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
--- /dev/null
+/*
+ * Based on corenet_ds ddr code
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | |delay |
+ */
+ {4, 850, 4, 6, 0xff, 2, 0},
+ {4, 950, 5, 7, 0xff, 2, 0},
+ {4, 1050, 5, 8, 0xff, 2, 0},
+ {4, 1250, 5, 10, 0xff, 2, 0},
+ {4, 1350, 5, 11, 0xff, 2, 0},
+ {4, 1666, 5, 12, 0xff, 2, 0},
+ {2, 850, 5, 6, 0xff, 2, 0},
+ {2, 1050, 5, 7, 0xff, 2, 0},
+ {2, 1250, 4, 6, 0xff, 2, 0},
+ {2, 1350, 5, 7, 0xff, 2, 0},
+ {2, 1666, 5, 8, 0xff, 2, 0},
+ {1, 1250, 4, 6, 0xff, 2, 0},
+ {1, 1335, 4, 7, 0xff, 2, 0},
+ {1, 1666, 4, 8, 0xff, 2, 0},
+ {}
+};
+
+/*
+ * The two slots have slightly different timing. The center values are good
+ * for both slots. We use identical speed tables for them. In future use, if
+ * DIMMs have fewer center values that require two separated tables, copy the
+ * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+ udimm0,
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | |delay |
+ */
+ {4, 850, 4, 6, 0xff, 2, 0},
+ {4, 950, 5, 7, 0xff, 2, 0},
+ {4, 1050, 5, 8, 0xff, 2, 0},
+ {4, 1250, 5, 10, 0xff, 2, 0},
+ {4, 1350, 5, 11, 0xff, 2, 0},
+ {4, 1666, 5, 12, 0xff, 2, 0},
+ {2, 850, 4, 6, 0xff, 2, 0},
+ {2, 1050, 4, 7, 0xff, 2, 0},
+ {2, 1666, 4, 8, 0xff, 2, 0},
+ {1, 850, 4, 5, 0xff, 2, 0},
+ {1, 950, 4, 7, 0xff, 2, 0},
+ {1, 1666, 4, 8, 0xff, 2, 0},
+ {}
+};
+
+/*
+ * The two slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+ rdimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[ctrl_num];
+ else
+ pbsp = udimms[ctrl_num];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 60 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....");
+
+ if (!fsl_use_spd())
+ panic("Cyrus only supports using SPD for DRAM\n");
+
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ debug(" DDR: ");
+ return dram_size;
+}
--- /dev/null
+/*
+ * Author Adrian Cox
+ * Based somewhat on board/freescale/corenet_ds/eth_hydra.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <fsl_dtsec.h>
+
+#ifdef CONFIG_FMAN_ENET
+
+#define FIRST_PORT_ADDR 3
+#define SECOND_PORT_ADDR 7
+
+#ifdef CONFIG_PPC_P5040
+#define FIRST_PORT FM1_DTSEC5
+#define SECOND_PORT FM2_DTSEC5
+#else
+#define FIRST_PORT FM1_DTSEC4
+#define SECOND_PORT FM1_DTSEC5
+#endif
+
+#define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT)
+
+static void cyrus_phy_tuning(int phy)
+{
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ */
+ printf("Tuning PHY @ %d\n", phy);
+
+ /* sets address 0x104 or reg 260 for writing */
+ miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104);
+ /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */
+ miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0);
+ /* sets address 0x105 or reg 261 for writing */
+ miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105);
+ /* writes to address 0x105 , RXD[3..0] to -0. */
+ miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
+ /* sets address 0x106 or reg 261 for writing */
+ miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106);
+ /* writes to address 0x106 , TXD[3..0] to -0.84ns */
+ miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
+ /* force re-negotiation */
+ miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+ unsigned int i;
+
+ printf("Initializing Fman\n");
+
+
+ /* Register the real 1G MDIO bus */
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+
+ fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR);
+ fm_info_set_mdio(FIRST_PORT,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR);
+ fm_info_set_mdio(SECOND_PORT,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+ /* Never disable DTSEC1 - it controls MDIO */
+ for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ if (!IS_VALID_PORT(i))
+ fm_disable_port(i);
+ }
+
+#ifdef CONFIG_PPC_P5040
+ for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ if (!IS_VALID_PORT(i))
+ fm_disable_port(i);
+ }
+#endif
+
+ cpu_eth_init(bis);
+
+ cyrus_phy_tuning(FIRST_PORT_ADDR);
+ cyrus_phy_tuning(SECOND_PORT_ADDR);
+#endif
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Author: Adrian Cox
+ * Based on corenet_ds law files.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_LBC0_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_LBC1_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#PBI commands
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
--- /dev/null
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
--- /dev/null
+#
+# Default RCW for Cyrus P5020
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0c540000 00000000 1e1e0000 00000000
+44808c00 ff002000 68000000 45000000
+00000000 00000000 00000000 0003000f
+a0000000 00000000 00000000 00000000
--- /dev/null
+#
+# Default RCW for Cyrus P5040
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+90e00000 00000000 acac9800 00440000
+44808c00 ff29a000 68000000 61000000
+00000000 00000000 00000000 0003000f
+a0000000 00000000 00000000 00000000
--- /dev/null
+/*
+ * Author: Adrian Cox
+ * Based on corenet_ds tlb code
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* Local Bus */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_64K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
# To include xil_io.h
CFLAGS_ps7_init_gpl.o := -I$(srctree)/$(src)
-
-# Warn if CONFIG_TARGET_ZYNQ_ZC70X is enabled
-ifeq ($(CONFIG_TARGET_ZYNQ_ZC70X),y)
-ifeq ($(CONFIG_SPL_BUILD),y)
-$(warning CONFIG_TARGET_ZYNQ_ZC70X is deprecated.)
-$(warning Enable CONFIG_TARGET_ZYNQ_ZC702 or CONFIG_TARGET_ZYNQ_706 instead.)
-$(warning "make zynq_zc70x_defconfig" is also deprecated.)
-$(warning Use "make zynq_zc702_defconfig" or "make zynq_zc706_defconfig".)
-endif
-endif
--- /dev/null
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_CYRUS=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
--- /dev/null
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_CYRUS=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep"
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_REGEX is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC70X=y
-CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
-CONFIG_SPL=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_SIGNATURE=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
obj-$(CONFIG_DM_MMC) += mmc-uclass.o
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/arch/clk.h>
+
+#define ATMEL_SDHC_MIN_FREQ 400000
+
+int atmel_sdhci_init(void *regbase, u32 id)
+{
+ struct sdhci_host *host;
+ u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
+
+ host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
+ if (!host) {
+ printf("%s: sdhci_host calloc failed\n", __func__);
+ return -ENOMEM;
+ }
+
+ host->name = "atmel_sdhci";
+ host->ioaddr = regbase;
+ host->quirks = 0;
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ max_clk = at91_get_periph_generated_clk(id);
+ if (!max_clk) {
+ printf("%s: Failed to get the proper clock\n", __func__);
+ free(host);
+ return -ENODEV;
+ }
+
+ add_sdhci(host, max_clk, min_clk);
+
+ return 0;
+}
static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
struct sdhci_host *host = mmc->priv;
- unsigned int div, clk, timeout;
+ unsigned int div, clk, timeout, reg;
- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+ /* Wait max 20 ms */
+ timeout = 200;
+ while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
+ (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
+ if (timeout == 0) {
+ printf("%s: Timeout to wait cmd & data inhibit\n",
+ __func__);
+ return -1;
+ }
+
+ timeout--;
+ udelay(100);
+ }
+
+ reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ reg &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
if (clock == 0)
return 0;
#
# SPDX-License-Identifier: GPL-2.0+
#
-
#ccflags-y += -DDEBUG
obj-$(CONFIG_DM_RTC) += rtc-uclass.o
obj-$(CONFIG_RTC_MAX6900) += max6900.o
obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
obj-$(CONFIG_RTC_MC146818) += mc146818.o
+obj-$(CONFIG_RTC_MCP79411) += ds1307.o
obj-$(CONFIG_MCFRTC) += mcfrtc.o
obj-$(CONFIG_RTC_MK48T59) += mk48t59.o
obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
#define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
#define RTC_CTL_BIT_OUT 0x80 /* Output Control */
+/* MCP7941X-specific bits */
+#define MCP7941X_BIT_ST 0x80
+#define MCP7941X_BIT_VBATEN 0x08
+
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year;
+#ifdef CONFIG_RTC_MCP79411
+read_rtc:
+#endif
sec = rtc_read (RTC_SEC_REG_ADDR);
min = rtc_read (RTC_MIN_REG_ADDR);
hour = rtc_read (RTC_HR_REG_ADDR);
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday, hour, min, sec);
+#ifdef CONFIG_RTC_DS1307
if (sec & RTC_SEC_BIT_CH) {
printf ("### Warning: RTC oscillator has stopped\n");
/* clear the CH flag */
rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH);
rel = -1;
}
+#endif
+
+#ifdef CONFIG_RTC_MCP79411
+ /* make sure that the backup battery is enabled */
+ if (!(wday & MCP7941X_BIT_VBATEN)) {
+ rtc_write(RTC_DAY_REG_ADDR,
+ wday | MCP7941X_BIT_VBATEN);
+ }
+
+ /* clock halted? turn it on, so clock can tick. */
+ if (!(sec & MCP7941X_BIT_ST)) {
+ rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST);
+ printf("Started RTC\n");
+ goto read_rtc;
+ }
+#endif
+
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
+#ifdef CONFIG_RTC_MCP79411
+ rtc_write (RTC_DAY_REG_ADDR,
+ bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN);
+#else
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
+#endif
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
+#ifdef CONFIG_RTC_MCP79411
+ rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST);
+#else
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
+#endif
return 0;
}
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
+config DEBUG_UART_ZYNQ
+ bool "Xilinx Zynq"
+ help
+ Select this to enable a debug UART using the serial_s5p driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
endchoice
config DEBUG_UART_BASE
static void serial_find_console_or_panic(void)
{
+ const void *blob = gd->fdt_blob;
struct udevice *dev;
int node;
- if (CONFIG_IS_ENABLED(OF_CONTROL) && gd->fdt_blob) {
+ if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
/* Check for a chosen console */
- node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
+ node = fdtdec_get_chosen_node(blob, "stdout-path");
+ if (node < 0) {
+ const char *str, *p, *name;
+
+ /*
+ * Deal with things like
+ * stdout-path = "serial0:115200n8";
+ *
+ * We need to look up the alias and then follow it to
+ * the correct node.
+ */
+ str = fdtdec_get_chosen_prop(blob, "stdout-path");
+ if (str) {
+ p = strchr(str, ':');
+ name = fdt_get_alias_namelen(blob, str,
+ p ? p - str : strlen(str));
+ if (name)
+ node = fdt_path_offset(blob, name);
+ }
+ }
if (node < 0)
- node = fdt_path_offset(gd->fdt_blob, "console");
+ node = fdt_path_offset(blob, "console");
if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node,
&dev)) {
gd->cur_serial_dev = dev;
* bind it anyway.
*/
if (node > 0 &&
- !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) {
+ !lists_bind_fdt(gd->dm_root, blob, node, &dev)) {
if (!device_probe(dev)) {
gd->cur_serial_dev = dev;
return;
}
}
}
- if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !gd->fdt_blob) {
+ if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) {
/*
* Try to use CONFIG_CONS_INDEX if available (it is numbered
* from 1!).
*/
#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <errno.h>
#include <fdtdec.h>
#include <watchdog.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
};
-static struct uart_zynq *uart_zynq_ports[2] = {
- [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
- [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
+struct zynq_uart_priv {
+ struct uart_zynq *regs;
};
/* Set up the baud rate in gd struct */
-static void uart_zynq_serial_setbrg(const int port)
+static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
+ unsigned long clock, unsigned long baud)
{
/* Calculation results. */
unsigned int calc_bauderror, bdiv, bgen;
unsigned long calc_baud = 0;
- unsigned long baud;
- unsigned long clock = get_uart_clk(port);
- struct uart_zynq *regs = uart_zynq_ports[port];
/* Covering case where input clock is so slow */
- if (clock < 1000000 && gd->baudrate > 4800)
- gd->baudrate = 4800;
-
- baud = gd->baudrate;
+ if (clock < 1000000 && baud > 4800)
+ baud = 4800;
/* master clock
* Baud rate = ------------------
}
/* Initialize the UART, with...some settings. */
-static int uart_zynq_serial_init(const int port)
+static void _uart_zynq_serial_init(struct uart_zynq *regs)
{
- struct uart_zynq *regs = uart_zynq_ports[port];
-
- if (!regs)
- return -1;
-
/* RX/TX enabled & reset */
writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
ZYNQ_UART_CR_RXRST, ®s->control);
writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */
- uart_zynq_serial_setbrg(port);
-
- return 0;
}
-static void uart_zynq_serial_putc(const char c, const int port)
+static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
{
- struct uart_zynq *regs = uart_zynq_ports[port];
+ if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL)
+ return -EAGAIN;
- while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
- WATCHDOG_RESET();
-
- if (c == '\n') {
- writel('\r', ®s->tx_rx_fifo);
- while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
- WATCHDOG_RESET();
- }
writel(c, ®s->tx_rx_fifo);
+
+ return 0;
}
-static void uart_zynq_serial_puts(const char *s, const int port)
+int zynq_serial_setbrg(struct udevice *dev, int baudrate)
{
- while (*s)
- uart_zynq_serial_putc(*s++, port);
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+ unsigned long clock = get_uart_clk(0);
+
+ _uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
+
+ return 0;
}
-static int uart_zynq_serial_tstc(const int port)
+static int zynq_serial_probe(struct udevice *dev)
{
- struct uart_zynq *regs = uart_zynq_ports[port];
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+
+ _uart_zynq_serial_init(priv->regs);
- return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
+ return 0;
}
-static int uart_zynq_serial_getc(const int port)
+static int zynq_serial_getc(struct udevice *dev)
{
- struct uart_zynq *regs = uart_zynq_ports[port];
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+ struct uart_zynq *regs = priv->regs;
+
+ if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
+ return -EAGAIN;
- while (!uart_zynq_serial_tstc(port))
- WATCHDOG_RESET();
return readl(®s->tx_rx_fifo);
}
-/* Multi serial device functions */
-#define DECLARE_PSSERIAL_FUNCTIONS(port) \
- static int uart_zynq##port##_init(void) \
- { return uart_zynq_serial_init(port); } \
- static void uart_zynq##port##_setbrg(void) \
- { return uart_zynq_serial_setbrg(port); } \
- static int uart_zynq##port##_getc(void) \
- { return uart_zynq_serial_getc(port); } \
- static int uart_zynq##port##_tstc(void) \
- { return uart_zynq_serial_tstc(port); } \
- static void uart_zynq##port##_putc(const char c) \
- { uart_zynq_serial_putc(c, port); } \
- static void uart_zynq##port##_puts(const char *s) \
- { uart_zynq_serial_puts(s, port); }
-
-/* Serial device descriptor */
-#define INIT_PSSERIAL_STRUCTURE(port, __name) { \
- .name = __name, \
- .start = uart_zynq##port##_init, \
- .stop = NULL, \
- .setbrg = uart_zynq##port##_setbrg, \
- .getc = uart_zynq##port##_getc, \
- .tstc = uart_zynq##port##_tstc, \
- .putc = uart_zynq##port##_putc, \
- .puts = uart_zynq##port##_puts, \
-}
+static int zynq_serial_putc(struct udevice *dev, const char ch)
+{
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
-DECLARE_PSSERIAL_FUNCTIONS(0);
-static struct serial_device uart_zynq_serial0_device =
- INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
-DECLARE_PSSERIAL_FUNCTIONS(1);
-static struct serial_device uart_zynq_serial1_device =
- INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
+ return _uart_zynq_serial_putc(priv->regs, ch);
+}
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-__weak struct serial_device *default_serial_console(void)
+static int zynq_serial_pending(struct udevice *dev, bool input)
{
- const void *blob = gd->fdt_blob;
- int node;
- unsigned int base_addr;
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+ struct uart_zynq *regs = priv->regs;
- node = fdt_path_offset(blob, "serial0");
- if (node < 0)
- return NULL;
+ if (input)
+ return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
+ else
+ return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
+}
- base_addr = fdtdec_get_addr(blob, node, "reg");
- if (base_addr == FDT_ADDR_T_NONE)
- return NULL;
+static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
- if (base_addr == ZYNQ_SERIAL_BASEADDR0)
- return &uart_zynq_serial0_device;
+ addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
- if (base_addr == ZYNQ_SERIAL_BASEADDR1)
- return &uart_zynq_serial1_device;
+ priv->regs = (struct uart_zynq *)addr;
- return NULL;
+ return 0;
}
-#else
-__weak struct serial_device *default_serial_console(void)
+
+static const struct dm_serial_ops zynq_serial_ops = {
+ .putc = zynq_serial_putc,
+ .pending = zynq_serial_pending,
+ .getc = zynq_serial_getc,
+ .setbrg = zynq_serial_setbrg,
+};
+
+static const struct udevice_id zynq_serial_ids[] = {
+ { .compatible = "xlnx,xuartps" },
+ { .compatible = "cdns,uart-r1p8" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_s5p) = {
+ .name = "serial_zynq",
+ .id = UCLASS_SERIAL,
+ .of_match = zynq_serial_ids,
+ .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct zynq_uart_priv),
+ .probe = zynq_serial_probe,
+ .ops = &zynq_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_ZYNQ
+
+#include <debug_uart.h>
+
+void _debug_uart_init(void)
{
-#if defined(CONFIG_ZYNQ_SERIAL_UART0)
- if (uart_zynq_ports[0])
- return &uart_zynq_serial0_device;
-#endif
-#if defined(CONFIG_ZYNQ_SERIAL_UART1)
- if (uart_zynq_ports[1])
- return &uart_zynq_serial1_device;
-#endif
- return NULL;
+ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
+
+ _uart_zynq_serial_init(regs);
+ _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE);
}
-#endif
-void zynq_serial_initialize(void)
+static inline void _debug_uart_putc(int ch)
{
- serial_register(&uart_zynq_serial0_device);
- serial_register(&uart_zynq_serial1_device);
+ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
+
+ while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
+ WATCHDOG_RESET();
}
+
+DEBUG_UART_FUNCS
+
+#endif
}
/* Calibration sequence to determine the read data capture delay register */
-static int spi_calibration(struct udevice *bus)
+static int spi_calibration(struct udevice *bus, uint hz)
{
- struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
void *base = priv->regbase;
u8 opcode_rdid = 0x9F;
}
/* use back the intended clock and find low range */
- cadence_spi_write_speed(bus, plat->max_hz);
+ cadence_spi_write_speed(bus, hz);
for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
/* Disable QSPI */
cadence_qspi_apb_controller_disable(base);
(range_hi + range_lo) / 2, range_lo, range_hi);
/* just to ensure we do once only when speed or chip select change */
- priv->qspi_calibrated_hz = plat->max_hz;
+ priv->qspi_calibrated_hz = hz;
priv->qspi_calibrated_cs = spi_chip_select(bus);
return 0;
struct cadence_spi_priv *priv = dev_get_priv(bus);
int err;
+ if (hz > plat->max_hz)
+ hz = plat->max_hz;
+
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
- cadence_spi_write_speed(bus, hz);
-
- /* Calibration required for different SCLK speed or chip select */
- if (priv->qspi_calibrated_hz != plat->max_hz ||
+ /*
+ * Calibration required for different current SCLK speed, requested
+ * SCLK speed or chip select
+ */
+ if (priv->previous_hz != hz ||
+ priv->qspi_calibrated_hz != hz ||
priv->qspi_calibrated_cs != spi_chip_select(bus)) {
- err = spi_calibration(bus);
+ err = spi_calibration(bus, hz);
if (err)
return err;
+
+ /* prevent calibration run when same as previous request */
+ priv->previous_hz = hz;
}
/* Enable QSPI */
plat->regbase = (void *)data[0];
plat->ahbbase = (void *)data[2];
- /* Use 500KHz as a suitable default */
- plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
- 500000);
-
/* All other paramters are embedded in the child node */
subnode = fdt_first_subnode(blob, node);
if (subnode < 0) {
return -ENODEV;
}
+ /* Use 500 KHz as a suitable default */
+ plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency",
+ 500000);
+
/* Read other parameters from DT */
plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
int qspi_is_init;
unsigned int qspi_calibrated_hz;
unsigned int qspi_calibrated_cs;
+ unsigned int previous_hz;
};
/* Functions call declaration */
extern char __bss_end[];
extern char __image_copy_start[];
extern char __image_copy_end[];
+extern char _image_binary_end[];
extern char __rel_dyn_start[];
extern char __rel_dyn_end[];
--- /dev/null
+/*
+ * Based on corenet_ds.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CYRUS
+
+#define CONFIG_PHYS_64BIT
+
+#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040)
+#error Must call Cyrus CONFIG with a specific CPU enabled.
+#endif
+
+
+#define CONFIG_MMC
+#define CONFIG_SDCARD
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE3
+#define CONFIG_PCIE4
+#ifdef CONFIG_PPC_P5020
+#define CONFIG_SYS_FSL_RAID_ENGINE
+#define CONFIG_SYS_DPAA_RMAN
+#endif
+#define CONFIG_SYS_DPAA_PME
+
+/*
+ * Corenet DS style board configuration file
+ */
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
+#if defined(CONFIG_PPC_P5020)
+#define CONFIG_SYS_CLK_FREQ 133000000
+#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
+#elif defined(CONFIG_PPC_P5040)
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
+#endif
+
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MP /* support multiple processors */
+
+
+#define CONFIG_SYS_MMC_MAX_DEVICE 1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_NO_FLASH
+
+#if defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1658)
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+/* test POST memory test */
+#undef CONFIG_POST
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
+#else
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
+#endif
+#define CONFIG_SYS_L3_SIZE (1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
+#else
+#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
+#endif
+
+#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
+#else
+#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
+#endif
+
+/* Set the local bus clock 1/16 of platform clock */
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
+
+#define CONFIG_SYS_BR0_PRELIM \
+(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM \
+(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM 0xfff00010
+#define CONFIG_SYS_OR1_PRELIM 0xfff00010
+
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+
+#define CONFIG_SYS_I2C_GENERIC_MAC
+#define CONFIG_SYS_I2C_MAC1_BUS 3
+#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
+#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
+#define CONFIG_SYS_I2C_MAC2_BUS 0
+#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
+#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
+
+#define CONFIG_CMD_DATE 1
+#define CONFIG_RTC_MCP79411 1
+#define CONFIG_SYS_RTC_BUS_NUM 3
+#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+/* Default address of microcode for the Linux Fman driver */
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
+
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_NET_MULTI
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_TBIPA_VALUE 8
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC4"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_HAS_FSL_MPH_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+ /* _VIA_CONTROL_EP */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE 115200
+
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
+"bank_intlv=cs0_cs1;" \
+"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"fdtaddr=c00000\0" \
+"bdev=sda3\0"
+
+#define CONFIG_HDBOOT \
+"setenv bootargs root=/dev/$bdev rw " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $loadaddr $bootfile;" \
+"tftp $fdtaddr $fdtfile;" \
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+"setenv bootargs root=/dev/nfs rw " \
+"nfsroot=$serverip:$rootpath " \
+"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $loadaddr $bootfile;" \
+"tftp $fdtaddr $fdtfile;" \
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+"setenv bootargs root=/dev/ram rw " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $ramdiskaddr $ramdiskfile;" \
+"tftp $loadaddr $bootfile;" \
+"tftp $fdtaddr $fdtfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
+
+#include <asm/fsl_secure_boot.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#endif
+
+#endif /* __CONFIG_H */
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
- * (C) Copyright 2009-2011
+ * (C) Copyright 2009-2015
* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* esd electronic system design gmbh <www.esd.eu>
*
* Since the linker has to swallow that define, we must use a pure
* hex number here!
*/
-#define CONFIG_SYS_TEXT_BASE 0x20002000
+#define CONFIG_SYS_TEXT_BASE 0x21F00000
/*
* since a number of boards are not being listed in linux
#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */
#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
/*
* Hardware drivers
*/
-/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-
/* general purpose I/O */
#define CONFIG_AT91_GPIO
/*
* Command line configuration.
*/
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
+#endif
/* LED */
#define CONFIG_AT91_LED
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
+#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
+#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
+
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */
-#define CONFIG_SYS_SDRAM_SIZE 0x02000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
#ifdef CONFIG_CMD_NAND
# define CONFIG_NAND_ATMEL
# define CONFIG_SYS_MAX_NAND_DEVICE 1
-# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */
+# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
# define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_NET_RETRY_COUNT 20
#undef CONFIG_RESET_PHY_R
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-
-/* CAN */
-#define CONFIG_AT91_CAN
-
/* hw-controller addresses */
#define CONFIG_ET1100_BASE 0x70000000
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
/*
* Size of malloc() pool
# define CONFIG_ARM_DCC
# define CONFIG_CPU_ARMV8
#else
-# if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
-# define CONFIG_ZYNQ_SERIAL
-# endif
+# define CONFIG_ZYNQ_SERIAL
#endif
#define CONFIG_CONS_INDEX 0
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
-#define CONFIG_ZYNQ_SERIAL_UART0
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_I2C0
#define CONFIG_SYS_I2C_ZYNQ
# define CONFIG_CMD_FS_GENERIC
#endif
+#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
#define CONFIG_SYS_I2C_ZYNQ
+#endif
+
/* I2C */
#if defined(CONFIG_SYS_I2C_ZYNQ)
# define CONFIG_CMD_I2C
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#ifdef CONFIG_OF_CONTROL
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
+#else
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
#endif
/* Disable dcache for SPL just for sure */
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
-#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
-#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
-#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
#define CONFIG_SYS_NO_FLASH
#if defined(CONFIG_ZC770_XM010)
-# define CONFIG_ZYNQ_SERIAL_UART1
# define CONFIG_ZYNQ_GEM0
# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
# define CONFIG_ZYNQ_SDHCI0
# define CONFIG_ZYNQ_SPI
#elif defined(CONFIG_ZC770_XM011)
-# define CONFIG_ZYNQ_SERIAL_UART1
#elif defined(CONFIG_ZC770_XM012)
-# define CONFIG_ZYNQ_SERIAL_UART1
# undef CONFIG_SYS_NO_FLASH
#elif defined(CONFIG_ZC770_XM013)
-# define CONFIG_ZYNQ_SERIAL_UART0
# define CONFIG_ZYNQ_GEM1
# define CONFIG_ZYNQ_GEM_PHY_ADDR1 7
-#else
-# define CONFIG_ZYNQ_SERIAL_UART0
#endif
#include <configs/zynq-common.h>
#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
-#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
-#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
s32 fdtdec_get_int(const void *blob, int node, const char *prop_name,
s32 default_val);
+/**
+ * Unsigned version of fdtdec_get_int. The property must have at least
+ * 4 bytes of data. The value of the first cell is returned.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param default_val default value to return if the property is not found
+ * @return unsigned integer value, if found, or default_val if not
+ */
+unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name,
+ unsigned int default_val);
+
/**
* Get a variable-sized number from a property
*
int *seqp);
/**
- * Get the offset of the given chosen node
+ * Get a property from the /chosen node
+ *
+ * @param blob Device tree blob (if NULL, then NULL is returned)
+ * @param name Property name to look up
+ * @return Value of property, or NULL if it does not exist
+ */
+const char *fdtdec_get_chosen_prop(const void *blob, const char *name);
+
+/**
+ * Get the offset of the given /chosen node
*
* This looks up a property in /chosen containing the path to another node,
* then finds the offset of that node.
return -ENOENT;
}
-int fdtdec_get_chosen_node(const void *blob, const char *name)
+const char *fdtdec_get_chosen_prop(const void *blob, const char *name)
{
- const char *prop;
int chosen_node;
- int len;
if (!blob)
- return -FDT_ERR_NOTFOUND;
+ return NULL;
chosen_node = fdt_path_offset(blob, "/chosen");
- prop = fdt_getprop(blob, chosen_node, name, &len);
+ return fdt_getprop(blob, chosen_node, name, NULL);
+}
+
+int fdtdec_get_chosen_node(const void *blob, const char *name)
+{
+ const char *prop;
+
+ prop = fdtdec_get_chosen_prop(blob, name);
if (!prop)
return -FDT_ERR_NOTFOUND;
return fdt_path_offset(blob, prop);
gd->fdt_blob = __dtb_dt_begin;
# elif defined CONFIG_OF_SEPARATE
# ifdef CONFIG_SPL_BUILD
- /* FDT is at end of BSS */
- gd->fdt_blob = (ulong *)&__bss_end;
+ /* FDT is at end of BSS unless it is in a different memory region */
+ if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
+ gd->fdt_blob = (ulong *)&_image_binary_end;
+ else
+ gd->fdt_blob = (ulong *)&__bss_end;
# else
/* FDT is at end of image */
gd->fdt_blob = (ulong *)&_end;
debug("(not found)\n");
return default_val;
}
+
+unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name,
+ unsigned int default_val)
+{
+ const int *cell;
+ int len;
+
+ debug("%s: %s: ", __func__, prop_name);
+ cell = fdt_getprop(blob, node, prop_name, &len);
+ if (cell && len >= sizeof(unsigned int)) {
+ unsigned int val = fdt32_to_cpu(cell[0]);
+
+ debug("%#x (%d)\n", val, val);
+ return val;
+ }
+ debug("(not found)\n");
+ return default_val;
+}
continue;
next = fdt_next_property_offset(fdt, offset);
if (next < 0)
- next = node_end - sizeof(fdt32_t);
+ next = node_end;
if (!did_alias_header) {
fdt_add_region(info, base + node, 12);
ALL-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).cfg
+ifdef CONFIG_SPL_OF_CONTROL
ALL-$(CONFIG_OF_SEPARATE) += $(obj)/$(SPL_BIN)-pad.bin $(obj)/$(SPL_BIN)-dtb.bin
+endif
ifdef CONFIG_SAMSUNG
ALL-y += $(obj)/$(BOARD)-spl.bin
new_count = fdt_add_alias_regions(fdt, region, count,
max_regions, &state);
- if (new_count > max_regions) {
- region = malloc(new_count * sizeof(struct fdt_region));
- if (!region) {
- fprintf(stderr,
- "Out of memory for %d regions\n",
- count);
- return -1;
- }
- memcpy(region, state.region,
- count * sizeof(struct fdt_region));
- free(state.region);
- new_count = fdt_add_alias_regions(fdt, region, count,
- max_regions, &state);
+ if (new_count <= max_regions) {
+ /*
+ * The alias regions will now be at the end of the list.
+ * Sort the regions by offset to get things into the
+ * right order
+ */
+ count = new_count;
+ qsort(region, count, sizeof(struct fdt_region),
+ h_cmp_region);
}
-
- /*
- * The alias regions will now be at the end of the list. Sort
- * the regions by offset to get things into the right order
- */
- qsort(region, new_count, sizeof(struct fdt_region),
- h_cmp_region);
- count = new_count;
}
if (ret != -FDT_ERR_NOTFOUND)
* The first pass will count the regions, but if it is too many,
* we do another pass to actually record them.
*/
- for (i = 0; i < 2; i++) {
+ for (i = 0; i < 3; i++) {
region = malloc(count * sizeof(struct fdt_region));
if (!region) {
fprintf(stderr, "Out of memory for %d regions\n",
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