- arm926ejs Files specific to ARM 926 CPUs
- arm1136 Files specific to ARM 1136 CPUs
- at32ap Files specific to Atmel AVR32 AP CPUs
+ - blackfin Files specific to Analog Devices Blackfin CPUs
- i386 Files specific to i386 CPUs
- ixp Files specific to Intel XScale IXP CPUs
- leon2 Files specific to Gaisler LEON2 SPARC CPU
- include Header Files
- lib_arm Files generic to ARM architecture
- lib_avr32 Files generic to AVR32 architecture
+- lib_blackfin Files generic to Blackfin architecture
- lib_generic Files generic to all architectures
- lib_i386 Files generic to i386 architecture
- lib_m68k Files generic to m68k architecture
CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
-PLATFORM_RELFLAGS += -ffixed-P5
+PLATFORM_RELFLAGS += -ffixed-P5 -fomit-frame-pointer
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
ifneq (,$(CONFIG_BFIN_CPU))
{
.text :
{
+ cpu/blackfin/start.o (.text)
+
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* it linked after the configuration sector.
*/
- cpu/blackfin/start.o (.text)
cpu/blackfin/traps.o (.text)
cpu/blackfin/interrupt.o (.text)
cpu/blackfin/serial.o (.text)
common/env_embedded.o (.text)
#endif
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text)
+ __initcode_end = .;
+
*(.text .text.*)
} >ram
*/
#include <common.h>
-#include <asm/mem_init.h>
#include <asm/io.h>
#include "bf533-stamp.h"
{
.text :
{
+ cpu/blackfin/start.o (.text)
+
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* it linked after the configuration sector.
*/
- cpu/blackfin/start.o (.text)
cpu/blackfin/traps.o (.text)
cpu/blackfin/interrupt.o (.text)
cpu/blackfin/serial.o (.text)
common/env_embedded.o (.text)
#endif
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text)
+ __initcode_end = .;
+
*(.text .text.*)
} >ram
{
.text :
{
+ cpu/blackfin/start.o (.text)
+
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* it linked after the configuration sector.
*/
- cpu/blackfin/start.o (.text)
cpu/blackfin/traps.o (.text)
cpu/blackfin/interrupt.o (.text)
cpu/blackfin/serial.o (.text)
common/env_embedded.o (.text)
#endif
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text)
+ __initcode_end = .;
+
*(.text .text.*)
} >ram
/*
- * U-boot - ezkit561.c
+ * U-boot - main board file
*
- * Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl>
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
int checkboard(void)
{
- printf("CPU: ADSP BF561\n");
printf("Board: ADI BF561 EZ-Kit Lite board\n");
printf(" Support: http://blackfin.uclinux.org/\n");
return 0;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return CONFIG_SYS_MAX_RAM_SIZE;
}
-
-#if defined(CONFIG_MISC_INIT_R)
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
- /* Keep PF12 low to be able to drive the USB-LAN Extender */
- *pFIO0_DIR = 0x0000;
- *pFIO0_FLAG_C = 0x1000; /* Clear PF12 */
- SSYNC();
- *pFIO0_POLAR = 0x0000;
- SSYNC();
-
- return 0;
-}
-#endif
{
.text :
{
+ cpu/blackfin/start.o (.text)
+
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* it linked after the configuration sector.
*/
- cpu/blackfin/start.o (.text)
cpu/blackfin/traps.o (.text)
cpu/blackfin/interrupt.o (.text)
cpu/blackfin/serial.o (.text)
common/env_embedded.o (.text)
#endif
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text)
+ __initcode_end = .;
+
*(.text .text.*)
} >ram
EXTRA :=
CEXTRA := initcode.o
SEXTRA := start.o
-SOBJS := interrupt.o cache.o flush.o
+SOBJS := interrupt.o cache.o
COBJS := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o
ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
#include <asm/blackfin.h>
#include <asm/cplb.h>
#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
#include <asm/mach-common/bits/trace.h>
#include "cpu.h"
#include "serial.h"
-void icache_enable(void)
-{
- bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB));
- SSYNC();
-}
-
-void icache_disable(void)
-{
- bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB));
- SSYNC();
-}
-
-int icache_status(void)
-{
- return bfin_read_IMEM_CONTROL() & ENICPLB;
-}
-
-void dcache_enable(void)
-{
- bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
- SSYNC();
-}
-
-void dcache_disable(void)
-{
- bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
- SSYNC();
-}
-
-int dcache_status(void)
-{
- return bfin_read_DMEM_CONTROL() & ENDCPLB;
-}
-
__attribute__ ((__noreturn__))
void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
{
bfin_write_EVT15(evt_default);
bfin_write_ILAT(0);
CSYNC();
- /* enable all interrupts except for core timer */
- irq_flags = 0xffffffbf;
+ /* enable hardware error irq */
+ irq_flags = 0x3f;
local_irq_enable();
- CSYNC();
return 0;
}
+++ /dev/null
-/* flush.S - low level cache flushing routines
- * Copyright (C) 2003-2007 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <asm/mach-common/bits/mpu.h>
-
-.text
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the data cache.
- */
-
-ENTRY(_flush_data_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = HI(DCPLB_ADDR0);
- P5.L = LO(DCPLB_ADDR0);
- P4.H = HI(DCPLB_DATA0);
- P4.L = LO(DCPLB_DATA0);
- R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
- R6 = 16;
-.Lnext: R0 = [P5++];
- R1 = [P4++];
- CC = BITTST(R1, 14); /* Is it write-through?*/
- IF CC JUMP .Lskip; /* If so, ignore it.*/
- R2 = R1 & R7; /* Is it a dirty, cached page?*/
- CC = R2;
- IF !CC JUMP .Lskip; /* If not, ignore it.*/
- [--SP] = RETS;
- CALL _dcplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-.Lskip: R6 += -1;
- CC = R6;
- IF CC JUMP .Lnext;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-ENDPROC(_flush_data_cache)
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular DCPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_dcplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP .Ldflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* The page could be mapped into Bank A or Bank B, depending
- * on (a) whether both banks are configured as cache, and
- * (b) on whether address bit A[x] is set. x is determined
- * by DCBS in DMEM_CONTROL
- */
-
- R2 = 0; /* Default to Bank A (Bank B would be 1)*/
-
- P0.L = LO(DMEM_CONTROL);
- P0.H = HI(DMEM_CONTROL);
-
- R3 = [P0]; /* If Bank B is not enabled as cache*/
- CC = BITTST(R3, 2); /* then Bank A is our only option.*/
- IF CC JUMP .Lbank_chosen;
-
- R4 = 1<<14; /* If DCBS==0, use A[14].*/
- R5 = R4 << 7; /* If DCBS==1, use A[23];*/
- CC = BITTST(R3, 4);
- IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
- R5 = R0 & R4; /* Use it to test the Page address*/
- CC = R5; /* and if that bit is set, we use Bank B,*/
- R2 = CC; /* else we use Bank A.*/
- R2 <<= 23; /* The Bank selection's at posn 23.*/
-
-.Lbank_chosen:
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- /* Save in extraction pattern for later deposit.*/
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R2 = Bank select mask
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = LO(DTEST_COMMAND);
- P5.H = HI(DTEST_COMMAND);
- P4.L = LO(DTEST_DATA0);
- P4.H = HI(DTEST_DATA0);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 2;
- LSETUP (.Lfs1, .Lfe1) LC1 = P2;
-.Lfs1: P0 = 64; /* iterate over all sets*/
- LSETUP (.Lfs0, .Lfe0) LC0 = P0;
-.Lfs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
- BITSET(R6,14);
- [P5] = R6; /* Issue Command*/
- SSYNC;
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP .Lfskip; /* and skip if not.*/
- CC = BITTST(R7, 1); /* Check if dirty*/
- IF !CC JUMP .Lfskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP .Lfskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- SSYNC;
- FLUSHINV [P3]; /* And flush the entry*/
-.Lfskip:
-.Lfe0: R5 += 1; /* Advance to next Set*/
-.Lfe1: BITSET(R2, 26); /* Go to next Way.*/
-
-.Ldfinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-.Ldflush_whole_page:
-
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (.Leall, .Leall) LC0 = P1;
-.Leall: FLUSHINV [P0++];
- SSYNC;
- JUMP .Ldfinished;
-ENDPROC(_dcplb_flush)
-
-.align 4;
-page_prefix_table:
-.byte4 0xFFFFFC00; /* 1K */
-.byte4 0xFFFFF000; /* 4K */
-.byte4 0xFFF00000; /* 1M */
-.byte4 0xFFC00000; /* 4M */
-.page_prefix_table.end:
#include "serial.h"
+#ifdef CONFIG_DEBUG_SERIAL
+uint16_t cached_lsr[256];
+uint16_t cached_rbr[256];
+size_t cache_count;
+
+/* The LSR is read-to-clear on some parts, so we have to make sure status
+ * bits aren't inadvertently lost when doing various tests.
+ */
+static uint16_t uart_lsr_save;
+static uint16_t uart_lsr_read(void)
+{
+ uint16_t lsr = *pUART_LSR;
+ uart_lsr_save |= (lsr & (OE|PE|FE|BI));
+ return lsr | uart_lsr_save;
+}
+/* Just do the clear for everyone since it can't hurt. */
+static void uart_lsr_clear(void)
+{
+ uart_lsr_save = 0;
+ *pUART_LSR |= -1;
+}
+#else
+static inline uint16_t uart_lsr_read(void) { return *pUART_LSR; }
+static inline void uart_lsr_clear(void) { *pUART_LSR = -1; }
+#endif
+
/* Symbol for our assembly to call. */
void serial_set_baud(uint32_t baud)
{
{
serial_initialize();
serial_setbrg();
+ uart_lsr_clear();
+#ifdef CONFIG_DEBUG_SERIAL
+ cache_count = 0;
+ memset(cached_lsr, 0x00, sizeof(cached_lsr));
+ memset(cached_rbr, 0x00, sizeof(cached_rbr));
+#endif
return 0;
}
WATCHDOG_RESET();
/* wait for the hardware fifo to clear up */
- while (!(*pUART_LSR & THRE))
+ while (!(uart_lsr_read() & THRE))
continue;
/* queue the character for transmission */
WATCHDOG_RESET();
/* wait for the byte to be shifted over the line */
- while (!(*pUART_LSR & TEMT))
+ while (!(uart_lsr_read() & TEMT))
continue;
}
int serial_tstc(void)
{
WATCHDOG_RESET();
- return (*pUART_LSR & DR) ? 1 : 0;
+ return (uart_lsr_read() & DR) ? 1 : 0;
}
int serial_getc(void)
{
- uint16_t uart_lsr_val, uart_rbr_val;
+ uint16_t uart_rbr_val;
/* wait for data ! */
while (!serial_tstc())
continue;
- /* clear the status and grab the new byte */
- uart_lsr_val = *pUART_LSR;
+ /* grab the new byte */
uart_rbr_val = *pUART_RBR;
+#ifdef CONFIG_DEBUG_SERIAL
+ /* grab & clear the LSR */
+ uint16_t uart_lsr_val = uart_lsr_read();
+
+ cached_lsr[cache_count] = uart_lsr_val;
+ cached_rbr[cache_count] = uart_rbr_val;
+ cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
+
if (uart_lsr_val & (OE|PE|FE|BI)) {
- /* Some parts are read-to-clear while others are
- * write-to-clear. Just do the write for everyone
- * since it cant hurt (other than code size).
- */
- *pUART_LSR = (OE|PE|FE|BI);
+ uint16_t dll, dlh;
+ printf("\n[SERIAL ERROR]\n");
+ ACCESS_LATCH();
+ dll = *pUART_DLL;
+ dlh = *pUART_DLH;
+ ACCESS_PORT_IER();
+ printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
+ do {
+ --cache_count;
+ printf("\t%3i: RBR=0x%02x LSR=0x%02x\n", cache_count,
+ cached_rbr[cache_count], cached_lsr[cache_count]);
+ } while (cache_count > 0);
return -1;
}
+#endif
+ uart_lsr_clear();
- return uart_rbr_val & 0xFF;
+ return uart_rbr_val;
}
void serial_puts(const char *s)
__attribute__((always_inline))
static inline void serial_early_set_baud(uint32_t baud)
{
- /* Translate from baud into divisor in terms of SCLK.
- * The +1 is to make sure we over sample just a little
- * rather than under sample the incoming signals.
+ /* Translate from baud into divisor in terms of SCLK. The
+ * weird multiplication is to make sure we over sample just
+ * a little rather than under sample the incoming signals.
*/
- uint16_t divisor = (get_sclk() / (baud * 16)) + 1;
+ uint16_t divisor = (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230;
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH();
/*
* U-boot - start.S Startup file for Blackfin u-boot
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* This file is based on head.S
* Copyright (c) 2003 Metrowerks/Motorola
ENTRY(_start)
/* Set our initial stack to L1 scratch space */
- sp.l = LO(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE);
- sp.h = HI(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE);
+ sp.l = LO(L1_SRAM_SCRATCH_END - 20);
+ sp.h = HI(L1_SRAM_SCRATCH_END - 20);
#ifdef CONFIG_HW_WATCHDOG
# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
serial_early_puts("Init Registers");
- /* Disable nested interrupts and enable CYCLES for udelay() */
+ /* Disable self-nested interrupts and enable CYCLES for udelay() */
R0 = CCEN | 0x30;
SYSCFG = R0;
/* Now lower ourselves from the highest interrupt level to
* the lowest. We do this by masking all interrupts but 15,
- * setting the 15 handler to "board_init_f", raising the 15
+ * setting the 15 handler to ".Lenable_nested", raising the 15
* interrupt, and then returning from the highest interrupt
* level to the dummy "jump" until the interrupt controller
* services the pending 15 interrupt.
r1 = r6;
p0.l = LO(EVT15);
p0.h = HI(EVT15);
- p1.l = _cpu_init_f;
- p1.h = _cpu_init_f;
+ p1.l = .Lenable_nested;
+ p1.h = .Lenable_nested;
[p0] = p1;
- p2.l = LO(IMASK);
- p2.h = HI(IMASK);
- p3.l = LO(EVT_IVG15);
- p3.h = HI(EVT_IVG15);
- [p2] = p3;
+ r7 = EVT_IVG15 (z);
+ sti r7;
raise 15;
p4.l = .LWAIT_HERE;
p4.h = .LWAIT_HERE;
reti = p4;
rti;
+ /* Enable nested interrupts before continuing with cpu init */
+.Lenable_nested:
+ cli r7;
+ [--sp] = reti;
+ jump.l _cpu_init_f;
+
.LWAIT_HERE:
jump .LWAIT_HERE;
ENDPROC(_start)
sprintf(buf, "<0x%p> /* unknown address */", address);
}
+static char *strhwerrcause(uint16_t hwerrcause)
+{
+ switch (hwerrcause) {
+ case 0x02: return "system mmr error";
+ case 0x03: return "external memory addressing error";
+ case 0x12: return "performance monitor overflow";
+ case 0x18: return "raise 5 instruction";
+ default: return "undef";
+ }
+}
+
+static char *strexcause(uint16_t excause)
+{
+ switch (excause) {
+ case 0x00 ... 0xf: return "custom exception";
+ case 0x10: return "single step";
+ case 0x11: return "trace buffer full";
+ case 0x21: return "undef inst";
+ case 0x22: return "illegal inst";
+ case 0x23: return "dcplb prot violation";
+ case 0x24: return "misaligned data";
+ case 0x25: return "unrecoverable event";
+ case 0x26: return "dcplb miss";
+ case 0x27: return "multiple dcplb hit";
+ case 0x28: return "emulation watchpoint";
+ case 0x2a: return "misaligned inst";
+ case 0x2b: return "icplb prot violation";
+ case 0x2c: return "icplb miss";
+ case 0x2d: return "multiple icplb hit";
+ case 0x2e: return "illegal use of supervisor resource";
+ default: return "undef";
+ }
+}
+
void dump(struct pt_regs *fp)
{
char buf[150];
size_t i;
+ uint16_t hwerrcause, excause;
if (!ENABLE_DUMP)
return;
+ /* fp->ipend is garbage, so load it ourself */
+ fp->ipend = bfin_read_IPEND();
+
+ hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
+ excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
+
printf("SEQUENCER STATUS:\n");
printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
fp->seqstat, fp->ipend, fp->syscfg);
- printf(" HWERRCAUSE: 0x%lx\n", (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P);
- printf(" EXCAUSE : 0x%lx\n", (fp->seqstat & EXCAUSE) >> EXCAUSE_P);
+ printf(" HWERRCAUSE: 0x%lx: %s\n", hwerrcause, strhwerrcause(hwerrcause));
+ printf(" EXCAUSE : 0x%lx: %s\n", excause, strexcause(excause));
for (i = 6; i <= 15; ++i) {
if (fp->ipend & (1 << i)) {
decode_address(buf, bfin_read32(EVT0 + 4*i));
printf(" RETX: %s\n", buf);
decode_address(buf, fp->rets);
printf(" RETS: %s\n", buf);
+ /* we lie and store RETI in "pc" */
decode_address(buf, fp->pc);
- printf(" PC : %s\n", buf);
+ printf(" RETI: %s\n", buf);
if (fp->seqstat & EXCAUSE) {
decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
);
dump(regs);
dump_bfin_trace_buffer();
- printf(
- "\n"
- "Please reset the board\n"
- "\n"
- );
+ puts("\n");
bfin_reset_or_hang();
}
These knobs control the timeouts during initial connection to the TFTP
server. Since a transfer is attempted during each boot, it is undesirable to
have a long delay when a TFTP server is not present.
- CONFIG_UPDATE_TFTP_MSEC_MAX specifies the number of seconds to wait for the
- server to respond to initial connection, and CONFIG_UPDATE_TFTP_CNT_MAX
+ CONFIG_UPDATE_TFTP_MSEC_MAX specifies the number of milliseconds to wait for
+ the server to respond to initial connection, and CONFIG_UPDATE_TFTP_CNT_MAX
gives the number of such connection retries. CONFIG_UPDATE_TFTP_CNT_MAX must
be non-negative and is 0 by default, CONFIG_UPDATE_TFTP_MSEC_MAX must be
- positive and is 1 by default.
+ positive and is 100 by default.
Since the update file is in FIT format, it is created from an *.its file using
the mkimage tool. dtc tool with support for binary includes, e.g. in version
#define NUM_SECS_IN_HR HRS_TO_SECS(1)
#define NUM_SECS_IN_DAY DAYS_TO_SECS(1)
+/* Enable the RTC prescaler enable register */
+static void rtc_init(void)
+{
+ if (!(bfin_read_RTC_PREN() & 0x1))
+ bfin_write_RTC_PREN(0x1);
+}
+
/* Our on-chip RTC has no notion of "reset" */
void rtc_reset(void)
{
- return;
+ rtc_init();
}
/* Wait for pending writes to complete */
bfin_write_RTC_ISTAT(WRITE_COMPLETE);
}
-/* Enable the RTC prescaler enable register */
-int rtc_init(void)
-{
- pr_stamp();
- bfin_write_RTC_PREN(0x1);
- return 0;
-}
-
/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
* based on this value.
*/
return -1;
}
+ rtc_init();
wait_for_complete();
/* Calculate number of seconds this incoming time represents */
return -1;
}
+ rtc_init();
wait_for_complete();
/* Read the RTC_STAT register */
#define CONFIG_SYS_BFIN_CMD_OTP 0x04
#define CONFIG_SYS_BFIN_CMD_CACHE_DUMP 0x08
-/* Bootmode defines -- your config needs to select this via BFIN_BOOT_MODE.
+/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
* Depending on your cpu, some of these may not be valid, check your HRM.
* The actual values here are meaningless as long as they're unique.
*/
#define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */
#define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */
#define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */
+#define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */
#endif
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#endif
-#if defined(CONFIG_BF561)
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */
-#else
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */
-#endif
#endif /* _CPLB_H */
#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define DSPID 0xFFE05000
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#endif /* __BFIN_CDEF_ADSP_BF523_proc__ */
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define DSPID 0xFFE05000
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define DSPID 0xFFE05000
#define USB_FADDR 0xFFC03800 /* Function address register */
#define USB_POWER 0xFFC03804 /* Power management register */
#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define DSPID 0xFFE05000
#define USB_FADDR 0xFFC03800 /* Function address register */
#define USB_POWER 0xFFC03804 /* Power management register */
#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define DSPID 0xFFE05000
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define DSPID 0xFFE05000
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
* File: include/asm-blackfin/mach-bf527/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
- * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
+ * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (1)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
#define ANOMALY_05000337 (1)
-/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
+/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
+#define ANOMALY_05000341 (1)
+/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
#define ANOMALY_05000342 (1)
-/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
+/* USB Calibration Value Is Not Initialized */
+#define ANOMALY_05000346 (1)
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (1)
+/* Security Features Are Not Functional */
+#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (1)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* Incorrect Revision Number in DSPID Register */
+#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* New Feature: Higher Default CCLK Rate */
+#define ANOMALY_05000368 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
+/* Authentication Fails To Initiate */
+#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
+/* Data Read From L3 Memory by USB DMA May be Corrupted */
+#define ANOMALY_05000380 (1)
+/* USB Full-speed Mode not Fully Tested */
+#define ANOMALY_05000381 (1)
+/* New Feature: Boot from OTP Memory */
+#define ANOMALY_05000385 (1)
+/* New Feature: bfrom_SysControl() Routine */
+#define ANOMALY_05000386 (1)
+/* New Feature: Programmable Preboot Settings */
+#define ANOMALY_05000387 (1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (1)
+/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (1)
+/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (1)
+/* New Feature: Log Buffer Functionality */
+#define ANOMALY_05000394 (1)
+/* New Feature: Hook Routine Functionality */
+#define ANOMALY_05000395 (1)
+/* New Feature: Header Indirect Bit */
+#define ANOMALY_05000396 (1)
+/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
+#define ANOMALY_05000397 (1)
+/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
+#define ANOMALY_05000398 (1)
+/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
+#define ANOMALY_05000399 (1)
+/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
+#define ANOMALY_05000401 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
+#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000363 (0)
#endif
* File: include/asm-blackfin/mach-bf533/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
- * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
#define ANOMALY_05000315 (1)
/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
+/* PPI Does Not Start Properly In Specific Mode */
+#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
/* Internal Voltage Regulator may not start up */
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000266 (0)
#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
#endif
#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define DSPID 0xFFE05000
#define CHIPID 0xFFC00014
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
* File: include/asm-blackfin/mach-bf537/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
- * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000322 (1)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
+/* New Feature: UART Remains Enabled after UART Boot */
+#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000359 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000363 (0)
#endif
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
* File: include/asm-blackfin/mach-bf548/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
- * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ * - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
/* Synchronous Burst Flash Boot Mode Is Not Functional */
#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Mode Is Not Functional */
+/* Host DMA Boot Modes Are Not Functional */
#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Intialized */
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
/* Data Lost when Core Reads SDH Data FIFO */
#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
/* PLL Status Register Is Inaccurate */
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
+#define ANOMALY_05000353 (1)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
+/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
+#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* External Memory Read Access Hangs Core With PLL Bypass */
#define ANOMALY_05000360 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000365 (1)
+/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
+#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
#define ANOMALY_05000369 (1)
+/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
+#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000371 (1)
+/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
+#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
/* Mobile DDR Operation Not Functional */
#define ANOMALY_05000377 (1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
#define ANOMALY_05000378 (1)
+/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
+#define ANOMALY_05000379 (1)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
+/* Some ATAPI Modes Are Not Functional */
+#define ANOMALY_05000383 (1)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
+/* Changed Meaning of BCODE Field in SYSCR Register */
+#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
+/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
+#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
+/* Lockbox SESR Disallows Certain User Interrupts */
+#define ANOMALY_05000404 (1)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
+#define ANOMALY_05000406 (1)
+/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
+#define ANOMALY_05000407 (1)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Lockbox firmware leaves MDMA0 channel enabled */
+#define ANOMALY_05000409 (1)
+/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
+#define ANOMALY_05000411 (1)
+/* FIFO Boot Mode Is Not Functional */
+#define ANOMALY_05000412 (1)
+/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
+#define ANOMALY_05000413 (1)
+/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
+#define ANOMALY_05000414 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
+#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
+#define ANOMALY_05000363 (0)
#endif
#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16)
+#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16)
+#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16)
+#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16)
+#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18)
+#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18)
+#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18)
+#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18)
+#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20)
+#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20)
+#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20)
+#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20)
+#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22)
+#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22)
+#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22)
+#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22)
+#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24)
+#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24)
+#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24)
+#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24)
+#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26)
+#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26)
+#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26)
+#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26)
+#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28)
+#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28)
+#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28)
+#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28)
+#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30)
+#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30)
+#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
+#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
/* Port A Masks */
#define PA0 0x0001
#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1)
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pSICA_SWRST ((uint32_t volatile *)SICA_SWRST)
-#define bfin_read_SICA_SWRST() bfin_read32(SICA_SWRST)
-#define bfin_write_SICA_SWRST(val) bfin_write32(SICA_SWRST, val)
+#define pSICA_SWRST ((uint16_t volatile *)SICA_SWRST)
+#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
+#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val)
#define pSICA_SYSCR ((uint32_t volatile *)SICA_SYSCR)
#define bfin_read_SICA_SYSCR() bfin_read32(SICA_SYSCR)
#define bfin_write_SICA_SYSCR(val) bfin_write32(SICA_SYSCR, val)
#define pSICA_IAR7 ((uint32_t volatile *)SICA_IAR7)
#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7, val)
-#define pSICB_SWRST ((uint32_t volatile *)SICB_SWRST)
-#define bfin_read_SICB_SWRST() bfin_read32(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val) bfin_write32(SICB_SWRST, val)
+#define pSICB_SWRST ((uint16_t volatile *)SICB_SWRST)
+#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
+#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val)
#define pSICB_SYSCR ((uint32_t volatile *)SICB_SYSCR)
#define bfin_read_SICB_SYSCR() bfin_read32(SICB_SYSCR)
#define bfin_write_SICB_SYSCR(val) bfin_write32(SICB_SYSCR, val)
#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE)
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
-#define pDBGSTAT ((uint32_t volatile *)DBGSTAT)
-#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
#define pUART_THR ((uint16_t volatile *)UART_THR)
#define bfin_read_UART_THR() bfin_read16(UART_THR)
#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val)
#define SRAM_BASE_ADDR_CORE_A 0xFFE00000
#define SRAM_BASE_ADDR_CORE_B 0xFFE00000
#define EVT_OVERRIDE 0xFFE02100
-#define DSPID 0xFFE05000
-#define DBGSTAT 0xFFE05008
#define UART_THR 0xFFC00400
#define UART_RBR 0xFFC00400
#define UART_DLL 0xFFC00400
* File: include/asm-blackfin/mach-bf561/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
- * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
+ * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000357 (1)
/* Conflicting Column Address Widths Causes SDRAM Errors */
#define ANOMALY_05000362 (1)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000158 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
+#define ANOMALY_05000353 (1)
#endif
#define pWPSTAT ((uint32_t volatile *)WPSTAT)
#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val)
+#define pDSPID ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID() bfin_read32(DSPID)
+#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
+#define pDBGSTAT ((uint32_t volatile *)DBGSTAT)
+#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
+#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
#endif /* __BFIN_CDEF_ADSP_EDN_core__ */
#define WPDACNT0 0xFFE07180
#define WPDACNT1 0xFFE07184
#define WPSTAT 0xFFE07200
+#define DSPID 0xFFE05000
+#define DBGSTAT 0xFFE05008
#endif /* __BFIN_DEF_ADSP_EDN_core__ */
#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pSWRST ((uint32_t volatile *)SWRST) /* Software Reset Register (16-bit) */
-#define bfin_read_SWRST() bfin_read32(SWRST)
-#define bfin_write_SWRST(val) bfin_write32(SWRST, val)
+#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
+#define bfin_read_SWRST() bfin_read16(SWRST)
+#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
#define pSYSCR ((uint32_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read32(SYSCR)
#define bfin_write_SYSCR(val) bfin_write32(SYSCR, val)
#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE)
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR 0xFFC00104 /* System Configuration register */
#define EVT_OVERRIDE 0xFFE02100
-#define DSPID 0xFFE05000
#define CHIPID 0xFFC00014
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
+++ /dev/null
-/*
- * U-boot - mem_init.h Header file for memory initialization
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
- CONFIG_MEM_MT48LC64M4A2FB_7E || \
- CONFIG_MEM_MT48LC16M8A2TG_75 || \
- CONFIG_MEM_MT48LC8M16A2TG_7E || \
- CONFIG_MEM_MT48LC8M32B2B5_7 || \
- CONFIG_MEM_MT48LC32M8A2_75)
-
- #if ( CONFIG_SCLK_HZ > 119402985 )
- #define SDRAM_tRP TRP_2
- #define SDRAM_tRP_num 2
- #define SDRAM_tRAS TRAS_7
- #define SDRAM_tRAS_num 7
- #define SDRAM_tRCD TRCD_2
- #define SDRAM_tWR TWR_2
- #endif
- #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
- #define SDRAM_tRP TRP_2
- #define SDRAM_tRP_num 2
- #define SDRAM_tRAS TRAS_6
- #define SDRAM_tRAS_num 6
- #define SDRAM_tRCD TRCD_2
- #define SDRAM_tWR TWR_2
- #endif
- #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
- #define SDRAM_tRP TRP_2
- #define SDRAM_tRP_num 2
- #define SDRAM_tRAS TRAS_5
- #define SDRAM_tRAS_num 5
- #define SDRAM_tRCD TRCD_2
- #define SDRAM_tWR TWR_2
- #endif
- #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 )
- #define SDRAM_tRP TRP_2
- #define SDRAM_tRP_num 2
- #define SDRAM_tRAS TRAS_4
- #define SDRAM_tRAS_num 4
- #define SDRAM_tRCD TRCD_2
- #define SDRAM_tWR TWR_2
- #endif
- #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
- #define SDRAM_tRP TRP_2
- #define SDRAM_tRP_num 2
- #define SDRAM_tRAS TRAS_3
- #define SDRAM_tRAS_num 3
- #define SDRAM_tRCD TRCD_2
- #define SDRAM_tWR TWR_2
- #endif
- #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
- #define SDRAM_tRP TRP_1
- #define SDRAM_tRP_num 1
- #define SDRAM_tRAS TRAS_3
- #define SDRAM_tRAS_num 3
- #define SDRAM_tRCD TRCD_1
- #define SDRAM_tWR TWR_2
- #endif
- #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 )
- #define SDRAM_tRP TRP_1
- #define SDRAM_tRP_num 1
- #define SDRAM_tRAS TRAS_3
- #define SDRAM_tRAS_num 3
- #define SDRAM_tRCD TRCD_1
- #define SDRAM_tWR TWR_2
- #endif
- #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 )
- #define SDRAM_tRP TRP_1
- #define SDRAM_tRP_num 1
- #define SDRAM_tRAS TRAS_2
- #define SDRAM_tRAS_num 2
- #define SDRAM_tRCD TRCD_1
- #define SDRAM_tWR TWR_2
- #endif
- #if ( CONFIG_SCLK_HZ <= 29850746 )
- #define SDRAM_tRP TRP_1
- #define SDRAM_tRP_num 1
- #define SDRAM_tRAS TRAS_1
- #define SDRAM_tRAS_num 1
- #define SDRAM_tRCD TRCD_1
- #define SDRAM_tWR TWR_2
- #endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
- /*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
- #define SDRAM_CL CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
- /*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
- #define SDRAM_CL CL_2
-#endif
-
-#if (CONFIG_MEM_MT48LC16M8A2TG_75)
- /*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
- #define SDRAM_CL CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M8A2_75)
-/*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
- /*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
- #define SDRAM_CL CL_2
-#endif
-
-#if (CONFIG_MEM_MT48LC8M32B2B5_7)
- /*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
- #define SDRAM_CL CL_3
-#endif
-
-#if ( CONFIG_MEM_SIZE == 128 )
- #define SDRAM_SIZE EBSZ_128
-#endif
-#if ( CONFIG_MEM_SIZE == 64 )
- #define SDRAM_SIZE EBSZ_64
-#endif
-#if ( CONFIG_MEM_SIZE == 32 )
- #define SDRAM_SIZE EBSZ_32
-#endif
-#if ( CONFIG_MEM_SIZE == 16 )
- #define SDRAM_SIZE EBSZ_16
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 11 )
- #define SDRAM_WIDTH EBCAW_11
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 10 )
- #define SDRAM_WIDTH EBCAW_10
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 9 )
- #define SDRAM_WIDTH EBCAW_9
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 8 )
- #define SDRAM_WIDTH EBCAW_8
-#endif
-
-#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
-
-#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) )
-#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3 )
- #define flash_EBIU_AMBCTL0_TT B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3 )
- #define flash_EBIU_AMBCTL0_TT B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2 )
- #define flash_EBIU_AMBCTL0_TT B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2 )
- #define flash_EBIU_AMBCTL0_TT B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3 )
- #define flash_EBIU_AMBCTL0_ST B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3 )
- #define flash_EBIU_AMBCTL0_ST B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2 )
- #define flash_EBIU_AMBCTL0_ST B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2 )
- #define flash_EBIU_AMBCTL0_ST B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2 )
- #define flash_EBIU_AMBCTL0_HT B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2 )
- #define flash_EBIU_AMBCTL0_HT B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1 )
- #define flash_EBIU_AMBCTL0_HT B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
- #define flash_EBIU_AMBCTL0_HT B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
- #define flash_EBIU_AMBCTL0_HT B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
- #define flash_EBIU_AMBCTL0_WAT B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
- #define flash_EBIU_AMBCTL0_RAT B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
extern int exception_init(void);
extern int irq_init(void);
-extern int rtc_init(void);
extern int timer_init(void);
void board_init_f(ulong bootflag)
display_banner();
checkboard();
-#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE)
- rtc_init();
-#endif
timer_init();
printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n",
spi_init_r();
#endif
+#ifdef CONFIG_CMD_NAND
+ puts("NAND: ");
+ nand_init(); /* go init the NAND */
+#endif
+
/* relocate environment function pointers etc. */
env_relocate();
copy_filename(BootFile, s, sizeof(BootFile));
#endif
-#ifdef CONFIG_CMD_NAND
- puts("NAND: ");
- nand_init(); /* go init the NAND */
-#endif
-
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#include <common.h>
#include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
void flush_cache(unsigned long addr, unsigned long size)
{
if (dcache_status())
blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
}
+
+void icache_enable(void)
+{
+ bfin_write_IMEM_CONTROL(IMC | ENICPLB);
+ SSYNC();
+}
+
+void icache_disable(void)
+{
+ bfin_write_IMEM_CONTROL(0);
+ SSYNC();
+}
+
+int icache_status(void)
+{
+ return bfin_read_IMEM_CONTROL() & IMC;
+}
+
+void dcache_enable(void)
+{
+ bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+ SSYNC();
+}
+
+void dcache_disable(void)
+{
+ bfin_write_DMEM_CONTROL(0);
+ SSYNC();
+}
+
+int dcache_status(void)
+{
+ return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
+}
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