cpu/mips/cpu.c: Fix flush_cache bug

Cache operations have to take line address (addr), not start_addr.
I noticed this bug when debugging ping failure.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>

diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 8b43d8eb36281c0522e58649c852c0e28d96151a..e267bba4691e281faf45e307594149c97a4ae05b 100644 (file)
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -56,8 +56,8 @@ void flush_cache(ulong start_addr, ulong size)
        unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
        while (1) {
-               cache_op(Hit_Writeback_Inv_D, start_addr);
-               cache_op(Hit_Invalidate_I, start_addr);
+               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(Hit_Invalidate_I, addr);
                if (addr == aend)
                        break;
                addr += lsize;