Tegra30: MMC: Add SD bus power-rail and SDMMC pad init routines

T30 requires specific SDMMC pad programming, and bus power-rail bringup.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
index 08e9b7bd5be83ded23930562e4b4b3ed19ba903a..3544b41cd02386013d0509363abcefde8f2ea41a 100644 (file)
--- a/board/nvidia/cardhu/cardhu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -25,6 +25,10 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/gp_padctrl.h>
 #include "pinmux-config-cardhu.h"
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS                0x2D
+#define MAX_I2C_RETRY          3
 
 /*
  * Routine: pinmux_init
@@ -41,3 +45,50 @@ void pinmux_init(void)
        /* Initialize any non-default pad configs (APB_MISC_GP regs) */
        padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
 }
+
+#if defined(CONFIG_TEGRA_MMC)
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+       uchar reg, data_buffer[1];
+       int i;
+
+       i2c_set_bus_num(0);     /* PMU is on bus 0 */
+
+       /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
+       data_buffer[0] = 0x65;
+       reg = 0x32;
+
+       for (i = 0; i < MAX_I2C_RETRY; ++i) {
+               if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+                       udelay(100);
+       }
+
+       /* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */
+       data_buffer[0] = 0x09;
+       reg = 0x67;
+
+       for (i = 0; i < MAX_I2C_RETRY; ++i) {
+               if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+                       udelay(100);
+       }
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+       /*
+        * NOTE: We don't do mmc-specific pin muxes here.
+        * They were done globally in pinmux_init().
+        */
+
+       /* Bring up the SDIO1 power rail */
+       board_sdmmc_voltage_init();
+}
+#endif /* MMC */

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index babbe08e06a719343d69abd12082d9404f7601f7..7d9f361a8abeb50ca870de9114048351ac7bf289 100644 (file)
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -49,6 +49,7 @@
 #include <asm/arch-tegra/usb.h>
 #endif
 #ifdef CONFIG_TEGRA_MMC
+#include <asm/arch-tegra/tegra_mmc.h>
 #include <asm/arch-tegra/mmc.h>
 #endif
 #include <i2c.h>
@@ -245,4 +246,32 @@ int board_mmc_init(bd_t *bd)
 
        return 0;
 }
-#endif
+
+void pad_init_mmc(struct mmc_host *host)
+{
+#if defined(CONFIG_TEGRA30)
+       enum periph_id id = host->mmc_id;
+       u32 val;
+
+       debug("%s: sdmmc address = %08x, id = %d\n", __func__,
+               (unsigned int)host->reg, id);
+
+       /* Set the pad drive strength for SDMMC1 or 3 only */
+       if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
+               debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
+                       __func__);
+               return;
+       }
+
+       val = readl(&host->reg->sdmemcmppadctl);
+       val &= 0xFFFFFFF0;
+       val |= MEMCOMP_PADCTRL_VREF;
+       writel(val, &host->reg->sdmemcmppadctl);
+
+       val = readl(&host->reg->autocalcfg);
+       val &= 0xFFFF0000;
+       val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+       writel(val, &host->reg->autocalcfg);
+#endif /* T30 */
+}
+#endif /* MMC */