driver/ddr/fsl: Update DDR4 RTT values

DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 3c09c643febd87085957a865a237f30381d5c674..791d6441010ae43e637838248ac47c8e9f80256f 100644 (file)
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -29,7 +29,240 @@ struct dynamic_odt {
        unsigned int odt_rtt_wr;
 };
 
-#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+#ifdef CONFIG_SYS_FSL_DDR4
+/* Quad rank is not verified yet due availability.
+ * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
+ */
+static const struct dynamic_odt single_Q[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_CS_AND_OTHER_DIMM,
+               DDR4_RTT_34_OHM,        /* unverified */
+               DDR4_RTT_120_OHM
+       },
+       {       /* cs1 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_NEVER,
+               DDR4_RTT_OFF,
+               DDR4_RTT_120_OHM
+       },
+       {       /* cs2 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_CS_AND_OTHER_DIMM,
+               DDR4_RTT_34_OHM,
+               DDR4_RTT_120_OHM
+       },
+       {       /* cs3 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_NEVER,      /* tied high */
+               DDR4_RTT_OFF,
+               DDR4_RTT_120_OHM
+       }
+};
+
+static const struct dynamic_odt single_D[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_ALL,
+               DDR4_RTT_40_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs1 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_NEVER,
+               DDR4_RTT_OFF,
+               DDR4_RTT_OFF
+       },
+       {0, 0, 0, 0},
+       {0, 0, 0, 0}
+};
+
+static const struct dynamic_odt single_S[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_ALL,
+               DDR4_RTT_40_OHM,
+               DDR4_RTT_OFF
+       },
+       {0, 0, 0, 0},
+       {0, 0, 0, 0},
+       {0, 0, 0, 0},
+};
+
+static const struct dynamic_odt dual_DD[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_SAME_DIMM,
+               DDR4_RTT_120_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs1 */
+               FSL_DDR_ODT_OTHER_DIMM,
+               FSL_DDR_ODT_OTHER_DIMM,
+               DDR4_RTT_34_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs2 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_SAME_DIMM,
+               DDR4_RTT_120_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs3 */
+               FSL_DDR_ODT_OTHER_DIMM,
+               FSL_DDR_ODT_OTHER_DIMM,
+               DDR4_RTT_34_OHM,
+               DDR4_RTT_OFF
+       }
+};
+
+static const struct dynamic_odt dual_DS[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_SAME_DIMM,
+               DDR4_RTT_120_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs1 */
+               FSL_DDR_ODT_OTHER_DIMM,
+               FSL_DDR_ODT_OTHER_DIMM,
+               DDR4_RTT_34_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs2 */
+               FSL_DDR_ODT_OTHER_DIMM,
+               FSL_DDR_ODT_ALL,
+               DDR4_RTT_34_OHM,
+               DDR4_RTT_120_OHM
+       },
+       {0, 0, 0, 0}
+};
+static const struct dynamic_odt dual_SD[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_OTHER_DIMM,
+               FSL_DDR_ODT_ALL,
+               DDR4_RTT_34_OHM,
+               DDR4_RTT_120_OHM
+       },
+       {0, 0, 0, 0},
+       {       /* cs2 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_SAME_DIMM,
+               DDR4_RTT_120_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs3 */
+               FSL_DDR_ODT_OTHER_DIMM,
+               FSL_DDR_ODT_OTHER_DIMM,
+               DDR4_RTT_34_OHM,
+               DDR4_RTT_OFF
+       }
+};
+
+static const struct dynamic_odt dual_SS[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_OTHER_DIMM,
+               FSL_DDR_ODT_ALL,
+               DDR4_RTT_34_OHM,
+               DDR4_RTT_120_OHM
+       },
+       {0, 0, 0, 0},
+       {       /* cs2 */
+               FSL_DDR_ODT_OTHER_DIMM,
+               FSL_DDR_ODT_ALL,
+               DDR4_RTT_34_OHM,
+               DDR4_RTT_120_OHM
+       },
+       {0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_D0[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_SAME_DIMM,
+               DDR4_RTT_40_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs1 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_NEVER,
+               DDR4_RTT_OFF,
+               DDR4_RTT_OFF
+       },
+       {0, 0, 0, 0},
+       {0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_0D[4] = {
+       {0, 0, 0, 0},
+       {0, 0, 0, 0},
+       {       /* cs2 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_SAME_DIMM,
+               DDR4_RTT_40_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs3 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_NEVER,
+               DDR4_RTT_OFF,
+               DDR4_RTT_OFF
+       }
+};
+
+static const struct dynamic_odt dual_S0[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_CS,
+               DDR4_RTT_40_OHM,
+               DDR4_RTT_OFF
+       },
+       {0, 0, 0, 0},
+       {0, 0, 0, 0},
+       {0, 0, 0, 0}
+
+};
+
+static const struct dynamic_odt dual_0S[4] = {
+       {0, 0, 0, 0},
+       {0, 0, 0, 0},
+       {       /* cs2 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_CS,
+               DDR4_RTT_40_OHM,
+               DDR4_RTT_OFF
+       },
+       {0, 0, 0, 0}
+
+};
+
+static const struct dynamic_odt odt_unknown[4] = {
+       {       /* cs0 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_CS,
+               DDR4_RTT_120_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs1 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_CS,
+               DDR4_RTT_120_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs2 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_CS,
+               DDR4_RTT_120_OHM,
+               DDR4_RTT_OFF
+       },
+       {       /* cs3 */
+               FSL_DDR_ODT_NEVER,
+               FSL_DDR_ODT_CS,
+               DDR4_RTT_120_OHM,
+               DDR4_RTT_OFF
+       }
+};
+#elif defined(CONFIG_SYS_FSL_DDR3)
 static const struct dynamic_odt single_Q[4] = {
        {       /* cs0 */
                FSL_DDR_ODT_NEVER,
@@ -259,7 +492,7 @@ static const struct dynamic_odt odt_unknown[4] = {
                DDR3_RTT_OFF
        }
 };
-#else  /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */
+#else  /* CONFIG_SYS_FSL_DDR3 */
 static const struct dynamic_odt single_Q[4] = {
        {0, 0, 0, 0},
        {0, 0, 0, 0},

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index c79fce089826f65cc6a5aa7ceddc3d6ab63e30d4..4b022d46391a50f8eb1b56d0f6c849231ccec5c6 100644 (file)
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -33,6 +33,15 @@
 #define DDR3_RTT_20_OHM                4 /* RTT_Nom = RZQ/12 */
 #define DDR3_RTT_30_OHM                5 /* RTT_Nom = RZQ/8 */
 
+#define DDR4_RTT_OFF           0
+#define DDR4_RTT_60_OHM                1       /* RZQ/4 */
+#define DDR4_RTT_120_OHM       2       /* RZQ/2 */
+#define DDR4_RTT_40_OHM                3       /* RZQ/6 */
+#define DDR4_RTT_240_OHM       4       /* RZQ/1 */
+#define DDR4_RTT_48_OHM                5       /* RZQ/5 */
+#define DDR4_RTT_80_OHM                6       /* RZQ/3 */
+#define DDR4_RTT_34_OHM                7       /* RZQ/7 */
+
 #define DDR2_RTT_OFF           0
 #define DDR2_RTT_75_OHM                1
 #define DDR2_RTT_150_OHM       2