]> git.sur5r.net Git - u-boot/commitdiff
imx: mx6 add i2c4 clock support for i.MX6SX
authorPeng Fan <Peng.Fan@freescale.com>
Wed, 1 Jul 2015 09:01:50 +0000 (17:01 +0800)
committerStefano Babic <sbabic@denx.de>
Fri, 10 Jul 2015 07:36:16 +0000 (09:36 +0200)
Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.

Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/crm_regs.h

index 113477028648ece073176b7699813420d7c6e04c..b4618989d9b66108fea2e22bc8000e0bfe6ed2e6 100644 (file)
@@ -126,6 +126,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
        u32 reg;
        u32 mask;
+       u32 *addr;
 
        if (i2c_num > 3)
                return -EINVAL;
@@ -140,14 +141,19 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
                        reg &= ~mask;
                __raw_writel(reg, &imx_ccm->CCGR2);
        } else {
-               mask = MXC_CCM_CCGR_CG_MASK
-                       << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
-               reg = __raw_readl(&imx_ccm->CCGR1);
+               if (is_cpu_type(MXC_CPU_MX6SX)) {
+                       mask = MXC_CCM_CCGR6_I2C4_MASK;
+                       addr = &imx_ccm->CCGR6;
+               } else {
+                       mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
+                       addr = &imx_ccm->CCGR1;
+               }
+               reg = __raw_readl(addr);
                if (enable)
                        reg |= mask;
                else
                        reg &= ~mask;
-               __raw_writel(reg, &imx_ccm->CCGR1);
+               __raw_writel(reg, addr);
        }
        return 0;
 }
index 887d04850f63f242948298dff167d41ad7b1c8be..98415ace022e1e66f6d32b193c15f345112d1340 100644 (file)
@@ -740,7 +740,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR6_USDHC4_MASK              (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET          10
 #define MXC_CCM_CCGR6_EMI_SLOW_MASK            (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
-#ifdef CONFIG_MX6SX
+/* The following *CCGR6* exist only i.MX6SX */
 #define MXC_CCM_CCGR6_PWM8_OFFSET              16
 #define MXC_CCM_CCGR6_PWM8_MASK                        (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
 #define MXC_CCM_CCGR6_VADC_OFFSET              20
@@ -755,10 +755,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR6_PWM6_MASK                        (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
 #define MXC_CCM_CCGR6_PWM7_OFFSET              30
 #define MXC_CCM_CCGR6_PWM7_MASK                        (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
-#else
+/* The two does not exist on i.MX6SX */
 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET         12
 #define MXC_CCM_CCGR6_VDOAXICLK_MASK           (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
-#endif
 
 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
 #define BP_ANADIG_PLL_SYS_RSVD0      20