#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
+#define DAVINCI_DDR_BASE (0x80000000)
#ifdef CONFIG_SOC_DM644X
#define DAVINCI_UART2_BASE 0x01c20800
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
#define DAVINCI_MMC_SD0_BASE 0x01e11000
+#elif defined(CONFIG_SOC_DM365)
+#define DAVINCI_MMC_SD1_BASE 0x01d00000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
+#define DAVINCI_MMC_SD0_BASE 0x01d11000
+
#endif
/* Power and Sleep Controller (PSC) Domains */