]> git.sur5r.net Git - u-boot/commitdiff
mpc83xx: turn on icache in core initialization to improve u-boot boot time
authorKim Phillips <kim.phillips@freescale.com>
Wed, 21 Apr 2010 00:37:54 +0000 (19:37 -0500)
committerKim Phillips <kim.phillips@freescale.com>
Thu, 22 Apr 2010 23:44:56 +0000 (18:44 -0500)
before, MPC8349ITX boots u-boot in 4.3sec:

        column1 is elapsed time since first message
        column2 is elapsed time since previous message
        column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA:  Configured for compact flash
0.032 0.000: I2C:   ready
0.061 0.028: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI:   Bus Dev VenId DevId Class Int
2.652 0.011:         00  10  1095  3114  0180  00
2.652 0.000: PCI:   Bus Dev VenId DevId Class Int
2.652 0.000: In:    serial
2.652 0.000: Out:   serial
2.652 0.000: Err:   serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE:   Bus 0: .** Timeout **

after, MPC8349ITX boots u-boot in 3.0sec:

0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA:  Configured for compact flash
0.038 0.000: I2C:   ready
0.038 0.000: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI:   Bus Dev VenId DevId Class Int
1.390 0.000:         00  10  1095  3114  0180  00
1.390 0.000: PCI:   Bus Dev VenId DevId Class Int
1.400 0.010: In:    serial
1.400 0.000: Out:   serial
1.400 0.000: Err:   serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE:   Bus 0: .** Timeout **

also tested on these boards (albeit with a less accurate
boottime measurement method):

seconds: before  after
8349MDS  ~2.6    ~2.2
8360MDS  ~2.8    ~2.6
8313RDB  ~2.5    ~2.3 #nand boot
837xRDB  ~3.1    ~2.3

also tested on an 8323ERDB.

v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
17 files changed:
arch/powerpc/lib/board.c
include/configs/MPC8313ERDB.h
include/configs/MPC8315ERDB.h
include/configs/MPC8323ERDB.h
include/configs/MPC832XEMDS.h
include/configs/MPC8349EMDS.h
include/configs/MPC8349ITX.h
include/configs/MPC8360EMDS.h
include/configs/MPC8360ERDK.h
include/configs/MPC837XEMDS.h
include/configs/MPC837XERDB.h
include/configs/MVBLM7.h
include/configs/SIMPC8313.h
include/configs/TQM834x.h
include/configs/kmeter1.h
include/configs/sbc8349.h
include/configs/vme8349.h

index a30acee4febf5ee5c675953cfd2feeacfa8da8e7..7b09fb51e25d18a8bd865c0ddf2cd4d5298a2b42 100644 (file)
@@ -686,7 +686,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
        WATCHDOG_RESET();
 
-#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx)
+#if defined(CONFIG_SYS_DELAYED_ICACHE)
        icache_enable ();       /* it's time to enable the instruction cache */
 #endif
 
index a2e4cd46fa3f827e5cda4a6d2821a7c13f95e75b..94695fc285d6ccdce7765db363558140deeeb02f 100644 (file)
 
 #define CONFIG_SYS_HID0_INIT   0x000000000
 #define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
-                        HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+                                HID0_ENABLE_INSTRUCTION_CACHE | \
+                                HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 
 #define CONFIG_SYS_HID2 HID2_HBE
 
index b106aa9c10d36de7b48899562904e34566e199db..6972fe8cd14d1e3a1b3b933da0041f87e58f8ece 100644 (file)
 /*
  * Core HID Setup
  */
-#define CONFIG_SYS_HID0_INIT           0x000000000
-#define CONFIG_SYS_HID0_FINAL          (HID0_ENABLE_MACHINE_CHECK | \
+#define CONFIG_SYS_HID0_INIT   0x000000000
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE | \
                                 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 #define CONFIG_SYS_HID2                HID2_HBE
 
index 50aea79e67fc8738594a34cadcbd4c452748c3f4..7c843939c280fa44504bc30e3dfedd5ce2f2ac50 100644 (file)
 /*
  * Core HID Setup
  */
-#define CONFIG_SYS_HID0_INIT           0x000000000
-#define CONFIG_SYS_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT   0x000000000
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2                HID2_HBE
 
 /*
index f7632e0d9683335f4067c32c0fa4875c51782277..7bd279369e4149c6dca158392e4604cdfda8f502 100644 (file)
 /*
  * Core HID Setup
  */
-#define CONFIG_SYS_HID0_INIT           0x000000000
-#define CONFIG_SYS_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT   0x000000000
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2                HID2_HBE
 
 /*
index 5c410c9e5009b00418c09d93768871e5978343c3..73dbea4b74111f0a286466039f8b4c11bd22a77d 100644 (file)
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 
 #define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 
 /* #define CONFIG_SYS_HID0_FINAL               (\
        HID0_ENABLE_INSTRUCTION_CACHE |\
index 09f9e38470f639743f615fa7bb6ec382dca712d9..9be571fecf5bc47c775f2809266ea8b820f9b079 100644 (file)
@@ -63,6 +63,7 @@
 /*
  * High Level Configuration Options
  */
+#define CONFIG_MPC83xx         1
 #define CONFIG_MPC834x         /* MPC834x family (8343, 8347, 8349) */
 #define CONFIG_MPC8349         /* MPC8349 specific */
 
@@ -596,8 +597,8 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_SICRH SICRH_TSOBI1  /* Needed for gigabit to work on TSEC 1 */
 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)    /* USB DR as device + USB MPH as host */
 
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID0_INIT   0x00000000
+#define CONFIG_SYS_HID0_FINAL  HID0_ENABLE_INSTRUCTION_CACHE
 
 #define CONFIG_SYS_HID2        HID2_HBE
 #define CONFIG_HIGH_BATS       1       /* High BATs supported */
index 620e32cda48b56c70b1896e59014146b8baf397d..87a137b3a33cca616b6b5f80219c200383e8f947 100644 (file)
 /*
  * Core HID Setup
  */
-#define CONFIG_SYS_HID0_INIT           0x000000000
-#define CONFIG_SYS_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT   0x000000000
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2                HID2_HBE
 
 /*
index a43e465520309c119b29ff29b2fd7b1c0f07357d..e78cf60a109ffb9d08aa71831e2c1f9839288240 100644 (file)
 /*
  * Core HID Setup
  */
-#define CONFIG_SYS_HID0_INIT           0x000000000
-#define CONFIG_SYS_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT   0x000000000
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2                HID2_HBE
 
 /*
index 1565ff94c8d40f362db3f1a7caaa66c383d09dc0..b30d0e385a492b9f0d91f4f7397e44d8dc5109e0 100644 (file)
@@ -544,8 +544,9 @@ extern int board_pci_host_broken(void);
 /*
  * Core HID Setup
  */
-#define CONFIG_SYS_HID0_INIT           0x000000000
-#define CONFIG_SYS_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT   0x000000000
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2                HID2_HBE
 
 /*
index 97a05a293dc819d1513c2a083e0f9ffc861cf660..1654f46a46574ee97063a06c697040b5be8c5311 100644 (file)
 /*
  * Core HID Setup
  */
-#define CONFIG_SYS_HID0_INIT           0x000000000
-#define CONFIG_SYS_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT   0x000000000
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2                HID2_HBE
 
 /*
index 6cc8d5876535b677cc7c1a4e0a55be1d1ce3354f..26897c69aff0635216b25f86dc4bb6a38f78a108 100644 (file)
 #define CONFIG_SYS_SICRL       (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
 
 #define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID0_FINAL  (CONFIG_SYS_HID0_INIT | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 
 #define CONFIG_SYS_HID2        HID2_HBE
 #define CONFIG_HIGH_BATS       1
index 40e89d9a5b19db92faccb4389ac8f2d483110905..84af8df9c999eec406187bfffb1c6e28e10fda33 100644 (file)
                                | SICRL_ETSEC2_A )
 
 #define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK      \
-                               | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE | \
+                                HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
 
 #define CONFIG_SYS_HID2                HID2_HBE
 
index f08c0a95eef817de0e2d01df94f3ba308638c209..c1e0e6429a234c8e7365e8e0910b83d65495e2f5 100644 (file)
@@ -405,7 +405,8 @@ extern int tqm834x_num_flash_banks;
 
 /* i-cache and d-cache disabled */
 #define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID0_FINAL  (CONFIG_SYS_HID0_INIT | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2        HID2_HBE
 
 #define CONFIG_HIGH_BATS       1       /* High BATs supported */
index d27b75b6471177755723ef5b898e532b7f4c995d..64972317fba17f518a7e9724860a613ded4e1ada 100644 (file)
  * Core HID Setup
  */
 #define CONFIG_SYS_HID0_INIT           0x000000000
-#define CONFIG_SYS_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL          (HID0_ENABLE_MACHINE_CHECK | \
+                                        HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2                        HID2_HBE
 
 /*
index 80f83ac5fa573dc7438262462e46a2b48a63bda3..deaddde3bfffacc58d25a10b2bbbd63bf52d855b 100644 (file)
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 
 #define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 
 /* #define CONFIG_SYS_HID0_FINAL               (\
        HID0_ENABLE_INSTRUCTION_CACHE |\
index cb987a1e42b1ad4751f0e83e51f797a813e34957..f493e75d6fb55754e4c3ef25ac91c47e118d08d5 100644 (file)
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 
 #define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE)
 
 #define CONFIG_SYS_HID2                HID2_HBE