rb_txdclk_pclk_en, /* value */
rb_txdclk_pclk_en, /* mask */
POLL_16B_REG); /* 16bit */
- if (ret == 0)
+ if (!ret)
printf("Failed to lock PCIe PLL\n");
debug_exit();
bs_pll_ready_tx, /* value */
bs_pll_ready_tx, /* mask */
POLL_32B_REG); /* 32bit */
- if (ret == 0)
+ if (!ret)
printf("Failed to lock SATA PLL\n");
debug_exit();
rb_txdclk_pclk_en, /* value */
rb_txdclk_pclk_en, /* mask */
POLL_16B_REG); /* 16bit */
- if (ret == 0)
+ if (!ret)
printf("Failed to lock USB3 PLL\n");
/*
rb_usb2phy_pllcal_done, /* value */
rb_usb2phy_pllcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (ret == 0)
+ if (!ret)
printf("Failed to end USB2 PLL calibration\n");
/* Assert impedance calibration done */
rb_usb2phy_impcal_done, /* value */
rb_usb2phy_impcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (ret == 0)
+ if (!ret)
printf("Failed to end USB2 impedance calibration\n");
/* Assert squetch calibration done */
rb_usb2phy_sqcal_done, /* value */
rb_usb2phy_sqcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (ret == 0)
+ if (!ret)
printf("Failed to end USB2 unknown calibration\n");
/* Assert PLL is ready */
rb_usb2phy_pll_ready, /* mask */
POLL_32B_REG); /* 32bit */
- if (ret == 0)
+ if (!ret)
printf("Failed to lock USB2 PLL\n");
debug_exit();
rb_pll_ready_tx | rb_pll_ready_rx, /* value */
rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
POLL_32B_REG); /* 32bit */
- if (ret == 0)
+ if (!ret)
printf("Failed to lock PLL for SGMII PHY %d\n", lane);
/*
rb_rx_init_done, /* value */
rb_rx_init_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (ret == 0)
+ if (!ret)
printf("Failed to init RX of SGMII PHY %d\n", lane);
debug_exit();
if (node > 0) {
if (fdtdec_get_is_enabled(blob, node)) {
ret = comphy_usb2_power_up(usb32);
- if (ret == 0)
+ if (!ret)
printf("Failed to initialize UTMI PHY\n");
else
debug("UTMI PHY init succeed\n");
if (node > 0) {
if (fdtdec_get_is_enabled(blob, node)) {
ret = comphy_sata_power_up();
- if (ret == 0)
+ if (!ret)
printf("Failed to initialize SATA PHY\n");
else
debug("SATA PHY init succeed\n");
if (node > 0) {
if (fdtdec_get_is_enabled(blob, node)) {
ret = comphy_emmc_power_up();
- if (ret == 0)
+ if (!ret)
printf("Failed to initialize SDIO/eMMC PHY\n");
else
debug("SDIO/eMMC PHY init succeed\n");
ret = 1;
break;
}
- if (ret == 0)
+ if (!ret)
printf("PLL is not locked - Failed to initialize lane %d\n",
lane);
}