]> git.sur5r.net Git - u-boot/commitdiff
powerpc/t1040qds: Update DDR option
authorYork Sun <yorksun@freescale.com>
Mon, 27 Oct 2014 18:45:11 +0000 (11:45 -0700)
committerYork Sun <yorksun@freescale.com>
Fri, 5 Dec 2014 16:06:08 +0000 (08:06 -0800)
Enable interactive debugging by default. Remove DDR controller interleaving
because this SoC only has one controller. Use auto chip-select interleaving
to detect number of ranks.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Poonam Aggrwal <poonam.aggrwal@freescale.com>
include/configs/T1040QDS.h

index 2178f9d1fd6cf3b086b50490d16e9e9ae6df0074..2ae0f4807a520a82df3e98572f767c987af8299b 100644 (file)
@@ -176,8 +176,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DDR_SPD
 #ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3
-#define CONFIG_FSL_DDR_INTERACTIVE
 #endif
+#define CONFIG_FSL_DDR_INTERACTIVE
 
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS     0x51
@@ -768,8 +768,7 @@ unsigned long get_board_ddr_clk(void);
 #define __USB_PHY_TYPE utmi
 
 #define        CONFIG_EXTRA_ENV_SETTINGS                               \
-       "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
-       "bank_intlv=cs0_cs1;"                                   \
+       "hwconfig=fsl_ddr:bank_intlv=auto;"                     \
        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
        "netdev=eth0\0"                                         \
        "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \