Enable the DWAPB GPIO driver for SoCFPGA Cyclone V and Arria V.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_DM_SEQ_ALIAS=y
 
 CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_DM_SEQ_ALIAS=y
 
 CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_DM_SEQ_ALIAS=y
 
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */
 
 
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */