]> git.sur5r.net Git - u-boot/commitdiff
at91: Add esd gmbh OTC570 board support
authorDaniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
Mon, 25 Jan 2010 09:50:41 +0000 (10:50 +0100)
committerTom Rix <Tom.Rix@windriver.com>
Sun, 31 Jan 2010 13:59:15 +0000 (07:59 -0600)
This patch adds support for esd gmbh OTC570 board.
The OTC570 is based on an Atmel AT91SAM9263 SoC.

Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
MAINTAINERS
MAKEALL
Makefile
board/esd/otc570/Makefile [new file with mode: 0644]
board/esd/otc570/config.mk [new file with mode: 0644]
board/esd/otc570/otc570.c [new file with mode: 0644]
board/esd/otc570/partition.c [new file with mode: 0644]
include/configs/otc570.h [new file with mode: 0644]
tools/Makefile
tools/logos/esd.bmp [new file with mode: 0644]

index e8ba4bc134d68f54baa8152d5562736bd37aeb44..0c2b1b1270b27161c7d044c316318ef3cb5c7678 100644 (file)
@@ -574,6 +574,7 @@ Peter Figuli <peposh@etc.sk>
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 
        meesc           ARM926EJS (AT91SAM9263 SoC)
+       otc570          ARM926EJS (AT91SAM9263 SoC)
 
 Sedji Gaouaou<sedji.gaouaou@atmel.com>
        at91sam9g10ek           ARM926EJS (AT91SAM9G10 SoC)
diff --git a/MAKEALL b/MAKEALL
index 15e93cf273d3c38042d30da089f372aad408d953..506dc780dec1c76dea1eed8aa4fe838feba5d929 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -659,6 +659,7 @@ LIST_at91="                 \
        meesc                   \
        mp2usb                  \
        m501sk                  \
+       otc570                  \
        pm9261                  \
        pm9263                  \
        SBC35_A9G20             \
index 69b963f2b87dd7b5ef1813b1f0f36974a076d923..628bcdb06ca6dd17c7ed5d145ba2da0074e4cd0b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2872,6 +2872,9 @@ at91sam9g45ekes_config    :       unconfig
        fi;
        @$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
 
+otc570_config  :       unconfig
+       @$(MKCONFIG) $(@:_config=) arm arm926ejs otc570 esd at91
+
 pm9263_config  :       unconfig
        @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
 
diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile
new file mode 100644 (file)
index 0000000..755c5ee
--- /dev/null
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS-y                                += $(BOARD).o
+COBJS-$(CONFIG_HAS_DATAFLASH)  += partition.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/otc570/config.mk b/board/esd/otc570/config.mk
new file mode 100644 (file)
index 0000000..ff2cfd1
--- /dev/null
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000
diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c
new file mode 100644 (file)
index 0000000..056df37
--- /dev/null
@@ -0,0 +1,365 @@
+/*
+ * (C) Copyright 2010
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <atmel_lcdc.h>
+#include <lcd.h>
+#include <netdev.h>
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1;        /* hardware revision */
+
+int get_hw_rev(void)
+{
+       if (hw_rev >= 0)
+               return hw_rev;
+
+       hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
+       hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
+       hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
+       hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
+
+       if (hw_rev == 15)
+               hw_rev = 0;
+
+       return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void otc570_nand_hw_init(void)
+{
+       unsigned long csa;
+
+       /* Enable CS3 */
+       csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+       at91_sys_write(AT91_MATRIX_EBI0CSA,
+               csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+
+       /* Configure SMC CS3 for NAND/SmartMedia */
+       at91_sys_write(AT91_SMC_SETUP(3),
+               AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+               AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+       at91_sys_write(AT91_SMC_PULSE(3),
+               AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+               AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+       at91_sys_write(AT91_SMC_CYCLE(3),
+               AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+       at91_sys_write(AT91_SMC_MODE(3),
+               AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+               AT91_SMC_EXNWMODE_DISABLE |
+               AT91_SMC_DBW_8 |
+               AT91_SMC_TDF_(2));
+
+       /* Configure RDY/BSY */
+       at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+       /* Enable NandFlash */
+       at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void otc570_macb_hw_init(void)
+{
+       /* Enable clock */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+       at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void otc570_ethercat_hw_init(void)
+{
+       /* Configure SMC EBI1_CS0 for EtherCAT */
+       at91_sys_write(AT91_SMC1_SETUP(0),
+               AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+               AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+       at91_sys_write(AT91_SMC1_PULSE(0),
+               AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
+               AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9));
+       at91_sys_write(AT91_SMC1_CYCLE(0),
+               AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6));
+       /*
+        * Configure behavior at external wait signal, byte-select mode, 16 bit
+        * data bus width, none data float wait states and TDF optimization
+        */
+       at91_sys_write(AT91_SMC1_MODE(0),
+               AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
+               AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
+               AT91_SMC_TDFMODE);
+
+       /* Configure RDY/BSY */
+       at91_set_B_periph(AT91_PIN_PE20, 0);    /* EBI1_NWAIT */
+}
+
+#ifdef CONFIG_LCD
+/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
+vidinfo_t panel_info = {
+       .vl_col =               640,
+       .vl_row =               480,
+       .vl_clk =               25175000,
+       .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
+                               ATMEL_LCDC_INVFRAME_INVERTED,
+
+       .vl_bpix =              3,      /* Bits per pixel, 0 = 1bit, 3 = 8bit */
+       .vl_tft =               1,      /* 0 = passive, 1 = TFT */
+       .vl_vsync_len =         1,      /* Length of vertical sync in NOL */
+       .vl_upper_margin =      35,     /* Idle lines at the frame start */
+       .vl_lower_margin =      5,      /* Idle lines at the end of the frame */
+       .vl_hsync_len =         5,      /* Width of the LCDHSYNC pulse */
+       .vl_left_margin =       112,    /* Idle cycles at the line beginning */
+       .vl_right_margin =      1,      /* Idle cycles at the end of the line */
+
+       .mmio =                 AT91SAM9263_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+       at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+       at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
+}
+
+static void otc570_lcd_hw_init(void)
+{
+       at91_set_A_periph(AT91_PIN_PC0, 0);     /* LCDVSYNC */
+       at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
+       at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
+       at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
+       at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
+       at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
+       at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
+       at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
+       at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
+       at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
+       at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
+       at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
+       at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
+       at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
+       at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
+       at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
+       at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
+       at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
+       at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
+       at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
+       at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
+       at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
+       at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
+       at91_set_gpio_output(AT91_PIN_PA30, 1); /* PCI */
+
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
+
+       gd->fb_base = CONFIG_OTC570_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+       ulong dram_size, nand_size;
+       int i;
+       char temp[32];
+
+       dram_size = 0;
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+               dram_size += gd->bd->bi_dram[i].size;
+       nand_size = 0;
+       for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+               nand_size += nand_info[i].size;
+
+       lcd_printf("\n%s\n", U_BOOT_VERSION);
+       lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME,
+                                       strmhz(temp, get_cpu_clk_rate()));
+       lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
+               dram_size >> 20,
+               nand_size >> 20 );
+       lcd_printf("  Board            : esd ARM9 HMI Panel - OTC570\n");
+       lcd_printf("  Hardware-revision: 1.%d\n", get_hw_rev());
+       lcd_printf("  Mach-type        : %lu\n", gd->bd->bi_arch_number);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+int dram_init(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM;
+       gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_MACB
+       rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+#endif
+       return rc;
+}
+
+int checkboard(void)
+{
+       char str[32];
+
+       puts("Board: esd ARM9 HMI Panel - OTC570");
+       if (getenv_r("serial#", str, sizeof(str)) > 0) {
+               puts(", serial# ");
+               puts(str);
+       }
+       printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+       printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+       return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+       char *str;
+
+       char *serial = getenv("serial#");
+       if (serial) {
+               str = strchr(serial, '_');
+               if (str && (strlen(str) >= 4)) {
+                       serialnr->high = (*(str + 1) << 8) | *(str + 2);
+                       serialnr->low = simple_strtoul(str + 3, NULL, 16);
+               }
+       } else {
+               serialnr->high = 0;
+               serialnr->low = 0;
+       }
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+       return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+       char str[64];
+
+       at91_set_gpio_output(AT91_PIN_PA29, 1);
+       at91_set_A_periph(AT91_PIN_PA26, 1);                    /* TXD0 */
+       at91_set_A_periph(AT91_PIN_PA27, 0);                    /* RXD0 */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
+       /* Set USART_MODE = 1 (RS485) */
+       at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1);
+
+       printf("USART0: ");
+
+       if (getenv_r("usart0", str, sizeof(str)) == -1) {
+               printf("No entry - assuming 1-wire\n");
+               /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
+               at91_set_gpio_output(AT91_PIN_PA29, 0);
+       } else {
+               if (strcmp(str, "1-wire") == 0) {
+                       printf("%s\n", str);
+                       at91_set_gpio_output(AT91_PIN_PA29, 0);
+               } else if (strcmp(str, "rs485") == 0) {
+                       printf("%s\n", str);
+                       at91_set_gpio_output(AT91_PIN_PA29, 1);
+               } else {
+                       printf("Wrong entry - assuming 1-wire ");
+                       printf("(valid values are '1-wire' or 'rs485')\n");
+                       at91_set_gpio_output(AT91_PIN_PA29, 0);
+               }
+       }
+       printf("Display memory address: 0x%08lX\n", gd->fb_base);
+
+       return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_init(void)
+{
+       /* Peripheral Clock Enable Register */
+       at91_sys_write(AT91_PMC_PCER,   1 << AT91SAM9263_ID_PIOA |
+                                       1 << AT91SAM9263_ID_PIOB |
+                                       1 << AT91SAM9263_ID_PIOCDE |
+                                       1 << AT91SAM9263_ID_TWI |
+                                       1 << AT91SAM9263_ID_SPI0 |
+                                       1 << AT91SAM9263_ID_LCDC |
+                                       1 << AT91SAM9263_ID_UHP);
+
+       /* arch number of OTC570-Board */
+       gd->bd->bi_arch_number = MACH_TYPE_OTC570;
+
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+       otc570_nand_hw_init();
+#endif
+       otc570_ethercat_hw_init();
+#ifdef CONFIG_HAS_DATAFLASH
+       at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+       otc570_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+       at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+       at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+       otc570_lcd_hw_init();
+#endif
+       return 0;
+}
diff --git a/board/esd/otc570/partition.c b/board/esd/otc570/partition.c
new file mode 100644 (file)
index 0000000..df0e1db
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+       {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},       /* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+       {0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+       {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+       {0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
new file mode 100644 (file)
index 0000000..bedaf13
--- /dev/null
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2010
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the esd OTC570 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Common stuff */
+#define CONFIG_OTC570                  1       /* Board is esd OTC570 */
+#define CONFIG_ARM926EJS               1       /* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9263             1       /* It's an AT91SAM9263 SoC */
+#define CONFIG_SYS_HZ                  1000    /* decrementer freq */
+#define CONFIG_DISPLAY_BOARDINFO       1
+#define CONFIG_DISPLAY_CPUINFO         1       /* display cpu info and speed */
+#define CONFIG_PREBOOT                         /* enable preboot variable */
+#define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS       1
+#define CONFIG_INITRD_TAG              1
+#define CONFIG_SERIAL_TAG              1
+#define CONFIG_REVISION_TAG            1
+#undef CONFIG_USE_IRQ                          /* don't need IRQ/FIQ stuff */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_MISC_INIT_R             1       /* Call misc_init_r */
+
+#define CONFIG_ARCH_CPU_INIT
+
+/*
+ * Hardware drivers
+ */
+
+/* Console output */
+#define CONFIG_ATMEL_USART             1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3                  1       /* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY               3
+#define CONFIG_ZERO_BOOTDELAY_CHECK    1
+
+/* LCD */
+#define CONFIG_LCD                     1
+#define LCD_BPP                                LCD_COLOR8
+
+#undef CONFIG_SPLASH_SCREEN
+
+#ifndef CONFIG_SPLASH_SCREEN
+#define CONFIG_LCD_LOGO                        1
+#define CONFIG_LCD_INFO                        1
+#undef CONFIG_LCD_INFO_BELOW_LOGO
+#endif /* CONFIG_SPLASH_SCREEN */
+
+#undef LCD_TEST_PATTERN
+#define CONFIG_SYS_WHITE_ON_BLACK      1
+#define CONFIG_ATMEL_LCD               1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV   1
+#define CONFIG_OTC570_LCD_BASE         0x23E00000      /* LCD is in SDRAM */
+#define CONFIG_CMD_BMP                 1
+
+/* RTC and I2C stuff */
+#define CONFIG_RTC_DS1338              1
+#define CONFIG_SYS_I2C_RTC_ADDR                0x68
+#undef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C                        1
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_SYS_I2C_SLAVE           0x7F
+
+#ifdef CONFIG_SOFT_I2C
+#define CONFIG_I2C_CMD_TREE            1
+#define CONFIG_I2C_MULTI_BUS           1
+/* Enable peripheral clock and configure data and clock pins for pio */
+#define I2C_INIT { \
+       at91_sys_write(AT91_PMC_PCER,   1 << AT91SAM9263_ID_PIOB |      \
+                                       1 << AT91SAM9263_ID_PIOCDE);    \
+       at91_set_gpio_output(AT91_PIN_PB4, 0);                          \
+       at91_set_gpio_output(AT91_PIN_PB5, 0);                          \
+}
+/* Configure data pin as output */
+#define I2C_ACTIVE                     at91_set_gpio_output(AT91_PIN_PB4, 0)
+/* Configure data pin as input */
+#define I2C_TRISTATE                   at91_set_gpio_input(AT91_PIN_PB4, 0)
+/* Read data pin */
+#define I2C_READ                       at91_get_gpio_value(AT91_PIN_PB4)
+/* Set data pin */
+#define I2C_SDA(bit)                   at91_set_gpio_value(AT91_PIN_PB4, bit)
+/* Set clock pin */
+#define I2C_SCL(bit)                   at91_set_gpio_value(AT91_PIN_PB5, bit)
+#define I2C_DELAY                      udelay(2) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CONFIG_BOOTDELAY               3
+#define CONFIG_ZERO_BOOTDELAY_CHECK    1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE      1
+#define CONFIG_BOOTP_BOOTPATH          1
+#define CONFIG_BOOTP_GATEWAY           1
+#define CONFIG_BOOTP_HOSTNAME          1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING                        1
+#define CONFIG_CMD_DHCP                        1
+#define CONFIG_CMD_NAND                        1
+#define CONFIG_CMD_USB                 1
+#define CONFIG_CMD_I2C                 1
+#define CONFIG_CMD_DATE                        1
+
+/* LED */
+#define CONFIG_AT91_LED                        1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS                   1
+#define PHYS_SDRAM                             0x20000000
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH                   1
+#define CONFIG_SYS_SPI_WRITE_TOUT              (5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS         1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0    0xC0000000      /* CS0 */
+#define AT91_SPI_CLK                           15000000
+#define DATAFLASH_TCSS                         (0x1a << 16)
+#define DATAFLASH_TCHS                         (0x1 << 24)
+
+/* NOR flash is not populated, disable it */
+#define CONFIG_SYS_NO_FLASH                    1
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE             1
+#define CONFIG_SYS_NAND_BASE                   0x40000000
+#define CONFIG_SYS_NAND_DBW_8                  1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE               (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN             AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN              AT91_PIN_PA22
+#define CONFIG_SYS_64BIT_VSPRINTF              /* needed for nand_util.c */
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB                            1
+#define CONFIG_RMII                            1
+#define CONFIG_NET_MULTI                       1
+#define CONFIG_NET_RETRY_COUNT                 20
+#undef CONFIG_RESET_PHY_R
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW                    1
+#define CONFIG_DOS_PARTITION                   1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT           1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE          0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME          "at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
+#define CONFIG_USB_STORAGE                     1
+#define CONFIG_CMD_FAT                         1
+
+#define CONFIG_SYS_LOAD_ADDR                   0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START               PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END                 0x23e00000
+
+#define CONFIG_SYS_USE_DATAFLASH               1
+#undef CONFIG_SYS_USE_NANDFLASH
+
+/* CAN */
+#define CONFIG_AT91_CAN                                1
+
+/* hw-controller addresses */
+#define CONFIG_ET1100_BASE                     0x70000000
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH     1
+#define CONFIG_SYS_MONITOR_BASE                (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+                                       0x8400)
+#define CONFIG_ENV_OFFSET              0x4200
+#define CONFIG_ENV_ADDR                        (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+                                       CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE                        0x4200
+
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT              "=> "
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP            1
+#define CONFIG_CMDLINE_EDITING         1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN          ROUND(3 * CONFIG_ENV_SIZE + \
+                                       128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE       128     /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE               (32 * 1024)     /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
index 266306e9bacec8f2e3aea555953313720e524605..743505f9299d5ba135655d9c377d27c63ac69269 100644 (file)
@@ -112,6 +112,9 @@ endif
 ifeq ($(VENDOR),atmel)
 LOGO_BMP= logos/atmel.bmp
 endif
+ifeq ($(VENDOR),esd)
+LOGO_BMP= logos/esd.bmp
+endif
 ifeq ($(VENDOR),ronetix)
 LOGO_BMP= logos/ronetix.bmp
 endif
diff --git a/tools/logos/esd.bmp b/tools/logos/esd.bmp
new file mode 100644 (file)
index 0000000..a6b4030
Binary files /dev/null and b/tools/logos/esd.bmp differ