#error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN
 #endif
 
-       gd->inp_clk = CONFIG_SYS_MPC8220_CLKIN;
+       gd->arch.inp_clk = CONFIG_SYS_MPC8220_CLKIN;
 
        /* Read XLB to PCI(INP) clock multiplier */
        pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
 
        /* FlexBus is temporary set as the same as input clock */
        /* will do dynamic in the future */
-       gd->flb_clk = CONFIG_SYS_MPC8220_CLKIN;
+       gd->arch.flb_clk = CONFIG_SYS_MPC8220_CLKIN;
 
        /* CPU Clock - Read HID1 */
        asm volatile ("mfspr %0, 1009":"=r" (hid1):);
        for (i = 0; i < size; i++)
                if (hid1 == bus2core[i].hid1) {
                        gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
-                       gd->vco_clk = CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
+                       gd->arch.vco_clk =
+                               CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER *
+                               (gd->pci_clk * bus2core[i].vco_div) / 2;
                        break;
                }
 
        /* hardcoded 81MHz for now */
-       gd->pev_clk = 81000000;
+       gd->arch.pev_clk = 81000000;
 
        return (0);
 }
                strmhz(buf1, gd->bus_clk),
                strmhz(buf2, gd->cpu_clk),
                strmhz(buf3, gd->pci_clk),
-               strmhz(buf4, gd->vco_clk)
+               strmhz(buf4, gd->arch.vco_clk)
        );
        return (0);
 }
 
        u32 ips_clk;
        u32 csb_clk;
 #endif /* CONFIG_MPC512X */
+#if defined(CONFIG_MPC8220)
+       unsigned long inp_clk;
+       unsigned long vco_clk;
+       unsigned long pev_clk;
+       unsigned long flb_clk;
+#endif
 };
 
 /*
        unsigned long   mem_clk;
 #if defined(CONFIG_FSL_ESDHC)
        u32 sdhc_clk;
-#endif
-#if defined(CONFIG_MPC8220)
-       unsigned long   bExtUart;
-       unsigned long   inp_clk;
-       unsigned long   vco_clk;
-       unsigned long   pev_clk;
-       unsigned long   flb_clk;
 #endif
        phys_size_t     ram_size;       /* RAM size */
        unsigned long   reset_status;   /* reset status register at boot        */
 
 #endif
 #if defined(CONFIG_MPC8220)
        bd->bi_mbar_base = CONFIG_SYS_MBAR;     /* base of internal registers */
-       bd->bi_inpfreq = gd->inp_clk;
+       bd->bi_inpfreq = gd->arch.inp_clk;
        bd->bi_pcifreq = gd->pci_clk;
-       bd->bi_vcofreq = gd->vco_clk;
-       bd->bi_pevfreq = gd->pev_clk;
-       bd->bi_flbfreq = gd->flb_clk;
+       bd->bi_vcofreq = gd->arch.vco_clk;
+       bd->bi_pevfreq = gd->arch.pev_clk;
+       bd->bi_flbfreq = gd->arch.flb_clk;
 
        /* store bootparam to sram (backward compatible), here? */
        {
 
                *sram++ = gd->ram_size;
                *sram++ = gd->bus_clk;
-               *sram++ = gd->inp_clk;
+               *sram++ = gd->arch.inp_clk;
                *sram++ = gd->cpu_clk;
-               *sram++ = gd->vco_clk;
-               *sram++ = gd->flb_clk;
+               *sram++ = gd->arch.vco_clk;
+               *sram++ = gd->arch.flb_clk;
                *sram++ = 0xb8c3ba11;   /* boot signature */
        }
 #endif