# Ignore "WARNING: Prefer ether_addr_copy() over memcpy() if the Ethernet
# addresses are __aligned(2)".
--ignore PREFER_ETHER_ADDR_COPY
+
+# A bit shorter of a description is OK with us.
+--min-conf-desc-length=2
- grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- mkdir ~/grub2-arm
- ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
+ - mkdir ~/grub2-arm64
+ - ( cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di )
env:
global:
tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu.tar.xz &&
tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf.tar.xz;
fi
+ - if [[ "${TOOLCHAIN}" == "riscv" ]]; then
+ wget https://github.com/PkmX/riscv-prebuilt-toolchains/releases/download/20180111/riscv32-unknown-elf-toolchain.tar.gz &&
+ tar -C /tmp -xf riscv32-unknown-elf-toolchain.tar.gz &&
+ echo -e "\n[toolchain-prefix]\nriscv = /tmp/riscv32-unknown-elf/bin/riscv32-unknown-elf-" >> ~/.buildman;
+ fi
- if [[ "${QEMU_TARGET}" != "" ]]; then
git clone git://git.qemu.org/qemu.git /tmp/qemu;
pushd /tmp/qemu;
- export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD};
cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/;
cp ~/grub2-arm/usr/lib/grub2/arm-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi;
+ cp ~/grub2-arm64/usr/lib/grub2/arm64-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi;
if [[ "${TEST_PY_BD}" != "" ]]; then
./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
-k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
--build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+ ret=$?;
+ if [[ $ret -ne 0 ]]; then
+ exit $ret;
+ fi;
+ fi;
+ if [[ -n "${TEST_PY_TOOLS}" ]]; then
+ PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
+ PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"
+ ./tools/binman/binman -t &&
+ ./tools/patman/patman --test &&
+ ./tools/buildman/buildman -t &&
+ PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
+ PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"
+ ./tools/dtoc/dtoc -t;
fi
matrix:
- env:
- BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
- env:
- - BUILDMAN="t208xrdb t4qds t102*"
+ - BUILDMAN="t208xrdb"
+ - env:
+ - BUILDMAN="t4qds"
+ - env:
+ - BUILDMAN="t102*"
- env:
- BUILDMAN="p1_p2_rdb_pc"
- env:
- env:
- BUILDMAN="xtensa"
TOOLCHAIN="xtensa"
+ - env:
+ - BUILDMAN="riscv"
+ TOOLCHAIN="riscv"
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
TEST_PY_TEST_SPEC="test_ofplatdata"
BUILDMAN="^sandbox$"
TOOLCHAIN="x86_64"
+ TEST_PY_TOOLS="yes"
- env:
- TEST_PY_BD="sandbox_flattree"
BUILDMAN="^sandbox_flattree$"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="arm-softmmu"
BUILDMAN="^qemu_arm$"
+ - env:
+ - TEST_PY_BD="qemu_arm64"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="aarch64-softmmu"
+ BUILDMAN="^qemu_arm64$"
- env:
- TEST_PY_BD="qemu_mips"
TEST_PY_TEST_SPEC="not sleep"
S: Maintained
T: git git://github.com/agraf/u-boot.git
F: include/efi*
-F: lib/efi*
+F: lib/efi*/
F: test/py/tests/test_efi*
F: cmd/bootefi.c
+F: tools/file2include.c
FLATTENED DEVICE TREE
M: Simon Glass <sjg@chromium.org>
T: git git://git.denx.de/u-boot-onenand.git
F: drivers/mtd/onenand/
+RISC-V
+M: Rick Chen <rick@andestech.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-riscv.git
+F: arch/riscv/
+F: tools/prelink-riscv.c
+
SANDBOX
M: Simon Glass <sjg@chromium.org>
S: Maintained
T: git git://git.denx.de/u-boot-usb.git topic-xhci
F: drivers/usb/host/xhci*
+ROCKUSB
+M: Eddie Cai <eddie.cai.linux@gmail.com>
+S: Maintained
+F: drivers/usb/gadget/f_rockusb.c
+F: cmd/rockusb.c
+F: doc/README.rockusb
+
VIDEO
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
endif
+ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),)
+ALL-y += init_sp_bss_offset_check
+endif
+
LDFLAGS_u-boot += $(LDFLAGS_FINAL)
# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
fi \
fi
+ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),)
+ifneq ($(CONFIG_SYS_MALLOC_F_LEN),)
+subtract_sys_malloc_f_len = space=$$(($${space} - $(CONFIG_SYS_MALLOC_F_LEN)))
+else
+subtract_sys_malloc_f_len = true
+endif
+# The 1/4 margin below is somewhat arbitrary. The likely initial SP usage is
+# so low that the DTB could probably use 90%+ of the available space, for
+# current values of CONFIG_SYS_INIT_SP_BSS_OFFSET at least. However, let's be
+# safe for now and tweak this later if space becomes tight.
+# A rejected alternative would be to check that some absolute minimum stack
+# space was available. However, since CONFIG_SYS_INIT_SP_BSS_OFFSET is
+# deliberately build-specific, to take account of build-to-build stack usage
+# differences due to different feature sets, there is no common absolute value
+# to check against.
+init_sp_bss_offset_check: u-boot.dtb FORCE
+ @dtb_size=$(shell wc -c u-boot.dtb | awk '{print $$1}') ; \
+ space=$(CONFIG_SYS_INIT_SP_BSS_OFFSET) ; \
+ $(subtract_sys_malloc_f_len) ; \
+ quarter_space=$$(($${space} / 4)) ; \
+ if [ $${dtb_size} -gt $${quarter_space} ]; then \
+ echo "u-boot.dtb is larger than 1 quarter of " >&2 ; \
+ echo "(CONFIG_SYS_INIT_SP_BSS_OFFSET - CONFIG_SYS_MALLOC_F_LEN)" >&2 ; \
+ exit 1 ; \
+ fi
+endif
+
u-boot-nodtb.bin: u-boot FORCE
$(call if_changed,objcopy)
$(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
$(call cmd,u-boot__) common/system_map.o
endif
+ifeq ($(CONFIG_RISCV),y)
+ @tools/prelink-riscv $@ 0
+endif
+
quiet_cmd_sym ?= SYM $@
cmd_sym ?= $(OBJDUMP) -t $< > $@
u-boot.sym: u-boot FORCE
/nios2 Files generic to Altera NIOS2 architecture
/openrisc Files generic to OpenRISC architecture
/powerpc Files generic to PowerPC architecture
+ /riscv Files generic to RISC-V architecture
/sandbox Files generic to HW-independent "sandbox"
/sh Files generic to SH architecture
/x86 Files generic to x86 architecture
globally (CONFIG_CMD_MEMORY).
- CONFIG_SKIP_LOWLEVEL_INIT
- [ARM, NDS32, MIPS only] If this variable is defined, then certain
+ [ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain
low level initializations (like setting up the memory
controller) are omitted and/or U-Boot does not
relocate itself into RAM.
NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
or current versions of GCC may "optimize" the code too much.
+On RISC-V, the following registers are used:
+
+ x0: hard-wired zero (zero)
+ x1: return address (ra)
+ x2: stack pointer (sp)
+ x3: global pointer (gp)
+ x4: thread pointer (tp)
+ x5: link register (t0)
+ x8: frame pointer (fp)
+ x10-x11: arguments/return values (a0-1)
+ x12-x17: arguments (a2-7)
+ x28-31: temporaries (t3-6)
+ pc: program counter (pc)
+
+ ==> U-Boot will use gp to hold a pointer to the global data
+
Memory Management:
------------------
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
+config RISCV
+ bool "riscv architecture"
+ select SUPPORT_OF_CONTROL
+
config SANDBOX
bool "Sandbox"
select BOARD_LATE_INIT
source "arch/sh/Kconfig"
source "arch/x86/Kconfig"
source "arch/xtensa/Kconfig"
+source "arch/riscv/Kconfig"
};
};
+ cgu_clk: cgu-clk@f0000000 {
+ compatible = "snps,hsdk-cgu-clock";
+ reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
+ #clock-cells = <1>;
+ };
+
uart0: serial0@f0005000 {
compatible = "snps,dw-apb-uart";
reg = <0xf0005000 0x1000>;
#define ARC_AUX_SLC_INVALIDATE 0x905
#define ARC_AUX_SLC_IVDL 0x910
#define ARC_AUX_SLC_FLDL 0x912
+#define ARC_AUX_SLC_RGN_START 0x914
+#define ARC_AUX_SLC_RGN_START1 0x915
+#define ARC_AUX_SLC_RGN_END 0x916
+#define ARC_AUX_SLC_RGN_END1 0x917
#define ARC_BCR_CLUSTER 0xcf
+/* MMU Management regs */
+#define ARC_AUX_MMU_BCR 0x06f
+
/* IO coherency related auxiliary registers */
#define ARC_AUX_IO_COH_ENABLE 0x500
#define ARC_AUX_IO_COH_PARTIAL 0x501
#include <asm/cache.h>
/* Bit values in IC_CTRL */
-#define IC_CTRL_CACHE_DISABLE (1 << 0)
+#define IC_CTRL_CACHE_DISABLE BIT(0)
/* Bit values in DC_CTRL */
-#define DC_CTRL_CACHE_DISABLE (1 << 0)
-#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
-#define DC_CTRL_FLUSH_STATUS (1 << 8)
+#define DC_CTRL_CACHE_DISABLE BIT(0)
+#define DC_CTRL_INV_MODE_FLUSH BIT(6)
+#define DC_CTRL_FLUSH_STATUS BIT(8)
#define CACHE_VER_NUM_MASK 0xF
-#define SLC_CTRL_SB (1 << 2)
#define OP_INV 0x1
#define OP_FLUSH 0x2
#define OP_INV_IC 0x3
+/* Bit val in SLC_CONTROL */
+#define SLC_CTRL_DIS 0x001
+#define SLC_CTRL_IM 0x040
+#define SLC_CTRL_BUSY 0x100
+#define SLC_CTRL_RGN_OP_INV 0x200
+
/*
* By default that variable will fall into .bss section.
* But .bss section is not relocated and so it will be initilized before
int slc_line_sz __section(".data");
bool slc_exists __section(".data") = false;
bool ioc_exists __section(".data") = false;
+bool pae_exists __section(".data") = false;
+
+/* To force enable IOC set ioc_enable to 'true' */
+bool ioc_enable __section(".data") = false;
-static unsigned int __before_slc_op(const int op)
+void read_decode_mmu_bcr(void)
{
- unsigned int reg = reg;
+ /* TODO: should we compare mmu version from BCR and from CONFIG? */
+#if (CONFIG_ARC_MMU_VER >= 4)
+ u32 tmp;
- if (op == OP_INV) {
- /*
- * IM is set by default and implies Flush-n-inv
- * Clear it here for vanilla inv
- */
- reg = read_aux_reg(ARC_AUX_SLC_CTRL);
- write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
- }
+ tmp = read_aux_reg(ARC_AUX_MMU_BCR);
- return reg;
-}
+ struct bcr_mmu_4 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
+ n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
+#else
+ /* DTLB ITLB JES JE JA */
+ unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
+ pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
+#endif /* CONFIG_CPU_BIG_ENDIAN */
+ } *mmu4;
-static void __after_slc_op(const int op, unsigned int reg)
-{
- if (op & OP_FLUSH) { /* flush / flush-n-inv both wait */
- /*
- * Make sure "busy" bit reports correct status,
- * see STAR 9001165532
- */
- read_aux_reg(ARC_AUX_SLC_CTRL);
- while (read_aux_reg(ARC_AUX_SLC_CTRL) &
- DC_CTRL_FLUSH_STATUS)
- ;
- }
+ mmu4 = (struct bcr_mmu_4 *)&tmp;
- /* Switch back to default Invalidate mode */
- if (op == OP_INV)
- write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
+ pae_exists = !!mmu4->pae;
+#endif /* (CONFIG_ARC_MMU_VER >= 4) */
}
-static inline void __slc_line_loop(unsigned long paddr, unsigned long sz,
- const int op)
+static void __slc_entire_op(const int op)
{
- unsigned int aux_cmd;
- int num_lines;
+ unsigned int ctrl;
-#define SLC_LINE_MASK (~(slc_line_sz - 1))
+ ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
- aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
+ if (!(op & OP_FLUSH)) /* i.e. OP_INV */
+ ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
+ else
+ ctrl |= SLC_CTRL_IM;
- sz += paddr & ~SLC_LINE_MASK;
- paddr &= SLC_LINE_MASK;
+ write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
- num_lines = DIV_ROUND_UP(sz, slc_line_sz);
+ if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
+ write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
+ else
+ write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
- while (num_lines-- > 0) {
- write_aux_reg(aux_cmd, paddr);
- paddr += slc_line_sz;
- }
+ /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+ read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ /* Important to wait for flush to complete */
+ while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
}
-static inline void __slc_entire_op(const int cacheop)
+static void slc_upper_region_init(void)
{
- int aux;
- unsigned int ctrl_reg = __before_slc_op(cacheop);
+ /*
+ * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
+ * as we don't use PAE40.
+ */
+ write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
+ write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
+}
- if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
- aux = ARC_AUX_SLC_INVALIDATE;
+static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
+{
+ unsigned int ctrl;
+ unsigned long end;
+
+ /*
+ * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
+ * - b'000 (default) is Flush,
+ * - b'001 is Invalidate if CTRL.IM == 0
+ * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
+ */
+ ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ /* Don't rely on default value of IM bit */
+ if (!(op & OP_FLUSH)) /* i.e. OP_INV */
+ ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
else
- aux = ARC_AUX_SLC_FLUSH;
+ ctrl |= SLC_CTRL_IM;
- write_aux_reg(aux, 0x1);
+ if (op & OP_INV)
+ ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
+ else
+ ctrl &= ~SLC_CTRL_RGN_OP_INV;
- __after_slc_op(cacheop, ctrl_reg);
-}
+ write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
-static inline void __slc_line_op(unsigned long paddr, unsigned long sz,
- const int cacheop)
-{
- unsigned int ctrl_reg = __before_slc_op(cacheop);
- __slc_line_loop(paddr, sz, cacheop);
- __after_slc_op(cacheop, ctrl_reg);
+ /*
+ * Lower bits are ignored, no need to clip
+ * END needs to be setup before START (latter triggers the operation)
+ * END can't be same as START, so add (l2_line_sz - 1) to sz
+ */
+ end = paddr + sz + slc_line_sz - 1;
+
+ /*
+ * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
+ * are always == 0 as we don't use PAE40, so we only setup lower ones
+ * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
+ */
+ write_aux_reg(ARC_AUX_SLC_RGN_END, end);
+ write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
+
+ /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+ read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
}
-#else
-#define __slc_entire_op(cacheop)
-#define __slc_line_op(paddr, sz, cacheop)
-#endif
+#endif /* CONFIG_ISA_ARCV2 */
#ifdef CONFIG_ISA_ARCV2
static void read_decode_cache_bcr_arcv2(void)
} cbcr;
cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
- if (cbcr.fields.c)
+ if (cbcr.fields.c && ioc_enable)
ioc_exists = true;
}
#endif
}
dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
- if (dbcr.fields.ver){
+ if (dbcr.fields.ver) {
dcache_exists = true;
l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
if (!dc_line_sz)
* so setting 0x11 implies 512M, 0x12 implies 1G...
*/
write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
- order_base_2(ap_size/1024) - 2);
-
+ order_base_2(ap_size / 1024) - 2);
/* IOC Aperture start must be aligned to the size of the aperture */
if (ap_base % ap_size != 0)
write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
-
}
-#endif
+
+ read_decode_mmu_bcr();
+
+ /*
+ * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
+ * only if PAE exists in current HW. So we had to check pae_exist
+ * before using them.
+ */
+ if (slc_exists && pae_exists)
+ slc_upper_region_init();
+#endif /* CONFIG_ISA_ARCV2 */
}
int icache_status(void)
IC_CTRL_CACHE_DISABLE);
}
-#ifndef CONFIG_SYS_DCACHE_OFF
void invalidate_icache_all(void)
{
/* Any write to IC_IVIC register triggers invalidation of entire I$ */
__builtin_arc_nop();
read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
}
-}
-#else
-void invalidate_icache_all(void)
-{
-}
+
+#ifdef CONFIG_ISA_ARCV2
+ if (slc_exists)
+ __slc_entire_op(OP_INV);
#endif
+}
int dcache_status(void)
{
static void __after_dc_op(const int op, unsigned int reg)
{
if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
- while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
- ;
+ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
/* Switch back to default Invalidate mode */
if (op == OP_INV)
const int cacheop)
{
unsigned int ctrl_reg = __before_dc_op(cacheop);
+
__cache_line_loop(paddr, sz, cacheop);
__after_dc_op(cacheop, ctrl_reg);
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
+ if (start >= end)
+ return;
+
#ifdef CONFIG_ISA_ARCV2
if (!ioc_exists)
#endif
#ifdef CONFIG_ISA_ARCV2
if (slc_exists && !ioc_exists)
- __slc_line_op(start, end - start, OP_INV);
+ __slc_rgn_op(start, end - start, OP_INV);
#endif
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
+ if (start >= end)
+ return;
+
#ifdef CONFIG_ISA_ARCV2
if (!ioc_exists)
#endif
#ifdef CONFIG_ISA_ARCV2
if (slc_exists && !ioc_exists)
- __slc_line_op(start, end - start, OP_FLUSH);
+ __slc_rgn_op(start, end - start, OP_FLUSH);
#endif
}
#endif
sr r5, [ARC_AUX_IC_CTRL]
+ mov r5, 1
+ sr r5, [ARC_AUX_IC_IVIC]
+ ; As per ARC HS databook (see chapter 5.3.3.2)
+ ; it is required to add 3 NOPs after each write to IC_IVIC.
+ nop
+ nop
+ nop
+
1:
; Disable/enable D-cache according to configuration
lr r5, [ARC_BCR_DC_BUILD]
#endif
sr r5, [ARC_AUX_DC_CTRL]
+ mov r5, 1
+ sr r5, [ARC_AUX_DC_IVDC]
+
+
1:
#ifdef CONFIG_ISA_ARCV2
; Disable System-Level Cache (SLC)
from almost any address. This logic relies on the relocation
information that is embedded into the binary to support U-Boot
relocating itself to the top-of-RAM later during execution.
+
+config SYS_INIT_SP_BSS_OFFSET
+ int
+ help
+ U-Boot typically uses a hard-coded value for the stack pointer
+ before relocation. Define this option to instead calculate the
+ initial SP at run-time. This is useful to avoid hard-coding addresses
+ into U-Boot, so that can be loaded and executed at arbitrary
+ addresses and thus avoid using arbitrary addresses at runtime. This
+ option's value is the offset added to &_bss_start in order to
+ calculate the stack pointer. This offset should be large enough so
+ that the early malloc region, global data (gd), and early stack usage
+ do not overlap any appended DTB.
+
+config LINUX_KERNEL_IMAGE_HEADER
+ bool
+ help
+ Place a Linux kernel image header at the start of the U-Boot binary.
+ The format of the header is described in the Linux kernel source at
+ Documentation/arm64/booting.txt. This feature is useful since the
+ image header reports the amount of memory (BSS and similar) that
+ U-Boot needs to use, but which isn't part of the binary.
+
+if LINUX_KERNEL_IMAGE_HEADER
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ hex
+ help
+ The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
+ TEXT_OFFSET value written in to the Linux kernel image header.
+endif
endif
config STATIC_RELA
config ARM_ERRATA_852423
bool
+config ARM_ERRATA_855873
+ bool
+
config CPU_ARM720T
bool
select SYS_CACHE_SHIFT_5
config ARCH_QEMU
bool "QEMU Virtual Platform"
- select CPU_V7
- select ARCH_SUPPORT_PSCI
select DM
select DM_SERIAL
select OF_CONTROL
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
+config TARGET_LS1012A2G5RDB
+ bool "Support ls1012a2g5rdb"
+ select ARCH_LS1012A
+ select ARM64
+ select BOARD_LATE_INIT
+ imply SCSI
+ help
+ Support for Freescale LS1012A2G5RDB platform.
+ The LS1012A 2G5 Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
config TARGET_LS1012AFRDM
bool "Support ls1012afrdm"
select ARCH_LS1012A
obj-y += generic.o
obj-y += timer.o
obj-y += devices.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += relocate.o
obj-y += generic.o
obj-y += timer.o
obj-y += mx35_sdram.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += relocate.o
#
# SPDX-License-Identifier: GPL-2.0+
-obj-y = generic.o timer.o reset.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += generic.o timer.o reset.o relocate.o
#
# SPDX-License-Identifier: GPL-2.0+
-obj-y = generic.o reset.o timer.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
-endif
+obj-y += generic.o timer.o reset.o relocate.o
#endif
#ifdef CONFIG_ARM_ERRATA_454179
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+
cmp r2, #0x21 @ Only on < r2p1
- bge skip_errata_454179
+ orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
- mrc p15, 0, r0, c1, c0, 1 @ Read ACR
- orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
-
-skip_errata_454179:
#endif
#ifdef CONFIG_ARM_ERRATA_430973
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+
cmp r2, #0x21 @ Only on < r2p1
- bge skip_errata_430973
+ orrlt r0, r0, #(0x1 << 6) @ Set IBE bit
- mrc p15, 0, r0, c1, c0, 1 @ Read ACR
- orr r0, r0, #(0x1 << 6) @ Set IBE bit
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
-
-skip_errata_430973:
#endif
#ifdef CONFIG_ARM_ERRATA_621766
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+
cmp r2, #0x21 @ Only on < r2p1
- bge skip_errata_621766
+ orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit
- mrc p15, 0, r0, c1, c0, 1 @ Read ACR
- orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
-
-skip_errata_621766:
#endif
#ifdef CONFIG_ARM_ERRATA_725233
+ mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
+
cmp r2, #0x21 @ Only on < r2p1 (Cortex A8)
- bge skip_errata_725233
+ orrlt r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
- mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
- orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_l2aux_ctrl
pop {r1-r5} @ Restore the cpu info - fall through
-
-skip_errata_725233:
#endif
#ifdef CONFIG_ARM_ERRATA_852421
config PSCI_RESET
bool "Use PSCI for reset and shutdown"
default y
- depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
+ depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
- !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+ !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
+ !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS2081ARDB && \
config ARCH_LS1012A
bool
select ARMV8_SET_SMPEN
+ select ARM_ERRATA_855873
select FSL_LSCH2
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
+ select ARM_ERRATA_855873
select FSL_LSCH2
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
+ select ARM_ERRATA_855873
select FSL_LSCH3
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved memory alignment"
depends on RESV_RAM
- default 0x20000000 if ARCH_LS2080A
- default 0x70000000 if ARCH_LS1088A
+ default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
help
Reserved memory needs to be aligned for MC to use. Default value
is 512MB.
obj-y += cpu.o
obj-y += lowlevel.o
obj-y += soc.o
+ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
+endif
obj-$(CONFIG_SPL) += spl.o
obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
#endif
#include <asm/arch/clock.h>
#include <hwconfig.h>
+#include <fsl_qbman.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
+#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_qbman_portals();
#endif
return 0;
}
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id;
#endif
out_le32(cltbenr, 0xf);
#endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
/*
* In certain Layerscape SoCs, the clock for each core's
* has an enable bit in the PMU Physical Core Time Base Enable
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
description = "ARM64 Linux kernel";
data = /incbin/("./arch/arm64/boot/Image.gz");
type = "kernel";
load = <0x80080000>;
entry = <0x80080000>;
};
- fdt@1 {
+ fdt-1 {
description = "Flattened Device Tree blob";
data = /incbin/("./fsl-ls1043ardb-static.dtb");
type = "flat_dt";
compression = "none";
load = <0x90000000>;
};
- ramdisk@1 {
+ ramdisk {
description = "LS1043 Ramdisk";
data = /incbin/("./rootfs.cpio.gz");
type = "ramdisk";
};
configurations {
- default = "config@1";
- config@1 {
+ default = "config-1";
+ config-1 {
description = "Boot Linux kernel";
- kernel = "kernel@1";
- fdt = "fdt@1";
- ramdisk = "ramdisk@1";
+ kernel = "kernel";
+ fdt = "fdt-1";
+ ramdisk = "ramdisk";
loadables = "fdt", "ramdisk";
};
};
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
+#include <asm/arch/speed.h>
+#include <fsl_qbman.h>
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
fdt_fixup_esdhc(blob, bd);
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ fdt_fixup_bportals(blob);
+ fdt_fixup_qportals(blob);
+ do_fixup_by_compat_u32(blob, "fsl,qman",
+ "clock-frequency", get_qman_freq(), 1);
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
sys_info->freq_localbus = sys_info->freq_systembus /
CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ sys_info->freq_qman = sys_info->freq_systembus;
+#endif
}
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void)
+{
+ struct sys_info sys_info;
+
+ get_sys_info(&sys_info);
+
+ return sys_info.freq_qman;
+}
+#endif
+
int get_clocks(void)
{
struct sys_info sys_info;
serdes_prtcl_map[NONE] = 1;
}
+__weak int get_serdes_volt(void)
+{
+ return -1;
+}
+
+__weak int set_serdes_volt(int svdd)
+{
+ return -1;
+}
+
+#define LNAGCR0_RT_RSTB 0x00600000
+
+#define RSTCTL_RESET_MASK 0x000000E0
+
+#define RSTCTL_RSTREQ 0x80000000
+#define RSTCTL_RST_DONE 0x40000000
+#define RSTCTL_RSTERR 0x20000000
+
+#define RSTCTL_SDEN 0x00000020
+#define RSTCTL_SDRST_B 0x00000040
+#define RSTCTL_PLLRST_B 0x00000080
+
+#define TCALCR_CALRST_B 0x08000000
+
+struct serdes_prctl_info {
+ u32 id;
+ u32 mask;
+ u32 shift;
+};
+
+struct serdes_prctl_info srds_prctl_info[] = {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ {.id = 1,
+ .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
+ .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
+ },
+
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ {.id = 2,
+ .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
+ .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
+ },
+#endif
+ {} /* NULL ENTRY */
+};
+
+static int get_serdes_prctl_info_idx(u32 serdes_id)
+{
+ int pos = 0;
+ struct serdes_prctl_info *srds_info;
+
+ /* loop until NULL ENTRY defined by .id=0 */
+ for (srds_info = srds_prctl_info; srds_info->id != 0;
+ srds_info++, pos++) {
+ if (srds_info->id == serdes_id)
+ return pos;
+ }
+
+ return -1;
+}
+
+static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base,
+ bool cmplt)
+{
+ int i, pos;
+ u32 cfg_tmp;
+
+ pos = get_serdes_prctl_info_idx(serdes_id);
+ if (pos == -1) {
+ printf("invalid serdes_id %d\n", serdes_id);
+ return;
+ }
+
+ cfg_tmp = cfg & srds_prctl_info[pos].mask;
+ cfg_tmp >>= srds_prctl_info[pos].shift;
+
+ for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
+ if (cmplt)
+ setbits_le32(&serdes_base->lane[i].gcr0,
+ LNAGCR0_RT_RSTB);
+ else
+ clrbits_le32(&serdes_base->lane[i].gcr0,
+ LNAGCR0_RT_RSTB);
+ }
+}
+
+static void do_pll_reset(u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ int i;
+
+ for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+ clrbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_RESET_MASK);
+ udelay(1);
+
+ setbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_RSTREQ);
+ }
+ udelay(1);
+}
+
+static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
+{
+ clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+ clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+}
+
+static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ if (!(cfg == 0x3 && i == 1)) {
+ udelay(1);
+ setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+ setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+ }
+ udelay(1);
+}
+
+static void do_pll_reset_done(u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ int i;
+ u32 reg = 0;
+
+ for (i = 0; i < 2; i++) {
+ reg = in_le32(&serdes_base->bank[i].pllcr0);
+ if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
+ setbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_RST_DONE);
+ }
+ }
+}
+
+static void do_serdes_enable(u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ int i;
+
+ for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+ setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
+ udelay(1);
+
+ setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
+ udelay(1);
+ /* Take the Rx/Tx calibration out of reset */
+ do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
+ }
+}
+
+static void do_pll_lock(u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ int i;
+ u32 reg = 0;
+
+ for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+ /* if the PLL is not locked, set RST_ERR */
+ reg = in_le32(&serdes_base->bank[i].pllcr0);
+ if (!((reg >> 23) & 0x1)) {
+ setbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_RSTERR);
+ } else {
+ udelay(1);
+ setbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_SDRST_B);
+ udelay(1);
+ }
+ }
+}
+
+int setup_serdes_volt(u32 svdd)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_serdes __iomem *serdes1_base =
+ (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
+ u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ struct ccsr_serdes __iomem *serdes2_base =
+ (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
+ u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
+#endif
+ u32 cfg_tmp;
+ int svdd_cur, svdd_tar;
+ int ret = 1;
+
+ /* Only support switch SVDD to 900mV */
+ if (svdd != 900)
+ return -EINVAL;
+
+ /* Scale up to the LTC resolution is 1/4096V */
+ svdd = (svdd * 4096) / 1000;
+
+ svdd_tar = svdd;
+ svdd_cur = get_serdes_volt();
+ if (svdd_cur < 0)
+ return -EINVAL;
+
+ debug("%s: current SVDD: %x; target SVDD: %x\n",
+ __func__, svdd_cur, svdd_tar);
+ if (svdd_cur == svdd_tar)
+ return 0;
+
+ /* Put the all enabled lanes in reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
+#endif
+
+ /* Put the all enabled PLL in reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ cfg_tmp = cfg_rcwsrds1 & 0x3;
+ do_pll_reset(cfg_tmp, serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ cfg_tmp = cfg_rcwsrds1 & 0xC;
+ cfg_tmp >>= 2;
+ do_pll_reset(cfg_tmp, serdes2_base);
+#endif
+
+ /* Put the Rx/Tx calibration into reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ do_rx_tx_cal_reset(serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ do_rx_tx_cal_reset(serdes2_base);
+#endif
+
+ ret = set_serdes_volt(svdd);
+ if (ret < 0) {
+ printf("could not change SVDD\n");
+ ret = -1;
+ }
+
+ /* For each PLL that’s not disabled via RCW enable the SERDES */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ cfg_tmp = cfg_rcwsrds1 & 0x3;
+ do_serdes_enable(cfg_tmp, serdes1_base);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ cfg_tmp = cfg_rcwsrds1 & 0xC;
+ cfg_tmp >>= 2;
+ do_serdes_enable(cfg_tmp, serdes2_base);
+#endif
+
+ /* Wait for at at least 625us, ensure the PLLs being reset are locked */
+ udelay(800);
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ cfg_tmp = cfg_rcwsrds1 & 0x3;
+ do_pll_lock(cfg_tmp, serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ cfg_tmp = cfg_rcwsrds1 & 0xC;
+ cfg_tmp >>= 2;
+ do_pll_lock(cfg_tmp, serdes2_base);
+#endif
+ /* Take the all enabled lanes out of reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
+#endif
+
+ /* For each PLL being reset, and achieved PLL lock set RST_DONE */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ cfg_tmp = cfg_rcwsrds1 & 0x3;
+ do_pll_reset_done(cfg_tmp, serdes1_base);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ cfg_tmp = cfg_rcwsrds1 & 0xC;
+ cfg_tmp >>= 2;
+ do_pll_reset_done(cfg_tmp, serdes2_base);
+#endif
+
+ return ret;
+}
+
void fsl_serdes_init(void)
{
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_SYS_SATA2
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
#endif
#ifdef CONFIG_SYS_SATA1
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
}
#endif
+/* Get VDD in the unit mV from voltage ID */
+int get_core_volt_from_fuse(void)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ int vdd;
+ u32 fusesr;
+ u8 vid;
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_le32(&gur->dcfg_fusesr);
+ debug("%s: fusesr = 0x%x\n", __func__, fusesr);
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+ }
+ debug("%s: VID = 0x%x\n", __func__, vid);
+ switch (vid) {
+ case 0x00: /* VID isn't supported */
+ vdd = -EINVAL;
+ debug("%s: The VID feature is not supported\n", __func__);
+ break;
+ case 0x08: /* 0.9V silicon */
+ vdd = 900;
+ break;
+ case 0x10: /* 1.0V silicon */
+ vdd = 1000;
+ break;
+ default: /* Other core voltage */
+ vdd = -EINVAL;
+ debug("%s: The VID(%x) isn't supported\n", __func__, vid);
+ break;
+ }
+ debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
+
+ return vdd;
+}
+
#elif defined(CONFIG_FSL_LSCH2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
+#endif
+#ifdef CONFIG_VID
+ init_func_vid();
#endif
dram_init();
#ifdef CONFIG_SPL_FSL_LS_PPA
--- /dev/null
+/*
+ * (C) Copyright 2017 NVIDIA Corporation <www.nvidia.com>
+ *
+ * Derived from Linux kernel v4.14 files:
+ *
+ * arch/arm64/include/asm/assembler.h:
+ * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
+ * Copyright (C) 1996-2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * arch/arm64/kernel/head.S:
+ * Based on arch/arm/kernel/head.S
+ * Copyright (C) 1994-2002 Russell King
+ * Copyright (C) 2003-2012 ARM Ltd.
+ * Authors: Catalin Marinas <catalin.marinas@arm.com>
+ * Will Deacon <will.deacon@arm.com>
+ *
+ * arch/arm64/kernel/image.h:
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * There aren't any ELF relocations we can use to endian-swap values known only
+ * at link time (e.g. the subtraction of two symbol addresses), so we must get
+ * the linker to endian-swap certain values before emitting them.
+ *
+ * Note that, in order for this to work when building the ELF64 PIE executable
+ * (for KASLR), these values should not be referenced via R_AARCH64_ABS64
+ * relocations, since these are fixed up at runtime rather than at build time
+ * when PIE is in effect. So we need to split them up in 32-bit high and low
+ * words.
+ */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define DATA_LE32(data) \
+ ((((data) & 0x000000ff) << 24) | \
+ (((data) & 0x0000ff00) << 8) | \
+ (((data) & 0x00ff0000) >> 8) | \
+ (((data) & 0xff000000) >> 24))
+#else
+#define DATA_LE32(data) ((data) & 0xffffffff)
+#endif
+
+#define DEFINE_IMAGE_LE64(sym, data) \
+ sym##_lo32 = DATA_LE32((data) & 0xffffffff); \
+ sym##_hi32 = DATA_LE32((data) >> 32)
+
+#define __MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define __CODE_DATA_SIZE (__bss_start - _start)
+#define __BSS_SIZE (__bss_end - __bss_start)
+#ifdef CONFIG_SYS_INIT_SP_BSS_OFFSET
+#define __MAX_EXTRA_RAM_USAGE __MAX(__BSS_SIZE, CONFIG_SYS_INIT_SP_BSS_OFFSET)
+#else
+#define __MAX_EXTRA_RAM_USAGE __BSS_SIZE
+#endif
+#define __MEM_USAGE (__CODE_DATA_SIZE + __MAX_EXTRA_RAM_USAGE)
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define __HEAD_FLAG_BE 1
+#else
+#define __HEAD_FLAG_BE 0
+#endif
+
+#define __HEAD_FLAG_PAGE_SIZE 1 /* 4K hard-coded */
+
+#define __HEAD_FLAG_PHYS_BASE 1
+
+#define __HEAD_FLAGS ((__HEAD_FLAG_BE << 0) | \
+ (__HEAD_FLAG_PAGE_SIZE << 1) | \
+ (__HEAD_FLAG_PHYS_BASE << 3))
+
+#define TEXT_OFFSET (CONFIG_SYS_TEXT_BASE - \
+ CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE)
+
+/*
+ * These will output as part of the Image header, which should be little-endian
+ * regardless of the endianness of the kernel. While constant values could be
+ * endian swapped in head.S, all are done here for consistency.
+ */
+#define HEAD_SYMBOLS \
+ DEFINE_IMAGE_LE64(_kernel_size_le, __MEM_USAGE); \
+ DEFINE_IMAGE_LE64(_kernel_offset_le, TEXT_OFFSET); \
+ DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS);
+
+ HEAD_SYMBOLS
#define SEC_FIRMWARE_FIT_IMAGE "firmware"
#endif
#ifndef SEC_FIRMEWARE_FIT_CNF_NAME
-#define SEC_FIRMEWARE_FIT_CNF_NAME "config@1"
+#define SEC_FIRMEWARE_FIT_CNF_NAME "config-1"
#endif
#ifndef SEC_FIRMWARE_TARGET_EL
#define SEC_FIRMWARE_TARGET_EL 2
.globl _start
_start:
-#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+#if defined(LINUX_KERNEL_IMAGE_HEADER)
+#include <asm/boot0-linux-kernel-header.h>
+#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
/*
* Various SoCs need something special and SoC-specific up front in
* order to boot, allow them to set that in their boot0.h file and then
WEAK(apply_core_errata)
mov x29, lr /* Save LR */
- /* For now, we support Cortex-A57 specific errata only */
+ /* For now, we support Cortex-A53, Cortex-A57 specific errata */
+
+ /* Check if we are running on a Cortex-A53 core */
+ branch_if_a53_core x0, apply_a53_core_errata
/* Check if we are running on a Cortex-A57 core */
branch_if_a57_core x0, apply_a57_core_errata
mov lr, x29 /* Restore LR */
ret
+apply_a53_core_errata:
+
+#ifdef CONFIG_ARM_ERRATA_855873
+ mrs x0, midr_el1
+ tst x0, #(0xf << 20)
+ b.ne 0b
+
+ mrs x0, midr_el1
+ and x0, x0, #0xf
+ cmp x0, #3
+ b.lt 0b
+
+ mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
+ /* Enable data cache clean as data cache clean/invalidate */
+ orr x0, x0, #1 << 44
+ msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+#endif
+ b 0b
+
apply_a57_core_errata:
#ifdef CONFIG_ARM_ERRATA_828024
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
+
+#ifdef CONFIG_LINUX_KERNEL_IMAGE_HEADER
+#include "linux-kernel-image-header-vars.h"
+#endif
}
dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
am57xx-beagle-x15-revb1.dtb \
am57xx-beagle-x15-revc.dtb \
+ am574x-idk.dtb \
am572x-idk.dtb \
am571x-idk.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
+ fsl-ls1012a-2g5rdb.dtb \
fsl-ls1012a-frdm.dtb
-dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
+dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
+dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
+
+dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
+ stm32f469-disco.dtb
dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
stm32f769-disco.dtb
dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
+ sun8i-h3-libretech-all-h3-cc.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb \
imx6sx-sabreauto.dtb \
+ imx6sx-sdb.dtb \
imx6ul-geam-kit.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-mmc.dtb \
omap3-evm-37xx.dtb \
omap3-evm.dtb
+dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
+ omap3-beagle-xm-ab.dtb \
+ omap3-beagle-xm.dtb \
+ omap3-beagle.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
at91-sama5d2_ptc_ek.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-idk-common.dtsi"
+
+/ {
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ status-leds {
+ compatible = "gpio-leds";
+ cpu0-led {
+ label = "status0:red:cpu0";
+ gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu0";
+ };
+
+ usr0-led {
+ label = "status0:green:usr";
+ gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ heartbeat-led {
+ label = "status0:blue:heartbeat";
+ gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ cpu1-led {
+ label = "status1:red:cpu1";
+ gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu1";
+ };
+
+ usr1-led {
+ label = "status1:green:usr";
+ gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ mmc0-led {
+ label = "status1:blue:mmc0";
+ gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ };
+ };
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
+
+&extcon_usb2 {
+ id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+};
+
+&sn65hvs882 {
+ load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+};
+
+&pcie1_rc {
+ status = "okay";
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
/dts-v1/;
#include "dra74x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "am572x-idk-common.dtsi"
#include "am57xx-idk-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
model = "TI AM5728 IDK";
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
"ti,dra7";
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x80000000>;
- };
-
- status-leds {
- compatible = "gpio-leds";
- cpu0-led {
- label = "status0:red:cpu0";
- gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "cpu0";
- };
-
- usr0-led {
- label = "status0:green:usr";
- gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- heartbeat-led {
- label = "status0:blue:heartbeat";
- gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "heartbeat";
- };
-
- cpu1-led {
- label = "status1:red:cpu1";
- gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "cpu1";
- };
-
- usr1-led {
- label = "status1:green:usr";
- gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- mmc0-led {
- label = "status1:blue:mmc0";
- gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "mmc0";
- };
- };
};
&mmc1 {
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
};
-
-&omap_dwc3_2 {
- extcon = <&extcon_usb2>;
-};
-
-&extcon_usb2 {
- id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
- vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
-};
-
-&sn65hvs882 {
- load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
-};
-
-&pcie1_rc {
- status = "okay";
- gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
-};
-
-&pcie1_ep {
- gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
-};
-
-&mailbox5 {
- status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
-};
-
-&mailbox6 {
- status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
- status = "okay";
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+
+/dts-v1/;
+
+#include "dra76x.dtsi"
+#include "am572x-idk-common.dtsi"
+
+/ {
+ model = "TI AM5748 IDK";
+ compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7";
+};
+
+&qspi {
+ spi-max-frequency = <96000000>;
+ m25p80@0 {
+ spi-max-frequency = <96000000>;
+ };
+};
+// SPDX-License-Identifier: GPL-2.0
&cpu_alert0 {
temperature = <80000>; /* milliCelsius */
};
+// SPDX-License-Identifier: GPL-2.0
&cpu_alert0 {
temperature = <90000>; /* milliCelsius */
};
aliases {
ethernet0 = ð0;
- ethernet1 = ð1;
+ ethernet1 = ð2;
i2c0 = &i2c0;
spi1 = &spi1;
};
jtag_gpio4: jtag_gpio4 {
brcm,pins = <4 5 6 12 13>;
- brcm,function = <BCM2835_FSEL_ALT4>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
};
jtag_gpio22: jtag_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
reg = <0 0x80000000 0 0x3da00000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ };
+
chosen {
stdout-path = "/soc/serial@78b0000";
};
-
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
clock = <&clkc 4>;
};
- restart@4ab000 {
- compatible = "qcom,pshold";
- reg = <0x4ab000 0x4>;
- };
-
soc_gpios: pinctrl@1000000 {
compatible = "qcom,apq8016-pinctrl";
reg = <0x1000000 0x300000>;
clock-frequency = <200000000>;
};
+ wcnss {
+ bt {
+ compatible="qcom,wcnss-bt";
+ };
+
+ wifi {
+ compatible="qcom,wcnss-wlan";
+ };
+ };
+
spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>;
--- /dev/null
+/*
+ * U-Boot addition to handle Dragonboard 820c pins
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&pm8994_pon {
+ key_vol_down {
+ gpios = <&pm8994_pon 1 0>;
+ label = "key_vol_down";
+ };
+
+ key_power {
+ gpios = <&pm8994_pon 0 0>;
+ label = "key_power";
+ };
+};
--- /dev/null
+/*
+ * Qualcomm APQ8096 based Dragonboard 820C board device tree source
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. DB820c";
+ compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &blsp2_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0xc0000000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@300000 {
+ compatible = "qcom,gcc-msm8996";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0x300000 0x90000>;
+ };
+
+ blsp2_uart1: serial@75b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x75b0000 0x1000>;
+ };
+
+ sdhc2: sdhci@74a4900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+ index = <0x0>;
+ bus-width = <4>;
+ clock = <&gcc 0>;
+ clock-frequency = <200000000>;
+ };
+
+ spmi@400f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x400f800 0x200>,
+ <0x4400000 0x400000>,
+ <0x4c00000 0x400000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ pmic0: pm8994@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ pm8994_pon: pm8994_pon@800 {
+ compatible = "qcom,pm8994-pwrkey";
+ reg = <0x800 0x96>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name="pm8994_key.";
+ };
+
+ pm8994_gpios: pm8994_gpios@c000 {
+ compatible = "qcom,pm8994-gpio";
+ reg = <0xc000 0x400>;
+ gpio-controller;
+ gpio-count = <24>;
+ #gpio-cells = <2>;
+ gpio-bank-name="pm8994.";
+ };
+ };
+
+ pmic1: pm8994@1 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x1 0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+ };
+ };
+
+};
+
+#include "dragonboard820c-uboot.dtsi"
--- /dev/null
+/*
+ * NXP ls1012a 2G5RDB board device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A 2G5RDB Board";
+
+ aliases {
+ spi0 = &qspi;
+ };
+
+ chosen {
+ stdout-path = &duart0;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};
*
* Copyright 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1012a.dtsi"
/*
* Copyright 2016 Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
/*
* Copyright 2016 Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1012a.dtsi"
&duart0 {
status = "okay";
};
+
+&usb0 {
+ status = "okay";
+ phy_type = "ulpi";
+};
*
* Copyright 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2016, Freescale Semiconductor
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1012a.dtsi"
/*
* Copyright 2016 Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton64.dtsi"
*
* Copyright (C) 2015, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright (C) 2015, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1043a.dtsi"
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton64.dtsi"
*
* Copyright (C) 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright (C) 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Mingkai Hu <Mingkai.hu@nxp.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1046a.dtsi"
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Mingkai Hu <mingkai.hu@nxp.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton64.dtsi"
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/ {
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/ {
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sx-sdb.dtsi"
+
+/ {
+ model = "Freescale i.MX6 SoloX SDB RevB Board";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pfuze100@8 {
+ compatible = "fsl,pfuze200";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&qspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi2>;
+ status = "okay";
+
+ flash0: n25q256a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ reg = <0>;
+ };
+
+ flash1: n25q256a@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ reg = <1>;
+ };
+};
+
+®_arm {
+ vin-supply = <&sw1a_reg>;
+};
+
+®_soc {
+ vin-supply = <&sw1a_reg>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sx.dtsi"
+
+/ {
+ model = "Freescale i.MX6 SoloX SDB Board";
+ compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vcc_sd3: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vcc_sd3>;
+ regulator-name = "VCC_SD3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg1_vbus: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg2_vbus: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg2>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_psu_5v: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "PSU-5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_lcd_3v3: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "lcd-3v3";
+ gpio = <&gpio3 27 0>;
+ enable-active-high;
+ };
+
+ reg_peri_3v3: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_peri_3v3>;
+ regulator-name = "peri_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_enet_3v3: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_3v3>;
+ regulator-name = "enet_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+ ssi-controller = <&ssi2>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "AMIC", "MICBIAS",
+ "IN3R", "AMIC";
+ mux-int-port = <2>;
+ mux-ext-port = <6>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-supply = <®_enet_3v3>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ };
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ codec: wm8962@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clks IMX6SX_CLK_AUDIO>;
+ DCVDD-supply = <&vgen4_reg>;
+ DBVDD-supply = <&vgen4_reg>;
+ AVDD-supply = <&vgen4_reg>;
+ CPVDD-supply = <&vgen4_reg>;
+ MICVDD-supply = <&vgen3_reg>;
+ PLLVDD-supply = <&vgen4_reg>;
+ SPKVDD1-supply = <®_psu_5v>;
+ SPKVDD2-supply = <®_psu_5v>;
+ };
+};
+
+&lcdif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd>;
+ lcd-supply = <®_lcd_3v3>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <16>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <33500000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <89>;
+ hfront-porch = <164>;
+ vback-porch = <23>;
+ vfront-porch = <10>;
+ hsync-len = <10>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ status = "disabled";
+};
+
+&ssi2 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart5 { /* for bluetooth */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1_id>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usb_otg2_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy1 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ non-removable;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <&vcc_sd3>;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ imx6x-sdb {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
+ MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
+ MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
+ MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
+ MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
+ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
+ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
+ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
+ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
+ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
+ MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
+ >;
+ };
+
+ pinctrl_enet_3v3: enet3v3grp {
+ fsl,pins = <
+ MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
+ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
+ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
+ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio_keysgrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
+ MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
+ MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
+ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
+ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_lcd: lcdgrp {
+ fsl,pins = <
+ MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
+ MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
+ MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+ MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+ MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
+ >;
+ };
+
+ pinctrl_peri_3v3: peri3v3grp {
+ fsl,pins = <
+ MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_qspi2: qspi2grp {
+ fsl,pins = <
+ MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
+ MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
+ MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
+ MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
+ MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
+ MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
+ MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
+ MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
+ MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
+ MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
+ MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
+ MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
+ >;
+ };
+
+ pinctrl_vcc_sd3: vccsd3grp {
+ fsl,pins = <
+ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
+ MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
+ MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
+ MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
+ MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
+ MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
+ MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
+ MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
+ >;
+ };
+
+ pinctrl_usb_otg1_id: usbotg1idgrp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usb_otg2: usbot2ggrp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
+ MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
+ MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
+ MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
+ MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
+ MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
+ MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
+ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
+ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
+ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+ MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
+ MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+ };
+};
};
};
- spi4 {
+ spi5 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "micron,n25q256a";
+ /* compatible = "micron,n25q256a"; */
+ compatible = "spi-flash";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
reg = <0>;
serial5 = &uart6;
serial6 = &uart7;
serial7 = &uart8;
- spi0 = &ecspi1;
- spi1 = &ecspi2;
- spi2 = &ecspi3;
- spi3 = &ecspi4;
+ spi0 = &qspi;
+ spi1 = &ecspi1;
+ spi2 = &ecspi2;
+ spi3 = &ecspi3;
+ spi4 = &ecspi4;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
serial2 = &lpuart6;
serial3 = &lpuart7;
usbphy0 = &usbphy1;
- i2c0 = &lpi2c4;
- i2c1 = &lpi2c5;
- i2c2 = &lpi2c6;
- i2c3 = &lpi2c7;
+ i2c4 = &lpi2c4;
+ i2c5 = &lpi2c5;
+ i2c6 = &lpi2c6;
+ i2c7 = &lpi2c7;
};
cpus {
--- /dev/null
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&mmc1 {
+ cd-inverted;
+};
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
--- /dev/null
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&mmc1 {
+ cd-inverted;
+};
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-beagle-xm.dts"
+
+/ {
+ /* HS USB Port 2 Power enable was inverted with the xM C */
+ hsusb2_power: hsusb2_power_reg {
+ enable-active-high;
+ };
+};
--- /dev/null
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&mmc1 {
+ cd-inverted;
+};
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+
+/ {
+ model = "TI OMAP3 BeagleBoard xM";
+ compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vcc>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+
+ aliases {
+ display0 = &dvi0;
+ display1 = &tv0;
+ ethernet = ðernet;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ label = "beagleboard::usr0";
+ gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
+ linux,default-trigger = "heartbeat";
+ };
+
+ mmc {
+ label = "beagleboard::usr1";
+ gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+
+ pmu_stat {
+ label = "beagleboard::pmu_stat";
+ pwms = <&twl_pwmled 1 7812500>;
+ max-brightness = <127>;
+ };
+ };
+
+ sound {
+ compatible = "ti,omap-twl4030";
+ ti,model = "omap3beagle";
+
+ ti,mcbsp = <&mcbsp2>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ user {
+ label = "user";
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ linux,code = <0x114>;
+ wakeup-source;
+ };
+
+ };
+
+ /* HS USB Port 2 Power */
+ hsusb2_power: hsusb2_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb2_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */
+ startup-delay-us = <70000>;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
+ vcc-supply = <&hsusb2_power>;
+ #phy-cells = <0>;
+ };
+
+ tfp410: encoder0 {
+ compatible = "ti,tfp410";
+ powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
+
+ /* XXX pinctrl from twl */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
+ dvi0: connector0 {
+ compatible = "dvi-connector";
+ label = "dvi";
+
+ digital;
+
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ tv0: connector1 {
+ compatible = "svideo-connector";
+ label = "tv";
+
+ port {
+ tv_connector_in: endpoint {
+ remote-endpoint = <&venc_out>;
+ };
+ };
+ };
+
+ etb@5401b000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0x5401b000 0x1000>;
+
+ clocks = <&emu_src_ck>;
+ clock-names = "apb_pclk";
+ port {
+ etb_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm_out>;
+ };
+ };
+ };
+
+ etm@54010000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x54010000 0x1000>;
+
+ clocks = <&emu_src_ck>;
+ clock-names = "apb_pclk";
+ port {
+ etm_out: endpoint {
+ remote-endpoint = <&etb_in>;
+ };
+ };
+ };
+};
+
+&omap3_pmx_wkup {
+ gpio1_pins: pinmux_gpio1_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
+ >;
+ };
+
+ dss_dpi_pins2: pinmux_dss_dpi_pins1 {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
+ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
+ OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
+ OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
+ OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
+ OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
+ >;
+ };
+};
+
+&omap3_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &hsusb2_pins
+ >;
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+ >;
+ };
+
+ hsusb2_pins: pinmux_hsusb2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
+ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
+ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
+ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
+ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
+ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
+ >;
+ };
+
+ dss_dpi_pins1: pinmux_dss_dpi_pins2 {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
+ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
+ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
+ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
+
+ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
+ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
+ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
+ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
+ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
+ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
+ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
+ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
+ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
+ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
+ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
+ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
+
+ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
+ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
+ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
+ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
+ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
+ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &hsusb2_2_pins
+ >;
+
+ hsusb2_2_pins: pinmux_hsusb2_2_pins {
+ pinctrl-single,pins = <
+ OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
+ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
+ OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
+ OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
+ OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
+ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
+ >;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <2600000>;
+
+ twl: twl@48 {
+ reg = <0x48>;
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+
+ twl_audio: audio {
+ compatible = "ti,twl4030-audio";
+ codec {
+ };
+ };
+
+ twl_power: power {
+ compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off";
+ ti,use_poweroff;
+ };
+ };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&i2c2 {
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc1>;
+ vqmmc-supply = <&vsim>;
+ bus-width = <8>;
+};
+
+&mmc2 {
+ status = "disabled";
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&twl_gpio {
+ ti,use-leds;
+ /* pullups: BIT(1) */
+ ti,pullups = <0x000002>;
+ /*
+ * pulldowns:
+ * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+ * BIT(15), BIT(16), BIT(17)
+ */
+ ti,pulldowns = <0x03a1c4>;
+};
+
+&usb_otg_hs {
+ interface-type = <0>;
+ usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
+ mode = <3>;
+ power = <50>;
+};
+
+&uart3 {
+ interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_pins>;
+};
+
+&usbhshost {
+ port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <0 &hsusb2_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub@2 {
+ compatible = "usb424,9514";
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ };
+ };
+};
+
+&vaux2 {
+ regulator-name = "usb_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+};
+
+&mcbsp2 {
+ status = "okay";
+};
+
+&dss {
+ status = "ok";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &dss_dpi_pins1
+ &dss_dpi_pins2
+ >;
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&venc {
+ status = "ok";
+
+ vdda-supply = <&vdac>;
+
+ port {
+ venc_out: endpoint {
+ remote-endpoint = <&tv_connector_in>;
+ ti,channels = <2>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap34xx.dtsi"
+
+/ {
+ model = "TI OMAP3 BeagleBoard";
+ compatible = "ti,omap3-beagle", "ti,omap3";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vcc>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ aliases {
+ display0 = &dvi0;
+ display1 = &tv0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pmu_stat {
+ label = "beagleboard::pmu_stat";
+ gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
+ };
+
+ heartbeat {
+ label = "beagleboard::usr0";
+ gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
+ linux,default-trigger = "heartbeat";
+ };
+
+ mmc {
+ label = "beagleboard::usr1";
+ gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ /* HS USB Port 2 Power */
+ hsusb2_power: hsusb2_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb2_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */
+ startup-delay-us = <70000>;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
+ vcc-supply = <&hsusb2_power>;
+ #phy-cells = <0>;
+ };
+
+ sound {
+ compatible = "ti,omap-twl4030";
+ ti,model = "omap3beagle";
+
+ ti,mcbsp = <&mcbsp2>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ user {
+ label = "user";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ linux,code = <0x114>;
+ wakeup-source;
+ };
+
+ };
+
+ tfp410: encoder0 {
+ compatible = "ti,tfp410";
+ powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tfp410_pins>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
+ dvi0: connector0 {
+ compatible = "dvi-connector";
+ label = "dvi";
+
+ digital;
+
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ tv0: connector1 {
+ compatible = "svideo-connector";
+ label = "tv";
+
+ port {
+ tv_connector_in: endpoint {
+ remote-endpoint = <&venc_out>;
+ };
+ };
+ };
+
+ etb@540000000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0x5401b000 0x1000>;
+
+ clocks = <&emu_src_ck>;
+ clock-names = "apb_pclk";
+ port {
+ etb_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm_out>;
+ };
+ };
+ };
+
+ etm@54010000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x54010000 0x1000>;
+
+ clocks = <&emu_src_ck>;
+ clock-names = "apb_pclk";
+ port {
+ etm_out: endpoint {
+ remote-endpoint = <&etb_in>;
+ };
+ };
+ };
+};
+
+&omap3_pmx_wkup {
+ gpio1_pins: pinmux_gpio1_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */
+ >;
+ };
+};
+
+&omap3_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &hsusb2_pins
+ >;
+
+ hsusb2_pins: pinmux_hsusb2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
+ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
+ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
+ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
+ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
+ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+ >;
+ };
+
+ tfp410_pins: pinmux_tfp410_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
+ >;
+ };
+
+ dss_dpi_pins: pinmux_dss_dpi_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
+ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
+ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
+ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
+ OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
+ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
+ OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
+ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
+ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
+ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
+ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
+ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
+ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
+ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
+ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
+ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
+ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
+ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
+ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
+ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
+ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
+ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
+ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
+ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
+ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
+ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
+ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
+ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &hsusb2_2_pins
+ >;
+
+ hsusb2_2_pins: pinmux_hsusb2_2_pins {
+ pinctrl-single,pins = <
+ OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
+ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
+ OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
+ OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
+ OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
+ OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
+ >;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <2600000>;
+
+ twl: twl@48 {
+ reg = <0x48>;
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+
+ twl_audio: audio {
+ compatible = "ti,twl4030-audio";
+ codec {
+ };
+ };
+ };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&i2c3 {
+ clock-frequency = <100000>;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc1>;
+ vqmmc-supply = <&vsim>;
+ bus-width = <8>;
+};
+
+&mmc2 {
+ status = "disabled";
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&usbhshost {
+ port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <0 &hsusb2_phy>;
+};
+
+&twl_gpio {
+ ti,use-leds;
+ /* pullups: BIT(1) */
+ ti,pullups = <0x000002>;
+ /*
+ * pulldowns:
+ * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+ * BIT(15), BIT(16), BIT(17)
+ */
+ ti,pulldowns = <0x03a1c4>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_pins>;
+};
+
+&usb_otg_hs {
+ interface-type = <0>;
+ usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
+ mode = <3>;
+ power = <50>;
+};
+
+&vaux2 {
+ regulator-name = "vdd_ehci";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+};
+
+&mcbsp2 {
+ status = "okay";
+};
+
+/* Needed to power the DPI pins */
+&vpll2 {
+ regulator-always-on;
+};
+
+&dss {
+ status = "ok";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_dpi_pins>;
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&venc {
+ status = "ok";
+
+ vdda-supply = <&vdac>;
+
+ port {
+ venc_out: endpoint {
+ remote-endpoint = <&tv_connector_in>;
+ ti,channels = <2>;
+ };
+ };
+};
+
+&gpmc {
+ status = "ok";
+ ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */
+
+ /* Chip select 0 */
+ nand@0,0 {
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* NAND I/O window, 4 bytes */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ ti,nand-ecc-opt = "ham1";
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ nand-bus-width = <16>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpmc,device-width = <2>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <36>;
+ gpmc,cs-wr-off-ns = <36>;
+ gpmc,adv-on-ns = <6>;
+ gpmc,adv-rd-off-ns = <24>;
+ gpmc,adv-wr-off-ns = <36>;
+ gpmc,oe-on-ns = <6>;
+ gpmc,oe-off-ns = <48>;
+ gpmc,we-on-ns = <6>;
+ gpmc,we-off-ns = <30>;
+ gpmc,rd-cycle-ns = <72>;
+ gpmc,wr-cycle-ns = <72>;
+ gpmc,access-ns = <54>;
+ gpmc,wr-access-ns = <30>;
+
+ partition@0 {
+ label = "X-Loader";
+ reg = <0 0x80000>;
+ };
+ partition@80000 {
+ label = "U-Boot";
+ reg = <0x80000 0x1e0000>;
+ };
+ partition@1c0000 {
+ label = "U-Boot Env";
+ reg = <0x260000 0x20000>;
+ };
+ partition@280000 {
+ label = "Kernel";
+ reg = <0x280000 0x400000>;
+ };
+ partition@780000 {
+ label = "Filesystem";
+ reg = <0x680000 0xf980000>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+#include <dt-bindings/mfd/stm32f4-rcc.h>
+
+/ {
+ soc {
+ pinctrl: pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
+ pins-are-numbered;
+
+ gpioa: gpio@40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
+ st,bank-name = "GPIOA";
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x400 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
+ st,bank-name = "GPIOB";
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x800 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
+ st,bank-name = "GPIOC";
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xc00 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
+ st,bank-name = "GPIOD";
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
+ st,bank-name = "GPIOE";
+ };
+
+ gpiof: gpio@40021400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1400 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
+ st,bank-name = "GPIOF";
+ };
+
+ gpiog: gpio@40021800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1800 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
+ st,bank-name = "GPIOG";
+ };
+
+ gpioh: gpio@40021c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1c00 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
+ st,bank-name = "GPIOH";
+ };
+
+ gpioi: gpio@40022000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
+ st,bank-name = "GPIOI";
+ };
+
+ gpioj: gpio@40022400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2400 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
+ st,bank-name = "GPIOJ";
+ };
+
+ gpiok: gpio@40022800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2800 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
+ st,bank-name = "GPIOK";
+ };
+
+ usart1_pins_a: usart1@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ usart3_pins_a: usart3@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
+ bias-disable;
+ };
+ };
+
+ usbotg_fs_pins_a: usbotg_fs@0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
+ <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
+ <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_fs_pins_b: usbotg_fs@1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
+ <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
+ <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_hs_pins_a: usbotg_hs@0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
+ <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
+ <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+ <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+ <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+ <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+ <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+ <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+ <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+ <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+ <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+ <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ ethernet_mii: mii@0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
+ <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
+ <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
+ <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
+ <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
+ <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
+ <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
+ slew-rate = <2>;
+ };
+ };
+
+ adc3_in8_pin: adc@200 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+ };
+ };
+
+ pwm1_pins: pwm@1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
+ <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
+ <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
+ };
+ };
+
+ pwm3_pins: pwm@3 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
+ <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
+ };
+ };
+
+ i2c1_pins: i2c1@0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
+ <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <3>;
+ };
+ };
+
+ ltdc_pins: ltdc@0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
+ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
+ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
+ <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
+ slew-rate = <2>;
+ };
+ };
+
+ dcmi_pins: dcmi@0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
+ <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
+ <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
+ <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
+ <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
+ <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
+ <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
+ <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
+ <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
+ <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
+ <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ sdio_pins: sdio_pins@0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>,
+ <STM32_PINMUX('C', 9, AF12)>,
+ <STM32_PINMUX('C', 10, AF12)>,
+ <STM32_PINMUX('c', 11, AF12)>,
+ <STM32_PINMUX('C', 12, AF12)>,
+ <STM32_PINMUX('D', 2, AF12)>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>,
+ <STM32_PINMUX('C', 9, AF12)>,
+ <STM32_PINMUX('C', 10, AF12)>,
+ <STM32_PINMUX('C', 11, AF12)>,
+ <STM32_PINMUX('C', 12, AF12)>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>;
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/memory/stm32-sdram.h>
+/{
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+
+ aliases {
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ pin-controller {
+ u-boot,dm-pre-reloc;
+ };
+
+ fmc: fmc@A0000000 {
+ compatible = "st,stm32-fmc";
+ reg = <0xA0000000 0x1000>;
+ clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
+ pinctrl-0 = <&fmc_pins>;
+ pinctrl-names = "default";
+ u-boot,dm-pre-reloc;
+
+ /*
+ * Memory configuration from sdram datasheet
+ * IS42S16400J
+ */
+ bank1: bank@1 {
+ st,sdram-control = /bits/ 8 <NO_COL_8
+ NO_ROW_12
+ MWIDTH_16
+ BANKS_4
+ CAS_3
+ SDCLK_2
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_3
+ TXSR_7
+ TRAS_4
+ TRC_6
+ TWR_2
+ TRP_2 TRCD_2>;
+ st,sdram-refcount = < 1386 >;
+ };
+ };
+ };
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_i2s_ckin {
+ u-boot,dm-pre-reloc;
+};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ usart1_pins_a: usart1@0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ fmc_pins: fmc@0 {
+ u-boot,dm-pre-reloc;
+ pins
+ {
+ pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
+ <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+ <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+ <STM32_PINMUX('E',15, AF12)>, /* D12 */
+ <STM32_PINMUX('E',14, AF12)>, /* D11 */
+ <STM32_PINMUX('E',13, AF12)>, /* D10 */
+ <STM32_PINMUX('E',12, AF12)>, /* D09 */
+ <STM32_PINMUX('E',11, AF12)>, /* D08 */
+ <STM32_PINMUX('E',10, AF12)>, /* D07 */
+ <STM32_PINMUX('E', 9, AF12)>, /* D06 */
+ <STM32_PINMUX('E', 8, AF12)>, /* D05 */
+ <STM32_PINMUX('E', 7, AF12)>, /* D04 */
+ <STM32_PINMUX('D', 1, AF12)>, /* D03 */
+ <STM32_PINMUX('D', 0, AF12)>, /* D02 */
+ <STM32_PINMUX('D',15, AF12)>, /* D01 */
+ <STM32_PINMUX('D',14, AF12)>, /* D00 */
+
+ <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+ <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+
+ <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+ <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+ <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+ <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+ <STM32_PINMUX('F',15, AF12)>, /* A09 */
+ <STM32_PINMUX('F',14, AF12)>, /* A08 */
+ <STM32_PINMUX('F',13, AF12)>, /* A07 */
+ <STM32_PINMUX('F',12, AF12)>, /* A06 */
+ <STM32_PINMUX('F', 5, AF12)>, /* A05 */
+ <STM32_PINMUX('F', 4, AF12)>, /* A04 */
+ <STM32_PINMUX('F', 3, AF12)>, /* A03 */
+ <STM32_PINMUX('F', 2, AF12)>, /* A02 */
+ <STM32_PINMUX('F', 1, AF12)>, /* A01 */
+ <STM32_PINMUX('F', 0, AF12)>, /* A00 */
+
+ <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */
+ <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
+ <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+ <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+ <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
+ <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
+ slew-rate = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
+ * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f429.dtsi"
+#include "stm32f429-pinctrl.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "STMicroelectronics STM32F429i-DISCO board";
+ compatible = "st,stm32f429i-disco", "st,stm32f429";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x90000000 0x800000>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ red {
+ gpios = <&gpiog 14 0>;
+ };
+ green {
+ gpios = <&gpiog 13 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "User";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpioa 0 0>;
+ };
+ };
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpioc 4 0>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
+};
+
+&clk_hse {
+ clock-frequency = <8000000>;
+};
+
+&crc {
+ status = "okay";
+};
+
+&rtc {
+ assigned-clocks = <&rcc 1 CLK_RTC>;
+ assigned-clock-parents = <&rcc 1 CLK_LSI>;
+ status = "okay";
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbotg_hs {
+ compatible = "st,stm32f4x9-fsotg";
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "stm32f4-pinctrl.dtsi"
+
+/ {
+ soc {
+ pinctrl: pin-controller {
+ compatible = "st,stm32f429-pinctrl";
+
+ gpioa: gpio@40020000 {
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@40021400 {
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@40021800 {
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@40021c00 {
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@40022000 {
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@40022400 {
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@40022800 {
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
+ * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f4-rcc.h>
+
+/ {
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_i2s_ckin: i2s-ckin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+ };
+
+ soc {
+ timer2: timer@40000000 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000000 0x400>;
+ interrupts = <28>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
+ status = "disabled";
+ };
+
+ timers2: timers@40000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@1 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+
+ timer3: timer@40000400 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000400 0x400>;
+ interrupts = <29>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
+ status = "disabled";
+ };
+
+ timers3: timers@40000400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000400 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@2 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
+ timer4: timer@40000800 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000800 0x400>;
+ interrupts = <30>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
+ status = "disabled";
+ };
+
+ timers4: timers@40000800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000800 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@3 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <3>;
+ status = "disabled";
+ };
+ };
+
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
+ };
+
+ timers5: timers@40000c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000C00 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@4 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+
+ timer6: timer@40001000 {
+ compatible = "st,stm32-timer";
+ reg = <0x40001000 0x400>;
+ interrupts = <54>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
+ status = "disabled";
+ };
+
+ timers6: timers@40001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
+ clock-names = "int";
+ status = "disabled";
+
+ timer@5 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ timer7: timer@40001400 {
+ compatible = "st,stm32-timer";
+ reg = <0x40001400 0x400>;
+ interrupts = <55>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
+ status = "disabled";
+ };
+
+ timers7: timers@40001400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001400 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
+ clock-names = "int";
+ status = "disabled";
+
+ timer@6 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <6>;
+ status = "disabled";
+ };
+ };
+
+ timers12: timers@40001800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001800 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@11 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <11>;
+ status = "disabled";
+ };
+ };
+
+ timers13: timers@40001c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001C00 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
+ timers14: timers@40002000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40002000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
+ rtc: rtc@40002800 {
+ compatible = "st,stm32-rtc";
+ reg = <0x40002800 0x400>;
+ clocks = <&rcc 1 CLK_RTC>;
+ clock-names = "ck_rtc";
+ assigned-clocks = <&rcc 1 CLK_RTC>;
+ assigned-clock-parents = <&rcc 1 CLK_LSE>;
+ interrupt-parent = <&exti>;
+ interrupts = <17 1>;
+ interrupt-names = "alarm";
+ st,syscfg = <&pwrcfg>;
+ status = "disabled";
+ };
+
+ iwdg: watchdog@40003000 {
+ compatible = "st,stm32-iwdg";
+ reg = <0x40003000 0x400>;
+ clocks = <&clk_lsi>;
+ status = "disabled";
+ };
+
+ usart2: serial@40004400 {
+ compatible = "st,stm32-uart";
+ reg = <0x40004400 0x400>;
+ interrupts = <38>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
+ status = "disabled";
+ };
+
+ usart3: serial@40004800 {
+ compatible = "st,stm32-uart";
+ reg = <0x40004800 0x400>;
+ interrupts = <39>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
+ status = "disabled";
+ dmas = <&dma1 1 4 0x400 0x0>,
+ <&dma1 3 4 0x400 0x0>;
+ dma-names = "rx", "tx";
+ };
+
+ usart4: serial@40004c00 {
+ compatible = "st,stm32-uart";
+ reg = <0x40004c00 0x400>;
+ interrupts = <52>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
+ status = "disabled";
+ };
+
+ usart5: serial@40005000 {
+ compatible = "st,stm32-uart";
+ reg = <0x40005000 0x400>;
+ interrupts = <53>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@40005400 {
+ compatible = "st,stm32f4-i2c";
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dac: dac@40007400 {
+ compatible = "st,stm32f4-dac-core";
+ reg = <0x40007400 0x400>;
+ resets = <&rcc STM32F4_APB1_RESET(DAC)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dac1: dac@1 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <1>;
+ status = "disabled";
+ };
+
+ dac2: dac@2 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
+ usart7: serial@40007800 {
+ compatible = "st,stm32-uart";
+ reg = <0x40007800 0x400>;
+ interrupts = <82>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
+ status = "disabled";
+ };
+
+ usart8: serial@40007c00 {
+ compatible = "st,stm32-uart";
+ reg = <0x40007c00 0x400>;
+ interrupts = <83>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
+ status = "disabled";
+ };
+
+ timers1: timers@40010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@0 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+ };
+
+ timers8: timers@40010400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40010400 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@7 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <7>;
+ status = "disabled";
+ };
+ };
+
+ usart1: serial@40011000 {
+ compatible = "st,stm32-uart";
+ reg = <0x40011000 0x400>;
+ interrupts = <37>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
+ status = "disabled";
+ dmas = <&dma2 2 4 0x400 0x0>,
+ <&dma2 7 4 0x400 0x0>;
+ dma-names = "rx", "tx";
+ };
+
+ usart6: serial@40011400 {
+ compatible = "st,stm32-uart";
+ reg = <0x40011400 0x400>;
+ interrupts = <71>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
+ status = "disabled";
+ };
+
+ adc: adc@40012000 {
+ compatible = "st,stm32f4-adc-core";
+ reg = <0x40012000 0x400>;
+ interrupts = <18>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
+ clock-names = "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc1: adc@0 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
+ interrupt-parent = <&adc>;
+ interrupts = <0>;
+ dmas = <&dma2 0 0 0x400 0x0>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ adc2: adc@100 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x100>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
+ interrupt-parent = <&adc>;
+ interrupts = <1>;
+ dmas = <&dma2 3 1 0x400 0x0>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ adc3: adc@200 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x200>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
+ interrupt-parent = <&adc>;
+ interrupts = <2>;
+ dmas = <&dma2 1 2 0x400 0x0>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+ };
+
+ syscfg: system-config@40013800 {
+ compatible = "syscon";
+ reg = <0x40013800 0x400>;
+ };
+
+ exti: interrupt-controller@40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+ };
+
+ timers9: timers@40014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40014000 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+
+ timer@8 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <8>;
+ status = "disabled";
+ };
+ };
+
+ timers10: timers@40014400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40014400 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
+ timers11: timers@40014800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40014800 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ };
+ };
+
+ pwrcfg: power-config@40007000 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
+ sdio: sdio@40012c00 {
+ compatible = "st,stm32f4xx-sdio";
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 171>;
+ interrupts = <49>;
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ pinctrl-names = "default", "opendrain";
+ max-frequency = <48000000>;
+ };
+
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+ status = "disabled";
+ };
+
+ crc: crc@40023000 {
+ compatible = "st,stm32f4-crc";
+ reg = <0x40023000 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
+ status = "disabled";
+ };
+
+ rcc: rcc@40023810 {
+ #reset-cells = <1>;
+ #clock-cells = <2>;
+ compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ reg = <0x40023800 0x400>;
+ clocks = <&clk_hse>, <&clk_i2s_ckin>;
+ st,syscfg = <&pwrcfg>;
+ assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
+ assigned-clock-rates = <1000000>;
+ };
+
+ dma1: dma-controller@40026000 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026000 0x400>;
+ interrupts = <11>,
+ <12>,
+ <13>,
+ <14>,
+ <15>,
+ <16>,
+ <17>,
+ <47>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
+ #dma-cells = <4>;
+ };
+
+ dma2: dma-controller@40026400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026400 0x400>;
+ interrupts = <56>,
+ <57>,
+ <58>,
+ <59>,
+ <60>,
+ <68>,
+ <69>,
+ <70>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ };
+
+ mac: ethernet@40028000 {
+ compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+ reg = <0x40028000 0x8000>;
+ reg-names = "stmmaceth";
+ interrupts = <61>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
+ <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
+ <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
+ st,syscon = <&syscfg 0x4>;
+ snps,pbl = <8>;
+ snps,mixed-burst;
+ status = "disabled";
+ };
+
+ usbotg_hs: usb@40040000 {
+ compatible = "snps,dwc2";
+ reg = <0x40040000 0x40000>;
+ interrupts = <77>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
+ usbotg_fs: usb@50000000 {
+ compatible = "st,stm32f4x9-fsotg";
+ reg = <0x50000000 0x40000>;
+ interrupts = <67>;
+ clocks = <&rcc 0 39>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
+ dcmi: dcmi@50050000 {
+ compatible = "st,stm32-dcmi";
+ reg = <0x50050000 0x400>;
+ interrupts = <78>;
+ resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
+ clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
+ clock-names = "mclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcmi_pins>;
+ dmas = <&dma2 1 1 0x414 0x3>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ rng: rng@50060800 {
+ compatible = "st,stm32-rng";
+ reg = <0x50060800 0x400>;
+ interrupts = <80>;
+ clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
+
+ };
+ };
+};
+
+&systick {
+ clocks = <&rcc 1 SYSTICK>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/memory/stm32-sdram.h>
+/{
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+
+ aliases {
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ pin-controller {
+ u-boot,dm-pre-reloc;
+ };
+
+ fmc: fmc@A0000000 {
+ compatible = "st,stm32-fmc";
+ reg = <0xA0000000 0x1000>;
+ clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
+ st,syscfg = <&syscfg>;
+ pinctrl-0 = <&fmc_pins_d32>;
+ pinctrl-names = "default";
+ st,mem_remap = <4>;
+ u-boot,dm-pre-reloc;
+
+ /*
+ * Memory configuration from sdram
+ * MICRON MT48LC4M32B2B5-6A
+ */
+ bank0: bank@0 {
+ st,sdram-control = /bits/ 8 <NO_COL_8
+ NO_ROW_12
+ MWIDTH_32
+ BANKS_4
+ CAS_3
+ SDCLK_2
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_2
+ TXSR_6
+ TRAS_4
+ TRC_6
+ TWR_2
+ TRP_2
+ TRCD_2>;
+ st,sdram-refcount = < 1292 >;
+ };
+ };
+ };
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_i2s_ckin {
+ u-boot,dm-pre-reloc;
+};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
+
+&syscfg {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ usart3_pins_a: usart3@0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ fmc_pins_d32: fmc_d32@0 {
+ u-boot,dm-pre-reloc;
+ pins
+ {
+ pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
+ <STM32_PINMUX('I', 9, AF12)>, /* D30 */
+ <STM32_PINMUX('I', 7, AF12)>, /* D29 */
+ <STM32_PINMUX('I', 6, AF12)>, /* D28 */
+ <STM32_PINMUX('I', 3, AF12)>, /* D27 */
+ <STM32_PINMUX('I', 2, AF12)>, /* D26 */
+ <STM32_PINMUX('I', 1, AF12)>, /* D25 */
+ <STM32_PINMUX('I', 0, AF12)>, /* D24 */
+ <STM32_PINMUX('H',15, AF12)>, /* D23 */
+ <STM32_PINMUX('H',14, AF12)>, /* D22 */
+ <STM32_PINMUX('H',13, AF12)>, /* D21 */
+ <STM32_PINMUX('H',12, AF12)>, /* D20 */
+ <STM32_PINMUX('H',11, AF12)>, /* D19 */
+ <STM32_PINMUX('H',10, AF12)>, /* D18 */
+ <STM32_PINMUX('H', 9, AF12)>, /* D17 */
+ <STM32_PINMUX('H', 8, AF12)>, /* D16 */
+
+ <STM32_PINMUX('D',10, AF12)>, /* D15 */
+ <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+ <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+ <STM32_PINMUX('E',15, AF12)>, /* D12 */
+ <STM32_PINMUX('E',14, AF12)>, /* D11 */
+ <STM32_PINMUX('E',13, AF12)>, /* D10 */
+ <STM32_PINMUX('E',12, AF12)>, /* D09 */
+ <STM32_PINMUX('E',11, AF12)>, /* D08 */
+ <STM32_PINMUX('E',10, AF12)>, /* D07 */
+ <STM32_PINMUX('E', 9, AF12)>, /* D06 */
+ <STM32_PINMUX('E', 8, AF12)>, /* D05 */
+ <STM32_PINMUX('E', 7, AF12)>, /* D04 */
+ <STM32_PINMUX('D', 1, AF12)>, /* D03 */
+ <STM32_PINMUX('D', 0, AF12)>, /* D02 */
+ <STM32_PINMUX('D',15, AF12)>, /* D01 */
+ <STM32_PINMUX('D',14, AF12)>, /* D00 */
+
+ <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+ <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+ <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
+ <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
+
+ <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+ <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+ <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+ <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+ <STM32_PINMUX('F',15, AF12)>, /* A09 */
+ <STM32_PINMUX('F',14, AF12)>, /* A08 */
+ <STM32_PINMUX('F',13, AF12)>, /* A07 */
+ <STM32_PINMUX('F',12, AF12)>, /* A06 */
+ <STM32_PINMUX('F', 5, AF12)>, /* A05 */
+ <STM32_PINMUX('F', 4, AF12)>, /* A04 */
+ <STM32_PINMUX('F', 3, AF12)>, /* A03 */
+ <STM32_PINMUX('F', 2, AF12)>, /* A02 */
+ <STM32_PINMUX('F', 1, AF12)>, /* A01 */
+ <STM32_PINMUX('F', 0, AF12)>, /* A00 */
+
+ <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
+ <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
+ <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+ <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+ <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
+ <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
+ slew-rate = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f429.dtsi"
+#include "stm32f469-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32F469i-DISCO board";
+ compatible = "st,stm32f469i-disco", "st,stm32f469";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x00000000 0x1000000>;
+ };
+
+ aliases {
+ serial0 = &usart3;
+ };
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ soc {
+ dma-ranges = <0xc0000000 0x0 0x10000000>;
+ };
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpiob 2 0>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
+};
+
+&rcc {
+ compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
+};
+
+&clk_hse {
+ clock-frequency = <8000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&timers1 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@0 {
+ status = "okay";
+ };
+};
+
+&timers3 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+};
+
+&usart3 {
+ pinctrl-0 = <&usart3_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbotg_fs {
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "stm32f4-pinctrl.dtsi"
+
+/ {
+ soc {
+ pinctrl: pin-controller {
+ compatible = "st,stm32f469-pinctrl";
+
+ gpioa: gpio@40020000 {
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@40021400 {
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@40021800 {
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@40021c00 {
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@40022000 {
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@40022400 {
+ gpio-ranges = <&pinctrl 0 144 6>,
+ <&pinctrl 12 156 4>;
+ };
+
+ gpiok: gpio@40022800 {
+ gpio-ranges = <&pinctrl 3 163 5>;
+ };
+ };
+ };
+};
aliases {
serial0 = &usart1;
spi0 = &qspi;
+ mmc0 = &sdio;
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
reg = <0>;
};
};
+
+&sdio {
+ status = "okay";
+ cd-gpios = <&gpioc 13 0>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+ max-frequency = <25000000>;
+};
u-boot,dm-pre-reloc;
};
+ sdio_pins: sdio_pins@0 {
+ pins {
+ pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+ <STM32F746_PC9_FUNC_SDMMC1_D1>,
+ <STM32F746_PC10_FUNC_SDMMC1_D2>,
+ <STM32F746_PC11_FUNC_SDMMC1_D3>,
+ <STM32F746_PC12_FUNC_SDMMC1_CK>,
+ <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od@0 {
+ pins1 {
+ pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+ <STM32F746_PC9_FUNC_SDMMC1_D1>,
+ <STM32F746_PC10_FUNC_SDMMC1_D2>,
+ <STM32F746_PC11_FUNC_SDMMC1_D3>,
+ <STM32F746_PC12_FUNC_SDMMC1_CK>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_b: sdio_pins_b@0 {
+ pins {
+ pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+ <STM32F769_PG10_FUNC_SDMMC2_D1>,
+ <STM32F769_PB3_FUNC_SDMMC2_D2>,
+ <STM32F769_PB4_FUNC_SDMMC2_D3>,
+ <STM32F769_PD6_FUNC_SDMMC2_CLK>,
+ <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od_b: sdio_pins_od_b@0 {
+ pins1 {
+ pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+ <STM32F769_PG10_FUNC_SDMMC2_D1>,
+ <STM32F769_PB3_FUNC_SDMMC2_D2>,
+ <STM32F769_PB4_FUNC_SDMMC2_D3>,
+ <STM32F769_PD6_FUNC_SDMMC2_CLK>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
+
+ };
+ sdio: sdio@40012c00 {
+ compatible = "st,stm32f4xx-sdio";
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 171>;
+ interrupts = <49>;
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ pinctrl-names = "default", "opendrain";
+ max-frequency = <48000000>;
+ };
+
+ sdio2: sdio2@40011c00 {
+ compatible = "st,stm32f4xx-sdio";
+ reg = <0x40011c00 0x400>;
+ clocks = <&rcc 0 167>;
+ interrupts = <103>;
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins_b>;
+ pinctrl-1 = <&sdio_pins_od_b>;
+ pinctrl-names = "default", "opendrain";
+ max-frequency = <48000000>;
};
};
};
aliases {
serial0 = &usart1;
spi0 = &qspi;
+ mmc0 = &sdio2;
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
reg = <0>;
};
};
+
+&sdio2 {
+ status = "okay";
+ cd-gpios = <&gpioi 15 0>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins_b>;
+ pinctrl-1 = <&sdio_pins_od_b>;
+ bus-width = <4>;
+ max-frequency = <25000000>;
+};
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
- cd-inverted;
status = "okay";
};
--- /dev/null
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Libre Computer Board ALL-H3-CC H3";
+ compatible = "libretech,all-h3-cc-h3", "allwinner,sun8i-h3";
+
+ aliases {
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr_led {
+ label = "librecomputer:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ default-state = "on";
+ };
+
+ status_led {
+ label = "librecomputer:blue:status";
+ gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ };
+ };
+
+ reg_vcc1v2: vcc1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vcc5v0>;
+ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ enable-active-high;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_vcc5v0>;
+ };
+
+ /* This represents the board's 5V input */
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_vcc_dram: vcc-dram {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-dram";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vcc5v0>;
+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ enable-active-high;
+ };
+
+ reg_vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vcc3v3>;
+ gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
+ };
+
+ reg_vdd_cpux: vdd-cpux {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpux";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vcc5v0>;
+ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ enable-active-high;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy = <&phy1>;
+ phy-mode = "mii";
+ allwinner,use-internal-phy;
+ allwinner,leds-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <®_vcc_io>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* VBUS on USB ports are always on */
+ usb0_vbus-supply = <®_vcc5v0>;
+ usb1_vbus-supply = <®_vcc5v0>;
+ usb2_vbus-supply = <®_vcc5v0>;
+ usb3_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
#include <config.h>
+#ifdef CONFIG_SPL_TEXT_BASE
+#define U_BOOT_OFFSET (CONFIG_SYS_TEXT_BASE - CONFIG_SPL_TEXT_BASE)
+#else
+#define U_BOOT_OFFSET 0
+#endif
+
/ {
binman {
multiple-images;
u-boot-spl {
};
u-boot {
- pos = <(CONFIG_SYS_TEXT_BASE -
- CONFIG_SPL_TEXT_BASE)>;
+ pos = <(U_BOOT_OFFSET)>;
};
};
u-boot-spl {
};
u-boot {
- pos = <(CONFIG_SYS_TEXT_BASE -
- CONFIG_SPL_TEXT_BASE)>;
+ pos = <(U_BOOT_OFFSET)>;
};
};
u-boot-spl {
};
u-boot-nodtb {
- pos = <(CONFIG_SYS_TEXT_BASE -
- CONFIG_SPL_TEXT_BASE)>;
+ pos = <(U_BOOT_OFFSET)>;
};
};
};
extern const struct dpll_regs dpll_core_regs;
extern const struct dpll_regs dpll_per_regs;
extern const struct dpll_regs dpll_ddr_regs;
+extern const struct dpll_regs dpll_disp_regs;
extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
/*
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x48060100
-#define OMAP_HSMMC2_BASE 0x481D8100
+#define OMAP_HSMMC1_BASE 0x48060000
+#define OMAP_HSMMC2_BASE 0x481D8000
#if defined(CONFIG_TI814X)
#undef MMC_CLOCK_REFERENCE
#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
int get_serdes_protocol(void);
+#endif
#ifdef CONFIG_SYS_HAS_SERDES
/* Get the volt of SVDD in unit mV */
int get_serdes_volt(void);
/* The target volt of SVDD in unit mV */
int setup_serdes_volt(u32 svdd);
#endif
-#endif
#endif /* __FSL_SERDES_H__ */
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
+#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
+#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
+#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
+ CONFIG_SYS_BMAN_MEM_BASE)
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
+#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
+#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
+#define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \
+ CONFIG_SYS_QMAN_MEM_BASE)
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
+#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
+
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
u32 gpporcr3;
u32 gpporcr4;
u8 res_030[0x60-0x30];
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
+#if defined(CONFIG_ARCH_LS1088A)
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
+#else
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
+#endif
u32 dcfg_fusesr; /* Fuse status register */
u8 res_064[0x70-0x64];
u32 devdisr; /* Device disable control 1 */
u32 ip_rev2; /* 0xbfc */
};
+struct ccsr_serdes {
+ struct {
+ u32 rstctl; /* Reset Control Register */
+ u32 pllcr0; /* PLL Control Register 0 */
+ u32 pllcr1; /* PLL Control Register 1 */
+ u32 pllcr2; /* PLL Control Register 2 */
+ u32 pllcr3; /* PLL Control Register 3 */
+ u32 pllcr4; /* PLL Control Register 4 */
+ u32 pllcr5; /* PLL Control Register 5 */
+ u8 res[0x20 - 0x1c];
+ } bank[2];
+ u8 res1[0x90 - 0x40];
+ u32 srdstcalcr; /* TX Calibration Control */
+ u32 srdstcalcr1; /* TX Calibration Control1 */
+ u8 res2[0xa0 - 0x98];
+ u32 srdsrcalcr; /* RX Calibration Control */
+ u32 srdsrcalcr1; /* RX Calibration Control1 */
+ u8 res3[0xb0 - 0xa8];
+ u32 srdsgr0; /* General Register 0 */
+ u8 res4[0x800 - 0xb4];
+ struct serdes_lane {
+ u32 gcr0; /* General Control Register 0 */
+ u32 gcr1; /* General Control Register 1 */
+ u32 gcr2; /* General Control Register 2 */
+ u32 ssc0; /* Speed Switch Control 0 */
+ u32 rec0; /* Receive Equalization Control 0 */
+ u32 rec1; /* Receive Equalization Control 1 */
+ u32 tec0; /* Transmit Equalization Control 0 */
+ u32 ssc1; /* Speed Switch Control 1 */
+ u8 res1[0x840 - 0x820];
+ } lane[8];
+ u8 res5[0x19fc - 0xa00];
+};
+
#endif /*__ASSEMBLY__*/
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
+#define AHCI_PORT_PHY2_CFG 0x28184d1f
+#define AHCI_PORT_PHY3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029
#define AHCI_PORT_AXICC_CFG 0x3fffffff
#ifdef CONFIG_FSL_LSCH3
void fsl_lsch3_early_init_f(void);
+int get_core_volt_from_fuse(void);
#elif defined(CONFIG_FSL_LSCH2)
void fsl_lsch2_early_init_f(void);
int setup_chip_volt(void);
#ifndef _FSL_LAYERSCAPE_SPEED_H
#define _FSL_LAYERSCAPE_SPEED_H
void get_sys_info(struct sys_info *sys_info);
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void);
+#endif
#endif /* _FSL_LAYERSCAPE_SPEED_H */
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x4809C100
-#define OMAP_HSMMC2_BASE 0x480B4100
-#define OMAP_HSMMC3_BASE 0x480AD100
+#define OMAP_HSMMC1_BASE 0x4809C000
+#define OMAP_HSMMC2_BASE 0x480B4000
+#define OMAP_HSMMC3_BASE 0x480AD000
#endif /* MMC_HOST_DEF_H */
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x4809C100
-#define OMAP_HSMMC2_BASE 0x480B4100
-#define OMAP_HSMMC3_BASE 0x480AD100
+#define OMAP_HSMMC1_BASE 0x4809C000
+#define OMAP_HSMMC2_BASE 0x480B4000
+#define OMAP_HSMMC3_BASE 0x480AD000
#endif /* MMC_HOST_DEF_H */
#define NMIN_DSP 0x460
#define RSTOUTN 0x464
+#define MCAN_SEL_ALT_MASK 0x6000
+#define MCAN_SEL 0x2000
+
#endif /* _MUX_DRA7XX_H_ */
#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F
+#define DRA762_ABZ_PACKAGE 0x2
+#define DRA762_ACD_PACKAGE 0x3
+
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
u32 cortex_rev(void);
void save_omap_boot_params(void);
void init_omap_revision(void);
+void init_package_revision(void);
void do_io_settings(void);
void sri2c_init(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
--- /dev/null
+/*
+ * (C) Copyright 2017
+ *
+ * Eddie Cai <eddie.cai.linux@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _F_ROCKUSB_H_
+#define _F_ROCKUSB_H_
+#include <blk.h>
+
+#define ROCKUSB_VERSION "0.1"
+
+#define ROCKUSB_INTERFACE_CLASS 0xff
+#define ROCKUSB_INTERFACE_SUB_CLASS 0x06
+#define ROCKUSB_INTERFACE_PROTOCOL 0x05
+
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 0x0200
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 0x0040
+#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE 0x0040
+
+#define EP_BUFFER_SIZE 4096
+/*
+ * EP_BUFFER_SIZE must always be an integral multiple of maxpacket size
+ * (64 or 512 or 1024), else we break on certain controllers like DWC3
+ * that expect bulk OUT requests to be divisible by maxpacket size.
+ */
+
+#define RKUSB_BUF_SIZE EP_BUFFER_SIZE * 2
+
+#define RKUSB_STATUS_IDLE 0
+#define RKUSB_STATUS_CMD 1
+#define RKUSB_STATUS_RXDATA 2
+#define RKUSB_STATUS_TXDATA 3
+#define RKUSB_STATUS_CSW 4
+#define RKUSB_STATUS_RXDATA_PREPARE 5
+#define RKUSB_STATUS_TXDATA_PREPARE 6
+
+enum rkusb_command {
+K_FW_TEST_UNIT_READY = 0x00,
+K_FW_READ_FLASH_ID = 0x01,
+K_FW_SET_DEVICE_ID = 0x02,
+K_FW_TEST_BAD_BLOCK = 0x03,
+K_FW_READ_10 = 0x04,
+K_FW_WRITE_10 = 0x05,
+K_FW_ERASE_10 = 0x06,
+K_FW_WRITE_SPARE = 0x07,
+K_FW_READ_SPARE = 0x08,
+
+K_FW_ERASE_10_FORCE = 0x0b,
+K_FW_GET_VERSION = 0x0c,
+
+K_FW_LBA_READ_10 = 0x14,
+K_FW_LBA_WRITE_10 = 0x15,
+K_FW_ERASE_SYS_DISK = 0x16,
+K_FW_SDRAM_READ_10 = 0x17,
+K_FW_SDRAM_WRITE_10 = 0x18,
+K_FW_SDRAM_EXECUTE = 0x19,
+K_FW_READ_FLASH_INFO = 0x1A,
+K_FW_GET_CHIP_VER = 0x1B,
+K_FW_LOW_FORMAT = 0x1C,
+K_FW_SET_RESET_FLAG = 0x1E,
+K_FW_SPI_READ_10 = 0x21,
+K_FW_SPI_WRITE_10 = 0x22,
+
+K_FW_SESSION = 0X30,
+K_FW_RESET = 0xff,
+};
+
+#define CBW_DIRECTION_OUT 0x00
+#define CBW_DIRECTION_IN 0x80
+
+struct cmd_dispatch_info {
+ enum rkusb_command cmd;
+ /* call back function to handle rockusb command */
+ void (*cb)(struct usb_ep *ep, struct usb_request *req);
+};
+
+/* Bulk-only data structures */
+
+/* Command Block Wrapper */
+struct fsg_bulk_cb_wrap {
+ __le32 signature; /* Contains 'USBC' */
+ u32 tag; /* Unique per command id */
+ __le32 data_transfer_length; /* Size of the data */
+ u8 flags; /* Direction in bit 7 */
+ u8 lun; /* lun (normally 0) */
+ u8 length; /* Of the CDB, <= MAX_COMMAND_SIZE */
+ u8 CDB[16]; /* Command Data Block */
+};
+
+#define USB_BULK_CB_WRAP_LEN 31
+#define USB_BULK_CB_SIG 0x43425355 /* Spells out USBC */
+#define USB_BULK_IN_FLAG 0x80
+
+/* Command status Wrapper */
+struct bulk_cs_wrap {
+ __le32 signature; /* Should = 'USBS' */
+ u32 tag; /* Same as original command */
+ __le32 residue; /* Amount not transferred */
+ u8 status; /* See below */
+};
+
+#define USB_BULK_CS_WRAP_LEN 13
+#define USB_BULK_CS_SIG 0x53425355 /* Spells out 'USBS' */
+#define USB_STATUS_PASS 0
+#define USB_STATUS_FAIL 1
+#define USB_STATUS_PHASE_ERROR 2
+
+#define CSW_GOOD 0x00
+#define CSW_FAIL 0x01
+
+struct f_rockusb {
+ struct usb_function usb_function;
+ struct usb_ep *in_ep, *out_ep;
+ struct usb_request *in_req, *out_req;
+ char *dev_type;
+ unsigned int dev_index;
+ unsigned int tag;
+ unsigned int lba;
+ unsigned int dl_size;
+ unsigned int dl_bytes;
+ struct blk_desc *desc;
+ int reboot_flag;
+ void *buf;
+ void *buf_head;
+};
+
+/* init rockusb device, tell rockusb which device you want to read/write*/
+void rockusb_dev_init(char *dev_type, int dev_index);
+#endif /* _F_ROCKUSB_H_ */
+
enum stm32_gpio_af af;
};
+struct stm32_gpio_regs {
+ u32 moder; /* GPIO port mode */
+ u32 otyper; /* GPIO port output type */
+ u32 ospeedr; /* GPIO port output speed */
+ u32 pupdr; /* GPIO port pull-up/pull-down */
+ u32 idr; /* GPIO port input data */
+ u32 odr; /* GPIO port output data */
+ u32 bsrr; /* GPIO port bit set/reset */
+ u32 lckr; /* GPIO port configuration lock */
+ u32 afr[2]; /* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+ struct stm32_gpio_regs *regs;
+};
+
static inline unsigned stm32_gpio_to_port(unsigned gpio)
{
return gpio / 16;
return gpio % 16;
}
-int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
- const struct stm32_gpio_ctl *gpio_ctl);
-int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
-
#endif /* _STM32_GPIO_H_ */
#define STM32_BUS_MASK 0xFFFF0000
-#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
-#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
-#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
-#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
-#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
-#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
-#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
-#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
-#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
-
/*
* Register maps
*/
u32 u_id_high;
};
-struct stm32_pwr_regs {
- u32 cr;
- u32 csr;
-};
-
/*
* Registers access macros
*/
#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
-#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
-#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
-
-/*
- * Peripheral base addresses
- */
-#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000)
-#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400)
-#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
-#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
-
#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[5 ... 11] = 128 * 1024
};
-enum clock {
- CLOCK_CORE,
- CLOCK_AHB,
- CLOCK_APB1,
- CLOCK_APB2
-};
-
-int configure_clocks(void);
-unsigned long clock_get(enum clock clck);
void stm32_flash_latency_cfg(int latency);
#endif /* _MACH_STM32_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2017 NVIDIA Corporation <www.nvidia.com>
+ *
+ * Derived from Linux kernel v4.14 files:
+ *
+ * arch/arm64/include/asm/assembler.h:
+ * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
+ * Copyright (C) 1996-2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * arch/arm64/kernel/head.S:
+ * Based on arch/arm/kernel/head.S
+ * Copyright (C) 1994-2002 Russell King
+ * Copyright (C) 2003-2012 ARM Ltd.
+ * Authors: Catalin Marinas <catalin.marinas@arm.com>
+ * Will Deacon <will.deacon@arm.com>
+ *
+ * arch/arm64/kernel/image.h:
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+ /*
+ * Emit a 64-bit absolute little endian symbol reference in a way that
+ * ensures that it will be resolved at build time, even when building a
+ * PIE binary. This requires cooperation from the linker script, which
+ * must emit the lo32/hi32 halves individually.
+ */
+ .macro le64sym, sym
+ .long \sym\()_lo32
+ .long \sym\()_hi32
+ .endm
+
+.globl _start
+_start:
+ /*
+ * DO NOT MODIFY. Image header expected by Linux boot-loaders.
+ */
+ b reset /* branch to kernel start, magic */
+ .long 0 /* reserved */
+ le64sym _kernel_offset_le /* Image load offset from start of RAM, little-endian */
+ le64sym _kernel_size_le /* Effective size of kernel image, little-endian */
+ le64sym _kernel_flags_le /* Informative flags, little-endian */
+ .quad 0 /* reserved */
+ .quad 0 /* reserved */
+ .quad 0 /* reserved */
+ .ascii "ARM\x64" /* Magic number */
+ .long 0 /* reserved */
#include <asm/io.h>
/* Base address */
+#ifndef EMIF1_BASE
#define EMIF1_BASE 0x4c000000
+#endif
#define EMIF2_BASE 0x4d000000
#define EMIF_4D 0x4
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
+/* EMIF ECC CTRL reg */
+#define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT 31
+#define EMIF_ECC_CTRL_REG_ECC_EN_MASK (1 << 31)
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT 30
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK (1 << 30)
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT 29
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK (1 << 29)
+#define EMIF_ECC_REG_RMW_EN_SHIFT 28
+#define EMIF_ECC_REG_RMW_EN_MASK (1 << 28)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT 1
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK (1 << 1)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT 0
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK (1 << 0)
+
+/* EMIF ECC ADDRESS RANGE */
+#define EMIF_ECC_REG_ECC_END_ADDR_SHIFT 16
+#define EMIF_ECC_REG_ECC_END_ADDR_MASK (0xffff << 16)
+#define EMIF_ECC_REG_ECC_START_ADDR_SHIFT 0
+#define EMIF_ECC_REG_ECC_START_ADDR_MASK (0xffff << 0)
+
+/* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT 5
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK (1 << 5)
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT 4
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK (1 << 4)
+#define EMIF_INT_WR_ECC_ERR_SYS_SHIFT 3
+#define EMIF_INT_WR_ECC_ERR_SYS_MASK (1 << 3)
+
/* Reg mapping structure */
struct emif_reg_struct {
u32 emif_mod_id_rev;
u32 emif_prio_class_serv_map;
u32 emif_connect_id_serv_1_map;
u32 emif_connect_id_serv_2_map;
- u32 padding8[5];
+ u32 padding8;
+ u32 emif_ecc_ctrl_reg;
+ u32 emif_ecc_address_range_1;
+ u32 emif_ecc_address_range_2;
+ u32 padding8_1;
u32 emif_rd_wr_exec_thresh;
u32 emif_cos_config;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE)
+ u32 padding9[2];
+ u32 emif_1b_ecc_err_cnt;
+ u32 emif_1b_ecc_err_thrush;
+ u32 emif_1b_ecc_err_dist_1;
+ u32 emif_1b_ecc_err_addr_log;
+ u32 emif_2b_ecc_err_addr_log;
+ u32 emif_ddr_phy_status[28];
+ u32 padding10[19];
+#else
u32 padding9[6];
u32 emif_ddr_phy_status[28];
u32 padding10[20];
+#endif
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
u32 emif_connect_id_serv_1_map;
u32 emif_connect_id_serv_2_map;
u32 emif_cos_config;
+ u32 emif_ecc_ctrl_reg;
+ u32 emif_ecc_address_range_1;
+ u32 emif_ecc_address_range_2;
};
struct lpddr2_mr_regs {
#define CONFIG_KEY_REVOCATION
+#if defined(CONFIG_FSL_LAYERSCAPE)
+/*
+ * For fsl layerscape based platforms, ESBC image Address in Header
+ * is 64 bit.
+ */
+#define CONFIG_ESBC_ADDR_64BIT
+#endif
+
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
#endif
-#if defined(CONFIG_FSL_LAYERSCAPE)
-/*
- * For fsl layerscape based platforms, ESBC image Address in Header
- * is 64 bit.
- */
-#define CONFIG_ESBC_ADDR_64BIT
-#endif
-
#ifdef CONFIG_ARCH_LS2080A
#define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xa0000000;" \
#include <linux/types.h>
+/*
+ * IVT header definitions
+ * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
+ * Rev. 0, 03/2017
+ * Section : 6.7.1.1
+ */
+#define IVT_HEADER_MAGIC 0xD1
+#define IVT_TOTAL_LENGTH 0x20
+#define IVT_HEADER_V1 0x40
+#define IVT_HEADER_V2 0x41
+
+struct ivt_header {
+ uint8_t magic;
+ uint16_t length;
+ uint8_t version;
+} __attribute__((packed));
+
+struct ivt {
+ struct ivt_header hdr; /* IVT header above */
+ uint32_t entry; /* Absolute address of first instruction */
+ uint32_t reserved1; /* Reserved should be zero */
+ uint32_t dcd; /* Absolute address of the image DCD */
+ uint32_t boot; /* Absolute address of the boot data */
+ uint32_t self; /* Absolute address of the IVT */
+ uint32_t csf; /* Absolute address of the CSF */
+ uint32_t reserved2; /* Reserved should be zero */
+};
+
/* -------- start of HAB API updates ------------*/
/* The following are taken from HAB4 SIS */
HAB_CTX_MAX
};
+enum hab_target {
+ HAB_TGT_MEMORY = 0x0f,
+ HAB_TGT_PERIPHERAL = 0xf0,
+ HAB_TGT_ANY = 0x55,
+};
+
struct imx_sec_config_fuse_t {
int bank;
int word;
typedef enum hab_status hab_rvt_exit_t(void);
typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
+typedef enum hab_status hab_rvt_check_target_t(enum hab_target, const void *,
+ size_t);
+typedef void hab_rvt_failsafe_t(void);
typedef void hapi_clock_init_t(void);
#define HAB_ENG_ANY 0x00 /* Select first compatible engine */
#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04))
#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_CHECK_TARGET (*(uint32_t *)(HAB_RVT_BASE + 0x0C))
#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20))
#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
+#define HAB_RVT_FAILSAFE (*(uint32_t *)(HAB_RVT_BASE + 0x28))
#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
#define HAB_CID_ROM 0 /**< ROM Caller ID */
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
+#define IVT_SIZE 0x20
+#define CSF_PAD_SIZE 0x2000
+
/* ----------- end of HAB API updates ------------*/
-uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size);
+int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
+ uint32_t ivt_offset);
+bool imx_hab_is_enabled(void);
#endif
extern struct dplls const **dplls_data;
extern struct dplls dra7xx_dplls;
extern struct dplls dra72x_dplls;
+extern struct dplls dra76x_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
extern u32 *const omap_si_rev;
return (*omap_si_rev & 0xFFF00000) == DRA76X;
}
+
+static inline u8 is_dra76x_abz(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xF) == 2;
+}
+
+static inline u8 is_dra76x_acd(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xF) == 3;
+}
#endif
/*
#define DRA722_ES2_0 0x07220200
#define DRA722_ES2_1 0x07220210
+#define DRA762_ABZ_ES1_0 0x07620102
+#define DRA762_ACD_ES1_0 0x07620103
/*
* silicon device type
* Moving to common from cpu.h, since it is shared by various omap devices
#include <mmc.h>
struct hsmmc {
+#ifndef CONFIG_OMAP34XX
+ unsigned int hl_rev;
+ unsigned int hl_hwinfo;
+ unsigned int hl_sysconfig;
+ unsigned char res0[0xf4];
+#endif
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
+ unsigned char res5[0x10];
+ unsigned int admaes; /* 0x154 */
+ unsigned int admasal; /* 0x158 */
};
struct omap_hsmmc_plat {
/*
* OMAP HS MMC Bit definitions
*/
+#define MADMA_EN (0x1 << 0)
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
+#define DMA_MASTER (0x1 << 20)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
+#define DE_ENABLE (0x1 << 0)
#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
+#define ACEN_ENABLE (0x1 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
+#define DMA_SELECT (0x2 << 3)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
+#define IE_ADMAE (0x01 << 25)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
enum edma3_sync_dimension sync_mode);
void edma3_transfer(unsigned long edma3_base_addr, unsigned int
edma_slot_num, void *dst, void *src, size_t len);
+void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+ void *dst, u8 val, size_t len);
#endif
CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
+extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC)
extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
void arch_lmb_reserve(struct lmb *lmb)
{
- ulong sp;
+ ulong sp, bank_end;
+ int bank;
/*
* Booting a (Linux) kernel image
/* adjust sp by 4K to be safe */
sp -= 4096;
- lmb_reserve(lmb, sp,
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ if (sp < gd->bd->bi_dram[bank].start)
+ continue;
+ bank_end = gd->bd->bi_dram[bank].start +
+ gd->bd->bi_dram[bank].size;
+ if (sp >= bank_end)
+ continue;
+ lmb_reserve(lmb, sp, bank_end - sp);
+ break;
+ }
}
__weak void board_quiesce_devices(void)
ldr x0, =(CONFIG_TPL_STACK)
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr x0, =(CONFIG_SPL_STACK)
+#elif defined(CONFIG_SYS_INIT_SP_BSS_OFFSET)
+ adr x0, __bss_start
+ add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
#else
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
#endif
config TARGET_IPAM390
bool "IPAM390 board"
+ select MACH_DAVINCI_DA850_EVM
+ select SOC_DA850
select SUPPORT_SPL
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
config TARGET_DA850EVM
bool "DA850 EVM board"
+ select MACH_DAVINCI_DA850_EVM
+ select SOC_DA850
select SUPPORT_SPL
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
config TARGET_EA20
bool "EA20 board"
+ select MACH_DAVINCI_DA850_EVM
+ select SOC_DA850
select BOARD_LATE_INIT
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
+ select SOC_DA8XX
select SUPPORT_SPL
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
config TARGET_CALIMAIN
bool "Calimain board"
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
+ select SOC_DA850
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
+ select MACH_DAVINCI_DA850_EVM
+ select SOC_DA850
endchoice
config SYS_SOC
default "davinci"
+config DA850_LOWLEVEL
+ bool "Enable Lowlevel DA850 initialization"
+ depends on SOC_DA850
+
config SYS_DA850_PLL_INIT
bool
config SYS_DA850_DDR_INIT
bool
+config SOC_DA850
+ bool
+ select SOC_DA8XX
+ select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
+
+config SOC_DA8XX
+ bool
+ select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
+
+config MACH_DAVINCI_DA850_EVM
+ bool
+
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/davinci/ea20/Kconfig"
obj-$(CONFIG_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
+ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
obj-$(CONFIG_SECURE_BOOT) += hab.o
obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
endif
((hab_rvt_exit_t *)HAB_RVT_EXIT) \
)
-#define IVT_SIZE 0x20
+static inline void hab_rvt_failsafe_new(void)
+{
+}
+
+#define hab_rvt_failsafe_p \
+( \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_failsafe_t *)hab_rvt_failsafe_new) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_failsafe_t *)hab_rvt_failsafe_new) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_failsafe_t *)hab_rvt_failsafe_new) : \
+ ((hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE) \
+)
+
+static inline enum hab_status hab_rvt_check_target_new(enum hab_target target,
+ const void *start,
+ size_t bytes)
+{
+ return HAB_SUCCESS;
+}
+
+#define hab_rvt_check_target_p \
+( \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_check_target_t *)hab_rvt_check_target_new) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_check_target_t *)hab_rvt_check_target_new) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_check_target_t *)hab_rvt_check_target_new) : \
+ ((hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET) \
+)
+
#define ALIGN_SIZE 0x1000
-#define CSF_PAD_SIZE 0x2000
#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
(is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2))
-/*
- * +------------+ 0x0 (DDR_UIMAGE_START) -
- * | Header | |
- * +------------+ 0x40 |
- * | | |
- * | | |
- * | | |
- * | | |
- * | Image Data | |
- * . | |
- * . | > Stuff to be authenticated ----+
- * . | | |
- * | | | |
- * | | | |
- * +------------+ | |
- * | | | |
- * | Fill Data | | |
- * | | | |
- * +------------+ Align to ALIGN_SIZE | |
- * | IVT | | |
- * +------------+ + IVT_SIZE - |
- * | | |
- * | CSF DATA | <---------------------------------------------------------+
- * | |
- * +------------+
- * | |
- * | Fill Data |
- * | |
- * +------------+ + CSF_PAD_SIZE
- */
+static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr)
+{
+ printf("%s magic=0x%x length=0x%02x version=0x%x\n", err_str,
+ ivt_hdr->magic, ivt_hdr->length, ivt_hdr->version);
-static bool is_hab_enabled(void);
+ return 1;
+}
+
+static int verify_ivt_header(struct ivt_header *ivt_hdr)
+{
+ int result = 0;
+
+ if (ivt_hdr->magic != IVT_HEADER_MAGIC)
+ result = ivt_header_error("bad magic", ivt_hdr);
+
+ if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH)
+ result = ivt_header_error("bad length", ivt_hdr);
+
+ if (ivt_hdr->version != IVT_HEADER_V1 &&
+ ivt_hdr->version != IVT_HEADER_V2)
+ result = ivt_header_error("bad version", ivt_hdr);
+
+ return result;
+}
#if !defined(CONFIG_SPL_BUILD)
bool any_rec_flag;
};
-char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
- "RSN = HAB_ENG_FAIL (0x30)\n",
- "RSN = HAB_INV_ADDRESS (0x22)\n",
- "RSN = HAB_INV_ASSERTION (0x0C)\n",
- "RSN = HAB_INV_CALL (0x28)\n",
- "RSN = HAB_INV_CERTIFICATE (0x21)\n",
- "RSN = HAB_INV_COMMAND (0x06)\n",
- "RSN = HAB_INV_CSF (0x11)\n",
- "RSN = HAB_INV_DCD (0x27)\n",
- "RSN = HAB_INV_INDEX (0x0F)\n",
- "RSN = HAB_INV_IVT (0x05)\n",
- "RSN = HAB_INV_KEY (0x1D)\n",
- "RSN = HAB_INV_RETURN (0x1E)\n",
- "RSN = HAB_INV_SIGNATURE (0x18)\n",
- "RSN = HAB_INV_SIZE (0x17)\n",
- "RSN = HAB_MEM_FAIL (0x2E)\n",
- "RSN = HAB_OVR_COUNT (0x2B)\n",
- "RSN = HAB_OVR_STORAGE (0x2D)\n",
- "RSN = HAB_UNS_ALGORITHM (0x12)\n",
- "RSN = HAB_UNS_COMMAND (0x03)\n",
- "RSN = HAB_UNS_ENGINE (0x0A)\n",
- "RSN = HAB_UNS_ITEM (0x24)\n",
- "RSN = HAB_UNS_KEY (0x1B)\n",
- "RSN = HAB_UNS_PROTOCOL (0x14)\n",
- "RSN = HAB_UNS_STATE (0x09)\n",
- "RSN = INVALID\n",
- NULL};
-
-char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
- "STS = HAB_FAILURE (0x33)\n",
- "STS = HAB_WARNING (0x69)\n",
- "STS = INVALID\n",
- NULL};
-
-char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
- "ENG = HAB_ENG_SCC (0x03)\n",
- "ENG = HAB_ENG_RTIC (0x05)\n",
- "ENG = HAB_ENG_SAHARA (0x06)\n",
- "ENG = HAB_ENG_CSU (0x0A)\n",
- "ENG = HAB_ENG_SRTC (0x0C)\n",
- "ENG = HAB_ENG_DCP (0x1B)\n",
- "ENG = HAB_ENG_CAAM (0x1D)\n",
- "ENG = HAB_ENG_SNVS (0x1E)\n",
- "ENG = HAB_ENG_OCOTP (0x21)\n",
- "ENG = HAB_ENG_DTCP (0x22)\n",
- "ENG = HAB_ENG_ROM (0x36)\n",
- "ENG = HAB_ENG_HDCP (0x24)\n",
- "ENG = HAB_ENG_RTL (0x77)\n",
- "ENG = HAB_ENG_SW (0xFF)\n",
- "ENG = INVALID\n",
- NULL};
-
-char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
- "CTX = HAB_CTX_FAB (0xFF)\n",
- "CTX = HAB_CTX_ENTRY (0xE1)\n",
- "CTX = HAB_CTX_TARGET (0x33)\n",
- "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
- "CTX = HAB_CTX_DCD (0xDD)\n",
- "CTX = HAB_CTX_CSF (0xCF)\n",
- "CTX = HAB_CTX_COMMAND (0xC0)\n",
- "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
- "CTX = HAB_CTX_ASSERT (0xA0)\n",
- "CTX = HAB_CTX_EXIT (0xEE)\n",
- "CTX = INVALID\n",
- NULL};
-
-uint8_t hab_statuses[5] = {
+static char *rsn_str[] = {
+ "RSN = HAB_RSN_ANY (0x00)\n",
+ "RSN = HAB_ENG_FAIL (0x30)\n",
+ "RSN = HAB_INV_ADDRESS (0x22)\n",
+ "RSN = HAB_INV_ASSERTION (0x0C)\n",
+ "RSN = HAB_INV_CALL (0x28)\n",
+ "RSN = HAB_INV_CERTIFICATE (0x21)\n",
+ "RSN = HAB_INV_COMMAND (0x06)\n",
+ "RSN = HAB_INV_CSF (0x11)\n",
+ "RSN = HAB_INV_DCD (0x27)\n",
+ "RSN = HAB_INV_INDEX (0x0F)\n",
+ "RSN = HAB_INV_IVT (0x05)\n",
+ "RSN = HAB_INV_KEY (0x1D)\n",
+ "RSN = HAB_INV_RETURN (0x1E)\n",
+ "RSN = HAB_INV_SIGNATURE (0x18)\n",
+ "RSN = HAB_INV_SIZE (0x17)\n",
+ "RSN = HAB_MEM_FAIL (0x2E)\n",
+ "RSN = HAB_OVR_COUNT (0x2B)\n",
+ "RSN = HAB_OVR_STORAGE (0x2D)\n",
+ "RSN = HAB_UNS_ALGORITHM (0x12)\n",
+ "RSN = HAB_UNS_COMMAND (0x03)\n",
+ "RSN = HAB_UNS_ENGINE (0x0A)\n",
+ "RSN = HAB_UNS_ITEM (0x24)\n",
+ "RSN = HAB_UNS_KEY (0x1B)\n",
+ "RSN = HAB_UNS_PROTOCOL (0x14)\n",
+ "RSN = HAB_UNS_STATE (0x09)\n",
+ "RSN = INVALID\n",
+ NULL
+};
+
+static char *sts_str[] = {
+ "STS = HAB_SUCCESS (0xF0)\n",
+ "STS = HAB_FAILURE (0x33)\n",
+ "STS = HAB_WARNING (0x69)\n",
+ "STS = INVALID\n",
+ NULL
+};
+
+static char *eng_str[] = {
+ "ENG = HAB_ENG_ANY (0x00)\n",
+ "ENG = HAB_ENG_SCC (0x03)\n",
+ "ENG = HAB_ENG_RTIC (0x05)\n",
+ "ENG = HAB_ENG_SAHARA (0x06)\n",
+ "ENG = HAB_ENG_CSU (0x0A)\n",
+ "ENG = HAB_ENG_SRTC (0x0C)\n",
+ "ENG = HAB_ENG_DCP (0x1B)\n",
+ "ENG = HAB_ENG_CAAM (0x1D)\n",
+ "ENG = HAB_ENG_SNVS (0x1E)\n",
+ "ENG = HAB_ENG_OCOTP (0x21)\n",
+ "ENG = HAB_ENG_DTCP (0x22)\n",
+ "ENG = HAB_ENG_ROM (0x36)\n",
+ "ENG = HAB_ENG_HDCP (0x24)\n",
+ "ENG = HAB_ENG_RTL (0x77)\n",
+ "ENG = HAB_ENG_SW (0xFF)\n",
+ "ENG = INVALID\n",
+ NULL
+};
+
+static char *ctx_str[] = {
+ "CTX = HAB_CTX_ANY(0x00)\n",
+ "CTX = HAB_CTX_FAB (0xFF)\n",
+ "CTX = HAB_CTX_ENTRY (0xE1)\n",
+ "CTX = HAB_CTX_TARGET (0x33)\n",
+ "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
+ "CTX = HAB_CTX_DCD (0xDD)\n",
+ "CTX = HAB_CTX_CSF (0xCF)\n",
+ "CTX = HAB_CTX_COMMAND (0xC0)\n",
+ "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
+ "CTX = HAB_CTX_ASSERT (0xA0)\n",
+ "CTX = HAB_CTX_EXIT (0xEE)\n",
+ "CTX = INVALID\n",
+ NULL
+};
+
+static uint8_t hab_statuses[5] = {
HAB_STS_ANY,
HAB_FAILURE,
HAB_WARNING,
-1
};
-uint8_t hab_reasons[26] = {
+static uint8_t hab_reasons[26] = {
HAB_RSN_ANY,
HAB_ENG_FAIL,
HAB_INV_ADDRESS,
-1
};
-uint8_t hab_contexts[12] = {
+static uint8_t hab_contexts[12] = {
HAB_CTX_ANY,
HAB_CTX_FAB,
HAB_CTX_ENTRY,
-1
};
-uint8_t hab_engines[16] = {
+static uint8_t hab_engines[16] = {
HAB_ENG_ANY,
HAB_ENG_SCC,
HAB_ENG_RTIC,
return -1;
}
-void process_event_record(uint8_t *event_data, size_t bytes)
+static void process_event_record(uint8_t *event_data, size_t bytes)
{
struct record *rec = (struct record *)event_data;
printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
}
-void display_event(uint8_t *event_data, size_t bytes)
+static void display_event(uint8_t *event_data, size_t bytes)
{
uint32_t i;
process_event_record(event_data, bytes);
}
-int get_hab_status(void)
+static int get_hab_status(void)
{
uint32_t index = 0; /* Loop index */
uint8_t event_data[128]; /* Event data buffer */
hab_rvt_report_event = hab_rvt_report_event_p;
hab_rvt_report_status = hab_rvt_report_status_p;
- if (is_hab_enabled())
+ if (imx_hab_is_enabled())
puts("\nSecure boot enabled\n");
else
puts("\nSecure boot disabled\n");
return 0;
}
-int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
if ((argc != 1)) {
cmd_usage(cmdtp);
}
static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+ char * const argv[])
{
- ulong addr, ivt_offset;
+ ulong addr, length, ivt_offset;
int rcode = 0;
- if (argc < 3)
+ if (argc < 4)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
- ivt_offset = simple_strtoul(argv[2], NULL, 16);
+ length = simple_strtoul(argv[2], NULL, 16);
+ ivt_offset = simple_strtoul(argv[3], NULL, 16);
- rcode = authenticate_image(addr, ivt_offset);
+ rcode = imx_hab_authenticate_image(addr, length, ivt_offset);
+ if (rcode == 0)
+ rcode = CMD_RET_SUCCESS;
+ else
+ rcode = CMD_RET_FAILURE;
return rcode;
}
+static int do_hab_failsafe(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ hab_rvt_failsafe_t *hab_rvt_failsafe;
+
+ if (argc != 1) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ hab_rvt_failsafe = hab_rvt_failsafe_p;
+ hab_rvt_failsafe();
+
+ return 0;
+}
+
U_BOOT_CMD(
hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
"display HAB status",
);
U_BOOT_CMD(
- hab_auth_img, 3, 0, do_authenticate_image,
+ hab_auth_img, 4, 0, do_authenticate_image,
"authenticate image via HAB",
- "addr ivt_offset\n"
+ "addr length ivt_offset\n"
"addr - image hex address\n"
+ "length - image hex length\n"
"ivt_offset - hex offset of IVT in the image"
);
+U_BOOT_CMD(
+ hab_failsafe, CONFIG_SYS_MAXARGS, 1, do_hab_failsafe,
+ "run BootROM failsafe routine",
+ ""
+ );
#endif /* !defined(CONFIG_SPL_BUILD) */
-static bool is_hab_enabled(void)
+bool imx_hab_is_enabled(void)
{
struct imx_sec_config_fuse_t *fuse =
(struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
}
-uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
+int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
+ uint32_t ivt_offset)
{
uint32_t load_addr = 0;
size_t bytes;
- ptrdiff_t ivt_offset = 0;
- int result = 0;
+ uint32_t ivt_addr = 0;
+ int result = 1;
ulong start;
hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
hab_rvt_entry_t *hab_rvt_entry;
hab_rvt_exit_t *hab_rvt_exit;
+ hab_rvt_check_target_t *hab_rvt_check_target;
+ struct ivt *ivt;
+ struct ivt_header *ivt_hdr;
+ enum hab_status status;
hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
hab_rvt_entry = hab_rvt_entry_p;
hab_rvt_exit = hab_rvt_exit_p;
+ hab_rvt_check_target = hab_rvt_check_target_p;
+
+ if (!imx_hab_is_enabled()) {
+ puts("hab fuse not enabled\n");
+ return 0;
+ }
+
+ printf("\nAuthenticate image from DDR location 0x%x...\n",
+ ddr_start);
- if (is_hab_enabled()) {
- printf("\nAuthenticate image from DDR location 0x%x...\n",
- ddr_start);
+ hab_caam_clock_enable(1);
- hab_caam_clock_enable(1);
+ /* Calculate IVT address header */
+ ivt_addr = ddr_start + ivt_offset;
+ ivt = (struct ivt *)ivt_addr;
+ ivt_hdr = &ivt->hdr;
- if (hab_rvt_entry() == HAB_SUCCESS) {
- /* If not already aligned, Align to ALIGN_SIZE */
- ivt_offset = (image_size + ALIGN_SIZE - 1) &
- ~(ALIGN_SIZE - 1);
+ /* Verify IVT header bugging out on error */
+ if (verify_ivt_header(ivt_hdr))
+ goto hab_caam_clock_disable;
+
+ /* Verify IVT body */
+ if (ivt->self != ivt_addr) {
+ printf("ivt->self 0x%08x pointer is 0x%08x\n",
+ ivt->self, ivt_addr);
+ goto hab_caam_clock_disable;
+ }
- start = ddr_start;
- bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
+ start = ddr_start;
+ bytes = image_size;
+
+ if (hab_rvt_entry() != HAB_SUCCESS) {
+ puts("hab entry function fail\n");
+ goto hab_exit_failure_print_status;
+ }
+
+ status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)ddr_start, bytes);
+ if (status != HAB_SUCCESS) {
+ printf("HAB check target 0x%08x-0x%08x fail\n",
+ ddr_start, ddr_start + bytes);
+ goto hab_exit_failure_print_status;
+ }
#ifdef DEBUG
- printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
- ivt_offset, ddr_start + ivt_offset);
- puts("Dumping IVT\n");
- print_buffer(ddr_start + ivt_offset,
- (void *)(ddr_start + ivt_offset),
- 4, 0x8, 0);
-
- puts("Dumping CSF Header\n");
- print_buffer(ddr_start + ivt_offset+IVT_SIZE,
- (void *)(ddr_start + ivt_offset+IVT_SIZE),
- 4, 0x10, 0);
+ printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr);
+ printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry,
+ ivt->dcd, ivt->csf);
+ puts("Dumping IVT\n");
+ print_buffer(ivt_addr, (void *)(ivt_addr), 4, 0x8, 0);
+
+ puts("Dumping CSF Header\n");
+ print_buffer(ivt->csf, (void *)(ivt->csf), 4, 0x10, 0);
#if !defined(CONFIG_SPL_BUILD)
- get_hab_status();
+ get_hab_status();
#endif
- puts("\nCalling authenticate_image in ROM\n");
- printf("\tivt_offset = 0x%x\n", ivt_offset);
- printf("\tstart = 0x%08lx\n", start);
- printf("\tbytes = 0x%x\n", bytes);
+ puts("\nCalling authenticate_image in ROM\n");
+ printf("\tivt_offset = 0x%x\n", ivt_offset);
+ printf("\tstart = 0x%08lx\n", start);
+ printf("\tbytes = 0x%x\n", bytes);
#endif
+ /*
+ * If the MMU is enabled, we have to notify the ROM
+ * code, or it won't flush the caches when needed.
+ * This is done, by setting the "pu_irom_mmu_enabled"
+ * word to 1. You can find its address by looking in
+ * the ROM map. This is critical for
+ * authenticate_image(). If MMU is enabled, without
+ * setting this bit, authentication will fail and may
+ * crash.
+ */
+ /* Check MMU enabled */
+ if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
+ if (is_mx6dq()) {
/*
- * If the MMU is enabled, we have to notify the ROM
- * code, or it won't flush the caches when needed.
- * This is done, by setting the "pu_irom_mmu_enabled"
- * word to 1. You can find its address by looking in
- * the ROM map. This is critical for
- * authenticate_image(). If MMU is enabled, without
- * setting this bit, authentication will fail and may
- * crash.
+ * This won't work on Rev 1.0.0 of
+ * i.MX6Q/D, since their ROM doesn't
+ * do cache flushes. don't think any
+ * exist, so we ignore them.
*/
- /* Check MMU enabled */
- if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
- if (is_mx6dq()) {
- /*
- * This won't work on Rev 1.0.0 of
- * i.MX6Q/D, since their ROM doesn't
- * do cache flushes. don't think any
- * exist, so we ignore them.
- */
- if (!is_mx6dqp())
- writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
- } else if (is_mx6sdl()) {
- writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
- } else if (is_mx6sl()) {
- writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
- }
- }
-
- load_addr = (uint32_t)hab_rvt_authenticate_image(
- HAB_CID_UBOOT,
- ivt_offset, (void **)&start,
- (size_t *)&bytes, NULL);
- if (hab_rvt_exit() != HAB_SUCCESS) {
- puts("hab exit function fail\n");
- load_addr = 0;
- }
- } else {
- puts("hab entry function fail\n");
+ if (!is_mx6dqp())
+ writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+ } else if (is_mx6sdl()) {
+ writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
+ } else if (is_mx6sl()) {
+ writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
}
+ }
- hab_caam_clock_enable(0);
+ load_addr = (uint32_t)hab_rvt_authenticate_image(
+ HAB_CID_UBOOT,
+ ivt_offset, (void **)&start,
+ (size_t *)&bytes, NULL);
+ if (hab_rvt_exit() != HAB_SUCCESS) {
+ puts("hab exit function fail\n");
+ load_addr = 0;
+ }
+hab_exit_failure_print_status:
#if !defined(CONFIG_SPL_BUILD)
- get_hab_status();
+ get_hab_status();
#endif
- } else {
- puts("hab fuse not enabled\n");
- }
- if ((!is_hab_enabled()) || (load_addr != 0))
- result = 1;
+hab_caam_clock_disable:
+ hab_caam_clock_enable(0);
+
+ if (load_addr != 0)
+ result = 0;
return result;
}
#include <common.h>
#include <command.h>
+#include <linux/compiler.h>
/* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
/* please define platform specific arch_auxiliary_core_up() */
return CMD_RET_FAILURE;
}
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
- __attribute__((weak, alias("__arch_auxiliary_core_up")));
-
/* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_check_up(u32 core_id)
+int __weak arch_auxiliary_core_check_up(u32 core_id)
{
/* please define platform specific arch_auxiliary_core_check_up() */
return 0;
}
-int arch_auxiliary_core_check_up(u32 core_id)
- __attribute__((weak, alias("__arch_auxiliary_core_check_up")));
-
/*
* To i.MX6SX and i.MX7D, the image supported by bootaux needs
* the reset vector at the head for the image, with SP and PC
* The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
* accessing the M4 TCMUL.
*/
-int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr;
int ret, up;
}
#endif
+#ifndef CONFIG_SPL_BUILD
/*
* Dump some core clockes.
*/
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;
"display clocks",
""
);
+#endif
bool "CM-FX6"
select SUPPORT_SPL
select MX6QDL
+ select BOARD_LATE_INIT
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_SECOMX6
bool "secomx6 boards"
+config TARGET_SKSIMX6
+ bool "sks-imx6"
+ select SUPPORT_SPL
+
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
+source "board/sks-kinkel/sksimx6/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
- if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
mmdc1->entry = value; \
} while (0)
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */
}
#endif
+#ifndef CONFIG_SPL_BUILD
/*
* Dump some core clockes.
*/
"display clocks",
""
);
+#endif
}
#endif
+#ifndef CONFIG_SPL_BUILD
/*
* Dump some core clockes.
*/
"display clocks",
""
);
+#endif
switch (boot_device_spl) {
case SD1_BOOT:
case MMC1_BOOT:
- return BOOT_DEVICE_MMC1;
case SD2_BOOT:
case MMC2_BOOT:
- return BOOT_DEVICE_MMC2;
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case NAND_BOOT:
+ return BOOT_DEVICE_NAND;
case SPI_NOR_BOOT:
return BOOT_DEVICE_SPI;
default:
#if defined(CONFIG_SECURE_BOOT)
+/*
+ * +------------+ 0x0 (DDR_UIMAGE_START) -
+ * | Header | |
+ * +------------+ 0x40 |
+ * | | |
+ * | | |
+ * | | |
+ * | | |
+ * | Image Data | |
+ * . | |
+ * . | > Stuff to be authenticated ----+
+ * . | | |
+ * | | | |
+ * | | | |
+ * +------------+ | |
+ * | | | |
+ * | Fill Data | | |
+ * | | | |
+ * +------------+ Align to ALIGN_SIZE | |
+ * | IVT | | |
+ * +------------+ + IVT_SIZE - |
+ * | | |
+ * | CSF DATA | <---------------------------------------------------------+
+ * | |
+ * +------------+
+ * | |
+ * | Fill Data |
+ * | |
+ * +------------+ + CSF_PAD_SIZE
+ */
+
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(void);
+ uint32_t offset;
image_entry_noargs_t image_entry =
(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
/* HAB looks for the CSF at the end of the authenticated data therefore,
* we need to subtract the size of the CSF from the actual filesize */
- if (authenticate_image(spl_image->load_addr,
- spl_image->size - CONFIG_CSF_SIZE)) {
+ offset = spl_image->size - CONFIG_CSF_SIZE;
+ if (!imx_hab_authenticate_image(spl_image->load_addr,
+ offset + IVT_SIZE + CSF_PAD_SIZE,
+ offset)) {
image_entry();
} else {
puts("spl: ERROR: image authentication unsuccessful\n");
config TARGET_K2HK_EVM
bool "TI Keystone 2 Kepler/Hawking EVM"
select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
imply DM_I2C
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
imply DM_I2C
config TARGET_K2L_EVM
bool "TI Keystone 2 Lamar EVM"
select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
imply DM_I2C
config TARGET_K2G_EVM
select BOARD_LATE_INIT
select SPL_BOARD_INIT if SPL
select TI_I2C_BOARD_DETECT
+ select CMD_DDR3
imply DM_I2C
endchoice
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += cmd_poweroff.o
-obj-y += cmd_ddr3.o
endif
obj-y += msmc.o
obj-y += ddr3.o
+++ /dev/null
-/*
- * Keystone2: DDR3 test commands
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/ddr3.h>
-#include <common.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
-#define STACKSIZE (512 << 10) /* 512 KiB */
-
-#define DDR_REMAP_ADDR 0x80000000
-#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
-
-#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
- STACKSIZE) >> 17) - 2)
-
-#define DDR_TEST_BURST_SIZE 1024
-
-static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
-{
- u32 index_start, value, index;
-
- index_start = start_address;
-
- while (1) {
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4)
- __raw_writel(index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4) {
- value = __raw_readl(index);
- if (value != index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readl(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- if (quick)
- continue;
-
- /* Write a pattern for complementary values */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4)
- __raw_writel((u32)~index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4) {
- value = __raw_readl(index);
- if (value != ~index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readl(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 2)
- __raw_writew((u16)index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 2) {
- value = __raw_readw(index);
- if (value != (u16)index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readw(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 1)
- __raw_writeb((u8)index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 1) {
- value = __raw_readb(index);
- if (value != (u8)index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readb(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
- }
-
- puts("ddr memory test PASSED!\n");
- return 0;
-}
-
-static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
-{
- u32 index, value, index2, value2;
-
- for (index = address1, index2 = address2;
- index < address1 + size;
- index += 4, index2 += 4) {
- value = __raw_readl(index);
- value2 = __raw_readl(index2);
-
- if (value != value2) {
- printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
- index, value, index2, value2);
-
- return -1;
- }
- }
-
- puts("ddr memory compare PASSED!\n");
- return 0;
-}
-
-static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
-{
- u32 value1, value2, value3;
-
- puts("Disabling DDR ECC ...\n");
- ddr3_disable_ecc(base);
-
- value1 = __raw_readl(address);
- value2 = value1 ^ ecc_err;
- __raw_writel(value2, address);
-
- value3 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
- address, value1, value2, ecc_err, value3);
-
- __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
- base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
-
- puts("Enabling DDR ECC ...\n");
- ddr3_enable_ecc(base, 1);
-
- value1 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
-
- ddr3_check_ecc_int(base);
- return 0;
-}
-
-static int do_ddr_test(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- u32 start_addr, end_addr, size, ecc_err;
-
- if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
- if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
- puts("ECC RMW isn't supported for this SOC\n");
- return 1;
- }
-
- start_addr = simple_strtoul(argv[2], NULL, 16);
- ecc_err = simple_strtoul(argv[3], NULL, 16);
-
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1))) {
- puts("Invalid address!\n");
- return cmd_usage(cmdtp);
- }
-
- ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
- start_addr, ecc_err);
- return 0;
- }
-
- if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
- ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
- return cmd_usage(cmdtp);
-
- start_addr = simple_strtoul(argv[2], NULL, 16);
- end_addr = simple_strtoul(argv[3], NULL, 16);
-
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
- (end_addr < CONFIG_SYS_SDRAM_BASE) ||
- (end_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
- puts("Invalid start or end address!\n");
- return cmd_usage(cmdtp);
- }
-
- puts("Please wait ...\n");
- if (argc == 5) {
- size = simple_strtoul(argv[4], NULL, 16);
- ddr_memory_compare(start_addr, end_addr, size);
- } else {
- ddr_memory_test(start_addr, end_addr, 0);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(ddr, 5, 1, do_ddr_test,
- "DDR3 test",
- "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
- " address to end address\n"
- "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
- " compare DDR data of (size) bytes from start address to end\n"
- " address\n"
- "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
- " in DDR data at <addr>, the command will read a 32-bit data\n"
- " from <addr>, and write (data ^ bit_err) back to <addr>\n"
-);
#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
#define KS2_DDR3A_DDRPHYC 0x02329000
+#define EMIF1_BASE KS2_DDR3A_EMIF_CTRL_BASE
#define KS2_DDR3_MIDR_OFFSET 0x00
#define KS2_DDR3_STATUS_OFFSET 0x04
#define CPU_66AK2Lx 0xb9a7
#define CPU_66AK2Gx 0xbb06
+/* Variant definitions */
+#define CPU_66AK2G1x 0x08
+
/* DEVSPEED register */
#define DEVSPEED_DEVSPEED_SHIFT 16
#define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x23000100
-#define OMAP_HSMMC2_BASE 0x23100100
+#define OMAP_HSMMC1_BASE 0x23000000
+#define OMAP_HSMMC2_BASE 0x23100000
#endif /* K2G_MMC_HOST_DEF_H */
puts("66AK2Ex SR");
break;
case CPU_66AK2Gx:
- puts("66AK2Gx SR");
+ puts("66AK2Gx");
+#ifdef CONFIG_SOC_K2G
+ {
+ int speed = get_max_arm_speed(speeds);
+ if (speed == SPD1000)
+ puts("-100 ");
+ else if (speed == SPD600)
+ puts("-60 ");
+ else
+ puts("-xx ");
+ }
+#endif
+ puts("SR");
break;
default:
puts("Unknown\n");
puts("1.1\n");
else if (rev == 0)
puts("1.0\n");
-
+ else if (rev == 8)
+ puts("1.0\n");
return 0;
}
#endif
.cm_div_m2_dpll = CM_WKUP + 0xA0,
};
+const struct dpll_regs dpll_disp_regs = {
+ .cm_clkmode_dpll = CM_WKUP + 0x98,
+ .cm_idlest_dpll = CM_WKUP + 0x48,
+ .cm_clksel_dpll = CM_WKUP + 0x54,
+ .cm_div_m2_dpll = CM_WKUP + 0xA4,
+};
+
struct dpll_params dpll_mpu_opp100 = {
CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_core_opp100 = {
const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
{505, 15, 2, -1, -1, -1, -1}, /*19.2*/
{101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
- {303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
- {303, 12, 2, -1, 4, -1, -1} /* 26 MHz */
+ {303, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
+ {303, 12, 2, -1, -1, -1, -1} /* 26 MHz */
};
const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
{125, 5, 1, -1, -1, -1, -1}, /*19.2*/
{50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
- {16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */
- {200, 12, 1, -1, 4, -1, -1} /* 26 MHz */
+ {16, 0, 1, -1, -1, -1, -1}, /* 25 MHz */
+ {200, 12, 1, -1, -1, -1, -1} /* 26 MHz */
};
const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
{665, 47, 1, -1, -1, -1, -1}, /*19.2*/
{133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
- {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
- {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
+ {266, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
+ {133, 12, 1, -1, -1, -1, -1} /* 26 MHz */
};
__weak const struct dpll_params *get_dpll_mpu_params(void)
#include <asm/omap_sec_common.h>
#include <asm/utils.h>
#include <linux/compiler.h>
+#include <asm/ti-common/ti-edma3.h>
static int emif1_enabled = -1, emif2_enabled = -1;
u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
u32 reg, i, phy;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6];
phy = readl(&emif->emif_ddr_phy_ctrl_1);
/* Update PHY_REG_RDDQS_RATIO */
/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11];
if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
reg = readl(emif_phy_status++);
/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16];
if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
reg = readl(emif_phy_status++);
update_hwleveling_output(base, regs);
}
+static void dra7_reset_ddr_data(u32 base, u32 size)
+{
+#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
+ enable_edma3_clocks();
+
+ edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size);
+
+ disable_edma3_clocks();
+#else
+ memset((void *)base, 0, size);
+#endif
+}
+
+static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 rgn, size;
+
+ /* ECC available only on dra76x EMIF1 */
+ if ((base != EMIF1_BASE) || !is_dra76x())
+ return;
+
+ if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) {
+ writel(regs->emif_ecc_address_range_1,
+ &emif->emif_ecc_address_range_1);
+ writel(regs->emif_ecc_address_range_2,
+ &emif->emif_ecc_address_range_2);
+ writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
+
+ /* Set region1 memory with 0 */
+ rgn = ((regs->emif_ecc_address_range_1 &
+ EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) +
+ CONFIG_SYS_SDRAM_BASE;
+ size = (regs->emif_ecc_address_range_1 &
+ EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000;
+
+ if (regs->emif_ecc_ctrl_reg &
+ EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK)
+ dra7_reset_ddr_data(rgn, size);
+
+ /* Set region2 memory with 0 */
+ rgn = ((regs->emif_ecc_address_range_2 &
+ EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) +
+ CONFIG_SYS_SDRAM_BASE;
+ size = (regs->emif_ecc_address_range_2 &
+ EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000;
+
+ if (regs->emif_ecc_ctrl_reg &
+ EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK)
+ dra7_reset_ddr_data(rgn, size);
+
+#ifdef CONFIG_DRA7XX
+ /* Clear the status flags and other history */
+ writel(readl(&emif->emif_1b_ecc_err_cnt),
+ &emif->emif_1b_ecc_err_cnt);
+ writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1);
+ writel(0x1, &emif->emif_2b_ecc_err_addr_log);
+ writel(EMIF_INT_WR_ECC_ERR_SYS_MASK |
+ EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK |
+ EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK,
+ &emif->emif_irqstatus_sys);
+#endif
+ }
+}
+
static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
- if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
+ if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) {
+ /*
+ * Perform Dummy ECC setup just to allow hardware
+ * leveling of ECC memories
+ */
+ if (is_dra76x() && (base == EMIF1_BASE) &&
+ (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) {
+ writel(0, &emif->emif_ecc_address_range_1);
+ writel(0, &emif->emif_ecc_address_range_2);
+ writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK |
+ EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK,
+ &emif->emif_ecc_ctrl_reg);
+ }
+
dra7_ddr3_leveling(base, regs);
+
+ /* Disable ECC */
+ if (is_dra76x())
+ writel(0, &emif->emif_ecc_ctrl_reg);
+ }
+
+ /* Enable ECC as necessary */
+ dra7_enable_ecc(base, regs);
}
static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
- const char *sec_s;
+ const char *sec_s, *package = NULL;
switch (get_device_type()) {
case TST_DEVICE:
sec_s = "?";
}
+#if defined(CONFIG_DRA7XX)
+ if (is_dra76x()) {
+ switch (omap_rev & 0xF) {
+ case DRA762_ABZ_PACKAGE:
+ package = "ABZ";
+ break;
+ case DRA762_ACD_PACKAGE:
+ default:
+ package = "ACD";
+ break;
+ }
+ }
+#endif
+
if (soc_variant)
printf("OMAP");
else
printf("DRA");
- printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
+ printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev);
+ if (package)
+ printf(" %s package\n", package);
+ else
+ puts("\n");
}
#ifdef CONFIG_SPL_BUILD
{
}
+/**
+ * init_package_revision() - Initialize package revision
+ *
+ * Function to get the pacakage information. This is expected to be
+ * overridden in the SoC family file where desired.
+ */
+void __weak init_package_revision(void)
+{
+}
+
/**
* early_system_init - Does Early system initialization.
*
{
init_omap_revision();
hw_data_init();
+ init_package_revision();
#ifdef CONFIG_SPL_BUILD
if (warm_reset())
select BOARD_LATE_INIT
select DRA7XX
select TI_I2C_BOARD_DETECT
+ select CMD_DDR3
imply SCSI
imply SPL_THERMAL
imply DM_THERMAL
*ctrl = &omap5_ctrl;
break;
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra76x_dplls;
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA762_ES1_0:
+ case DRA762_ACD_ES1_0:
+ case DRA762_ABZ_ES1_0:
*regs = &ioregs_dra7xx_es1;
break;
case DRA722_ES1_0:
init_cpu_configuration();
}
+void init_package_revision(void)
+{
+ unsigned int die_id[4] = { 0 };
+ u8 package;
+
+ omap_die_id(die_id);
+ package = (die_id[2] >> 16) & 0x3;
+
+ if (is_dra76x()) {
+ switch (package) {
+ case DRA762_ABZ_PACKAGE:
+ *omap_si_rev = DRA762_ABZ_ES1_0;
+ break;
+ case DRA762_ACD_PACKAGE:
+ default:
+ *omap_si_rev = DRA762_ACD_ES1_0;
+ break;
+ }
+ }
+}
+
void omap_die_id(unsigned int *die_id)
{
die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
break;
case DRA762_ES1_0:
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA722_ES2_0:
case DRA722_ES2_1:
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
*iterations = sizeof(omap5_bug_00339_regs)/
sizeof(omap5_bug_00339_regs[0]);
break;
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
case DRA752_ES1_0:
case DRA752_ES1_1:
*size = sig_addr - cert_addr; /* Subtract out the signature size */
/* Subtract header if present */
if (strncmp((char *)sig_addr, "CERT_ISW_", 9) == 0)
- *size = ((u32 *)*image)[HEADER_SIZE_OFFSET];
+ *size -= ((u32 *)*image)[HEADER_SIZE_OFFSET];
cert_size = *size;
/* Check if image load address is 32-bit aligned */
}
/*
- * Output notification of successful authentication as well the name of
- * the signing certificate used to re-assure the user that the secure
- * code is being processed as expected. However suppress any such log
- * output in case of building for SPL and booting via YMODEM. This is
- * done to avoid disturbing the YMODEM serial protocol transactions.
+ * Output notification of successful authentication to re-assure the
+ * user that the secure code is being processed as expected. However
+ * suppress any such log output in case of building for SPL and booting
+ * via YMODEM. This is done to avoid disturbing the YMODEM serial
+ * protocol transactions.
*/
if (!(IS_ENABLED(CONFIG_SPL_BUILD) &&
IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) &&
spl_boot_device() == BOOT_DEVICE_UART))
- printf("Authentication passed: %s\n", (char *)sig_addr);
+ printf("Authentication passed\n");
return result;
}
default "qemu-arm"
endif
+
+config TARGET_QEMU_ARM_32BIT
+ bool "Support qemu_arm"
+ depends on ARCH_QEMU
+ select CPU_V7
+ select ARCH_SUPPORT_PSCI
+
+config TARGET_QEMU_ARM_64BIT
+ bool "Support qemu_arm64"
+ depends on ARCH_QEMU
+ select ARM64
select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
select SPL
+ imply USB_FUNCTION_ROCKUSB
+ imply CMD_ROCKUSB
help
The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
- HDMI
- 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
+config TARGET_DRAGONBOARD820C
+ bool "96Boards Dragonboard 820C"
+ help
+ Support for 96Boards Dragonboard 820C. This board complies with
+ 96Board Open Platform Specifications. Features:
+ - Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU)
+ - 3GiB RAM
+ - 32GiB UFS drive
+
endchoice
source "board/qualcomm/dragonboard410c/Kconfig"
+source "board/qualcomm/dragonboard820c/Kconfig"
endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += clock-apq8016.o
-obj-y += sysmap-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
+obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
+obj-y += clock-snapdragon.o
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include "clock-snapdragon.h"
/* GPLL0 clock control registers */
-#define GPLL0_STATUS 0x2101C
#define GPLL0_STATUS_ACTIVE BIT(17)
-
-#define APCS_GPLL_ENA_VOTE 0x45000
#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
-/* vote reg for blsp1 clock */
-#define APCS_CLOCK_BRANCH_ENA_VOTE 0x45004
-#define APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1 BIT(10)
-
-/* SDC(n) clock control registers; n=1,2 */
-
-/* block control register */
-#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
-/* cmd */
-#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
-/* cfg */
-#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
-/* m */
-#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
-/* n */
-#define SDCC_N(n) ((n * 0x1000) + 0x41010)
-/* d */
-#define SDCC_D(n) ((n * 0x1000) + 0x41014)
-/* branch control */
-#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
-#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
-
-/* BLSP1 AHB clock (root clock for BLSP) */
-#define BLSP1_AHB_CBCR 0x1008
-
-/* Uart clock control registers */
-#define BLSP1_UART2_BCR 0x3028
-#define BLSP1_UART2_APPS_CBCR 0x302C
-#define BLSP1_UART2_APPS_CMD_RCGR 0x3034
-#define BLSP1_UART2_APPS_CFG_RCGR 0x3038
-#define BLSP1_UART2_APPS_M 0x303C
-#define BLSP1_UART2_APPS_N 0x3040
-#define BLSP1_UART2_APPS_D 0x3044
-
-/* CBCR register fields */
-#define CBCR_BRANCH_ENABLE_BIT BIT(0)
-#define CBCR_BRANCH_OFF_BIT BIT(31)
-
-struct msm_clk_priv {
- phys_addr_t base;
-};
-
-/* Enable clock controlled by CBC soft macro */
-static void clk_enable_cbc(phys_addr_t cbcr)
-{
- setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
-
- while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
- ;
-}
-
-/* clock has 800MHz */
-static void clk_enable_gpll0(phys_addr_t base)
-{
- if (readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE)
- return; /* clock already enabled */
-
- setbits_le32(base + APCS_GPLL_ENA_VOTE, APCS_GPLL_ENA_VOTE_GPLL0);
-
- while ((readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE) == 0)
- ;
-}
-
-#define APPS_CMD_RGCR_UPDATE BIT(0)
-
-/* Update clock command via CMD_RGCR */
-static void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
-{
- setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
-
- /* Wait for frequency to be updated. */
- while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
- ;
-}
-
-struct bcr_regs {
- uintptr_t cfg_rcgr;
- uintptr_t cmd_rcgr;
- uintptr_t M;
- uintptr_t N;
- uintptr_t D;
-};
-
-/* RCGR_CFG register fields */
-#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
-
-/* sources */
-#define CFG_CLK_SRC_CXO (0 << 8)
-#define CFG_CLK_SRC_GPLL0 (1 << 8)
-#define CFG_CLK_SRC_MASK (7 << 8)
-
-/* Mask for supported fields */
-#define CFG_MASK 0x3FFF
-
-#define CFG_DIVIDER_MASK 0x1F
-
-/* root set rate for clocks with half integer and MND divider */
-static void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
- int div, int m, int n, int source)
-{
- uint32_t cfg;
- /* M value for MND divider. */
- uint32_t m_val = m;
- /* NOT(N-M) value for MND divider. */
- uint32_t n_val = ~((n)-(m)) * !!(n);
- /* NOT 2D value for MND divider. */
- uint32_t d_val = ~(n);
-
- /* Program MND values */
- writel(m_val, base + regs->M);
- writel(n_val, base + regs->N);
- writel(d_val, base + regs->D);
-
- /* setup src select and divider */
- cfg = readl(base + regs->cfg_rcgr);
- cfg &= ~CFG_MASK;
- cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
-
- /* Set the divider; HW permits fraction dividers (+0.5), but
- for simplicity, we will support integers only */
- if (div)
- cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
-
- if (n_val)
- cfg |= CFG_MODE_DUAL_EDGE;
-
- writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
-
- /* Inform h/w to start using the new config. */
- clk_bcr_update(base + regs->cmd_rcgr);
-}
-
static const struct bcr_regs sdc_regs[] = {
{
.cfg_rcgr = SDCC_CFG_RCGR(1),
}
};
-/* Init clock for SDHCI controller */
+static struct gpll0_ctrl gpll0_ctrl = {
+ .status = GPLL0_STATUS,
+ .status_bit = GPLL0_STATUS_ACTIVE,
+ .ena_vote = APCS_GPLL_ENA_VOTE,
+ .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
+};
+
+/* SDHCI */
static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
{
int div = 8; /* 100MHz default */
/* 800Mhz/div, gpll0 */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
CFG_CLK_SRC_GPLL0);
- clk_enable_gpll0(priv->base);
+ clk_enable_gpll0(priv->base, &gpll0_ctrl);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
return rate;
.D = BLSP1_UART2_APPS_D,
};
-/* Init UART clock, 115200 */
+/* UART: 115200 */
static int clk_init_uart(struct msm_clk_priv *priv)
{
/* Enable iface clk */
/* 7372800 uart block clock @ GPLL0 */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
CFG_CLK_SRC_GPLL0);
- clk_enable_gpll0(priv->base);
+ clk_enable_gpll0(priv->base, &gpll0_ctrl);
/* Enable core clk */
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
return 0;
}
}
-
-static int msm_clk_probe(struct udevice *dev)
-{
- struct msm_clk_priv *priv = dev_get_priv(dev);
-
- priv->base = devfdt_get_addr(dev);
- if (priv->base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- return 0;
-}
-
-static struct clk_ops msm_clk_ops = {
- .set_rate = msm_set_rate,
-};
-
-static const struct udevice_id msm_clk_ids[] = {
- { .compatible = "qcom,gcc-msm8916" },
- { .compatible = "qcom,gcc-apq8016" },
- { }
-};
-
-U_BOOT_DRIVER(clk_msm) = {
- .name = "clk_msm",
- .id = UCLASS_CLK,
- .of_match = msm_clk_ids,
- .ops = &msm_clk_ops,
- .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
- .probe = msm_clk_probe,
-};
--- /dev/null
+/*
+ * Clock drivers for Qualcomm APQ8096
+ *
+ * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * Based on Little Kernel driver, simplified
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include "clock-snapdragon.h"
+
+/* GPLL0 clock control registers */
+#define GPLL0_STATUS_ACTIVE BIT(30)
+#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
+
+static const struct bcr_regs sdc_regs = {
+ .cfg_rcgr = SDCC2_CFG_RCGR,
+ .cmd_rcgr = SDCC2_CMD_RCGR,
+ .M = SDCC2_M,
+ .N = SDCC2_N,
+ .D = SDCC2_D,
+};
+
+static const struct gpll0_ctrl gpll0_ctrl = {
+ .status = GPLL0_STATUS,
+ .status_bit = GPLL0_STATUS_ACTIVE,
+ .ena_vote = APCS_GPLL_ENA_VOTE,
+ .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
+};
+
+static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
+{
+ int div = 3;
+
+ clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
+ clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
+ CFG_CLK_SRC_GPLL0);
+ clk_enable_gpll0(priv->base, &gpll0_ctrl);
+ clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
+
+ return rate;
+}
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case 0: /* SDC1 */
+ return clk_init_sdc(priv, rate);
+ break;
+ default:
+ return 0;
+ }
+}
--- /dev/null
+/*
+ * Clock drivers for Qualcomm APQ8016, APQ8096
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Based on Little Kernel driver, simplified
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include "clock-snapdragon.h"
+
+/* CBCR register fields */
+#define CBCR_BRANCH_ENABLE_BIT BIT(0)
+#define CBCR_BRANCH_OFF_BIT BIT(31)
+
+extern ulong msm_set_rate(struct clk *clk, ulong rate);
+
+/* Enable clock controlled by CBC soft macro */
+void clk_enable_cbc(phys_addr_t cbcr)
+{
+ setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
+
+ while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
+ ;
+}
+
+void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0)
+{
+ if (readl(base + gpll0->status) & gpll0->status_bit)
+ return; /* clock already enabled */
+
+ setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit);
+
+ while ((readl(base + gpll0->status) & gpll0->status_bit) == 0)
+ ;
+}
+
+#define APPS_CMD_RGCR_UPDATE BIT(0)
+
+/* Update clock command via CMD_RGCR */
+void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
+{
+ setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
+
+ /* Wait for frequency to be updated. */
+ while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
+ ;
+}
+
+#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
+
+#define CFG_MASK 0x3FFF
+
+#define CFG_DIVIDER_MASK 0x1F
+
+/* root set rate for clocks with half integer and MND divider */
+void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
+ int div, int m, int n, int source)
+{
+ u32 cfg;
+ /* M value for MND divider. */
+ u32 m_val = m;
+ /* NOT(N-M) value for MND divider. */
+ u32 n_val = ~((n) - (m)) * !!(n);
+ /* NOT 2D value for MND divider. */
+ u32 d_val = ~(n);
+
+ /* Program MND values */
+ writel(m_val, base + regs->M);
+ writel(n_val, base + regs->N);
+ writel(d_val, base + regs->D);
+
+ /* setup src select and divider */
+ cfg = readl(base + regs->cfg_rcgr);
+ cfg &= ~CFG_MASK;
+ cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
+
+ /* Set the divider; HW permits fraction dividers (+0.5), but
+ for simplicity, we will support integers only */
+ if (div)
+ cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
+
+ if (n_val)
+ cfg |= CFG_MODE_DUAL_EDGE;
+
+ writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
+
+ /* Inform h/w to start using the new config. */
+ clk_bcr_update(base + regs->cmd_rcgr);
+}
+
+static int msm_clk_probe(struct udevice *dev)
+{
+ struct msm_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = devfdt_get_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
+{
+ return msm_set_rate(clk, rate);
+}
+
+static struct clk_ops msm_clk_ops = {
+ .set_rate = msm_clk_set_rate,
+};
+
+static const struct udevice_id msm_clk_ids[] = {
+ { .compatible = "qcom,gcc-msm8916" },
+ { .compatible = "qcom,gcc-apq8016" },
+ { .compatible = "qcom,gcc-msm8996" },
+ { .compatible = "qcom,gcc-apq8096" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_msm) = {
+ .name = "clk_msm",
+ .id = UCLASS_CLK,
+ .of_match = msm_clk_ids,
+ .ops = &msm_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
+ .probe = msm_clk_probe,
+};
--- /dev/null
+/*
+ * Qualcomm APQ8016, APQ8096
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _CLOCK_SNAPDRAGON_H
+#define _CLOCK_SNAPDRAGON_H
+
+#define CFG_CLK_SRC_CXO (0 << 8)
+#define CFG_CLK_SRC_GPLL0 (1 << 8)
+#define CFG_CLK_SRC_MASK (7 << 8)
+
+struct gpll0_ctrl {
+ uintptr_t status;
+ int status_bit;
+ uintptr_t ena_vote;
+ int vote_bit;
+};
+
+struct bcr_regs {
+ uintptr_t cfg_rcgr;
+ uintptr_t cmd_rcgr;
+ uintptr_t M;
+ uintptr_t N;
+ uintptr_t D;
+};
+
+struct msm_clk_priv {
+ phys_addr_t base;
+};
+
+void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0);
+void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
+void clk_enable_cbc(phys_addr_t cbcr);
+void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
+ int div, int m, int n, int source);
+
+#endif
#ifndef _MACH_SYSMAP_APQ8016_H
#define _MACH_SYSMAP_APQ8016_H
-#define GICD_BASE 0x0b000000
-#define GICC_BASE 0x0a20c000
+#define GICD_BASE (0x0b000000)
+#define GICC_BASE (0x0a20c000)
+
+/* Clocks: (from CLK_CTL_BASE) */
+#define GPLL0_STATUS (0x2101C)
+#define APCS_GPLL_ENA_VOTE (0x45000)
+
+#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
+#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
+#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
+#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
+#define SDCC_N(n) ((n * 0x1000) + 0x41010)
+#define SDCC_D(n) ((n * 0x1000) + 0x41014)
+#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
+#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
+
+/* BLSP1 AHB clock (root clock for BLSP) */
+#define BLSP1_AHB_CBCR 0x1008
+
+/* Uart clock control registers */
+#define BLSP1_UART2_BCR (0x3028)
+#define BLSP1_UART2_APPS_CBCR (0x302C)
+#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
+#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
+#define BLSP1_UART2_APPS_M (0x303C)
+#define BLSP1_UART2_APPS_N (0x3040)
+#define BLSP1_UART2_APPS_D (0x3044)
#endif
--- /dev/null
+/*
+ * Qualcomm APQ8096 sysmap
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _MACH_SYSMAP_APQ8096_H
+#define _MACH_SYSMAP_APQ8096_H
+
+#define TLMM_BASE_ADDR (0x1010000)
+
+/* Strength (sdc1) */
+#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
+
+/* Clocks: (from CLK_CTL_BASE) */
+#define GPLL0_STATUS (0x0000)
+#define APCS_GPLL_ENA_VOTE (0x52000)
+
+#define SDCC2_BCR (0x14000) /* block reset */
+#define SDCC2_APPS_CBCR (0x14004) /* branch control */
+#define SDCC2_AHB_CBCR (0x14008)
+#define SDCC2_CMD_RCGR (0x14010)
+#define SDCC2_CFG_RCGR (0x14014)
+#define SDCC2_M (0x14018)
+#define SDCC2_N (0x1401C)
+#define SDCC2_D (0x14020)
+
+#endif
--- /dev/null
+/*
+ * Qualcomm APQ8096 memory map
+ *
+ * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region apq8096_mem_map[] = {
+ {
+ .virt = 0x0UL, /* Peripheral block */
+ .phys = 0x0UL, /* Peripheral block */
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL, /* DDR */
+ .phys = 0x80000000UL, /* DDR */
+ .size = 0xC0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = apq8096_mem_map;
return 0;
}
-int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+#ifndef CONFIG_SPL_BUILD
+static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cm_print_clock_quick_summary();
return 0;
"display clocks",
""
);
+#endif
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
- (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
-static struct socfpga_sdr_ctrl *sdr_ctrl =
- (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
/*
* DesignWare Ethernet initialization
return 0;
}
+#ifndef CONFIG_SPL_BUILD
+static struct socfpga_reset_manager *reset_manager_base =
+ (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+ (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
static void socfpga_sdram_apply_static_cfg(void)
{
const u32 applymask = 0x8;
: : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
}
-int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 2)
return CMD_RET_USAGE;
"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
""
);
+#endif
config STM32F4
bool "stm32f4 family"
+ select CLK
+ select DM_GPIO
+ select DM_RESET
+ select MISC
+ select PINCTRL
+ select PINCTRL_STM32
+ select RAM
+ select STM32_SDRAM
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SERIAL
config STM32F7
bool "stm32f7 family"
+ select CLK
+ select DM_GPIO
+ select DM_RESET
+ select MISC
+ select PINCTRL
+ select PINCTRL_STM32
+ select RAM
+ select STM32_SDRAM
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SERIAL
select SUPPORT_SPL
select SPL
select SPL_CLK
select STM32_SDRAM
select STM32_RCC
select STM32_RESET
- select STM32X7_SERIAL
+ select STM32_SERIAL
select SYSCON
source "arch/arm/mach-stm32/stm32f4/Kconfig"
config TARGET_STM32F429_DISCOVERY
bool "STM32F429 Discovery board"
+config TARGET_STM32F469_DISCOVERY
+ bool "STM32F469 Discovery board"
+
source "board/st/stm32f429-discovery/Kconfig"
+source "board/st/stm32f469-discovery/Kconfig"
endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += clock.o timer.o
+obj-y += timer.o
+++ /dev/null
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * (C) Copyright 2014
- * STMicroelectronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stm32_rcc.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_periph.h>
-
-#define RCC_CR_HSION (1 << 0)
-#define RCC_CR_HSEON (1 << 16)
-#define RCC_CR_HSERDY (1 << 17)
-#define RCC_CR_HSEBYP (1 << 18)
-#define RCC_CR_CSSON (1 << 19)
-#define RCC_CR_PLLON (1 << 24)
-#define RCC_CR_PLLRDY (1 << 25)
-
-#define RCC_PLLCFGR_PLLM_MASK 0x3F
-#define RCC_PLLCFGR_PLLN_MASK 0x7FC0
-#define RCC_PLLCFGR_PLLP_MASK 0x30000
-#define RCC_PLLCFGR_PLLQ_MASK 0xF000000
-#define RCC_PLLCFGR_PLLSRC (1 << 22)
-#define RCC_PLLCFGR_PLLN_SHIFT 6
-#define RCC_PLLCFGR_PLLP_SHIFT 16
-#define RCC_PLLCFGR_PLLQ_SHIFT 24
-
-#define RCC_CFGR_AHB_PSC_MASK 0xF0
-#define RCC_CFGR_APB1_PSC_MASK 0x1C00
-#define RCC_CFGR_APB2_PSC_MASK 0xE000
-#define RCC_CFGR_SW0 (1 << 0)
-#define RCC_CFGR_SW1 (1 << 1)
-#define RCC_CFGR_SW_MASK 0x3
-#define RCC_CFGR_SW_HSI 0
-#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
-#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
-#define RCC_CFGR_SWS0 (1 << 2)
-#define RCC_CFGR_SWS1 (1 << 3)
-#define RCC_CFGR_SWS_MASK 0xC
-#define RCC_CFGR_SWS_HSI 0
-#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
-#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
-#define RCC_CFGR_HPRE_SHIFT 4
-#define RCC_CFGR_PPRE1_SHIFT 10
-#define RCC_CFGR_PPRE2_SHIFT 13
-
-#define RCC_APB1ENR_PWREN (1 << 28)
-
-/*
- * RCC USART specific definitions
- */
-#define RCC_ENR_USART1EN (1 << 4)
-#define RCC_ENR_USART2EN (1 << 17)
-#define RCC_ENR_USART3EN (1 << 18)
-#define RCC_ENR_USART6EN (1 << 5)
-
-#define PWR_CR_VOS0 (1 << 14)
-#define PWR_CR_VOS1 (1 << 15)
-#define PWR_CR_VOS_MASK 0xC000
-#define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
-
-/*
- * RCC GPIO specific definitions
- */
-#define RCC_ENR_GPIO_A_EN (1 << 0)
-#define RCC_ENR_GPIO_B_EN (1 << 1)
-#define RCC_ENR_GPIO_C_EN (1 << 2)
-#define RCC_ENR_GPIO_D_EN (1 << 3)
-#define RCC_ENR_GPIO_E_EN (1 << 4)
-#define RCC_ENR_GPIO_F_EN (1 << 5)
-#define RCC_ENR_GPIO_G_EN (1 << 6)
-#define RCC_ENR_GPIO_H_EN (1 << 7)
-#define RCC_ENR_GPIO_I_EN (1 << 8)
-#define RCC_ENR_GPIO_J_EN (1 << 9)
-#define RCC_ENR_GPIO_K_EN (1 << 10)
-
-#if !defined(CONFIG_STM32_HSE_HZ)
-#error "CONFIG_STM32_HSE_HZ not defined!"
-#else
-#if (CONFIG_STM32_HSE_HZ == 8000000)
-#if (CONFIG_SYS_CLK_FREQ == 180000000)
-/* 180 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 8,
- .pll_n = 360,
- .pll_p = 2,
- .pll_q = 8,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
-};
-#else
-/* default 168 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 8,
- .pll_n = 336,
- .pll_p = 2,
- .pll_q = 7,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
-};
-#endif
-#else
-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
-#endif
-#endif
-
-int configure_clocks(void)
-{
- /* Reset RCC configuration */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
- writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
- clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
- | RCC_CR_PLLON));
- writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
- clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
- writel(0, &STM32_RCC->cir); /* Disable all interrupts */
-
- /* Configure for HSE+PLL operation */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
- while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
- ;
-
- /* Enable high performance mode, System frequency up to 180 MHz */
- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
- writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
-
- setbits_le32(&STM32_RCC->cfgr, ((
- sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
- | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
- | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
-
- writel(sys_pll_psc.pll_m
- | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
- | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
- | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
- &STM32_RCC->pllcfgr);
- setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
-
- setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
-
- while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
- ;
-
- stm32_flash_latency_cfg(5);
- clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
- setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
-
- while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
- RCC_CFGR_SWS_PLL)
- ;
-
- return 0;
-}
-
-unsigned long clock_get(enum clock clck)
-{
- u32 sysclk = 0;
- u32 shift = 0;
- /* Prescaler table lookups for clock computation */
- u8 ahb_psc_table[16] = {
- 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
- };
- u8 apb_psc_table[8] = {
- 0, 0, 0, 0, 1, 2, 3, 4
- };
-
- if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
- RCC_CFGR_SWS_PLL) {
- u16 pllm, plln, pllp;
- pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
- plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
- >> RCC_PLLCFGR_PLLN_SHIFT);
- pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
- >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
- sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
- }
-
- switch (clck) {
- case CLOCK_CORE:
- return sysclk;
- break;
- case CLOCK_AHB:
- shift = ahb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
- >> RCC_CFGR_HPRE_SHIFT)];
- return sysclk >>= shift;
- break;
- case CLOCK_APB1:
- shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
- >> RCC_CFGR_PPRE1_SHIFT)];
- return sysclk >>= shift;
- break;
- case CLOCK_APB2:
- shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
- >> RCC_CFGR_PPRE2_SHIFT)];
- return sysclk >>= shift;
- break;
- default:
- return 0;
- break;
- }
-}
-
-void clock_setup(int peripheral)
-{
- switch (peripheral) {
- case USART1_CLOCK_CFG:
- setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
- break;
- case GPIO_A_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
- break;
- case GPIO_B_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
- break;
- case GPIO_C_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
- break;
- case GPIO_D_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
- break;
- case GPIO_E_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
- break;
- case GPIO_F_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
- break;
- case GPIO_G_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
- break;
- case GPIO_H_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
- break;
- case GPIO_I_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
- break;
- case GPIO_J_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
- break;
- case GPIO_K_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
- break;
- default:
- break;
- }
-}
setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
- if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1))
- writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1,
- &tim->psc);
- else
- writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1,
- &tim->psc);
+ writel(((CONFIG_SYS_CLK_FREQ / 2) / CONFIG_SYS_HZ_CLOCK) - 1,
+ &tim->psc);
writel(0xFFFFFFFF, &tim->arr);
writel(TIM_CR1_CEN, &tim->cr1);
config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
select ARM64
+ select LINUX_KERNEL_IMAGE_HEADER
select TEGRA_COMMON
+if TEGRA_ARMV8_COMMON
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ default 0x80000000
+endif
+
choice
prompt "Tegra SoC select"
optional
#include <asm/system.h>
#include <asm/armv8/mmu.h>
-static struct mm_region tegra_mem_map[] = {
+/* size: IO + NR_DRAM_BANKS + terminator */
+struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
config SYS_SOC
default "tegra186"
+config SYS_INIT_SP_BSS_OFFSET
+ default 524288
+
source "board/nvidia/p2771-0000/Kconfig"
endif
/*
- * Copyright (c) 2016, NVIDIA CORPORATION.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <stdlib.h>
#include <common.h>
#include <fdt_support.h>
#include <fdtdec.h>
#include <asm/arch/tegra.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
extern unsigned long nvtboot_boot_x0;
+/*
+ * The following few functions run late during the boot process and dynamically
+ * calculate the load address of various binaries. To keep track of multiple
+ * allocations, some writable list of RAM banks must be used. tegra_mem_map[]
+ * is used for this purpose to avoid making yet another copy of the list of RAM
+ * banks. This is safe because tegra_mem_map[] is only used once during very
+ * early boot to create U-Boot's page tables, long before this code runs. If
+ * this assumption becomes invalid later, we can just fix the code to copy the
+ * list of RAM banks into some private data structure before running.
+ */
+
+extern struct mm_region tegra_mem_map[];
+
+static char *gen_varname(const char *var, const char *ext)
+{
+ size_t len_var = strlen(var);
+ size_t len_ext = strlen(ext);
+ size_t len = len_var + len_ext + 1;
+ char *varext = malloc(len);
+
+ if (!varext)
+ return 0;
+ strcpy(varext, var);
+ strcpy(varext + len_var, ext);
+ return varext;
+}
+
+static void mark_ram_allocated(int bank, u64 allocated_start, u64 allocated_end)
+{
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+ bool keep_front = allocated_start != bank_start;
+ bool keep_tail = allocated_end != bank_end;
+
+ if (keep_front && keep_tail) {
+ /*
+ * There are CONFIG_NR_DRAM_BANKS DRAM entries in the array,
+ * starting at index 1 (index 0 is MMIO). So, we are at DRAM
+ * entry "bank" not "bank - 1" as for a typical 0-base array.
+ * The number of remaining DRAM entries is therefore
+ * "CONFIG_NR_DRAM_BANKS - bank". We want to duplicate the
+ * current entry and shift up the remaining entries, dropping
+ * the last one. Thus, we must copy one fewer entry than the
+ * number remaining.
+ */
+ memmove(&tegra_mem_map[bank + 1], &tegra_mem_map[bank],
+ CONFIG_NR_DRAM_BANKS - bank - 1);
+ tegra_mem_map[bank].size = allocated_start - bank_start;
+ bank++;
+ tegra_mem_map[bank].virt = allocated_end;
+ tegra_mem_map[bank].phys = allocated_end;
+ tegra_mem_map[bank].size = bank_end - allocated_end;
+ } else if (keep_front) {
+ tegra_mem_map[bank].size = allocated_start - bank_start;
+ } else if (keep_tail) {
+ tegra_mem_map[bank].virt = allocated_end;
+ tegra_mem_map[bank].phys = allocated_end;
+ tegra_mem_map[bank].size = bank_end - allocated_end;
+ } else {
+ /*
+ * We could move all subsequent banks down in the array but
+ * that's not necessary for subsequent allocations to work, so
+ * we skip doing so.
+ */
+ tegra_mem_map[bank].size = 0;
+ }
+}
+
+static void reserve_ram(u64 start, u64 size)
+{
+ int bank;
+ u64 end = start + size;
+
+ for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+
+ if (end <= bank_start || start > bank_end)
+ continue;
+ mark_ram_allocated(bank, start, end);
+ break;
+ }
+}
+
+static u64 alloc_ram(u64 size, u64 align, u64 offset)
+{
+ int bank;
+
+ for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+ u64 allocated = ROUND(bank_start, align) + offset;
+ u64 allocated_end = allocated + size;
+
+ if (allocated_end > bank_end)
+ continue;
+ mark_ram_allocated(bank, allocated, allocated_end);
+ return allocated;
+ }
+ return 0;
+}
+
+static void set_calculated_aliases(char *aliases, u64 address)
+{
+ char *tmp, *alias;
+ int err;
+
+ aliases = strdup(aliases);
+ if (!aliases) {
+ pr_err("strdup(aliases) failed");
+ return;
+ }
+
+ tmp = aliases;
+ while (true) {
+ alias = strsep(&tmp, " ");
+ if (!alias)
+ break;
+ debug("%s: alias: %s\n", __func__, alias);
+ err = env_set_hex(alias, address);
+ if (err)
+ pr_err("Could not set %s\n", alias);
+ }
+
+ free(aliases);
+}
+
+static void set_calculated_env_var(const char *var)
+{
+ char *var_size;
+ char *var_align;
+ char *var_offset;
+ char *var_aliases;
+ u64 size;
+ u64 align;
+ u64 offset;
+ char *aliases;
+ u64 address;
+ int err;
+
+ var_size = gen_varname(var, "_size");
+ if (!var_size)
+ return;
+ var_align = gen_varname(var, "_align");
+ if (!var_align)
+ goto out_free_var_size;
+ var_offset = gen_varname(var, "_offset");
+ if (!var_offset)
+ goto out_free_var_align;
+ var_aliases = gen_varname(var, "_aliases");
+ if (!var_aliases)
+ goto out_free_var_offset;
+
+ size = env_get_hex(var_size, 0);
+ if (!size) {
+ pr_err("%s not set or zero\n", var_size);
+ goto out_free_var_aliases;
+ }
+ align = env_get_hex(var_align, 1);
+ /* Handle extant variables, but with a value of 0 */
+ if (!align)
+ align = 1;
+ offset = env_get_hex(var_offset, 0);
+ aliases = env_get(var_aliases);
+
+ debug("%s: Calc var %s; size=%llx, align=%llx, offset=%llx\n",
+ __func__, var, size, align, offset);
+ if (aliases)
+ debug("%s: Aliases: %s\n", __func__, aliases);
+
+ address = alloc_ram(size, align, offset);
+ if (!address) {
+ pr_err("Could not allocate %s\n", var);
+ goto out_free_var_aliases;
+ }
+ debug("%s: Address %llx\n", __func__, address);
+
+ err = env_set_hex(var, address);
+ if (err)
+ pr_err("Could not set %s\n", var);
+ if (aliases)
+ set_calculated_aliases(aliases, address);
+
+out_free_var_aliases:
+ free(var_aliases);
+out_free_var_offset:
+ free(var_offset);
+out_free_var_align:
+ free(var_align);
+out_free_var_size:
+ free(var_size);
+}
+
+#ifdef DEBUG
+static void dump_ram_banks(void)
+{
+ int bank;
+
+ for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+
+ if (!bank_size)
+ continue;
+ printf("%d: %010llx..%010llx (+%010llx)\n", bank - 1,
+ bank_start, bank_end, bank_size);
+ }
+}
+#endif
+
+static void set_calculated_env_vars(void)
+{
+ char *vars, *tmp, *var;
+
+#ifdef DEBUG
+ printf("RAM banks before any calculated env. var.s:\n");
+ dump_ram_banks();
+#endif
+
+ reserve_ram(nvtboot_boot_x0, fdt_totalsize(nvtboot_boot_x0));
+
+#ifdef DEBUG
+ printf("RAM after reserving cboot DTB:\n");
+ dump_ram_banks();
+#endif
+
+ vars = env_get("calculated_vars");
+ if (!vars) {
+ debug("%s: No env var calculated_vars\n", __func__);
+ return;
+ }
+
+ vars = strdup(vars);
+ if (!vars) {
+ pr_err("strdup(calculated_vars) failed");
+ return;
+ }
+
+ tmp = vars;
+ while (true) {
+ var = strsep(&tmp, " ");
+ if (!var)
+ break;
+ debug("%s: var: %s\n", __func__, var);
+ set_calculated_env_var(var);
+#ifdef DEBUG
+ printf("RAM banks affter allocating %s:\n", var);
+ dump_ram_banks();
+#endif
+ }
+
+ free(vars);
+}
+
static int set_fdt_addr(void)
{
int ret;
int tegra_soc_board_init_late(void)
{
+ set_calculated_env_vars();
/*
* Ignore errors here; the value may not be used depending on
* extlinux.conf or boot script content.
/*
- * Copyright (c) 2016, NVIDIA CORPORATION.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <fdt_support.h>
#include <fdtdec.h>
#include <asm/arch/tegra.h>
+#include <asm/armv8/mmu.h>
+
+#define SZ_4G 0x100000000ULL
+
+/*
+ * Size of a region that's large enough to hold the relocated U-Boot and all
+ * other allocations made around it (stack, heap, page tables, etc.)
+ * In practice, running "bdinfo" at the shell prompt, the stack reaches about
+ * 5MB from the address selected for ram_top as of the time of writing,
+ * so a 16MB region should be plenty.
+ */
+#define MIN_USABLE_RAM_SIZE SZ_16M
+/*
+ * The amount of space we expect to require for stack usage. Used to validate
+ * that all reservations fit into the region selected for the relocation target
+ */
+#define MIN_USABLE_STACK_SIZE SZ_1M
DECLARE_GLOBAL_DATA_PTR;
extern unsigned long nvtboot_boot_x0;
+extern struct mm_region tegra_mem_map[];
/*
- * A parsed version of /memory/reg from the DTB that is passed to U-Boot in x0.
- *
- * We only support up to two banks since that's all the binary bootloader
- * ever sets. We assume bank 0 is RAM below 4G and bank 1 is RAM above 4G.
- * This is all a fairly safe assumption, since the L4T kernel makes the same
- * assumptions, so the bootloader is unlikely to change.
- *
- * This is written to before relocation, and hence cannot be in .bss, since
- * .bss overlaps the DTB that's appended to the U-Boot binary. The initializer
- * forces this into .data and avoids this issue. This also has the nice side-
- * effect of the content being valid after relocation.
+ * These variables are written to before relocation, and hence cannot be
+ * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary.
+ * The section attribute forces this into .data and avoids this issue. This
+ * also has the nice side-effect of the content being valid after relocation.
+ */
+
+/* The number of valid entries in ram_banks[] */
+static int ram_bank_count __attribute__((section(".data")));
+
+/*
+ * The usable top-of-RAM for U-Boot. This is both:
+ * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing.
+ * b) At the end of a region that has enough space to hold the relocated U-Boot
+ * and all other allocations made around it (stack, heap, page tables, etc.)
*/
-static struct {
- u64 start;
- u64 size;
-} ram_banks[2] = {{1}};
+static u64 ram_top __attribute__((section(".data")));
+/* The base address of the region of RAM that ends at ram_top */
+static u64 region_base __attribute__((section(".data")));
int dram_init(void)
{
int node, len, i;
const u32 *prop;
- memset(ram_banks, 0, sizeof(ram_banks));
-
na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
hang();
}
- len /= (na + ns);
- if (len > ARRAY_SIZE(ram_banks))
- len = ARRAY_SIZE(ram_banks);
+ /* Calculate the true # of base/size pairs to read */
+ len /= 4; /* Convert bytes to number of cells */
+ len /= (na + ns); /* Convert cells to number of banks */
+ if (len > CONFIG_NR_DRAM_BANKS)
+ len = CONFIG_NR_DRAM_BANKS;
+ /* Parse the /memory node, and save useful entries */
gd->ram_size = 0;
+ ram_bank_count = 0;
for (i = 0; i < len; i++) {
- ram_banks[i].start = fdt_read_number(prop, na);
+ u64 bank_start, bank_end, bank_size, usable_bank_size;
+
+ /* Extract raw memory region data from DTB */
+ bank_start = fdt_read_number(prop, na);
prop += na;
- ram_banks[i].size = fdt_read_number(prop, ns);
+ bank_size = fdt_read_number(prop, ns);
prop += ns;
- gd->ram_size += ram_banks[i].size;
+ gd->ram_size += bank_size;
+ bank_end = bank_start + bank_size;
+ debug("Bank %d: %llx..%llx (+%llx)\n", i,
+ bank_start, bank_end, bank_size);
+
+ /*
+ * Align the bank to MMU section size. This is not strictly
+ * necessary, since the translation table construction code
+ * handles page granularity without issue. However, aligning
+ * the MMU entries reduces the size and number of levels in the
+ * page table, so is worth it.
+ */
+ bank_start = ROUND(bank_start, SZ_2M);
+ bank_end = bank_end & ~(SZ_2M - 1);
+ bank_size = bank_end - bank_start;
+ debug(" aligned: %llx..%llx (+%llx)\n",
+ bank_start, bank_end, bank_size);
+ if (bank_end <= bank_start)
+ continue;
+
+ /* Record data used to create MMU translation tables */
+ ram_bank_count++;
+ /* Index below is deliberately 1-based to skip MMIO entry */
+ tegra_mem_map[ram_bank_count].virt = bank_start;
+ tegra_mem_map[ram_bank_count].phys = bank_start;
+ tegra_mem_map[ram_bank_count].size = bank_size;
+ tegra_mem_map[ram_bank_count].attrs =
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE;
+
+ /* Determine best bank to relocate U-Boot into */
+ if (bank_end > SZ_4G)
+ bank_end = SZ_4G;
+ debug(" end %llx (usable)\n", bank_end);
+ usable_bank_size = bank_end - bank_start;
+ debug(" size %llx (usable)\n", usable_bank_size);
+ if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) &&
+ (bank_end > ram_top)) {
+ ram_top = bank_end;
+ region_base = bank_start;
+ debug("ram top now %llx\n", ram_top);
+ }
+ }
+
+ /* Ensure memory map contains the desired sentinel entry */
+ tegra_mem_map[ram_bank_count + 1].virt = 0;
+ tegra_mem_map[ram_bank_count + 1].phys = 0;
+ tegra_mem_map[ram_bank_count + 1].size = 0;
+ tegra_mem_map[ram_bank_count + 1].attrs = 0;
+
+ /* Error out if a relocation target couldn't be found */
+ if (!ram_top) {
+ pr_err("Can't find a usable RAM top");
+ hang();
}
return 0;
}
-extern unsigned long nvtboot_boot_x0;
-
int dram_init_banksize(void)
{
int i;
- for (i = 0; i < 2; i++) {
- gd->bd->bi_dram[i].start = ram_banks[i].start;
- gd->bd->bi_dram[i].size = ram_banks[i].size;
+ if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) {
+ pr_err("Reservations exceed chosen region size");
+ hang();
+ }
+
+ for (i = 0; i < ram_bank_count; i++) {
+ gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
+ gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
}
+#ifdef CONFIG_PCI
+ gd->pci_ram_top = ram_top;
+#endif
+
return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
{
- return ram_banks[0].start + ram_banks[0].size;
+ return ram_top;
}
config SYS_SOC
default "tegra210"
+config SYS_INIT_SP_BSS_OFFSET
+ default 524288
+
source "board/nvidia/e2220-1170/Kconfig"
source "board/nvidia/p2371-0000/Kconfig"
source "board/nvidia/p2371-2180/Kconfig"
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
return 0;
}
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf1[32], buf2[32];
strmhz(buf2, gd->bus_clk));
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
#endif /* #ifdef CONFIG_M5208 */
#ifdef CONFIG_M5271
+#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
* determine which one we are running on, based on the Chip Identification
* Register (CIR).
*/
-int checkcpu(void)
+int print_cpuinfo(void)
{
char buf[32];
unsigned short cir; /* Chip Identification Register */
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
uchar msk;
printf("Freescale MCF5272 %s\n", suf);
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf[32];
strmhz(buf, CONFIG_SYS_CLK));
return 0;
};
-
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
#endif /* #ifdef CONFIG_M5275 */
#ifdef CONFIG_M5282
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
unsigned char resetsource = MCFRESET_RSR;
(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#endif
#ifdef CONFIG_M5249
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf[32];
strmhz(buf, CONFIG_SYS_CLK));
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#endif
#ifdef CONFIG_M5253
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf[32];
}
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return 0;
}
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf[32];
strmhz(buf, CONFIG_SYS_CPU_CLK));
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
#endif
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
return 1;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
siu_t *siu = (siu_t *) MMAP_SIU;
u16 id = 0;
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_HW_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
#ifdef CONFIG_FSL_CORENET
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
+#include <fsl_qbman.h>
#endif
#include <fsl_usb.h>
#include <hwconfig.h>
#ifdef CONFIG_FSL_CORENET
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
+ setup_qbman_portals();
#endif
#endif
#include <asm/io.h>
#include <asm/fsl_fdt.h>
#include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
#include <hwconfig.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
-#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
-#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
-static void inhibit_portals(void __iomem *addr, int max_portals,
- int arch_max_portals, int portal_cinh_size)
-{
- uint32_t val;
- int i;
-
- /* arch_max_portals is the maximum based on memory size. This includes
- * the reserved memory in the SoC. max_portals the number of physical
- * portals in the SoC */
- if (max_portals > arch_max_portals) {
- printf("ERROR: portal config error\n");
- max_portals = arch_max_portals;
- }
-
- for (i = 0; i < max_portals; i++) {
- out_be32(addr, -1);
- val = in_be32(addr);
- if (!val) {
- printf("ERROR: Stopped after %d portals\n", i);
- goto done;
- }
- addr += portal_cinh_size;
- }
-#ifdef DEBUG
- printf("Cleared %d portals\n", i);
-#endif
-done:
-
- return;
-}
-
-void setup_portals(void)
-{
- ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
- void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
- CONFIG_SYS_BMAN_SWP_ISDR_REG;
- void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
- CONFIG_SYS_QMAN_SWP_ISDR_REG;
-#ifdef CONFIG_FSL_CORENET
- int i;
-
- for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
- u8 sdest = qp_info[i].sdest;
- u16 fliodn = qp_info[i].fliodn;
- u16 dliodn = qp_info[i].dliodn;
- u16 liodn_off = qp_info[i].liodn_offset;
-
- out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
- dliodn);
- /* set frame liodn */
- out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
- }
-#endif
-
- /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
-#ifdef CONFIG_PHYS_64BIT
- out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
-#endif
- out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-
- /* Change default state of BMan ISDR portals to all 1s */
- inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
- CONFIG_SYS_BMAN_SP_CINH_SIZE);
- inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
- CONFIG_SYS_QMAN_SP_CINH_SIZE);
-}
-
/* Update portal containter to match LAW setup of portal in phy map */
void fdt_portal(void *blob, const char *compat, const char *container,
u64 addr, u32 size)
printf("ERROR: %s isn't in a container. Not supported\n", compat);
}
-
-static int fdt_qportal(void *blob, int off, int id, char *name,
- enum fsl_dpaa_dev dev, int create)
-{
- int childoff, dev_off, ret = 0;
- uint32_t dev_handle;
-#ifdef CONFIG_FSL_CORENET
- int num;
- u32 liodns[2];
-#endif
-
- childoff = fdt_subnode_offset(blob, off, name);
- if (create) {
- char handle[64], *p;
-
- strncpy(handle, name, sizeof(handle));
- p = strchr(handle, '@');
- if (!strncmp(name, "fman", 4)) {
- *p = *(p + 1);
- p++;
- }
- *p = '\0';
-
- dev_off = fdt_path_offset(blob, handle);
- /* skip this node if alias is not found */
- if (dev_off == -FDT_ERR_BADPATH)
- return 0;
- if (dev_off < 0)
- return dev_off;
-
- if (childoff <= 0)
- childoff = fdt_add_subnode(blob, off, name);
-
- /* need to update the dev_off after adding a subnode */
- dev_off = fdt_path_offset(blob, handle);
- if (dev_off < 0)
- return dev_off;
-
- if (childoff > 0) {
- dev_handle = fdt_get_phandle(blob, dev_off);
- if (dev_handle <= 0) {
- dev_handle = fdt_alloc_phandle(blob);
- ret = fdt_set_phandle(blob, dev_off,
- dev_handle);
- if (ret < 0)
- return ret;
- }
-
- ret = fdt_setprop(blob, childoff, "dev-handle",
- &dev_handle, sizeof(dev_handle));
- if (ret < 0)
- return ret;
-
-#ifdef CONFIG_FSL_CORENET
- num = get_dpaa_liodn(dev, &liodns[0], id);
- ret = fdt_setprop(blob, childoff, "fsl,liodn",
- &liodns[0], sizeof(u32) * num);
- if (!strncmp(name, "pme", 3)) {
- u32 pme_rev1, pme_rev2;
- ccsr_pme_t *pme_regs =
- (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
-
- pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
- pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
- ret = fdt_setprop(blob, childoff,
- "fsl,pme-rev1", &pme_rev1, sizeof(u32));
- if (ret < 0)
- return ret;
- ret = fdt_setprop(blob, childoff,
- "fsl,pme-rev2", &pme_rev2, sizeof(u32));
- }
-#endif
- } else {
- return childoff;
- }
- } else {
- if (childoff > 0)
- ret = fdt_del_node(blob, childoff);
- }
-
- return ret;
-}
-
-void fdt_fixup_qportals(void *blob)
-{
- int off, err;
- unsigned int maj, min;
- unsigned int ip_cfg;
- ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
- u32 rev_1 = in_be32(&qman->ip_rev_1);
- u32 rev_2 = in_be32(&qman->ip_rev_2);
- char compat[64];
- int compat_len;
-
- maj = (rev_1 >> 8) & 0xff;
- min = rev_1 & 0xff;
- ip_cfg = rev_2 & 0xff;
-
- compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
- maj, min, ip_cfg) + 1;
- compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
-
- off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
- while (off != -FDT_ERR_NOTFOUND) {
-#ifdef CONFIG_FSL_CORENET
- u32 liodns[2];
-#endif
- const int *ci = fdt_getprop(blob, off, "cell-index", &err);
- int i;
-
- if (!ci)
- goto err;
-
- i = *ci;
-#ifdef CONFIG_SYS_DPAA_FMAN
- int j;
-#endif
-
- err = fdt_setprop(blob, off, "compatible", compat, compat_len);
- if (err < 0)
- goto err;
-
-#ifdef CONFIG_FSL_CORENET
- liodns[0] = qp_info[i].dliodn;
- liodns[1] = qp_info[i].fliodn;
-
- err = fdt_setprop(blob, off, "fsl,liodn",
- &liodns, sizeof(u32) * 2);
- if (err < 0)
- goto err;
-#endif
-
- i++;
-
- err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
- IS_E_PROCESSOR(get_svr()));
- if (err < 0)
- goto err;
-
-#ifdef CONFIG_FSL_CORENET
-#ifdef CONFIG_SYS_DPAA_PME
- err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
- if (err < 0)
- goto err;
-#else
- fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
-#endif
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
- char name[] = "fman@0";
-
- name[sizeof(name) - 2] = '0' + j;
- err = fdt_qportal(blob, off, i, name,
- FSL_HW_PORTAL_FMAN1 + j, 1);
- if (err < 0)
- goto err;
- }
-#endif
-#ifdef CONFIG_SYS_DPAA_RMAN
- err = fdt_qportal(blob, off, i, "rman@0",
- FSL_HW_PORTAL_RMAN, 1);
- if (err < 0)
- goto err;
-#endif
-
-err:
- if (err < 0) {
- printf("ERROR: unable to create props for %s: %s\n",
- fdt_get_name(blob, off, NULL), fdt_strerror(err));
- return;
- }
-
- off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal");
- }
-}
-
-void fdt_fixup_bportals(void *blob)
-{
- int off, err;
- unsigned int maj, min;
- unsigned int ip_cfg;
- ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
- u32 rev_1 = in_be32(&bman->ip_rev_1);
- u32 rev_2 = in_be32(&bman->ip_rev_2);
- char compat[64];
- int compat_len;
-
- maj = (rev_1 >> 8) & 0xff;
- min = rev_1 & 0xff;
-
- ip_cfg = rev_2 & 0xff;
-
- compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
- maj, min, ip_cfg) + 1;
- compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
-
- off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
- while (off != -FDT_ERR_NOTFOUND) {
- err = fdt_setprop(blob, off, "compatible", compat, compat_len);
- if (err < 0) {
- printf("ERROR: unable to create props for %s: %s\n",
- fdt_get_name(blob, off, NULL),
- fdt_strerror(err));
- return;
- }
-
- off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal");
- }
-
-}
#define _FSL_LIODN_H_
#include <asm/types.h>
+#include <fsl_qbman.h>
struct srio_liodn_id_table {
u32 id[2];
CONFIG_SYS_MPC85xx_TDM_OFFSET)
#define SET_QMAN_LIODN(liodn) \
- SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
+ SET_LIODN_ENTRY_1("fsl,qman", liodn, \
+ offsetof(struct ccsr_qman, liodnr) + \
CONFIG_SYS_FSL_QMAN_OFFSET, \
CONFIG_SYS_FSL_QMAN_OFFSET)
#define SET_BMAN_LIODN(liodn) \
- SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
+ SET_LIODN_ENTRY_1("fsl,bman", liodn, \
+ offsetof(struct ccsr_bman, liodnr) + \
CONFIG_SYS_FSL_BMAN_OFFSET, \
CONFIG_SYS_FSL_BMAN_OFFSET)
extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
u32 *liodns, int liodn_offset);
-extern void setup_portals(void);
-extern void fdt_fixup_qportals(void *blob);
-extern void fdt_fixup_bportals(void *blob);
-
extern struct qportal_info qp_info[];
extern void fdt_portal(void *blob, const char *compat, const char *container,
u64 addr, u32 size);
FSL_SRDS_B3_LANE_D = 23,
};
-typedef struct ccsr_qman {
-#ifdef CONFIG_SYS_FSL_QMAN_V3
- u8 res0[0x200];
-#else
- struct {
- u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
- u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
- u32 res;
- u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
- } qcsp[32];
-#endif
- /* Not actually reserved, but irrelevant to u-boot */
- u8 res[0xbf8 - 0x200];
- u32 ip_rev_1;
- u32 ip_rev_2;
- u32 fqd_bare; /* FQD Extended Base Addr Register */
- u32 fqd_bar; /* FQD Base Addr Register */
- u8 res1[0x8];
- u32 fqd_ar; /* FQD Attributes Register */
- u8 res2[0xc];
- u32 pfdr_bare; /* PFDR Extended Base Addr Register */
- u32 pfdr_bar; /* PFDR Base Addr Register */
- u8 res3[0x8];
- u32 pfdr_ar; /* PFDR Attributes Register */
- u8 res4[0x4c];
- u32 qcsp_bare; /* QCSP Extended Base Addr Register */
- u32 qcsp_bar; /* QCSP Base Addr Register */
- u8 res5[0x78];
- u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
- u32 srcidr; /* Source ID Register */
- u32 liodnr; /* LIODN Register */
- u8 res6[4];
- u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
- u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
- u8 res7[0x2e8];
-#ifdef CONFIG_SYS_FSL_QMAN_V3
- struct {
- u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
- u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
- u32 res;
- u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
- } qcsp[50];
-#endif
-} ccsr_qman_t;
-
-typedef struct ccsr_bman {
- /* Not actually reserved, but irrelevant to u-boot */
- u8 res[0xbf8];
- u32 ip_rev_1;
- u32 ip_rev_2;
- u32 fbpr_bare; /* FBPR Extended Base Addr Register */
- u32 fbpr_bar; /* FBPR Base Addr Register */
- u8 res1[0x8];
- u32 fbpr_ar; /* FBPR Attributes Register */
- u8 res2[0xf0];
- u32 srcidr; /* Source ID Register */
- u32 liodnr; /* LIODN Register */
- u8 res7[0x2f4];
-} ccsr_bman_t;
-
typedef struct ccsr_pme {
u8 res0[0x804];
u32 liodnbr; /* LIODN Base Register */
--- /dev/null
+menu "RISCV architecture"
+ depends on RISCV
+
+config SYS_ARCH
+ default "riscv"
+
+choice
+ prompt "Target select"
+ optional
+
+config TARGET_NX25_AE250
+ bool "Support nx25-ae250"
+
+endchoice
+
+source "board/AndesTech/nx25-ae250/Kconfig"
+
+choice
+ prompt "CPU selection"
+ default CPU_RISCV_32
+
+config CPU_RISCV_32
+ bool "RISCV 32 bit"
+ select 32BIT
+ help
+ Choose this option to build an U-Boot for RISCV32 architecture.
+
+config CPU_RISCV_64
+ bool "RISCV 64 bit"
+ select 64BIT
+ help
+ Choose this option to build an U-Boot for RISCV64 architecture.
+
+endchoice
+
+config 32BIT
+ bool
+
+config 64BIT
+ bool
+
+endmenu
--- /dev/null
+#
+# Copyright (C) 2017 Andes Technology Corporation.
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/riscv/cpu/$(CPU)/start.o
+
+libs-y += arch/riscv/cpu/$(CPU)/
+libs-y += arch/riscv/lib/
--- /dev/null
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (c) 2017 Microsemi Corporation.
+# Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := riscv32-unknown-linux-gnu-
+endif
+
+32bit-emul := elf32lriscv
+64bit-emul := elf64lriscv
+
+ifdef CONFIG_32BIT
+PLATFORM_LDFLAGS += -m $(32bit-emul)
+endif
+
+ifdef CONFIG_64BIT
+PLATFORM_LDFLAGS += -m $(64bit-emul)
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \
+ -T $(srctree)/examples/standalone/riscv.lds
+
+PLATFORM_CPPFLAGS += -ffixed-gp -fpic
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2
+LDFLAGS_u-boot += --gc-sections -static -pie
--- /dev/null
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+extra-y = start.o
+
+obj-y := cpu.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ /* turn off I/D-cache */
+
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+ panic("nx25-ae250 wdt not support yet.\n");
+}
--- /dev/null
+/*
+ * Startup Code for RISC-V Core
+ *
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <elf.h>
+#include <asm/encoding.h>
+
+#ifdef CONFIG_32BIT
+#define LREG lw
+#define SREG sw
+#define REGBYTES 4
+#define RELOC_TYPE R_RISCV_32
+#define SYM_INDEX 0x8
+#define SYM_SIZE 0x10
+#else
+#define LREG ld
+#define SREG sd
+#define REGBYTES 8
+#define RELOC_TYPE R_RISCV_64
+#define SYM_INDEX 0x20
+#define SYM_SIZE 0x18
+#endif
+
+.section .text
+.globl _start
+_start:
+ j handle_reset
+
+nmi_vector:
+ j nmi_vector
+
+trap_vector:
+ j trap_entry
+
+.global trap_entry
+handle_reset:
+ la t0, trap_entry
+ csrw mtvec, t0
+ csrwi mstatus, 0
+ csrwi mie, 0
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+ jal cpu_init_crit /* Do CPU critical regs init */
+#endif
+
+/*
+ * Set stackpointer in internal/ex RAM to call board_init_f
+ */
+call_board_init_f:
+ li t0, -16
+ li t1, CONFIG_SYS_INIT_SP_ADDR
+ and sp, t1, t0 /* force 16 byte alignment */
+
+#ifdef CONFIG_DEBUG_UART
+ jal debug_uart_init
+#endif
+
+call_board_init_f_0:
+ mv a0, sp
+ jal board_init_f_alloc_reserve
+ mv sp, a0
+ jal board_init_f_init_reserve
+
+ mv a0, zero /* a0 <-- boot_flags = 0 */
+ la t5, board_init_f
+ jr t5 /* jump to board_init_f() */
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl relocate_code
+relocate_code:
+ mv s2, a0 /* save addr_sp */
+ mv s3, a1 /* save addr of gd */
+ mv s4, a2 /* save addr of destination */
+
+/*
+ *Set up the stack
+ */
+stack_setup:
+ mv sp, s2
+ la t0, _start
+ sub t6, s4, t0 /* t6 <- relocation offset */
+ beq t0, s4, clear_bss /* skip relocation */
+
+ mv t1, s4 /* t1 <- scratch for copy_loop */
+ la t3, __bss_start
+ sub t3, t3, t0 /* t3 <- __bss_start_ofs */
+ add t2, t0, t3 /* t2 <- source end address */
+
+copy_loop:
+ LREG t5, 0(t0)
+ addi t0, t0, REGBYTES
+ SREG t5, 0(t1)
+ addi t1, t1, REGBYTES
+ blt t0, t2, copy_loop
+
+/*
+ * Update dynamic relocations after board_init_f
+ */
+fix_rela_dyn:
+ la t1, __rel_dyn_start
+ la t2, __rel_dyn_end
+ beq t1, t2, clear_bss
+ add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
+ add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
+
+/*
+ * skip first reserved entry: address, type, addend
+ */
+ bne t1, t2, 7f
+
+6:
+ LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
+ li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
+ bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
+ LREG t3, -(REGBYTES*3)(t1)
+ LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
+ add t5, t5, t6 /* t5 <-- location to fix up in RAM */
+ add t3, t3, t6 /* t3 <-- location to fix up in RAM */
+ SREG t5, 0(t3)
+7:
+ addi t1, t1, (REGBYTES*3)
+ ble t1, t2, 6b
+
+8:
+ la t4, __dyn_sym_start
+ add t4, t4, t6
+
+9:
+ LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
+ srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
+ andi t5, t5, 0xFF /* t5 <--- relocation type */
+ li t3, RELOC_TYPE
+ bne t5, t3, 10f /* skip non-addned entries */
+
+ LREG t3, -(REGBYTES*3)(t1)
+ li t5, SYM_SIZE
+ mul t0, t0, t5
+ add s1, t4, t0
+ LREG t5, REGBYTES(s1)
+ add t5, t5, t6 /* t5 <-- location to fix up in RAM */
+ add t3, t3, t6 /* t3 <-- location to fix up in RAM */
+ SREG t5, 0(t3)
+10:
+ addi t1, t1, (REGBYTES*3)
+ ble t1, t2, 9b
+
+/*
+ * trap update
+*/
+ la t0, trap_entry
+ add t0, t0, t6
+ csrw mtvec, t0
+
+clear_bss:
+ la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
+ add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
+ la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
+ add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
+ li t2, 0x00000000 /* clear */
+ beq t0, t1, call_board_init_r
+
+clbss_l:
+ SREG t2, 0(t0) /* clear loop... */
+ addi t0, t0, REGBYTES
+ bne t0, t1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+ la t0, board_init_r
+ mv t4, t0 /* offset of board_init_r() */
+ add t4, t4, t6 /* real address of board_init_r() */
+/*
+ * setup parameters for board_init_r
+ */
+ mv a0, s3 /* gd_t */
+ mv a1, s4 /* dest_addr */
+
+/*
+ * jump to it ...
+ */
+ jr t4 /* jump to board_init_r() */
+
+/*
+ * trap entry
+ */
+trap_entry:
+ addi sp, sp, -32*REGBYTES
+ SREG x1, 1*REGBYTES(sp)
+ SREG x2, 2*REGBYTES(sp)
+ SREG x3, 3*REGBYTES(sp)
+ SREG x4, 4*REGBYTES(sp)
+ SREG x5, 5*REGBYTES(sp)
+ SREG x6, 6*REGBYTES(sp)
+ SREG x7, 7*REGBYTES(sp)
+ SREG x8, 8*REGBYTES(sp)
+ SREG x9, 9*REGBYTES(sp)
+ SREG x10, 10*REGBYTES(sp)
+ SREG x11, 11*REGBYTES(sp)
+ SREG x12, 12*REGBYTES(sp)
+ SREG x13, 13*REGBYTES(sp)
+ SREG x14, 14*REGBYTES(sp)
+ SREG x15, 15*REGBYTES(sp)
+ SREG x16, 16*REGBYTES(sp)
+ SREG x17, 17*REGBYTES(sp)
+ SREG x18, 18*REGBYTES(sp)
+ SREG x19, 19*REGBYTES(sp)
+ SREG x20, 20*REGBYTES(sp)
+ SREG x21, 21*REGBYTES(sp)
+ SREG x22, 22*REGBYTES(sp)
+ SREG x23, 23*REGBYTES(sp)
+ SREG x24, 24*REGBYTES(sp)
+ SREG x25, 25*REGBYTES(sp)
+ SREG x26, 26*REGBYTES(sp)
+ SREG x27, 27*REGBYTES(sp)
+ SREG x28, 28*REGBYTES(sp)
+ SREG x29, 29*REGBYTES(sp)
+ SREG x30, 30*REGBYTES(sp)
+ SREG x31, 31*REGBYTES(sp)
+ csrr a0, mcause
+ csrr a1, mepc
+ mv a2, sp
+ jal handle_trap
+ csrw mepc, a0
+
+/*
+ * Remain in M-mode after mret
+ */
+ li t0, MSTATUS_MPP
+ csrs mstatus, t0
+ LREG x1, 1*REGBYTES(sp)
+ LREG x2, 2*REGBYTES(sp)
+ LREG x3, 3*REGBYTES(sp)
+ LREG x4, 4*REGBYTES(sp)
+ LREG x5, 5*REGBYTES(sp)
+ LREG x6, 6*REGBYTES(sp)
+ LREG x7, 7*REGBYTES(sp)
+ LREG x8, 8*REGBYTES(sp)
+ LREG x9, 9*REGBYTES(sp)
+ LREG x10, 10*REGBYTES(sp)
+ LREG x11, 11*REGBYTES(sp)
+ LREG x12, 12*REGBYTES(sp)
+ LREG x13, 13*REGBYTES(sp)
+ LREG x14, 14*REGBYTES(sp)
+ LREG x15, 15*REGBYTES(sp)
+ LREG x16, 16*REGBYTES(sp)
+ LREG x17, 17*REGBYTES(sp)
+ LREG x18, 18*REGBYTES(sp)
+ LREG x19, 19*REGBYTES(sp)
+ LREG x20, 20*REGBYTES(sp)
+ LREG x21, 21*REGBYTES(sp)
+ LREG x22, 22*REGBYTES(sp)
+ LREG x23, 23*REGBYTES(sp)
+ LREG x24, 24*REGBYTES(sp)
+ LREG x25, 25*REGBYTES(sp)
+ LREG x26, 26*REGBYTES(sp)
+ LREG x27, 27*REGBYTES(sp)
+ LREG x28, 28*REGBYTES(sp)
+ LREG x29, 29*REGBYTES(sp)
+ LREG x30, 30*REGBYTES(sp)
+ LREG x31, 31*REGBYTES(sp)
+ addi sp, sp, 32*REGBYTES
+ mret
+
+#ifdef CONFIG_INIT_CRITICAL
+cpu_init_crit:
+ ret
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+ . = ALIGN(4);
+ .text :
+ {
+ arch/riscv/cpu/nx25/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ __global_pointer$ = . + 0x800;
+ *(.data*)
+ }
+ . = ALIGN(4);
+
+ .got : {
+ __got_start = .;
+ *(.got.plt) *(.got)
+ __got_end = .;
+ }
+
+ . = ALIGN(4);
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ /DISCARD/ : { *(.rela.plt*) }
+ .rela.dyn : {
+ __rel_dyn_start = .;
+ *(.rela*)
+ __rel_dyn_end = .;
+ }
+
+ . = ALIGN(4);
+
+ .dynsym : {
+ __dyn_sym_start = .;
+ *(.dynsym)
+ __dyn_sym_end = .;
+ }
+
+ . = ALIGN(4);
+
+ _end = .;
+
+ .bss : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
+
+}
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+dtb-$(CONFIG_TARGET_NX25_AE250) += ae250.dtb
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
--- /dev/null
+/dts-v1/;
+/ {
+ compatible = "riscv32 nx25";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ aliases {
+ uart0 = &serial0;
+ ethernet0 = &mac0;
+ spi0 = &spi;
+ } ;
+
+ chosen {
+ bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
+ stdout-path = "uart0:38400n8";
+ tick-timer = &timer0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ spiclk: virt_100mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "andestech,n13";
+ reg = <0>;
+ /* FIXME: to fill correct frqeuency */
+ clock-frequency = <60000000>;
+ };
+ };
+
+ intc: interrupt-controller {
+ compatible = "andestech,atnointc010";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ serial0: serial@f0300000 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0xf0300000 0x1000>;
+ interrupts = <7 4>;
+ clock-frequency = <19660800>;
+ reg-shift = <2>;
+ reg-offset = <32>;
+ no-loopback-test = <1>;
+ };
+
+ timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0xf0400000 0x1000>;
+ interrupts = <2 4>;
+ clock-frequency = <40000000>;
+ };
+
+ mac0: mac@e0100000 {
+ compatible = "andestech,atmac100";
+ reg = <0xe0100000 0x1000>;
+ interrupts = <25 4>;
+ };
+
+ mmc0: mmc@f0e00000 {
+ compatible = "andestech,atsdc010";
+ max-frequency = <100000000>;
+ fifo-depth = <0x10>;
+ reg = <0xf0e00000 0x1000>;
+ interrupts = <17 4>;
+ };
+
+ spi: spi@f0b00000 {
+ compatible = "andestech,atcspi200";
+ reg = <0xf0b00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ clocks = <&spiclk>;
+ interrupts = <3 4>;
+ flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
+
+};
--- /dev/null
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ * Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space. Many of these are not implemented in assembler
+ * since they would be too costly. Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_RISCV_BITOPS_H
+#define __ASM_RISCV_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+#define smp_mb__before_clear_bit() do { } while (0)
+#define smp_mb__after_clear_bit() do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+static inline void __set_bit(int nr, void *addr)
+{
+ int *a = (int *)addr;
+ int mask;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ *a |= mask;
+}
+
+static inline void __clear_bit(int nr, void *addr)
+{
+ int *a = (int *)addr;
+ int mask;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ *a &= ~mask;
+}
+
+static inline void __change_bit(int nr, void *addr)
+{
+ int mask;
+ unsigned long *ADDR = (unsigned long *)addr;
+
+ ADDR += nr >> 5;
+ mask = 1 << (nr & 31);
+ *ADDR ^= mask;
+}
+
+static inline int __test_and_set_bit(int nr, void *addr)
+{
+ int mask, retval;
+ unsigned int *a = (unsigned int *)addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a |= mask;
+ return retval;
+}
+
+static inline int __test_and_clear_bit(int nr, void *addr)
+{
+ int mask, retval;
+ unsigned int *a = (unsigned int *)addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a &= ~mask;
+ return retval;
+}
+
+static inline int __test_and_change_bit(int nr, void *addr)
+{
+ int mask, retval;
+ unsigned int *a = (unsigned int *)addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a ^= mask;
+ return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+ return ((unsigned char *)addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+ int k;
+
+ word = ~word;
+ k = 31;
+ if (word & 0x0000ffff) {
+ k -= 16; word <<= 16;
+ }
+ if (word & 0x00ff0000) {
+ k -= 8; word <<= 8;
+ }
+ if (word & 0x0f000000) {
+ k -= 4; word <<= 4;
+ }
+ if (word & 0x30000000) {
+ k -= 2; word <<= 2;
+ }
+ if (word & 0x40000000)
+ k -= 1;
+
+ return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit test_and_set_bit
+#define ext2_clear_bit test_and_clear_bit
+#define ext2_test_bit test_bit
+#define ext2_find_first_zero_bit find_first_zero_bit
+#define ext2_find_next_zero_bit find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr) test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr) set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr) test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size) find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_RISCV_BITOPS_H */
--- /dev/null
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef NDS32_BOOTM_H
+#define NDS32_BOOTM_H
+
+#include <asm/setup.h>
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+# define BOOTM_ENABLE_TAGS 1
+#else
+# define BOOTM_ENABLE_TAGS 0
+#endif
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+# define BOOTM_ENABLE_MEMORY_TAGS 1
+#else
+# define BOOTM_ENABLE_MEMORY_TAGS 0
+#endif
+
+#ifdef CONFIG_CMDLINE_TAG
+ #define BOOTM_ENABLE_CMDLINE_TAG 1
+#else
+ #define BOOTM_ENABLE_CMDLINE_TAG 0
+#endif
+
+#ifdef CONFIG_INITRD_TAG
+ #define BOOTM_ENABLE_INITRD_TAG 1
+#else
+ #define BOOTM_ENABLE_INITRD_TAG 0
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+ #define BOOTM_ENABLE_SERIAL_TAG 1
+void get_board_serial(struct tag_serialnr *serialnr);
+#else
+ #define BOOTM_ENABLE_SERIAL_TAG 0
+static inline void get_board_serial(struct tag_serialnr *serialnr)
+{
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+ #define BOOTM_ENABLE_REVISION_TAG 1
+u32 get_board_rev(void);
+#else
+ #define BOOTM_ENABLE_REVISION_TAG 0
+static inline u32 get_board_rev(void)
+{
+ return 0;
+}
+#endif
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * ARM Endian-ness. In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ * d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ * d0...d31
+ */
+
+#ifndef __ASM_RISCV_BYTEORDER_H
+#define __ASM_RISCV_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __RISCVEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_RISCV_CACHE_H
+#define _ASM_RISCV_CACHE_H
+
+/*
+ * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 32
+#endif
+
+#endif /* _ASM_RISCV_CACHE_H */
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_LMB
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE 0x00000001
+#define MSTATUS_SIE 0x00000002
+#define MSTATUS_HIE 0x00000004
+#define MSTATUS_MIE 0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP 0x00000100
+#define MSTATUS_HPP 0x00000600
+#define MSTATUS_MPP 0x00001800
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_XS 0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_PUM 0x00040000
+#define MSTATUS_VM 0x1F000000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS64_SD 0x8000000000000000
+
+#define MCAUSE32_CAUSE 0x7FFFFFFF
+#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
+#define MCAUSE32_INT 0x80000000
+#define MCAUSE64_INT 0x8000000000000000
+
+#define SSTATUS_UIE 0x00000001
+#define SSTATUS_SIE 0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP 0x00000100
+#define SSTATUS_FS 0x00006000
+#define SSTATUS_XS 0x00018000
+#define SSTATUS_PUM 0x00040000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define MIP_SSIP BIT(IRQ_S_SOFT)
+#define MIP_HSIP BIT(IRQ_H_SOFT)
+#define MIP_MSIP BIT(IRQ_M_SOFT)
+#define MIP_STIP BIT(IRQ_S_TIMER)
+#define MIP_HTIP BIT(IRQ_H_TIMER)
+#define MIP_MTIP BIT(IRQ_M_TIMER)
+#define MIP_SEIP BIT(IRQ_S_EXT)
+#define MIP_HEIP BIT(IRQ_H_EXT)
+#define MIP_MEIP BIT(IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB 1
+#define VM_MBBID 2
+#define VM_SV32 8
+#define VM_SV39 9
+#define VM_SV48 10
+
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_COP 12
+#define IRQ_HOST 13
+
+#define DEFAULT_RSTVEC 0x00001000
+#define DEFAULT_NMIVEC 0x00001004
+#define DEFAULT_MTVEC 0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Valid
+#define PTE_TYPE 0x01E // Type
+#define PTE_R 0x020 // Referenced
+#define PTE_D 0x040 // Dirty
+#define PTE_SOFT 0x380 // Reserved for Software
+
+#define PTE_TYPE_TABLE 0x00
+#define PTE_TYPE_TABLE_GLOBAL 0x02
+#define PTE_TYPE_URX_SR 0x04
+#define PTE_TYPE_URWX_SRW 0x06
+#define PTE_TYPE_UR_SR 0x08
+#define PTE_TYPE_URW_SRW 0x0A
+#define PTE_TYPE_URX_SRX 0x0C
+#define PTE_TYPE_URWX_SRWX0x0E
+#define PTE_TYPE_SR 0x10
+#define PTE_TYPE_SRW 0x12
+#define PTE_TYPE_SRX 0x14
+#define PTE_TYPE_SRWX 0x16
+#define PTE_TYPE_SR_GLOBAL 0x18
+#define PTE_TYPE_SRW_GLOBAL 0x1A
+#define PTE_TYPE_SRX_GLOBAL 0x1C
+#define PTE_TYPE_SRWX_GLOBAL 0x1E
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
+#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
+
+#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
+ ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
+ (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
+ ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
+
+#ifdef __riscv
+#ifdef CONFIG_64BIT
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define MCAUSE_INT MCAUSE64_INT
+# define MCAUSE_CAUSE MCAUSE64_CAUSE
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define MCAUSE_INT MCAUSE32_INT
+# define MCAUSE_CAUSE MCAUSE32_CAUSE
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_csr(reg, val) ({ \
+if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+else \
+ asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+else \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+ __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+else \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+else \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+#endif
+#endif
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("gp")
+
+#endif /* __ASM_GBL_DATA_H */
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+#ifndef __ASM_RISCV_IO_H
+#define __ASM_RISCV_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+#ifdef CONFIG_ARCH_MAP_SYSMEM
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)
+ paddr = paddr | 0x40000000;
+ return (void *)(uintptr_t)paddr;
+}
+
+static inline void *unmap_sysmem(const void *vaddr)
+{
+ phys_addr_t paddr = (phys_addr_t)vaddr;
+
+ paddr = paddr & ~0x40000000;
+ return (void *)(uintptr_t)paddr;
+}
+
+static inline phys_addr_t map_to_sysmem(const void *ptr)
+{
+ return (phys_addr_t)(uintptr_t)ptr;
+}
+#endif
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+ return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write. Note that we don't support half-word
+ * read/writes. We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a) (*(unsigned char *)(a))
+#define __arch_getw(a) (*(unsigned short *)(a))
+#define __arch_getl(a) (*(unsigned int *)(a))
+#define __arch_getq(a) (*(unsigned long *)(a))
+
+#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
+#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
+#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
+#define __arch_putq(v, a) (*(unsigned long *)(a) = (v))
+
+#define __raw_writeb(v, a) __arch_putb(v, a)
+#define __raw_writew(v, a) __arch_putw(v, a)
+#define __raw_writel(v, a) __arch_putl(v, a)
+#define __raw_writeq(v, a) __arch_putq(v, a)
+
+#define __raw_readb(a) __arch_getb(a)
+#define __raw_readw(a) __arch_getw(a)
+#define __raw_readl(a) __arch_getl(a)
+#define __raw_readq(a) __arch_getq(a)
+
+/*
+ * TODO: The kernel offers some more advanced versions of barriers, it might
+ * have some advantages to use them instead of the simple one here.
+ */
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#define __iormb() dmb()
+#define __iowmb() dmb()
+
+static inline void writeb(u8 val, volatile void __iomem *addr)
+{
+ __iowmb();
+ __arch_putb(val, addr);
+}
+
+static inline void writew(u16 val, volatile void __iomem *addr)
+{
+ __iowmb();
+ __arch_putw(val, addr);
+}
+
+static inline void writel(u32 val, volatile void __iomem *addr)
+{
+ __iowmb();
+ __arch_putl(val, addr);
+}
+
+static inline void writeq(u64 val, volatile void __iomem *addr)
+{
+ __iowmb();
+ __arch_putq(val, addr);
+}
+
+static inline u8 readb(const volatile void __iomem *addr)
+{
+ u8 val;
+
+ val = __arch_getb(addr);
+ __iormb();
+ return val;
+}
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+ u16 val;
+
+ val = __arch_getw(addr);
+ __iormb();
+ return val;
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+ u32 val;
+
+ val = __arch_getl(addr);
+ __iormb();
+ return val;
+}
+
+static inline u64 readq(const volatile void __iomem *addr)
+{
+ u32 val;
+
+ val = __arch_getq(addr);
+ __iormb();
+ return val;
+}
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly. Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off) __arch_base_getb(base, off)
+#define __raw_base_readw(base, off) __arch_base_getw(base, off)
+#define __raw_base_readl(base, off) __arch_base_getl(base, off)
+
+#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v) out_arch(l, le32, a, v)
+#define out_le16(a, v) out_arch(w, le16, a, v)
+
+#define in_le32(a) in_arch(l, le32, a)
+#define in_le16(a) in_arch(w, le16, a)
+
+#define out_be32(a, v) out_arch(l, be32, a, v)
+#define out_be16(a, v) out_arch(w, be16, a, v)
+
+#define in_be32(a) in_arch(l, be32, a)
+#define in_be16(a) in_arch(w, be16, a)
+
+#define out_8(a, v) __raw_writeb(v, a)
+#define in_8(a) __raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+ out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+ out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+ out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ * IO port access primitives
+ * -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only. Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ * PCI: D0-D7 D8-D15 D16-D23 D24-D31
+ * ARM: D24-D31 D16-D23 D8-D15 D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions. Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p) __raw_writeb(v, __io(p))
+#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l) writesb(__io(p), d, l)
+#define outsw(p, d, l) writesw(__io(p), d, l)
+#define outsl(p, d, l) writesl(__io(p), d, l)
+
+#define insb(p, d, l) readsb(__io(p), d, l)
+#define insw(p, d, l) readsw(__io(p), d, l)
+#define insl(p, d, l) readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void *data, int bytelen)
+{
+ unsigned char *ptr;
+ unsigned char *ptr2;
+
+ ptr = (unsigned char *)addr;
+ ptr2 = (unsigned char *)data;
+
+ while (bytelen) {
+ *ptr2 = *ptr;
+ ptr2++;
+ bytelen--;
+ }
+}
+
+static inline void readsw(unsigned int *addr, void *data, int wordlen)
+{
+ unsigned short *ptr;
+ unsigned short *ptr2;
+
+ ptr = (unsigned short *)addr;
+ ptr2 = (unsigned short *)data;
+
+ while (wordlen) {
+ *ptr2 = *ptr;
+ ptr2++;
+ wordlen--;
+ }
+}
+
+static inline void readsl(unsigned int *addr, void *data, int longlen)
+{
+ unsigned int *ptr;
+ unsigned int *ptr2;
+
+ ptr = (unsigned int *)addr;
+ ptr2 = (unsigned int *)data;
+
+ while (longlen) {
+ *ptr2 = *ptr;
+ ptr2++;
+ longlen--;
+ }
+}
+
+static inline void writesb(unsigned int *addr, const void *data, int bytelen)
+{
+ unsigned char *ptr;
+ unsigned char *ptr2;
+
+ ptr = (unsigned char *)addr;
+ ptr2 = (unsigned char *)data;
+
+ while (bytelen) {
+ *ptr = *ptr2;
+ ptr2++;
+ bytelen--;
+ }
+}
+
+static inline void writesw(unsigned int *addr, const void *data, int wordlen)
+{
+ unsigned short *ptr;
+ unsigned short *ptr2;
+
+ ptr = (unsigned short *)addr;
+ ptr2 = (unsigned short *)data;
+
+ while (wordlen) {
+ *ptr = *ptr2;
+ ptr2++;
+ wordlen--;
+ }
+}
+
+static inline void writesl(unsigned int *addr, const void *data, int longlen)
+{
+ unsigned int *ptr;
+ unsigned int *ptr2;
+
+ ptr = (unsigned int *)addr;
+ ptr2 = (unsigned int *)data;
+
+ while (longlen) {
+ *ptr = *ptr2;
+ ptr2++;
+ longlen--;
+ }
+}
+#endif
+
+#define outb_p(val, port) outb((val), (port))
+#define outw_p(val, port) outw((val), (port))
+#define outl_p(val, port) outl((val), (port))
+#define inb_p(port) inb((port))
+#define inw_p(port) inw((port))
+#define inl_p(port) inl((port))
+
+#define outsb_p(port, from, len) outsb(port, from, len)
+#define outsw_p(port, from, len) outsw(port, from, len)
+#define outsl_p(port, from, len) outsl(port, from, len)
+#define insb_p(port, to, len) insb(port, to, len)
+#define insw_p(port, to, len) insw(port, to, len)
+#define insl_p(port, to, len) insl(port, to, len)
+
+/*
+ * DMA-consistent mapping functions. These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices. This is the "generic" version. The PCI specific version
+ * is in pci.h
+ */
+
+/*
+ * String version of IO memory access ops:
+ */
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros. These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = \
+ __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = \
+ le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = \
+ le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
+#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+ eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+ int length)
+{
+ int retval = 0;
+
+ do {
+ if (readb(io_addr) != *signature)
+ goto out;
+ io_addr++;
+ signature++;
+ length--;
+ } while (length);
+ retval = 1;
+out:
+ return retval;
+}
+#endif /* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr) __raw_readb(__mem_isa(addr))
+#define isa_readw(addr) __raw_readw(__mem_isa(addr))
+#define isa_readl(addr) __raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+ eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+ int length)
+{
+ int retval = 0;
+
+ do {
+ if (isa_readb(io_addr) != *signature)
+ goto out;
+ io_addr++;
+ signature++;
+ length--;
+ } while (length);
+ retval = 1;
+out:
+ return retval;
+}
+
+#else /* __mem_isa */
+
+#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr) __readwrite_bug("isa_writeb")
+#define isa_writew(val, addr) __readwrite_bug("isa_writew")
+#define isa_writel(val, addr) __readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+ __readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len) (0)
+
+#endif /* __mem_isa */
+#endif /* __KERNEL__ */
+#endif /* __ASM_RISCV_IO_H */
--- /dev/null
+/*
+ * U-Boot - linkage.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_RISCV_MACH_TYPE_H
+#define __ASM_RISCV_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+#define MACH_TYPE_AE250 1
+
+#ifdef CONFIG_ARCH_AE250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AE250
+# endif
+# define machine_is_ae250() (machine_arch_type == MACH_TYPE_AE250)
+#else
+# define machine_is_ae250() (1)
+#endif
+
+#endif /* __ASM_RISCV_MACH_TYPE_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ * 27-06-1996 RMK Created
+ * 25-10-2017 Modified for arch RISCV
+ */
+#ifndef __ARCH_RISCV_POSIX_TYPES_H
+#define __ARCH_RISCV_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+#ifdef __GNUC__
+typedef __SIZE_TYPE__ __kernel_size_t;
+#else
+typedef unsigned int __kernel_size_t;
+#endif
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_daddr_t;
+typedef char *__kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+ int val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+ int __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+#define __FD_SET(fd, fdsetp) \
+ (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1 << (fd & 31)))
+
+#undef __FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+ (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1 << (fd & 31)))
+
+#undef __FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+ ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1 << (fd & 31))) != 0)
+
+#undef __FD_ZERO
+#define __FD_ZERO(fdsetp) \
+ (memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif
+
+#endif /* __ARCH_RISCV_POSIX_TYPES_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_RISCV_PROCESSOR_H
+#define __ASM_RISCV_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ * - do not implement for RISCV Arch yet.
+ * - so far some files include /asm/processor.h, but
+ * no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_RISCV_PROCESSOR_H */
--- /dev/null
+/*
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_RISCV_PTRACE_H
+#define __ASM_RISCV_PTRACE_H
+
+struct pt_regs {
+ unsigned long sepc;
+ unsigned long ra;
+ unsigned long sp;
+ unsigned long gp;
+ unsigned long tp;
+ unsigned long t0;
+ unsigned long t1;
+ unsigned long t2;
+ unsigned long s0;
+ unsigned long s1;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long a4;
+ unsigned long a5;
+ unsigned long a6;
+ unsigned long a7;
+ unsigned long s2;
+ unsigned long s3;
+ unsigned long s4;
+ unsigned long s5;
+ unsigned long s6;
+ unsigned long s7;
+ unsigned long s8;
+ unsigned long s9;
+ unsigned long s10;
+ unsigned long s11;
+ unsigned long t3;
+ unsigned long t4;
+ unsigned long t5;
+ unsigned long t6;
+ /* Supervisor CSRs */
+ unsigned long sstatus;
+ unsigned long sbadaddr;
+ unsigned long scause;
+};
+
+#ifdef CONFIG_64BIT
+#define REG_FMT "%016lx"
+#else
+#define REG_FMT "%08lx"
+#endif
+
+#define user_mode(regs) (((regs)->sstatus & SR_PS) == 0)
+
+/* Helpers for working with the instruction pointer */
+#define GET_IP(regs) ((regs)->sepc)
+#define SET_IP(regs, val) (GET_IP(regs) = (val))
+
+static inline unsigned long instruction_pointer(struct pt_regs *regs)
+{
+ return GET_IP(regs);
+}
+
+static inline void instruction_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ SET_IP(regs, val);
+}
+
+#define profile_pc(regs) instruction_pointer(regs)
+
+/* Helpers for working with the user stack pointer */
+#define GET_USP(regs) ((regs)->sp)
+#define SET_USP(regs, val) (GET_USP(regs) = (val))
+
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+ return GET_USP(regs);
+}
+
+static inline void user_stack_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ SET_USP(regs, val);
+}
+
+/* Helpers for working with the frame pointer */
+#define GET_FP(regs) ((regs)->s0)
+#define SET_FP(regs, val) (GET_FP(regs) = (val))
+
+static inline unsigned long frame_pointer(struct pt_regs *regs)
+{
+ return GET_FP(regs);
+}
+
+static inline void frame_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ SET_FP(regs, val);
+}
+
+#endif /* __ASM_RISCV_PTRACE_H */
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_RISCV_SECTIONS_H
+#define __ASM_RISCV_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
--- /dev/null
+/*
+ * linux/arch/nds32/include/asm/setup.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ * Copyright (C) 2008 Andes Technology Corporation
+ * Copyright (C) 2013 Ken Kuo (ken_kuo@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Structure passed to kernel to tell it about the
+ * hardware it's running on. See Documentation/arm/Setup
+ * for more info.
+ */
+#ifndef __RISCV_SETUP_H
+#define __RISCV_SETUP_H
+
+#define COMMAND_LINE_SIZE 256
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE 0x00000000
+
+struct tag_header {
+ u32 size;
+ u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE 0x54410001
+
+struct tag_core {
+ u32 flags; /* bit 0 = read-only */
+ u32 pagesize;
+ u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM 0x54410002
+
+struct tag_mem32 {
+ u32 size;
+ u32 start; /* physical start address */
+};
+
+/* VGA text type displays */
+#define ATAG_VIDEOTEXT 0x54410003
+
+struct tag_videotext {
+ u8 x;
+ u8 y;
+ u16 video_page;
+ u8 video_mode;
+ u8 video_cols;
+ u16 video_ega_bx;
+ u8 video_lines;
+ u8 video_isvga;
+ u16 video_points;
+};
+
+/* describes how the ramdisk will be used in kernel */
+#define ATAG_RAMDISK 0x54410004
+
+struct tag_ramdisk {
+ u32 flags; /* bit 0 = load, bit 1 = prompt */
+ u32 size; /* decompressed ramdisk size in _kilo_ bytes */
+ u32 start; /* starting block of floppy-based RAM disk image */
+};
+
+/*
+ * this one accidentally used virtual addresses - as such,
+ * it's deprecated.
+ * describes where the compressed ramdisk image lives (virtual address)
+ */
+#define ATAG_INITRD 0x54410005
+
+/* describes where the compressed ramdisk image lives (physical address) */
+#define ATAG_INITRD2 0x54420005
+
+struct tag_initrd {
+ u32 start; /* physical start address */
+ u32 size; /* size of compressed ramdisk image in bytes */
+};
+
+/* board serial number. "64 bits should be enough for everybody" */
+#define ATAG_SERIAL 0x54410006
+
+struct tag_serialnr {
+ u32 low;
+ u32 high;
+};
+
+/* board revision */
+#define ATAG_REVISION 0x54410007
+
+struct tag_revision {
+ u32 rev;
+};
+
+/* initial values for vesafb-type framebuffers. see struct screen_info
+ * in include/linux/tty.h
+ */
+#define ATAG_VIDEOLFB 0x54410008
+
+struct tag_videolfb {
+ u16 lfb_width;
+ u16 lfb_height;
+ u16 lfb_depth;
+ u16 lfb_linelength;
+ u32 lfb_base;
+ u32 lfb_size;
+ u8 red_size;
+ u8 red_pos;
+ u8 green_size;
+ u8 green_pos;
+ u8 blue_size;
+ u8 blue_pos;
+ u8 rsvd_size;
+ u8 rsvd_pos;
+};
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE 0x54410009
+
+struct tag_cmdline {
+ char cmdline[COMMAND_LINE_SIZE];
+};
+
+struct tag {
+ struct tag_header hdr;
+ union {
+ struct tag_core core;
+ struct tag_mem32 mem;
+ struct tag_videotext videotext;
+ struct tag_ramdisk ramdisk;
+ struct tag_initrd initrd;
+ struct tag_serialnr serialnr;
+ struct tag_revision revision;
+ struct tag_videolfb videolfb;
+ struct tag_cmdline cmdline;
+ } u;
+};
+
+struct tagtable {
+ u32 tag;
+ int (*parse)(const struct tag *);
+};
+
+#define tag_member_present(tag, member) \
+ ((unsigned long)(&((struct tag *)0L)->member + 1) \
+ <= (tag)->hdr.size * 4)
+
+#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t, base) \
+ for (t = base; t->hdr.size; t = tag_next(t))
+
+#ifdef __KERNEL__
+
+#define __tag __used __attribute__((__section__(".taglist")))
+#define __tagtable(tag, fn) \
+static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+/*
+ * Memory map description
+ */
+#define NR_BANKS 8
+
+struct meminfo {
+ int nr_banks;
+ struct {
+ unsigned long start;
+ unsigned long size;
+ int node;
+ } bank[NR_BANKS];
+};
+
+/*
+ * Early command line parameters.
+ */
+struct early_params {
+ const char *arg;
+ void (*fn)(char **p);
+};
+
+#define __early_param(name, fn) \
+static struct early_params __early_##fn __used \
+__attribute__((__section__("__early_param"))) = { name, fn }
+
+#endif
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_RISCV_STRING_H
+#define __ASM_RISCV_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+#undef __HAVE_ARCH_STRCHR
+#undef __HAVE_ARCH_MEMCPY
+#undef __HAVE_ARCH_MEMMOVE
+#undef __HAVE_ARCH_MEMCHR
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+
+#ifdef CONFIG_MARCO_MEMSET
+#define memset(p, v, n) \
+ ({ \
+ if ((n) != 0) { \
+ if (__builtin_constant_p((v)) && (v) == 0) \
+ __memzero((p), (n)); \
+ else \
+ memset((p), (v), (n)); \
+ } \
+ (p); \
+ })
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#endif
+
+#endif /* __ASM_RISCV_STRING_H */
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_RISCV_SYSTEM_H
+#define __ASM_RISCV_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ *
+ * TODO
+ *
+ */
+
+#endif /* __ASM_RISCV_SYSTEM_H */
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_RISCV_TYPES_H
+#define __ASM_RISCV_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _U_BOOT_RISCV_H_
+#define _U_BOOT_RISCV_H_ 1
+
+/* cpu/.../cpu.c */
+int cleanup_before_linux(void);
+
+/* board/.../... */
+int board_init(void);
+
+#endif /* _U_BOOT_RISCV_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_ 1
+
+#include <asm/u-boot-riscv.h>
+
+#include <environment.h>
+
+typedef struct bd_info {
+ unsigned long bi_arch_number; /* unique id for this board */
+ unsigned long bi_boot_params; /* where this board expects params */
+ unsigned long bi_memstart; /* start of DRAM memory */
+ unsigned long bi_memsize; /* size of DRAM memory in bytes */
+ unsigned long bi_flashstart; /* start of FLASH memory */
+ unsigned long bi_flashsize; /* size of FLASH memory */
+ unsigned long bi_flashoffset; /* reserved area for startup monitor */
+ unsigned char bi_enetaddr[6];
+
+ struct /* RAM configuration */
+ {
+ unsigned long start;
+ unsigned long size;
+ } bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_RISCV
+
+#endif /* _U_BOOT_H_ */
--- /dev/null
+#include <asm-generic/unaligned.h>
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_GO) += boot.o
+obj-y += cache.o
+obj-y += interrupts.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long do_go_exec(ulong (*entry)(int, char * const []),
+ int argc, char * const argv[])
+{
+ cleanup_before_linux();
+
+ return entry(argc, argv);
+}
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+#include <asm/bootm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+ bd_t *bd = gd->bd;
+ char *s;
+ int machid = bd->bi_arch_number;
+ void (*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+ char *commandline = env_get("bootargs");
+#endif
+
+ /*
+ * allow the PREP bootm subcommand, it is required for bootm to work
+ */
+ if (flag & BOOTM_STATE_OS_PREP)
+ return 0;
+
+ if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+ return 1;
+
+ theKernel = (void (*)(int, int, uint))images->ep;
+
+ s = env_get("machid");
+ if (s) {
+ machid = simple_strtoul(s, NULL, 16);
+ printf("Using machid 0x%x from environment\n", machid);
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+ debug("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong)theKernel);
+
+ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+#ifdef CONFIG_OF_LIBFDT
+ debug("using: FDT\n");
+ if (image_setup_linux(images)) {
+ printf("FDT creation failed! hanging...");
+ hang();
+ }
+#endif
+ } else if (BOOTM_ENABLE_TAGS) {
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+ setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+ setup_serial_tag(¶ms);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ setup_revision_tag(¶ms);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+ setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+ setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+ if (images->rd_start && images->rd_end)
+ setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+ setup_end_tag(bd);
+#endif
+
+ /* we assume that the kernel is in place */
+ printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+ {
+ extern void udc_disconnect(void);
+ udc_disconnect();
+ }
+#endif
+ }
+ cleanup_before_linux();
+ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+ theKernel(0, machid, (unsigned long)images->ft_addr);
+ else
+ theKernel(0, machid, bd->bi_boot_params);
+ /* does not return */
+
+ return 1;
+}
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+ params = (struct tag *)bd->bi_boot_params;
+
+ params->hdr.tag = ATAG_CORE;
+ params->hdr.size = tag_size(tag_core);
+
+ params->u.core.flags = 0;
+ params->u.core.pagesize = 0;
+ params->u.core.rootdev = 0;
+
+ params = tag_next(params);
+}
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ params->hdr.tag = ATAG_MEM;
+ params->hdr.size = tag_size(tag_mem32);
+
+ params->u.mem.start = bd->bi_dram[i].start;
+ params->u.mem.size = bd->bi_dram[i].size;
+
+ params = tag_next(params);
+ }
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+ char *p;
+
+ if (!commandline)
+ return;
+
+ /* eat leading white space */
+ for (p = commandline; *p == ' '; p++)
+ ;
+
+ /* skip non-existent command lines so the kernel will still
+ * use its default command line.
+ */
+ if (*p == '\0')
+ return;
+
+ params->hdr.tag = ATAG_CMDLINE;
+ params->hdr.size =
+ (sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+ strcpy(params->u.cmdline.cmdline, p)
+ ;
+
+ params = tag_next(params);
+}
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+ /* an ATAG_INITRD node tells the kernel where the compressed
+ * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+ */
+ params->hdr.tag = ATAG_INITRD2;
+ params->hdr.size = tag_size(tag_initrd);
+
+ params->u.initrd.start = initrd_start;
+ params->u.initrd.size = initrd_end - initrd_start;
+
+ params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+ struct tag *params;
+ struct tag_serialnr serialnr;
+ void get_board_serial(struct tag_serialnr *serialnr);
+
+ params = *tmp;
+ get_board_serial(&serialnr);
+ params->hdr.tag = ATAG_SERIAL;
+ params->hdr.size = tag_size(tag_serialnr);
+ params->u.serialnr.low = serialnr.low;
+ params->u.serialnr.high = serialnr.high;
+ params = tag_next(params);
+ *tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+ u32 rev;
+ u32 get_board_rev(void);
+
+ rev = get_board_rev();
+ params->hdr.tag = ATAG_REVISION;
+ params->hdr.size = tag_size(tag_revision);
+ params->u.revision.rev = rev;
+ params = tag_next(params);
+}
+#endif /* CONFIG_REVISION_TAG */
+
+static void setup_end_tag(bd_t *bd)
+{
+ params->hdr.tag = ATAG_NONE;
+ params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+}
+
+void invalidate_icache_range(unsigned long start, unsigned long end)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+}
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+ return 0;
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2016-17 Microsemi Corporation.
+ * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/encoding.h>
+
+static void _exit_trap(int code, uint epc, struct pt_regs *regs);
+
+int interrupt_init(void)
+{
+ return 0;
+}
+
+/*
+ * enable interrupts
+ */
+void enable_interrupts(void)
+{
+}
+
+/*
+ * disable interrupts
+ */
+int disable_interrupts(void)
+{
+ return 0;
+}
+
+uint handle_trap(uint mcause, uint epc, struct pt_regs *regs)
+{
+ uint is_int;
+
+ is_int = (mcause & MCAUSE_INT);
+ if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
+ external_interrupt(0); /* handle_m_ext_interrupt */
+ else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))
+ timer_interrupt(0); /* handle_m_timer_interrupt */
+ else
+ _exit_trap(mcause, epc, regs);
+
+ return epc;
+}
+
+/*
+ *Entry Point for PLIC Interrupt Handler
+ */
+__attribute__((weak)) void external_interrupt(struct pt_regs *regs)
+{
+}
+
+__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
+{
+}
+
+static void _exit_trap(int code, uint epc, struct pt_regs *regs)
+{
+ static const char *exception_code[] = {
+ "Instruction address misaligned",
+ "Instruction access fault",
+ "Illegal instruction",
+ "Breakpoint",
+ "Load address misaligned"
+ };
+
+ printf("exception code: %d , %s , epc %08x , ra %08lx\n",
+ code, exception_code[code], epc, regs->ra);
+}
wdt0: wdt@0 {
compatible = "sandbox,wdt";
};
+
+ chosen {
+ chosen-test {
+ compatible = "denx,u-boot-fdt-test";
+ reg = <9 1>;
+ };
+ };
};
#include "sandbox_pmic.dtsi"
#
obj-y += interrupts.o
-ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_PCI) += pci_io.o
-endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o
--- /dev/null
+if TARGET_NX25_AE250
+
+config SYS_CPU
+ default "nx25"
+
+config SYS_BOARD
+ default "nx25-ae250"
+
+config SYS_VENDOR
+ default "AndesTech"
+
+config SYS_SOC
+ default "ae250"
+
+config SYS_CONFIG_NAME
+ default "nx25-ae250"
+
+config ENV_SIZE
+ default 0x2000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+ default 0x140000 if ENV_IS_IN_SPI_FLASH
+
+endif
--- /dev/null
+NX25-AE250 BOARD
+M: Rick Chen <rick@andestech.com>
+S: Maintained
+F: board/AndesTech/nx25-ae250/
+F: include/configs/nx25-ae250.h
+F: configs/nx25-ae250_defconfig
--- /dev/null
+#
+# Copyright (C) 2017 Andes Technology Corporation.
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nx25-ae250.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/mach-types.h>
+#include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <faraday/ftsdc010.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_AE250;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_DM_MMC
+#ifdef CONFIG_FTSDC010
+ ftsdc010_mmc_init(0);
+#endif
+#endif
+ return 0;
+}
};
do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
- /* setup LCD-Pixel Clock */
- writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */
-
/* setup I2C */
enable_i2c_pin_mux();
i2c_set_bus_num(0);
0
};
do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
- /* setup LCD-Pixel Clock */
- writel(0x2, CM_DPLL + 0x34);
/* power-OFF LCD-Display */
gpio_direction_output(LCD_PWR, 0);
pnltmp.vsw = FDTPROP(PATHTIM, "vsync-len");
pnltmp.pup_delay = FDTPROP(PATHTIM, "pupdelay");
pnltmp.pon_delay = FDTPROP(PATHTIM, "pondelay");
-
- /* calc. proper clk-divisor */
- dtbprop = FDTPROP(PATHTIM, "clock-frequency");
- if (dtbprop != ~0UL)
- pnltmp.pxl_clk_div = 192000000 / dtbprop;
- else
- pnltmp.pxl_clk_div = ~0UL;
+ pnltmp.pxl_clk = FDTPROP(PATHTIM, "clock-frequency");
/* check polarity of control-signals */
dtbprop = FDTPROP(PATHTIM, "hsync-active");
pnltmp.vfp = env_get_ulong("ds1_vfp", 10, ~0UL);
pnltmp.vbp = env_get_ulong("ds1_vbp", 10, ~0UL);
pnltmp.vsw = env_get_ulong("ds1_vsw", 10, ~0UL);
- pnltmp.pxl_clk_div = env_get_ulong("ds1_pxlclkdiv", 10, ~0UL);
+ pnltmp.pxl_clk = env_get_ulong("ds1_pxlclk", 10, ~0UL);
pnltmp.pol = env_get_ulong("ds1_pol", 16, ~0UL);
pnltmp.pup_delay = env_get_ulong("ds1_pupdelay", 10, ~0UL);
pnltmp.pon_delay = env_get_ulong("ds1_tondelay", 10, ~0UL);
~0UL == (pnltmp.vfp) ||
~0UL == (pnltmp.vbp) ||
~0UL == (pnltmp.vsw) ||
- ~0UL == (pnltmp.pxl_clk_div) ||
+ ~0UL == (pnltmp.pxl_clk) ||
~0UL == (pnltmp.pol) ||
~0UL == (pnltmp.pup_delay) ||
~0UL == (pnltmp.pon_delay)
pnltmp.hactive, pnltmp.vactive, pnltmp.bpp,
pnltmp.hfp, pnltmp.hbp, pnltmp.hsw,
pnltmp.vfp, pnltmp.vbp, pnltmp.vsw,
- pnltmp.pxl_clk_div, pnltmp.pol, pnltmp.pon_delay);
+ pnltmp.pxl_clk, pnltmp.pol, pnltmp.pon_delay);
return -1;
}
#
obj-y += board.o
-ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o
obj-$(CONFIG_DM_VIDEO) += video_display.o
-endif
return 0;
}
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ char baseboard_name[16];
+ int err;
+
+ if (is_mx6dq())
+ env_set("board_rev", "MX6Q");
+ else if (is_mx6dl())
+ env_set("board_rev", "MX6DL");
+
+ err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
+ if (err)
+ return 0;
+
+ if (!strncmp("SB-FX6m", baseboard_name, 7))
+ env_set("board_name", "Utilite");
+#endif
+ return 0;
+}
+
int checkboard(void)
{
puts("Board: CM-FX6\n");
F: board/emulation/qemu-arm/
F: include/configs/qemu-arm.h
F: configs/qemu_arm_defconfig
+F: configs/qemu_arm64_defconfig
#include <common.h>
#include <fdtdec.h>
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region qemu_arm64_mem_map[] = {
+ {
+ /* Flash */
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x08000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Peripherals */
+ .virt = 0x08000000UL,
+ .phys = 0x08000000UL,
+ .size = 0x38000000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* RAM */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0xc0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = qemu_arm64_mem_map;
+#endif
+
int board_init(void)
{
return 0;
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
+ select CMD_EXT4 if ARM
+ select CMD_EXT4_WRITE if ARM
bool
default y
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
+
+config VOL_MONITOR_LTC3882_READ
+ depends on VID
+ bool "Enable the LTC3882 voltage monitor read"
+ default n
+ help
+ This option enables LTC3882 voltage monitor read
+ functionality. It is used by common VID driver.
+
+config VOL_MONITOR_LTC3882_SET
+ depends on VID
+ bool "Enable the LTC3882 voltage monitor set"
+ default n
+ help
+ This option enables LTC3882 voltage monitor set
+ functionality. It is used by common VID driver.
obj-$(CONFIG_FSL_PIXIS) += pixis.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
-obj-$(CONFIG_VID) += vid.o
endif
+obj-$(CONFIG_VID) += vid.o
obj-$(CONFIG_FSL_QIXIS) += qixis.o
obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
+obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
return 0;
}
+#ifndef CONFIG_SPL_BUILD
static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
"Put the core in spin loop (Secure Boot Only)",
""
);
+#endif
return p;
}
+#else
+int pfuze_mode_init(struct udevice *dev, u32 mode)
+{
+ unsigned char offset, i, switch_num;
+ u32 id;
+ int ret;
+
+ id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+ id = id & 0xf;
+
+ if (id == 0) {
+ switch_num = 6;
+ offset = PFUZE100_SW1CMODE;
+ } else if (id == 1) {
+ switch_num = 4;
+ offset = PFUZE100_SW2MODE;
+ } else {
+ printf("Not supported, id=%d\n", id);
+ return -EINVAL;
+ }
+
+ ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
+ if (ret < 0) {
+ printf("Set SW1AB mode error!\n");
+ return ret;
+ }
+
+ for (i = 0; i < switch_num - 1; i++) {
+ ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
+ if (ret < 0) {
+ printf("Set switch 0x%x mode error!\n",
+ offset + i * SWITCH_SIZE);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+struct udevice *pfuze_common_init(void)
+{
+ struct udevice *dev;
+ int ret;
+ unsigned int reg, dev_id, rev_id;
+
+ ret = pmic_get("pfuze100", &dev);
+ if (ret == -ENODEV)
+ return NULL;
+
+ dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+ printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
+ return dev;
+}
#endif
#ifndef __PFUZE_BOARD_HELPER__
#define __PFUZE_BOARD_HELPER__
+#ifdef CONFIG_DM_PMIC_PFUZE100
+struct udevice *pfuze_common_init(void);
+int pfuze_mode_init(struct udevice *dev, u32 mode);
+#else
struct pmic *pfuze_common_init(unsigned char i2cbus);
int pfuze_mode_init(struct pmic *p, u32 mode);
+#endif
#endif
#include <common.h>
#include <command.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#include <linux/time.h>
#include <i2c.h>
#include "qixis.h"
}
#endif
-void qixis_reset(void)
+#ifndef CONFIG_SPL_BUILD
+static void qixis_reset(void)
{
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
}
-void qixis_bank_reset(void)
+static void qixis_bank_reset(void)
{
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
}
-static void __qixis_dump_switch(void)
+void __weak qixis_dump_switch(void)
{
puts("Reverse engineering switch is not implemented for this board\n");
}
-void qixis_dump_switch(void)
- __attribute__((weak, alias("__qixis_dump_switch")));
-
-int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
QIXIS_WRITE(rcfg_ctl, 0x21);
#else
printf("Not implemented\n");
+#endif
+ } else if (strcmp(argv[1], "ifc") == 0) {
+#ifdef QIXIS_LBMAP_IFC
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_IFC);
+ set_rcw_src(QIXIS_RCW_SRC_IFC);
+ QIXIS_WRITE(rcfg_ctl, 0x20);
+ QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+ printf("Not implemented\n");
+#endif
+ } else if (strcmp(argv[1], "emmc") == 0) {
+#ifdef QIXIS_LBMAP_EMMC
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_EMMC);
+ set_rcw_src(QIXIS_RCW_SRC_EMMC);
+ QIXIS_WRITE(rcfg_ctl, 0x20);
+ QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+ printf("Not implemented\n");
#endif
} else if (strcmp(argv[1], "sd_qspi") == 0) {
#ifdef QIXIS_LBMAP_SD_QSPI
"qixis_reset dump - display the QIXIS registers\n"
"qixis_reset switch - display switch\n"
);
+#endif
return 0;
}
+/*
+ * Board specific settings for specific voltage value
+ */
+int __weak board_adjust_vdd(int vdd)
+{
+ return 0;
+}
+
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
/*
* Get the i2c address configuration for the IR regulator chip
*
}
return -1;
}
+#endif
/* Maximum loop count waiting for new voltage to take effect */
#define MAX_LOOP_WAIT_NEW_VOL 100
}
#endif
+#ifdef CONFIG_VOL_MONITOR_LTC3882_READ
+/* read the current value of the LTC Regulator Voltage */
+static int read_voltage_from_LTC(int i2caddress)
+{
+ int ret, vcode = 0;
+ u8 chan = PWM_CHANNEL0;
+
+ /* select the PAGE 0 using PMBus commands PAGE for VDD*/
+ ret = i2c_write(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_PAGE, 1, &chan, 1);
+ if (ret) {
+ printf("VID: failed to select VDD Page 0\n");
+ return ret;
+ }
+
+ /*read the output voltage using PMBus command READ_VOUT*/
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+ if (ret) {
+ printf("VID: failed to read the volatge\n");
+ return ret;
+ }
+
+ /* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */
+ vcode = DIV_ROUND_UP(vcode * 1000, 4096);
+
+ return vcode;
+}
+#endif
+
static int read_voltage(int i2caddress)
{
int voltage_read;
voltage_read = read_voltage_from_INA220(i2caddress);
#elif defined CONFIG_VOL_MONITOR_IR36021_READ
voltage_read = read_voltage_from_IR(i2caddress);
+#elif defined CONFIG_VOL_MONITOR_LTC3882_READ
+ voltage_read = read_voltage_from_LTC(i2caddress);
#else
return -1;
#endif
return voltage_read;
}
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
/*
* We need to calculate how long before the voltage stops to drop
* or increase. It returns with the loop count. Each loop takes
return vdd_current;
}
-#ifdef CONFIG_VOL_MONITOR_IR36021_SET
/* Set the voltage to the IR chip */
static int set_voltage_to_IR(int i2caddress, int vdd)
{
debug("VID: Current voltage is %d mV\n", vdd_last);
return vdd_last;
}
+
+#endif
+
+#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
+/* this function sets the VDD and returns the value set */
+static int set_voltage_to_LTC(int i2caddress, int vdd)
+{
+ int ret, vdd_last, vdd_target = vdd;
+
+ /* Scale up to the LTC resolution is 1/4096V */
+ vdd = (vdd * 4096) / 1000;
+
+ /* 5-byte buffer which needs to be sent following the
+ * PMBus command PAGE_PLUS_WRITE.
+ */
+ u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
+ vdd & 0xFF, (vdd & 0xFF00) >> 8};
+
+ /* Write the desired voltage code to the regulator */
+ ret = i2c_write(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+ if (ret) {
+ printf("VID: I2C failed to write to the volatge regulator\n");
+ return -1;
+ }
+
+ /* Wait for the volatge to get to the desired value */
+ do {
+ vdd_last = read_voltage_from_LTC(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjust\n");
+ return -1;
+ }
+ } while (vdd_last != vdd_target);
+
+ return vdd_last;
+}
#endif
static int set_voltage(int i2caddress, int vdd)
#ifdef CONFIG_VOL_MONITOR_IR36021_SET
vdd_last = set_voltage_to_IR(i2caddress, vdd);
+#elif defined CONFIG_VOL_MONITOR_LTC3882_SET
+ vdd_last = set_voltage_to_LTC(i2caddress, vdd);
#else
#error Specific voltage monitor must be defined
#endif
int re_enable = disable_interrupts();
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 fusesr;
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
u8 vid, buf;
+#else
+ u8 vid;
+#endif
int vdd_target, vdd_current, vdd_last;
int ret, i2caddress;
unsigned long vdd_string_override;
char *vdd_string;
+#ifdef CONFIG_ARCH_LS1088A
+ static const uint16_t vdd[32] = {
+ 10250,
+ 9875,
+ 9750,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 9000,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+
+#else
static const uint16_t vdd[32] = {
10500,
0, /* reserved */
0, /* reserved */
0, /* reserved */
};
+#endif
struct vdd_drive {
u8 vid;
unsigned voltage;
ret = -1;
goto exit;
}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
ret = -1;
goto exit;
}
+#endif
/* get the voltage ID from fuse status register */
fusesr = in_le32(&gur->dcfg_fusesr);
}
vdd_current = vdd_last;
debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+
+#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
+ /* Set the target voltage */
+ vdd_last = vdd_current = set_voltage(i2caddress, vdd_target);
+#else
/*
* Adjust voltage to at or one step above target.
* As measurements are less precise than setting the values
vdd_last = set_voltage(i2caddress, vdd_current);
}
+#endif
+ if (board_adjust_vdd(vdd_target) < 0) {
+ ret = -1;
+ goto exit;
+ }
+
if (vdd_last > 0)
printf("VID: Core voltage after adjustment is at %d mV\n",
vdd_last);
ret = -1;
goto exit;
}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
ret = -1;
goto exit;
}
+#endif
/* get the voltage ID from fuse status register */
fusesr = in_be32(&gur->dcfg_fusesr);
debug("VID : I2c failed to switch channel\n");
return -1;
}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
i2caddress = ret;
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
}
+#endif
/*
* Read voltage monitor to check real voltage.
source "board/freescale/common/Kconfig"
endif
+
+if TARGET_LS1012A2G5RDB
+
+config SYS_BOARD
+ default "ls1012ardb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012a2g5rdb"
+
+source "board/freescale/common/Kconfig"
+
+endif
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+
+LS1012A2G5RDB BOARD
+M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
+S: Maintained
+F: board/freescale/ls1012ardb/
+F: include/configs/ls1012a2g5rdb.h
+F: configs/ls1012a2g5rdb_qspi_defconfig
U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
+
+LS1012A2G5RDB board Overview
+-----------------------
+ - SERDES Connections, 3 lanes supporting:
+ - SGMII, SGMII 2.5
+ - SATA 3.0
+ - DDR Controller
+ - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+ - QSPI NOR flash memory
+ - USB 3.0
+ - one high-speed USB 2.0/3.0 port.
+ - SDIO WiFi, SPI
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - The LS1012A processor consists of two UART controllers,
+ out of which only UART1 is used on 2G5RDB.
+ - ARM JTAG support
+
+Major Difference between LS1012ARDB and LS1012A-2G5RDB
+------------------------------------------------------
+1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB
+2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs
+ of LS1012ARDB
+3. LS1012A-2G5RDB is not having Arduino header
+4. LS1012A-2G5RDB doesn't have PCI slot
+
+Booting Options
+---------------
+QSPI Flash
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4030_0000
+PPA FIT image | 2MB | 0x4040_0000
+PFE firmware | 20K | 0x00a0_0000
+Linux ITB | ~53MB | 0x4100_0000
int checkboard(void)
{
+#ifdef CONFIG_TARGET_LS1012ARDB
u8 in1;
puts("Board: LS1012ARDB ");
puts(": bank2\n");
else
puts("unknown\n");
+#else
+ puts("Board: LS1012A2G5RDB ");
+#endif
return 0;
}
return 0;
}
+#ifdef CONFIG_TARGET_LS1012ARDB
int esdhc_status_fixup(void *blob, const char *compat)
{
char esdhc1_path[] = "/soc/esdhc@1580000";
if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
sdhc2_en = true;
}
-
if (sdhc2_en)
do_fixup_by_path(blob, esdhc1_path, "status", "okay",
sizeof("okay"), 1);
sizeof("disabled"), 1);
return 0;
}
+#endif
int ft_board_setup(void *blob, bd_t *bd)
{
};
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-static void convert_serdes_mux(int type, int need_reset);
-
-void cpld_show(void)
+static void cpld_show(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
}
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+static void convert_serdes_mux(int type, int need_reset)
+{
+ char current_serdes;
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ current_serdes = cpld_data->serdes_mux;
+
+ switch (type) {
+ case LANEB_SATA:
+ current_serdes &= ~MASK_LANE_B;
+ break;
+ case LANEB_SGMII1:
+ current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
+ break;
+ case LANEC_SGMII1:
+ current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
+ break;
+ case LANED_SGMII2:
+ current_serdes |= MASK_LANE_D;
+ break;
+ case LANEC_PCIEX1:
+ current_serdes |= MASK_LANE_C;
+ break;
+ case (LANED_PCIEX2 | LANEC_PCIEX1):
+ current_serdes |= MASK_LANE_C;
+ current_serdes &= ~MASK_LANE_D;
+ break;
+ default:
+ printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
+ return;
+ }
+
+ cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
+ cpld_data->serdes_mux = current_serdes;
+
+ if (need_reset == 1) {
+ printf("Reset board to enable configuration\n");
+ cpld_data->system_rst = CONFIG_RESET;
+ }
+}
+
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
+ && !defined(CONFIG_SPL_BUILD)
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
);
-static void convert_serdes_mux(int type, int need_reset)
-{
- char current_serdes;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- current_serdes = cpld_data->serdes_mux;
-
- switch (type) {
- case LANEB_SATA:
- current_serdes &= ~MASK_LANE_B;
- break;
- case LANEB_SGMII1:
- current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
- break;
- case LANEC_SGMII1:
- current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
- break;
- case LANED_SGMII2:
- current_serdes |= MASK_LANE_D;
- break;
- case LANEC_PCIEX1:
- current_serdes |= MASK_LANE_C;
- break;
- case (LANED_PCIEX2 | LANEC_PCIEX1):
- current_serdes |= MASK_LANE_C;
- current_serdes &= ~MASK_LANE_D;
- break;
- default:
- printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
- return;
- }
-
- cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
- cpld_data->serdes_mux = current_serdes;
-
- if (need_reset == 1) {
- printf("Reset board to enable configuration\n");
- cpld_data->system_rst = CONFIG_RESET;
- }
-}
-
-void print_serdes_mux(void)
+static void print_serdes_mux(void)
{
char current_serdes;
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
S: Maintained
F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+
+LS1088ARDB_SD_SECURE_BOOT BOARD
+M: Sumit Garg <sumit.garg@nxp.com>
+S: Maintained
+F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
#
obj-y += ls1088a.o
+obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
-obj-y += ddr.o
+endif
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts)
+{
+ int vdd;
+
+ vdd = get_core_volt_from_fuse();
+ /* Nothing to do for silicons doesn't support VID */
+ if (vdd < 0)
+ return;
+
+ if (vdd == 900) {
+ popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN;
+ debug("VID: configure DDR to support 900 mV\n");
+ }
+}
+#endif
+
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
popts->addr_hash = 1;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+ fsl_ddr_setup_0v9_volt(popts);
+#endif
+
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
}
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch/ppa.h>
#include <hwconfig.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
#include "../common/qixis.h"
#include "ls1088a_qixis.h"
+#include "../common/vid.h"
+#include <fsl_immap.h>
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void)
+{
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+#ifdef CONFIG_FSL_QIXIS
unsigned long long get_qixis_addr(void)
{
unsigned long long addr;
return addr;
}
+#endif
+
+#if defined(CONFIG_VID)
+int init_func_vid(void)
+{
+ if (adjust_vdd(0) < 0)
+ printf("core voltage not adjusted\n");
+
+ return 0;
+}
+#endif
+#if !defined(CONFIG_SPL_BUILD)
int checkboard(void)
{
char buf[64];
return 66666666;
}
+#endif
int select_i2c_ch_pca9547(u8 ch)
{
return 0;
}
+#if !defined(CONFIG_SPL_BUILD)
void board_retimer_init(void)
{
u8 reg;
return 0;
}
#endif
+#endif
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+/* read the current value(SVDD) of the LTM Regulator Voltage */
+int get_serdes_volt(void)
+{
+ int ret, vcode = 0;
+ u8 chan = PWM_CHANNEL0;
+
+ /* Select the PAGE 0 using PMBus commands PAGE for VDD */
+ ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
+ PMBUS_CMD_PAGE, 1, &chan, 1);
+ if (ret) {
+ printf("VID: failed to select VDD Page 0\n");
+ return ret;
+ }
+
+ /* Read the output voltage using PMBus command READ_VOUT */
+ ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
+ PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+ if (ret) {
+ printf("VID: failed to read the volatge\n");
+ return ret;
+ }
+
+ return vcode;
+}
+
+int set_serdes_volt(int svdd)
+{
+ int ret, vdd_last;
+ u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
+ svdd & 0xFF, (svdd & 0xFF00) >> 8};
+
+ /* Write the desired voltage code to the SVDD regulator */
+ ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
+ PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+ if (ret) {
+ printf("VID: I2C failed to write to the volatge regulator\n");
+ return -1;
+ }
+
+ /* Wait for the volatge to get to the desired value */
+ do {
+ vdd_last = get_serdes_volt();
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjust\n");
+ return -1;
+ }
+ } while (vdd_last != svdd);
+
+ return 1;
+}
+#else
+int get_serdes_volt(void)
+{
+ return 0;
+}
+
+int set_serdes_volt(int svdd)
+{
+ int ret;
+ u8 brdcfg4;
+
+ printf("SVDD changing of RDB\n");
+
+ /* Read the BRDCFG54 via CLPD */
+ ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
+ QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+ if (ret) {
+ printf("VID: I2C failed to read the CPLD BRDCFG4\n");
+ return -1;
+ }
+
+ brdcfg4 = brdcfg4 | 0x08;
+
+ /* Write to the BRDCFG4 */
+ ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
+ QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+ if (ret) {
+ debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
+ return -1;
+ }
+
+ /* Wait for the volatge to get to the desired value */
+ udelay(10000);
+
+ return 1;
+}
+#endif
+/* this function disables the SERDES, changes the SVDD Voltage and enables it*/
+int board_adjust_vdd(int vdd)
+{
+ int ret = 0;
+
+ debug("%s: vdd = %d\n", __func__, vdd);
+
+ /* Special settings to be performed when voltage is 900mV */
+ if (vdd == 900) {
+ ret = setup_serdes_volt(vdd);
+ if (ret < 0) {
+ ret = -1;
+ goto exit;
+ }
+ }
+exit:
+ return ret;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
int board_init(void)
{
init_final_memctl_regs();
return 0;
}
-int board_early_init_f(void)
-{
- fsl_lsch3_early_init_f();
- return 0;
-}
-
void detail_board_ddr_info(void)
{
puts("\nDDR ");
return 0;
}
#endif
+#endif /* defined(CONFIG_SPL_BUILD) */
#ifdef CONFIG_TARGET_LS2081ARDB
#ifdef CONFIG_FSL_QIXIS
sw = QIXIS_READ(arch);
- printf("Board Arch: V%d, ", sw >> 4);
printf("Board version: %c, ", (sw & 0xf) + 'A');
sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
+ sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
switch (sw) {
case 0:
puts("boot from QSPI DEV#0\n");
printf("invalid setting of SW%u\n", sw);
break;
}
+ printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
#endif
puts("SERDES1 Reference : ");
printf("Clock1 = 100MHz ");
1.2 Configuration settings for M52277EVB Development Board
CONFIG_MCF5227x -- define for all MCF5227x CPUs
CONFIG_M52277 -- define for all Freescale MCF52277 CPUs
-CONFIG_M52277EVB -- define for M52277EVB board
CONFIG_MCFUART -- define to use common CF Uart driver
CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
CONFIG_MCF52x2 Processor family
CONFIG_MCF5253 MCF5253 specific
- CONFIG_M5253EVBE Amadeus Plus board specific
CONFIG_SYS_CLK Define Amadeus Plus CPU Clock
CONFIG_SYS_MBAR MBAR base address
CONFIG_SYS_MBAR2 MBAR2 base address
CONFIG_MPC83xx MPC83xx family
CONFIG_MPC8349 MPC8349 specific
CONFIG_MPC8349ITX MPC8349E-mITX
- CONFIG_MPC8349ITXGP MPC8349E-mITX-GP
5. Compilation
NXP SABRELite.
config UART1_CSI0_DAT10_11
- bool "UART1 on CSI0_DAT10/11 (Wand)"
+ bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)"
depends on SERIAL_CONSOLE_UART1
help
Choose this configuration if you're using pads
CSI0_DAT10 and DAT11 for a console on UART1 as
- is done on the i.MX6 Wand board.
-
- config UART1_SD3_DAT6_7
- bool "UART1 on SD3_DAT6/7 (SabreSD, SabreAuto)"
- depends on SERIAL_CONSOLE_UART1
- help
- Choose this configuration if you're using pads
- SD3_DAT6 and DAT7 for a console on UART1 as is
- done on the NXP SABRESD or SABREAUTO designs.
+ is done on the i.MX6 Wand board and i.MX6 SabreSD.
config UART1_UART1
bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
if (sysinfo.dsize != 1) {
if (is_cpu_type(MXC_CPU_MX6SX) ||
is_cpu_type(MXC_CPU_MX6UL) ||
+ is_cpu_type(MXC_CPU_MX6ULL) ||
is_cpu_type(MXC_CPU_MX6SL)) {
printf("cpu type 0x%x doesn't support 64-bit bus\n",
get_cpu_type());
} else {
errs = mmdc_do_dqs_calibration(&sysinfo);
if (errs) {
- printf("error %d from write level calibration\n", errs);
+ printf("error %d from dqs calibration\n", errs);
} else {
printf("completed successfully\n");
mmdc_read_calibration(&sysinfo, &calibration);
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
-#include <usb.h>
-#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
-
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
-
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm)
+
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- /* CD pin */
- MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
- /* RST_B, used for power reset cycle */
- MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+static iomux_v3_cfg_t const wdog_b_pad = {
+ MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
-
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
ARRAY_SIZE(phy_control_pads));
/* Enable the ENET power, active low */
+ gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
/* Reset AR8031 PHY */
+ gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(2, 7), 1);
return cpu_eth_init(bis);
}
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
- .gp = IMX_GPIO_NR(1, 0),
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
- .gp = IMX_GPIO_NR(1, 1),
- },
-};
-
int power_init_board(void)
{
- struct pmic *p;
+ struct udevice *dev;
unsigned int reg;
int ret;
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
+ dev = pfuze_common_init();
+ if (!dev)
return -ENODEV;
- ret = pfuze_mode_init(p, APS_PFM);
+ ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
/* Enable power of VGEN5 3V3, needed for SD3 */
- pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
+ reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
reg &= ~LDO_VOL_MASK;
reg |= (LDOB_3_30V | (1 << LDO_EN));
- pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+ pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
return 0;
}
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_OTHERREGS_OFFSET 0x800
-#define UCTRL_PWR_POL (1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
- /* OGT1 */
- MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* OTG2 */
- MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
-static void setup_usb(void)
-{
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
- ARRAY_SIZE(usb_otg_pads));
-}
-
-int board_usb_phy_mode(int port)
-{
- if (port == 1)
- return USB_INIT_HOST;
- else
- return usb_phy_mode(port);
-}
-
-int board_ehci_hcd_init(int port)
-{
- u32 *usbnc_usb_ctrl;
-
- if (port > 1)
- return -EINVAL;
-
- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
- port * 4);
-
- /* Set Power polarity */
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
- return 0;
-}
-#endif
-
int board_phy_config(struct phy_device *phydev)
{
/*
imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
ARRAY_SIZE(peri_3v3_pads));
- /* Active high for ncp692 */
- gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
-
-#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
-#endif
-
return 0;
}
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC2_BASE_ADDR, 0, 4},
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
-#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
-#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
-
int board_mmc_get_env_dev(int devno)
{
- return devno - 1;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = 1; /* Assume uSDHC2 is always present */
- break;
- case USDHC3_BASE_ADDR:
- ret = !gpio_get_value(USDHC3_CD_GPIO);
- break;
- case USDHC4_BASE_ADDR:
- ret = !gpio_get_value(USDHC4_CD_GPIO);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 USDHC2
- * mmc1 USDHC3
- * mmc2 USDHC4
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- gpio_direction_input(USDHC3_CD_GPIO);
- gpio_direction_output(USDHC3_PWR_GPIO, 1);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- case 2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- gpio_direction_input(USDHC4_CD_GPIO);
- usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) than supported by the board\n", i + 1);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize mmc dev %d\n", i);
- return ret;
- }
- }
-
- return 0;
-#else
- struct src *src_regs = (struct src *)SRC_BASE_ADDR;
- u32 val;
- u32 port;
-
- val = readl(&src_regs->sbmr1);
-
- if ((val & 0xc0) != 0x40) {
- printf("Not boot from USDHC!\n");
- return -EINVAL;
- }
-
- port = (val >> 11) & 0x3;
- printf("port %d\n", port);
- switch (port) {
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
- break;
- case 2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- gpio_direction_input(USDHC3_CD_GPIO);
- gpio_direction_output(USDHC3_PWR_GPIO, 1);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
- break;
- case 3:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- gpio_direction_input(USDHC4_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
- break;
- }
-
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
+ return devno;
}
#ifdef CONFIG_FSL_QSPI
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Reset the LCD */
+ gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
/* Set Brightness to high */
+ gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
return 0;
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-#endif
+ /*
+ * Because kernel set WDOG_B mux before pad with the common pinctrl
+ * framwork now and wdog reset will be triggered once set WDOG_B mux
+ * with default pad setting, we set pad setting here to workaround this.
+ * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
+ * as GPIO mux firstly here to workaround it.
+ */
+ imx_iomux_v3_setup_pad(wdog_b_pad);
+
+ /* Active high for ncp692 */
+ gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
+ gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
+#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD pin */
+ MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* RST_B, used for power reset cycle */
+ MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u32 val;
+ u32 port;
+
+ val = readl(&src_regs->sbmr1);
+
+ if ((val & 0xc0) != 0x40) {
+ printf("Not boot from USDHC!\n");
+ return -EINVAL;
+ }
+
+ port = (val >> 11) & 0x3;
+ printf("port %d\n", port);
+ switch (port) {
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ gpio_direction_output(USDHC3_PWR_GPIO, 1);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ break;
+ case 3:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ gpio_direction_input(USDHC4_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+ break;
+ }
+
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = 1; /* Assume uSDHC2 is always present */
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = !gpio_get_value(USDHC4_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000028,
.dram_dqm1 = 0x00000028,
return 0;
}
+#ifndef CONFIG_SPL_BUILD
static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
"configure multiplexing pin for IFC/SDHC bus in runtime",
"bus_type (e.g. mux sdhc)"
);
+#endif
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <netdev.h>
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- setup_portals();
+ setup_qbman_portals();
return 0;
}
{ /* Sentinel */ }
};
-#ifdef CONFIG_CMD_EECONFIG
+#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_SPL_BUILD)
static struct ventana_eeprom_config *get_config(const char *name)
{
struct ventana_eeprom_config *cfg = econfig;
static u8 econfig_bytes[sizeof(ventana_info.config)];
static int econfig_init = -1;
-int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct ventana_eeprom_config *cfg;
struct ventana_board_info *info = &ventana_info;
return 1;
}
-#ifdef CONFIG_CMD_GSC
+#if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD)
static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
invalidate_icache();
set_liodns();
- setup_portals();
+ setup_qbman_portals();
ret = trigger_fpga_config();
if (ret)
DECLARE_GLOBAL_DATA_PTR;
-/* This is only needed until SPL gets OF support */
-#ifdef CONFIG_SPL_BUILD
-static const struct ns16550_platdata omap3logic_serial = {
- .base = OMAP34XX_UART1,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(omap3logic_uart) = {
- "ns16550_serial",
- &omap3logic_serial
-};
-#endif
-
/*
* two dimensional array of strucures containining board name and Linux
* machine IDs; row it selected based on CPU column is slected based
#
obj-y := dragonboard410c.o
+obj-y += lowlevel_init.o
extra-y += head.o
#include <dm.h>
#include <usb.h>
#include <asm/gpio.h>
+#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
+/* pointer to the device tree ammended by the firmware */
+extern void *fw_dtb;
+
+void *board_fdt_blob_setup(void)
+{
+ if (fdt_magic(fw_dtb) != FDT_MAGIC) {
+ printf("Firmware provided invalid dtb!\n");
+ return NULL;
+ }
+
+ return fw_dtb;
+}
+
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
+
return 0;
}
return 0;
}
-
int board_prepare_usb(enum usb_init_type type)
{
static struct udevice *pmic_gpio;
return 0;
}
-int board_init(void)
-{
- return 0;
-}
-
/* Check for vol- button - if pressed - stop autoboot */
int misc_init_r(void)
{
return 0;
}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int offset, len, i;
+ const char *mac;
+ struct {
+ const char *compatible;
+ const char *property;
+ } fix[] = {
+ [0] = {
+ /* update the kernel's dtb with wlan mac */
+ .compatible = "qcom,wcnss-wlan",
+ .property = "local-mac-address",
+ },
+ [1] = {
+ /* update the kernel's dtb with bt mac */
+ .compatible = "qcom,wcnss-bt",
+ .property = "local-bd-address",
+ },
+ };
+
+ for (i = 0; i < sizeof(fix) / sizeof(fix[0]); i++) {
+ offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ fix[i].compatible);
+ if (offset < 0)
+ continue;
+
+ mac = fdt_getprop(gd->fdt_blob, offset, fix[i].property, &len);
+ if (mac)
+ do_fixup_by_compat(blob, fix[i].compatible,
+ fix[i].property, mac, ARP_HLEN, 1);
+ }
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
--- /dev/null
+/*
+ * (C) Copyright 2016
+ * Cédric Schieli <cschieli@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.align 8
+.global fw_dtb
+fw_dtb:
+ .dword 0x0
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: save ATAG/FDT address provided by the firmware at boot time
+ */
+
+.global save_boot_params
+save_boot_params:
+
+ /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+ adr x8, fw_dtb
+ str x0, [x8]
+
+ /* Returns */
+ b save_boot_params_ret
--- /dev/null
+if TARGET_DRAGONBOARD820C
+
+config SYS_BOARD
+ default "dragonboard820c"
+
+config SYS_VENDOR
+ default "qualcomm"
+
+config SYS_SOC
+ default "apq8096"
+
+config SYS_CONFIG_NAME
+ default "dragonboard820c"
+
+endif
--- /dev/null
+DRAGONBOARD820C BOARD
+M: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+S: Maintained
+F: board/qualcomm/dragonboard820c/
+F: include/configs/dragonboard820c.h
+F: configs/dragonboard820c_defconfig
--- /dev/null
+#
+# (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dragonboard820c.o
+extra-y += head.o
--- /dev/null
+/*
+ * Board init file for Dragonboard 820C
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/sysmap-apq8096.h>
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <asm/psci.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ return 0;
+}
+
+static void sdhci_power_init(void)
+{
+ const u32 TLMM_PULL_MASK = 0x3;
+ const u32 TLMM_HDRV_MASK = 0x7;
+
+ struct tlmm_cfg {
+ u32 bit; /* bit in the register */
+ u8 mask; /* mask clk/dat/cmd control */
+ u8 val;
+ };
+
+ /* bit offsets in the sdc tlmm register */
+ enum { SDC1_DATA_HDRV = 0,
+ SDC1_CMD_HDRV = 3,
+ SDC1_CLK_HDRV = 6,
+ SDC1_DATA_PULL = 9,
+ SDC1_CMD_PULL = 11,
+ SDC1_CLK_PULL = 13,
+ SDC1_RCLK_PULL = 15,
+ };
+
+ enum { TLMM_PULL_DOWN = 0x1,
+ TLMM_PULL_UP = 0x3,
+ TLMM_NO_PULL = 0x0,
+ };
+
+ enum { TLMM_CUR_VAL_10MA = 0x04,
+ TLMM_CUR_VAL_16MA = 0x07,
+ };
+ int i;
+
+ /* drive strength configs for sdhc pins */
+ const struct tlmm_cfg hdrv[] = {
+
+ { SDC1_CLK_HDRV, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, },
+ { SDC1_CMD_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, },
+ { SDC1_DATA_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, },
+ };
+
+ /* pull configs for sdhc pins */
+ const struct tlmm_cfg pull[] = {
+
+ { SDC1_CLK_PULL, TLMM_NO_PULL, TLMM_PULL_MASK, },
+ { SDC1_CMD_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, },
+ { SDC1_DATA_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, },
+ };
+
+ const struct tlmm_cfg rclk[] = {
+
+ { SDC1_RCLK_PULL, TLMM_PULL_DOWN, TLMM_PULL_MASK,},
+ };
+
+ for (i = 0; i < ARRAY_SIZE(hdrv); i++)
+ clrsetbits_le32(SDC1_HDRV_PULL_CTL_REG,
+ hdrv[i].mask << hdrv[i].bit,
+ hdrv[i].val << hdrv[i].bit);
+
+ for (i = 0; i < ARRAY_SIZE(pull); i++)
+ clrsetbits_le32(SDC1_HDRV_PULL_CTL_REG,
+ pull[i].mask << pull[i].bit,
+ pull[i].val << pull[i].bit);
+
+ for (i = 0; i < ARRAY_SIZE(rclk); i++)
+ clrsetbits_le32(SDC1_HDRV_PULL_CTL_REG,
+ rclk[i].mask << rclk[i].bit,
+ rclk[i].val << rclk[i].bit);
+}
+
+static void show_psci_version(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ printf("PSCI: v%ld.%ld\n",
+ PSCI_VERSION_MAJOR(res.a0),
+ PSCI_VERSION_MINOR(res.a0));
+}
+
+int board_init(void)
+{
+ sdhci_power_init();
+ show_psci_version();
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+/* Check for vol- button - if pressed - stop autoboot */
+int misc_init_r(void)
+{
+ struct udevice *pon;
+ struct gpio_desc resin;
+ int node, ret;
+
+ ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8994_pon@800", &pon);
+ if (ret < 0) {
+ printf("Failed to find PMIC pon node. Check device tree\n");
+ return 0;
+ }
+
+ node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+ "key_vol_down");
+ if (node < 0) {
+ printf("Failed to find key_vol_down node. Check device tree\n");
+ return 0;
+ }
+
+ if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+ &resin, 0)) {
+ printf("Failed to request key_vol_down button.\n");
+ return 0;
+ }
+
+ if (dm_gpio_get_value(&resin)) {
+ env_set("bootdelay", "-1");
+ printf("Power button pressed - dropping to console.\n");
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * ARM64 header for proper chain-loading with Little Kernel.
+ *
+ * Little Kernel shipped with Dragonboard820C boots standard Linux images for
+ * ARM64. This file adds header that is required to boot U-Boot properly.
+ *
+ * For details see:
+ * https://www.kernel.org/doc/Documentation/arm64/booting.txt
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/*
+ * per document in linux/Doc/arm64/booting.text
+ */
+.global _arm64_header
+_arm64_header:
+ b _start
+ .word 0
+ .quad CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
+ .quad 0 /* Effective size of kernel image, little-endian */
+ .quad 0 /* kernel flags, little-endian */
+ .quad 0 /* reserved */
+ .quad 0 /* reserved */
+ .quad 0 /* reserved */
+ .byte 0x41 /* Magic number, "ARM\x64" */
+ .byte 0x52
+ .byte 0x4d
+ .byte 0x64
+ .word 0 /* reserved (used for PE COFF offset) */
--- /dev/null
+#
+# (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+================================================================================
+ What is working (enough to boot a distro from SD card)
+================================================================================
+ - UART
+ - SD card
+ - PSCI reset
+ - Environment in EXT4 partition 1 in SD card (check defconfig for details)
+ dont forget to insert the card in the SD slot before booting if you
+ are going to make mods to the environment
+
+================================================================================
+ Build & Run instructions
+================================================================================
+
+1) Install mkbootimg and dtbTool from Codeaurora:
+
+ git://codeaurora.org/quic/kernel/skales
+ commit 8492547e404e969262d9070dee9bdd15668bb70f worked for me.
+
+2) Setup CROSS_COMPILE to aarch64 compiler or if you use ccache just do
+ CROSS_COMPILE="ccache aarch64-linux-gnu-"
+
+3) cd to the u-boot tree
+
+ $ make dragonboard820c_config
+ $ make -j `nproc`
+
+4) generate fake, empty ramdisk (can have 0 bytes)
+
+ $ touch rd
+
+5) Generate qualcomm device tree table with dtbTool
+
+ $ dtbTool -o dt.img arch/arm/dts
+
+6) Generate Android boot image with mkbootimg:
+
+ $ mkbootimg --kernel=u-boot-dtb.bin \
+ --output=u-boot.img \
+ --dt=dt.img \
+ --pagesize 4096 \
+ --base 0x80000000 \
+ --ramdisk=rd \
+ --cmdline=""
+
+7) Reboot the board into fastboot mode
+ - plug the board micro-usb to your laptop usb host.
+ - reboot the board with vol- button pressed
+
+8) Boot the uboot image using fastboot
+
+ $ fastboot boot u-boot.img
+
+ or flash it to the UFS drive boot partition:
+
+ $ fastboot flash boot u-boot.img
+ $ fastboot reboot
+
+
+================================================================================
+ To boot a linux kernel from SDHCI with the ROOTFS on an NFS share:
+================================================================================
+
+1) create an EXT4 partition on the SD card (must be partition #1)
+
+2) build the kernel image and dtb (documented extensively somewhere else)
+
+3) copy the drivers to the NFS partition (ie: 192.168.1.2 /exports/db820c-rootfs)
+
+4) add the u-boot headers to the image:
+
+ $ mkimage -A arm64 \
+ -O linux \
+ -C none \
+ -T kernel \
+ -a 0x80080000 \
+ -e 0x80080000 \
+ -n Dragonboard820c \
+ -d $kernel/arch/arm64/boot/Image \
+ uImage
+
+5) copy the generated uImage and the device tree binary to the SD card EXT4
+ partition
+
+ $ cp uImage /mnt/boot/
+ $ cp apq8096-db820c.dtb /mnt/boot/
+
+6) on the SD card create /extlinux/extlinux.conf as follows:
+
+ default nfs
+ prompt 1
+ timeout 10
+
+ LABEL nfs
+ MENU NFS entry
+ LINUX /uImage
+ FDT /apq8096-db820c.dtb
+ APPEND root=/dev/nfs rw \
+ nfsroot=192.168.1.2:/exports/db829c-rootfs,v3,tcp \
+ rootwait \
+ ip=dhcp consoleblank=0 \
+ console=tty0 \
+ console=ttyMSM0,115200n8 \
+ earlyprintk earlycon=msm_serial_dm,0x75b0000 \
+ androidboot.bootdevice=624000.ufshc \
+ androidboot.verifiedbootstate=orange \
+ androidboot.ver0
+
+7) remove the SD card from the laptop and insert it back to the db820 board.
+ the SD card EXT4 partition#1 should contain:
+ /uImage
+ /apq8096-db820c.dtb
+ /extlinux/extlinux.conf
+
+8) reboot the db820 board
+
+================================================================================
+ Successful boot sequence
+================================================================================
+
+Format: Log Type - Time(microsec) - Message - Optional Info
+Log Type: B - Since Boot(Power On Reset), D - Delta, S - Statistic
+S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.0-00301
+S - IMAGE_VARIANT_STRING=M8996LAB
+S - OEM_IMAGE_VERSION_STRING=crm-ubuntu68
+S - Boot Interface: UFS
+S - Secure Boot: Off
+S - Boot Config @ 0x00076044 = 0x000001c9
+S - JTAG ID @ 0x000760f4 = 0x4003e0e1
+S - OEM ID @ 0x000760f8 = 0x00000000
+S - Serial Number @ 0x00074138 = 0x2e8844ce
+S - OEM Config Row 0 @ 0x00074188 = 0x0000000000000000
+S - OEM Config Row 1 @ 0x00074190 = 0x0000000000000000
+S - Feature Config Row 0 @ 0x000741a0 = 0x0050000010000100
+S - Feature Config Row 1 @ 0x000741a8 = 0x00fff00001ffffff
+S - Core 0 Frequency, 1228 MHz
+B - 0 - PBL, Start
+B - 10412 - bootable_media_detect_entry, Start
+B - 47480 - bootable_media_detect_success, Start
+B - 47481 - elf_loader_entry, Start
+B - 49027 - auth_hash_seg_entry, Start
+B - 49129 - auth_hash_seg_exit, Start
+B - 82403 - elf_segs_hash_verify_entry, Start
+B - 84905 - PBL, End
+B - 86955 - SBL1, Start
+B - 182969 - usb: hs_phy_nondrive_start
+B - 183305 - usb: PLL lock success - 0x3
+B - 186294 - usb: hs_phy_nondrive_finish
+B - 190442 - boot_flash_init, Start
+D - 30 - boot_flash_init, Delta
+B - 197548 - sbl1_ddr_set_default_params, Start
+D - 30 - sbl1_ddr_set_default_params, Delta
+B - 205509 - boot_config_data_table_init, Start
+D - 200659 - boot_config_data_table_init, Delta - (60 Bytes)
+B - 410713 - CDT Version:3,Platform ID:24,Major ID:1,Minor ID:0,Subtype:0
+B - 415410 - Image Load, Start
+D - 22570 - PMIC Image Loaded, Delta - (37272 Bytes)
+B - 437980 - pm_device_init, Start
+B - 443744 - PON REASON:PM0:0x200000061 PM1:0x200000021
+B - 480161 - PM_SET_VAL:Skip
+D - 40016 - pm_device_init, Delta
+B - 482083 - pm_driver_init, Start
+D - 2928 - pm_driver_init, Delta
+B - 488671 - pm_sbl_chg_init, Start
+D - 91 - pm_sbl_chg_init, Delta
+B - 495442 - vsense_init, Start
+D - 0 - vsense_init, Delta
+B - 505171 - Pre_DDR_clock_init, Start
+D - 396 - Pre_DDR_clock_init, Delta
+B - 509045 - ddr_initialize_device, Start
+B - 512766 - 8996 v3.x detected, Max frequency = 1.8 GHz
+B - 522373 - ddr_initialize_device, Delta
+B - 522404 - DDR ID, Rank 0, Rank 1, 0x6, 0x300, 0x300
+B - 526247 - Basic DDR tests done
+B - 594994 - clock_init, Start
+D - 274 - clock_init, Delta
+B - 598349 - Image Load, Start
+D - 4331 - QSEE Dev Config Image Loaded, Delta - (46008 Bytes)
+B - 603808 - Image Load, Start
+D - 5338 - APDP Image Loaded, Delta - (0 Bytes)
+B - 612409 - usb: UFS Serial - 2f490ecf
+B - 616801 - usb: fedl, vbus_low
+B - 620431 - Image Load, Start
+D - 55418 - QSEE Image Loaded, Delta - (1640572 Bytes)
+B - 675849 - Image Load, Start
+D - 2013 - SEC Image Loaded, Delta - (4096 Bytes)
+B - 683413 - sbl1_efs_handle_cookies, Start
+D - 457 - sbl1_efs_handle_cookies, Delta
+B - 691892 - Image Load, Start
+D - 14396 - QHEE Image Loaded, Delta - (254184 Bytes)
+B - 706319 - Image Load, Start
+D - 14061 - RPM Image Loaded, Delta - (223900 Bytes)
+B - 721111 - Image Load, Start
+D - 3233 - STI Image Loaded, Delta - (0 Bytes)
+B - 727913 - Image Load, Start
+D - 34709 - APPSBL Image Loaded, Delta - (748716 Bytes)
+B - 762713 - SBL1, End
+D - 680028 - SBL1, Delta
+S - Flash Throughput, 94000 KB/s (2959024 Bytes, 31250 us)
+S - DDR Frequency, 1017 MHz
+Android Bootloader - UART_DM Initialized!!!
+
+[0] BUILD_VERSION=
+[0] BUILD_DATE=16:07:51 - Nov 17 2017
+[0] welcome to lk
+[10] platform_init()
+[10] target_init()
+[10] RPM GLink Init
+[10] Opening RPM Glink Port success
+[10] Opening SSR Glink Port success
+[20] Glink Connection between APPS and RPM established
+[20] Glink Connection between APPS and RPM established
+[40] UFS init success
+[80] Qseecom Init Done in Appsbl
+[80] secure app region addr=0x86600000 size=0x2200000[90] TZ App region notif returned with status:0 addr:86600000 size:35651584
+[100] TZ App log region register returned with status:0 addr:916d4000 size:4096
+[100] Qseecom TZ Init Done in Appsbl
+[120] Loading cmnlib done
+[120] qseecom_start_app: Loading app keymaster for the first time
+[150] <8>keymaster: "\"KEYMASTER Init \""
+[160] Selected panel: none
+Skip panel configuration
+[160] pm8x41_get_is_cold_boot: cold boot
+[170] boot_verifier: Device is in ORANGE boot state.
+[180] Device is unlocked! Skipping verification...
+[180] Loading (boot) image (348160): start
+[190] Loading (boot) image (348160): done
+[190] use_signed_kernel=1, is_unlocked=1, is_tampered=0.
+[200] Your device has been unlocked and cant be trusted.
+Wait for 5 seconds before proceeding
+
+[5200] mdtp: mdtp_img loaded
+[5210] mdtp: is_test_mode: test mode is set to 1
+[5210] mdtp: read_metadata: SUCCESS
+[5230] LK SEC APP Handle: 0x1
+[5230] Return value from recv_data: 14
+[5240] Return value from recv_data: 14
+[5250] Return value from recv_data: 14
+[5260] DTB Total entry: 1, DTB version: 3
+[5260] Using DTB entry 0x00000123/00000000/0x00000018/0 for device 0x00000123/00030001/0x00010018/0
+[5270] cmdline: androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.veritymode=enforcing androidboot.serialno=2f490ecf androidboot.baseband=apq mdss_mdp.panel=0
+[5290] Updating device tree: start
+[5290] Updating device tree: done
+[5290] Return value from recv_data: 14
+[5300] RPM GLINK UnInit
+[5300] Qseecom De-Init Done in Appsbl
+[5300] booting linux @ 0x80080000, ramdisk @ 0x82200000 (0), tags/device tree @ 0x82000000
+[5310] Jumping to kernel via monitor
+
+U-Boot 2017.11-00145-ge895117 (Nov 29 2017 - 10:04:06 +0100)
+Qualcomm-DragonBoard 820C
+
+DRAM: 3 GiB
+PSCI: v1.0
+MMC: sdhci@74a4900: 0
+In: serial@75b0000
+Out: serial@75b0000
+Err: serial@75b0000
+Net: Net Initialization Skipped
+No ethernet found.
+Hit any key to stop autoboot: 0
+switch to partitions #0, OK
+mmc0 is current device
+Scanning mmc 0:1...
+Found /extlinux/extlinux.conf
+Retrieving file: /extlinux/extlinux.conf
+433 bytes read in 71 ms (5.9 KiB/s)
+1: nfs root
+
+Retrieving file: /uImage
+19397184 bytes read in 2024 ms (9.1 MiB/s)
+append: root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0 console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.ver0
+
+Retrieving file: /apq8096-db820c.dtb
+38134 bytes read in 37 ms (1005.9 KiB/s)
+
+## Booting kernel from Legacy Image at 95000000 ...
+ Image Name: Dragonboard820c
+ Image Type: AArch64 Linux Kernel Image (uncompressed)
+ Data Size: 19397120 Bytes = 18.5 MiB
+ Load Address: 80080000
+ Entry Point: 80080000
+ Verifying Checksum ... OK
+## Flattened Device Tree blob at 93000000
+ Booting using the fdt blob at 0x93000000
+ Loading Kernel Image ... OK
+ Using Device Tree in place at 0000000093000000, end 000000009300c4f5
+
+Starting kernel ...
+
+[ 0.000000] Booting Linux on physical CPU 0x0
+[ 0.000000] Linux version 4.11.3-30039-g5a922a1 (jramirez@igloo) (gcc version 6.3.1 20170404 (Linaro GCC 6.3-2017.05) ) #1 SMP PREEMPT Wed Oct 18 10:21:11 CEST 2017
+[ 0.000000] Boot CPU: AArch64 Processor [511f2112]
+[ 0.000000] earlycon: msm_serial_dm0 at MMIO 0x00000000075b0000 (options '')
+[ 0.000000] bootconsole [msm_serial_dm0] enabled
+[ 0.000000] efi: Getting EFI parameters from FDT:
+[ 0.000000] efi: UEFI not found.
+[ 0.000000] OF: reserved mem: OVERLAP DETECTED!
+[ 0.000000] adsp@8ea00000 (0x000000008ea00000--0x0000000090400000) overlaps with gpu@8f200000 (0x000000008f200000--0x000000008f300000)
+[ 0.000000] Reserved memory: created DMA memory pool at 0x000000008f200000, size 1 MiB
+[ 0.000000] OF: reserved mem: initialized node gpu@8f200000, compatible id shared-dma-pool
+[ 0.000000] Reserved memory: created DMA memory pool at 0x0000000090400000, size 8 MiB
+[ 0.000000] OF: reserved mem: initialized node venus@90400000, compatible id shared-dma-pool
+[ 0.000000] cma: Reserved 128 MiB at 0x00000000b8000000
+[ 0.000000] NUMA: No NUMA configuration found
+[ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000bfffffff]
+[ 0.000000] NUMA: Adding memblock [0x80000000 - 0x857fffff] on node 0
+[ 0.000000] NUMA: Adding memblock [0x91800000 - 0xbfffffff] on node 0
+[ 0.000000] NUMA: Initmem setup node 0 [mem 0x80000000-0xbfffffff]
+[ 0.000000] NUMA: NODE_DATA [mem 0xb7fb6680-0xb7fb817f]
+[ 0.000000] Zone ranges:
+[ 0.000000] DMA [mem 0x0000000080000000-0x00000000bfffffff]
+[ 0.000000] Normal empty
+[ 0.000000] Movable zone start for each node
+[ 0.000000] Early memory node ranges
+[ 0.000000] node 0: [mem 0x0000000080000000-0x00000000857fffff]
+[ 0.000000] node 0: [mem 0x0000000091800000-0x00000000bfffffff]
+[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000bfffffff]
+[ 0.000000] psci: probing for conduit method from DT.
+[ 0.000000] psci: PSCIv1.0 detected in firmware.
+[ 0.000000] psci: Using standard PSCI v0.2 function IDs
+[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
+[ 0.000000] percpu: Embedded 23 pages/cpu @ffff8000de9a3000 s57240 r8192 d28776 u94208
+[ 0.000000] pcpu-alloc: s57240 r8192 d28776 u94208 alloc=23*4096
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+[ 0.000000] Detected PIPT I-cache on CPU0
+[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 720293
+[ 0.000000] Policy zone: Normal
+[ 0.000000] Kernel command line: root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0
+console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange a
+ndroidboot.ver0
+[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
+[ 0.000000] software IO TLB [mem 0xd3fff000-0xd7fff000] (64MB) mapped at [ffff800053fff000-ffff800057ffefff]
+[ 0.000000] Memory: 2644172K/2926908K available (11196K kernel code, 1470K rwdata, 5132K rodata, 1088K init, 449K bss, 151664K reserved, 131072K cma-reser
+ved)
+[ 0.000000] Virtual kernel memory layout:
+[ 0.000000] modules : 0xffff000000000000 - 0xffff000008000000 ( 128 MB)
+[ 0.000000] vmalloc : 0xffff000008000000 - 0xffff7dffbfff0000 (129022 GB)
+[ 0.000000] .text : 0xffff000008080000 - 0xffff000008b70000 ( 11200 KB)
+[ 0.000000] .rodata : 0xffff000008b70000 - 0xffff000009080000 ( 5184 KB)
+[ 0.000000] .init : 0xffff000009080000 - 0xffff000009190000 ( 1088 KB)
+[ 0.000000] .data : 0xffff000009190000 - 0xffff0000092ffa00 ( 1471 KB)
+[ 0.000000] .bss : 0xffff0000092ffa00 - 0xffff00000937014c ( 450 KB)
+[ 0.000000] fixed : 0xffff7dfffe7fd000 - 0xffff7dfffec00000 ( 4108 KB)
+[ 0.000000] PCI I/O : 0xffff7dfffee00000 - 0xffff7dffffe00000 ( 16 MB)
+[ 0.000000] vmemmap : 0xffff7e0000000000 - 0xffff800000000000 ( 2048 GB maximum)
+[ 0.000000] 0xffff7e0000000000 - 0xffff7e00037a93c0 ( 55 MB actual)
+[ 0.000000] memory : 0xffff800000000000 - 0xffff8000dea4f000 ( 3562 MB)
+[ 0.000000] SLUB: HWalign=128, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[ 0.000000] Preemptible hierarchical RCU implementation.
+[ 0.000000] Build-time adjustment of leaf fanout to 64.
+[ 0.000000] RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0
+[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000009c00000
+[ 0.000000] GICv2m: range[mem 0x09bd0000-0x09bd0fff], SPI[544:639]
+[ 0.000000] arm_arch_timer: Architected cp15 and mmio timer(s) running at 19.20MHz (virt/virt).
+[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns
+[ 0.000002] sched_clock: 56 bits at 19MHz, resolution 52ns, wraps every 4398046511078ns
+
+[....]
+
+
+Some kernel information:
+
+root@linaro-developer:~# cat /proc/cpuinfo
+processor : 0
+BogoMIPS : 38.40
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
+CPU implementer : 0x51
+CPU architecture: 8
+CPU variant : 0x1
+CPU part : 0x211
+CPU revision : 2
+
+processor : 1
+BogoMIPS : 38.40
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
+CPU implementer : 0x51
+CPU architecture: 8
+CPU variant : 0x1
+CPU part : 0x211
+CPU revision : 2
+
+processor : 2
+BogoMIPS : 38.40
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
+CPU implementer : 0x51
+CPU architecture: 8
+CPU variant : 0x1
+CPU part : 0x205
+CPU revision : 2
+
+processor : 3
+BogoMIPS : 38.40
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
+CPU implementer : 0x51
+CPU architecture: 8
+CPU variant : 0x1
+CPU part : 0x205
+CPU revision : 2
+
+root@linaro-developer:~# uname -a
+Linux linaro-developer 4.11.3-30039-g5a922a1 #1 SMP PREEMPT Wed Oct 18 10:21:11 CEST 2017 aarch64 GNU/Linux
+
+root@linaro-developer:~# cat /proc/cmdline
+root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0 console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.ver0
+
+root@linaro-developer:~# cat /proc/meminfo
+MemTotal: 2776332 kB
+MemFree: 2593696 kB
+MemAvailable: 2561432 kB
+Buffers: 0 kB
+Cached: 94744 kB
+SwapCached: 0 kB
+Active: 43888 kB
+Inactive: 72972 kB
+Active(anon): 22968 kB
+Inactive(anon): 24616 kB
+Active(file): 20920 kB
+Inactive(file): 48356 kB
+Unevictable: 0 kB
+Mlocked: 0 kB
+SwapTotal: 0 kB
+SwapFree: 0 kB
+Dirty: 0 kB
+Writeback: 0 kB
+AnonPages: 22120 kB
+Mapped: 29284 kB
+Shmem: 25468 kB
+Slab: 32876 kB
+SReclaimable: 12924 kB
+SUnreclaim: 19952 kB
+KernelStack: 2144 kB
+PageTables: 928 kB
+NFS_Unstable: 0 kB
+Bounce: 0 kB
+WritebackTmp: 0 kB
+CommitLimit: 1388164 kB
+Committed_AS: 204192 kB
+VmallocTotal: 135290290112 kB
+VmallocUsed: 0 kB
+VmallocChunk: 0 kB
+AnonHugePages: 2048 kB
+ShmemHugePages: 0 kB
+ShmemPmdMapped: 0 kB
+CmaTotal: 131072 kB
+CmaFree: 130356 kB
+HugePages_Total: 0
+HugePages_Free: 0
+HugePages_Rsvd: 0
+HugePages_Surp: 0
+Hugepagesize: 2048 kB
--- /dev/null
+/*
+ * Override linker script for fastboot-readable images
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_arm64_header)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(8);
+ .text :
+ {
+ *(.__image_copy_start)
+ board/qualcomm/dragonboard820c/head.o (.text*)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(8);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(8);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(8);
+
+ . = .;
+
+ . = ALIGN(8);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(8);
+
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(efi_runtime_text)
+ *(efi_runtime_data)
+ __efi_runtime_stop = .;
+ }
+
+ .efi_runtime_rel : {
+ __efi_runtime_rel_start = .;
+ *(.relaefi_runtime_text)
+ *(.relaefi_runtime_data)
+ __efi_runtime_rel_stop = .;
+ }
+
+ . = ALIGN(8);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ . = ALIGN(8);
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rela.dyn : {
+ *(.rela*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ _end = .;
+
+ . = ALIGN(8);
+
+ .bss_start : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss : {
+ *(.bss*)
+ . = ALIGN(8);
+ }
+
+ .bss_end : {
+ KEEP(*(.__bss_end));
+ }
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
#
obj-y += arndale_spl.o
-
-ifndef CONFIG_SPL_BUILD
obj-y += arndale.o
-endif
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SPL_BUILD
obj-y += espresso7420.o
-endif
--- /dev/null
+if TARGET_SKSIMX6
+
+config SYS_BOARD
+ default "sksimx6"
+
+config SYS_VENDOR
+ default "sks-kinkel"
+
+config SYS_CONFIG_NAME
+ default "sksimx6"
+endif
--- /dev/null
+SKS-Kinkel sksimx6
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/sks-kinkel/sksimx6/
+F: include/configs/sksimx6.h
+F: configs/sksimx6_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-y := sksimx6.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <micrel.h>
+
+#include <common.h>
+#include <malloc.h>
+#include <fuse.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const gpios_pads[] = {
+ IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+iomux_v3_cfg_t const enet_pads1[] = {
+ /* pin 35 - 1 (PHY_AD2) on reset */
+ IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* pin 32 - 1 - (MODE0) all */
+ IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* pin 31 - 1 - (MODE1) all */
+ IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* pin 28 - 1 - (MODE2) all */
+ IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* pin 27 - 1 - (MODE3) all */
+ IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* pin 42 PHY nRST */
+ IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+
+ /* min rx data delay */
+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ /* min tx data delay */
+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ /* max rx/tx clock delay, min rx/tx control */
+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#define ENET_NRST IMX_GPIO_NR(1, 25)
+
+void setup_iomux_enet(void)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+
+}
+
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ setup_iomux_enet();
+
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return -EINVAL;
+ /* scan phy */
+ phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
+ PHY_INTERFACE_MODE_RGMII);
+
+ if (!phydev) {
+ ret = -EINVAL;
+ goto free_bus;
+ }
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret)
+ goto free_phydev;
+
+ return 0;
+
+free_phydev:
+ free(phydev);
+free_bus:
+ free(bus);
+ return ret;
+}
+
+int board_early_init_f(void)
+{
+ SETUP_IOMUX_PADS(uart1_pads);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ /* Take in reset the ATMega processor */
+ SETUP_IOMUX_PADS(gpios_pads);
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC2_BASE_ADDR, 0},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+ ret = 1;
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev \n");
+ return ret;
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+
+/*
+ * Driving strength:
+ * 0x30 == 40 Ohm
+ * 0x28 == 48 Ohm
+ */
+#define IMX6SDL_DRIVE_STRENGTH 0x230
+
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_cas = IMX6SDL_DRIVE_STRENGTH,
+ .dram_ras = IMX6SDL_DRIVE_STRENGTH,
+ .dram_reset = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+ /* quad = 1066, duallite = 800 */
+ .mem_speed = 1066,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+ .SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x0043004E,
+ .p0_mpwldectrl1 = 0x003D003F,
+ .p1_mpwldectrl0 = 0x00230021,
+ .p1_mpwldectrl1 = 0x0028003E,
+ .p0_mpdgctrl0 = 0x42580250,
+ .p0_mpdgctrl1 = 0x0238023C,
+ .p1_mpdgctrl0 = 0x422C0238,
+ .p1_mpdgctrl1 = 0x02180228,
+ .p0_mprddlctl = 0x44464A46,
+ .p1_mprddlctl = 0x44464A42,
+ .p0_mpwrdlctl = 0x36343236,
+ .p1_mpwrdlctl = 0x36343230,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_qdl = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 1,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+ .refsel = 1, /* Refresh cycles at 32KHz */
+ .refr = 7, /* 8 refresh commands per refresh cycle */
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* set the default clock gate to save power */
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6DL)) {
+ mt41k128m16jt_125.mem_speed = 800;
+ mem_qdl.rtt_nom = 1;
+ mem_qdl.rtt_wr = 1;
+
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
+ } else {
+ printf("Wrong CPU for this board\n");
+ return;
+ }
+
+ udelay(100);
+
+#ifdef CONFIG_MX6_DDRCAL
+
+ /* Perform DDR DRAM calibration */
+ mmdc_do_write_level_calibration(&mem_qdl);
+ mmdc_do_dqs_calibration(&mem_qdl);
+#endif
+}
+
+static void check_bootcfg(void)
+{
+ u32 val5, val6;
+
+ fuse_sense(0, 5, &val5);
+ fuse_sense(0, 6, &val6);
+ /* Check if boot from MMC */
+ if (val6 & 0x10) {
+ puts("BT_FUSE_SEL already fused, will do nothing\n");
+ return;
+ }
+ fuse_prog(0, 5, 0x00000840);
+ /* BT_FUSE_SEL */
+ fuse_prog(0, 6, 0x00000010);
+
+ do_reset(NULL, 0, 0, NULL);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Set fuses for new boards and reboot if not set */
+ check_bootcfg();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
Please use the correct device node for your setup instead
of "/dev/sdX" here!
+Boot selection:
+---------------
+
+Before powering up the board, boot selection should be done via the SW1 dip
+switch (0: OFF, 1: ON):
+
+ - SPI: 00010
+ - SD/eMMC: 00111
+ - M.2 SSD: 11100
+ - UART: 01001 [1]
+
+[1]: According to SolidRun's manual, 11110 should be used for UART booting on
+ the ClearFog 'Pro' variant.
+ However, this doesn't work (anymore) at least on Rev. 2.1 (but '01001' as
+ mentionend for the 'Base' variant does).
+
Boot from UART:
---------------
Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
to your host.
-Set the SW1 DIP switches to UART boot (0: OFF, 1: ON):
-
- ClearFog Base: 01001
- ClearFog Pro: 11110
+Set the SW1 DIP switches to UART boot (see above).
Run the following command to initiate U-Boot download:
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SPL_BUILD
-obj-y := spear600.o
-endif
+obj-y += spear600.o
#include <common.h>
#include <dm.h>
-#include <stm32_rcc.h>
+
#include <asm/io.h>
-#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/fmc.h>
-#include <dm/platform_data/serial_stm32.h>
-#include <asm/arch/stm32_periph.h>
-#include <asm/arch/stm32_defs.h>
DECLARE_GLOBAL_DATA_PTR;
-const struct stm32_gpio_ctl gpio_ctl_gpout = {
- .mode = STM32_GPIO_MODE_OUT,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_50M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF0
-};
-
-const struct stm32_gpio_ctl gpio_ctl_usart = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_50M,
- .pupd = STM32_GPIO_PUPD_UP,
- .af = STM32_GPIO_USART
-};
-
-static const struct stm32_gpio_dsc usart_gpio[] = {
- {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */
- {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */
-};
-
-int uart_setup_gpio(void)
-{
- int i;
- int rv = 0;
-
- clock_setup(GPIO_A_CLOCK_CFG);
- for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
- rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
- if (rv)
- goto out;
- }
-
-out:
- return rv;
-}
-
-const struct stm32_gpio_ctl gpio_ctl_fmc = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_100M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF12
-};
-
-static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
- /* Chip is LQFP144, see DM00077036.pdf for details */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */
- {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
- {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
-};
-
-static int fmc_setup_gpio(void)
-{
- int rv = 0;
- int i;
-
- clock_setup(GPIO_B_CLOCK_CFG);
- clock_setup(GPIO_C_CLOCK_CFG);
- clock_setup(GPIO_D_CLOCK_CFG);
- clock_setup(GPIO_E_CLOCK_CFG);
- clock_setup(GPIO_F_CLOCK_CFG);
- clock_setup(GPIO_G_CLOCK_CFG);
-
- for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
- rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
- &gpio_ctl_fmc);
- if (rv)
- goto out;
- }
-
-out:
- return rv;
-}
-
-/*
- * STM32 RCC FMC specific definitions
- */
-#define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */
-
-static inline u32 _ns2clk(u32 ns, u32 freq)
-{
- u32 tmp = freq/1000000;
- return (tmp * ns) / 1000;
-}
-
-#define NS2CLK(ns) (_ns2clk(ns, freq))
-
-/*
- * Following are timings for IS42S16400J, from corresponding datasheet
- */
-#define SDRAM_CAS 3 /* 3 cycles */
-#define SDRAM_NB 1 /* Number of banks */
-#define SDRAM_MWID 1 /* 16 bit memory */
-
-#define SDRAM_NR 0x1 /* 12-bit row */
-#define SDRAM_NC 0x0 /* 8-bit col */
-#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
-#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
-
-#define SDRAM_TRRD (NS2CLK(14) - 1)
-#define SDRAM_TRCD (NS2CLK(15) - 1)
-#define SDRAM_TRP (NS2CLK(15) - 1)
-#define SDRAM_TRAS (NS2CLK(42) - 1)
-#define SDRAM_TRC (NS2CLK(63) - 1)
-#define SDRAM_TRFC (NS2CLK(63) - 1)
-#define SDRAM_TCDL (1 - 1)
-#define SDRAM_TRDL (2 - 1)
-#define SDRAM_TBDL (1 - 1)
-#define SDRAM_TREF 1386
-#define SDRAM_TCCD (1 - 1)
-
-#define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */
-#define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */
-
-/* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */
-#define SDRAM_TWR max(\
- (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \
- (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\
-)
-
-#define SDRAM_MODE_BL_SHIFT 0
-#define SDRAM_MODE_CAS_SHIFT 4
-#define SDRAM_MODE_BL 0
-#define SDRAM_MODE_CAS SDRAM_CAS
-
int dram_init(void)
{
- u32 freq;
int rv;
+ struct udevice *dev;
- rv = fmc_setup_gpio();
- if (rv)
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
return rv;
+ }
- setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
-
- /*
- * Get frequency for NS2CLK calculation.
- */
- freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
-
- writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
- | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
- | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
- &STM32_SDRAM_FMC->sdcr1);
-
- writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
- | SDRAM_CAS << FMC_SDCR_CAS_SHIFT
- | SDRAM_NB << FMC_SDCR_NB_SHIFT
- | SDRAM_MWID << FMC_SDCR_MWID_SHIFT
- | SDRAM_NR << FMC_SDCR_NR_SHIFT
- | SDRAM_NC << FMC_SDCR_NC_SHIFT
- | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
- | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
- &STM32_SDRAM_FMC->sdcr2);
-
- writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT
- | SDRAM_TRC << FMC_SDTR_TRC_SHIFT,
- &STM32_SDRAM_FMC->sdtr1);
-
- writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
- | SDRAM_TRP << FMC_SDTR_TRP_SHIFT
- | SDRAM_TWR << FMC_SDTR_TWR_SHIFT
- | SDRAM_TRC << FMC_SDTR_TRC_SHIFT
- | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
- | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
- | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
- &STM32_SDRAM_FMC->sdtr2);
-
- writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK,
- &STM32_SDRAM_FMC->sdcmr);
-
- udelay(200); /* 200 us delay, page 10, "Power-Up" */
- FMC_BUSY_WAIT();
-
- writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE,
- &STM32_SDRAM_FMC->sdcmr);
-
- udelay(100);
- FMC_BUSY_WAIT();
-
- writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH
- | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
-
- udelay(100);
- FMC_BUSY_WAIT();
-
- writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
- | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
- << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
- &STM32_SDRAM_FMC->sdcmr);
-
- udelay(100);
-
- FMC_BUSY_WAIT();
-
- writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL,
- &STM32_SDRAM_FMC->sdcmr);
-
- FMC_BUSY_WAIT();
-
- /* Refresh timer */
- writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
-
- /*
- * Fill in global info with description of SRAM configuration
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
-
- gd->ram_size = CONFIG_SYS_RAM_SIZE;
+ if (fdtdec_setup_memory_size() != 0)
+ rv = -EINVAL;
return rv;
}
-static const struct stm32_serial_platdata serial_platdata = {
- .base = (struct stm32_usart *)STM32_USART1_BASE,
-};
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
-U_BOOT_DEVICE(stm32_serials) = {
- .name = "serial_stm32",
- .platdata = &serial_platdata,
-};
+ return 0;
+}
u32 get_board_rev(void)
{
int board_early_init_f(void)
{
- int res;
-
- configure_clocks();
-
- res = uart_setup_gpio();
- if (res)
- return res;
- clock_setup(USART1_CLOCK_CFG);
-
return 0;
}
--- /dev/null
+if TARGET_STM32F469_DISCOVERY
+
+config SYS_BOARD
+ string
+ default "stm32f469-discovery"
+
+config SYS_VENDOR
+ string
+ default "st"
+
+config SYS_SOC
+ string
+ default "stm32f4"
+
+config SYS_CONFIG_NAME
+ string
+ default "stm32f469-discovery"
+
+endif
--- /dev/null
+STM32F469-DISCOVERY BOARD
+M: Patrice Chotard <patrice.chotard@st.com>
+S: Maintained
+F: board/st/stm32f469-discovery/
+F: include/configs/stm32f469-discovery.h
+F: configs/stm32f469-discovery_defconfig
--- /dev/null
+#
+# Copyright (C) STMicroelectronics SA 2017
+# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := stm32f469-discovery.o
--- /dev/null
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int rv;
+ struct udevice *dev;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+ }
+
+ if (fdtdec_setup_memory_size() != 0)
+ rv = -EINVAL;
+
+ return rv;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ char serialno[25];
+ u32 u_id_low, u_id_mid, u_id_high;
+
+ if (!env_get("serial#")) {
+ u_id_low = readl(&STM32_U_ID->u_id_low);
+ u_id_mid = readl(&STM32_U_ID->u_id_mid);
+ u_id_high = readl(&STM32_U_ID->u_id_high);
+ sprintf(serialno, "%08x%08x%08x",
+ u_id_high, u_id_mid, u_id_low);
+ env_set("serial#", serialno);
+ }
+
+ return 0;
+}
+#endif
S: Maintained
F: configs/MSI_Primo81_defconfig
+LIBRETECH ALL-H3-CC H3 BOARD
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/libretech_all_h3_cc_h3_defconfig
+
NANOPI-M1 BOARD
M: Mylène Josserand <mylene.josserand@free-electrons.com>
S: Maintained
F: configs/Sunchip_CX-A99_defconfig
W: https://linux-sunxi.org/Sunchip_CX-A99
+TBS A711 BOARD
+M: Maxime Ripard <maxime.ripard@free-electrons.com>
+S: Maintained
+F: configs/tbs_a711_defconfig
+
WEXLER-TAB7200 BOARD
M: Aleksei Mamlin <mamlinav@gmail.com>
S: Maintained
#address-cells = <1>;
images {
- uboot@1 {
+ uboot {
description = "U-Boot (64-bit)";
data = /incbin/("u-boot-nodtb.bin");
type = "standalone";
compression = "none";
load = <0x4a000000>;
};
- atf@1 {
+ atf {
description = "ARM Trusted Firmware";
data = /incbin/("$BL31");
type = "firmware";
for dtname in $*
do
cat << __FDT_IMAGE_EOF
- fdt@$cnt {
+ fdt_$cnt {
description = "$(basename $dtname .dtb)";
data = /incbin/("$dtname");
type = "flat_dt";
cat << __CONF_HEADER_EOF
};
configurations {
- default = "config@1";
+ default = "config_1";
__CONF_HEADER_EOF
for dtname in $*
do
cat << __CONF_SECTION_EOF
- config@$cnt {
+ config_$cnt {
description = "$(basename $dtname .dtb)";
- firmware = "uboot@1";
- loadables = "atf@1";
- fdt = "fdt@$cnt";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt_$cnt";
};
__CONF_SECTION_EOF
cnt=$((cnt+1))
#define board_is_am572x_evm_reva3() \
(board_ti_is("AM572PM_") && \
!strncmp("A.30", board_ti_get_rev(), 3))
+#define board_is_am574x_idk() board_ti_is("AM574IDK")
#define board_is_am572x_idk() board_ti_is("AM572IDK")
#define board_is_am571x_idk() board_ti_is("AM571IDK")
.is_ma_present = 0x1
};
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+ .dmm_lisa_map_2 = 0xc0600200,
+ .dmm_lisa_map_3 = 0x80600100,
+ .is_ma_present = 0x1
+};
+
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
if (board_is_am571x_idk())
*dmm_lisa_regs = &am571x_idk_lisa_regs;
+ else if (board_is_am574x_idk())
+ *dmm_lisa_regs = &am574x_idk_lisa_regs;
else
*dmm_lisa_regs = &beagle_x15_lisa_regs;
}
.ref_ctrl = 0x0000514d,
.ref_ctrl_final = 0x0000144a,
.sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x40b37fe3,
- .sdram_tim3 = 0x409f8ada,
+ .sdram_tim2 = 0x30b37fe3,
+ .sdram_tim3 = 0x409f8ad8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
+ .sdram_config_init = 0x61863332,
+ .sdram_config = 0x61863332,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x0000514d,
+ .ref_ctrl_final = 0x0000144a,
+ .sdram_tim1 = 0xd333887c,
+ .sdram_tim2 = 0x30b37fe3,
+ .sdram_tim3 = 0x409f8ad8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400f,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400f,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305,
+ .emif_ecc_ctrl_reg = 0xD0000001,
+ .emif_ecc_address_range_1 = 0x3FFF0000,
+ .emif_ecc_address_range_2 = 0x00000000
+};
+
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
switch (emif_nr) {
case 1:
if (board_is_am571x_idk())
*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+ else if (board_is_am574x_idk())
+ *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
else
*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
break;
case 2:
- *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+ if (board_is_am574x_idk())
+ *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+ else
+ *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
break;
}
}
bname = "BeagleBoard X15";
else if (board_is_am572x_evm())
bname = "AM572x EVM";
+ else if (board_is_am574x_idk())
+ bname = "AM574x IDK";
else if (board_is_am572x_idk())
bname = "AM572x IDK";
else if (board_is_am571x_idk())
name = "am57xx_evm_reva3";
else
name = "am57xx_evm";
+ } else if (board_is_am574x_idk()) {
+ name = "am574x_idk";
} else if (board_is_am572x_idk()) {
name = "am572x_idk";
} else if (board_is_am571x_idk()) {
void vcores_init(void)
{
- if (board_is_am572x_idk())
+ if (board_is_am572x_idk() || board_is_am574x_idk())
*omap_vcores = &am572x_idk_volts;
else if (board_is_am571x_idk())
*omap_vcores = &am571x_idk_volts;
*prcm = &dra7xx_prcm;
if (is_dra72x())
*dplls_data = &dra72x_dplls;
+ else if (is_dra76x())
+ *dplls_data = &dra76x_dplls;
else
*dplls_data = &dra7xx_dplls;
*ctrl = &dra7xx_ctrl;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
iod = iodelay_cfg_array_am572x_idk;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+ } else if (board_is_am574x_idk()) {
+ pconf = core_padconf_array_essential_am574x_idk;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
+ iod = iodelay_cfg_array_am574x_idk;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
} else if (board_is_am571x_idk()) {
pconf = core_padconf_array_essential_am571x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
writel(ctrl_val, (*ctrl)->control_core_control_io1);
/* The phy address for the AM57xx IDK are different than x15 */
- if (board_is_am572x_idk() || board_is_am571x_idk()) {
+ if (board_is_am572x_idk() || board_is_am571x_idk() ||
+ board_is_am574x_idk()) {
cpsw_data.slave_data[0].phy_addr = 0;
cpsw_data.slave_data[1].phy_addr = 1;
}
return 0;
} else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
return 0;
+ } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
+ return 0;
} else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
return 0;
}
{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
};
+const struct pad_conf_entry core_padconf_array_essential_am574x_idk[] = {
+ {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
+ {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
+ {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
+ {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
+ {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
+ {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
+ {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
+ {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
+ {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
+ {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
+ {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
+ {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
+ {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
+ {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+ {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
+ {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
+ {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */
+ {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */
+ {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
+ {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */
+ {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */
+ {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */
+ {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */
+ {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */
+ {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
+ {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */
+ {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */
+ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
+ {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
+ {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */
+ {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
+ {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
+ {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */
+ {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */
+ {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
+ {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
+ {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
+ {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
+ {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
+ {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
+ {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
+ {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
+ {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
+ {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
+ {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
+ {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
+ {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
+ {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
+ {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
+ {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
+ {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
+ {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
+ {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
+ {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
+ {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
+ {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
+ {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
+ {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
+ {MCASP2_AXR4, (M14 | PIN_INPUT)}, /* mcasp2_axr4.gpio1_4 */
+ {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
+ {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
+ {MCASP2_AXR7, (M14 | PIN_INPUT)}, /* mcasp2_axr7.gpio1_5 */
+ {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
+ {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
+ {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
+ {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
+ {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */
+ {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
+ {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
+ {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
+ {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
+ {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
+ {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
+ {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
+ {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
+ {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
+ {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
+ {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
+ {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
+ {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
+ {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
+ {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
+ {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
+ {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
+ {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
+ {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
+ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
+ {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
+ {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
+ {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
+ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
+ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
+ {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
+ {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */
+ {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
+ {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
+ {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
+ {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
+ {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
+ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
+ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
+ {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
+ {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
+ {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
+ {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
+ {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
+ {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
+ {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
+ {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
+ {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
+ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
+};
+
const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
{GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
{GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
{0x0CEC, 2739, 0}, /* CFG_VOUT1_VSYNC_OUT */
};
+const struct iodelay_cfg_entry iodelay_cfg_array_am574x_idk[] = {
+ {0x0114, 2199, 621}, /* CFG_GPMC_A0_IN */
+ {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
+ {0x012C, 2133, 859}, /* CFG_GPMC_A11_IN */
+ {0x0138, 2258, 562}, /* CFG_GPMC_A12_IN */
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0198, 1989, 612}, /* CFG_GPMC_A1_IN */
+ {0x0204, 2218, 912}, /* CFG_GPMC_A2_IN */
+ {0x0210, 2168, 963}, /* CFG_GPMC_A3_IN */
+ {0x021C, 2196, 813}, /* CFG_GPMC_A4_IN */
+ {0x0228, 2082, 782}, /* CFG_GPMC_A5_IN */
+ {0x0234, 2098, 407}, /* CFG_GPMC_A6_IN */
+ {0x0240, 2343, 585}, /* CFG_GPMC_A7_IN */
+ {0x024C, 2030, 685}, /* CFG_GPMC_A8_IN */
+ {0x0258, 2116, 832}, /* CFG_GPMC_A9_IN */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x0590, 1000, 3900}, /* CFG_MCASP5_ACLKX_OUT */
+ {0x05AC, 1000, 3800}, /* CFG_MCASP5_FSX_IN */
+ {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */
+ {0x0B30, 0, 200}, /* CFG_VIN2A_D5_OUT */
+ {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */
+ {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */
+ {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */
+ {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */
+ {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */
+ {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */
+ {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */
+ {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */
+ {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */
+ {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */
+ {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */
+ {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */
+ {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */
+ {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */
+ {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */
+ {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */
+ {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */
+ {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */
+ {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */
+ {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */
+ {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */
+ {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */
+ {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */
+ {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */
+ {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */
+ {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
+ {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
+ {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */
+};
+
const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
{0x0114, 1861, 901}, /* CFG_GPMC_A0_IN */
{0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
return 0;
}
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
/*
* Routine: get_board_revision
* Description: Detect if we are running on a Beagle revision Ax/Bx,
break;
}
break;
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
if (emif_nr == 1)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
ram_size = board_ti_get_emif_size();
switch (omap_revision()) {
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
case DRA752_ES1_0:
case DRA752_ES1_1:
name = "dra71x";
else
name = "dra72x";
- } else if (is_dra76x()) {
- name = "dra76x";
+ } else if (is_dra76x_abz()) {
+ name = "dra76x_abz";
+ } else if (is_dra76x_acd()) {
+ name = "dra76x_acd";
} else {
name = "dra7xx";
}
iodelay = dra742_es1_1_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
break;
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
pads = dra76x_core_padconf_array;
npads = ARRAY_SIZE(dra76x_core_padconf_array);
break;
default:
case DRA752_ES2_0:
+ case DRA762_ABZ_ES1_0:
pads = dra74x_core_padconf_array;
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es2_0_iodelay_cfg_array;
do_set_mux32((*ctrl)->control_padconf_core_base,
delta_pads, delta_npads);
+ if (is_dra76x())
+ /* Set mux for MCAN instead of DCAN1 */
+ clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
+ MCAN_SEL_ALT_MASK, MCAN_SEL);
+
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
err:
} else if (!strcmp(name, "dra72-evm")) {
return 0;
}
- } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
+ } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
return 0;
- } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
+ } else if (!is_dra72x() && !is_dra76x_acd() &&
+ !strcmp(name, "dra7-evm")) {
return 0;
}
{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
{WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */
{WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */
- {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */
+ {WAKEUP2, (M14 | PIN_INPUT)}, /* N/A.gpio1_2 */
{WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */
};
{
return board_ti_is("66AK2GGP");
}
+static inline int board_is_k2g_g1(void)
+{
+ return board_ti_is("66AK2GG1");
+}
static inline int board_is_k2g_ice(void)
{
return board_ti_is("66AK2GIC");
return clk_freq;
}
-static int arm_speeds[DEVSPEED_NUMSPDS] = {
+int speeds[DEVSPEED_NUMSPDS] = {
SPD400,
SPD600,
SPD800,
[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
};
-static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
+static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
};
+static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
+ [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
+ [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
+ [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
+ [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
+};
+
struct pll_init_data *get_pll_init_data(int pll)
{
int speed;
data = &main_pll_config[sysclk_index][speed];
break;
case TETRIS_PLL:
- speed = get_max_arm_speed(arm_speeds);
+ speed = get_max_arm_speed(speeds);
data = &tetris_pll_config[sysclk_index][speed];
break;
case NSS_PLL:
data = &uart_pll_config[sysclk_index];
break;
case DDR3_PLL:
- data = &ddr3_pll_config[sysclk_index];
+ if (cpu_revision() & CPU_66AK2G1x) {
+ speed = get_max_arm_speed(speeds);
+ if (speed == SPD1000)
+ data = &ddr3_pll_config_1066[sysclk_index];
+ else
+ data = &ddr3_pll_config_800[sysclk_index];
+ } else {
+ data = &ddr3_pll_config_800[sysclk_index];
+ }
break;
default:
data = NULL;
return -1;
}
- if (board_is_k2g_gp())
+ if (board_is_k2g_gp() || board_is_k2g_g1())
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
return 0;
- else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
+ else if (!strcmp(name, "keystone-k2g-evm") &&
+ (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
return 0;
else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
return 0;
k2g_reset_mux_config();
- if (board_is_k2g_gp()) {
+ if (board_is_k2g_gp() || board_is_k2g_g1()) {
/* deassert FLASH_HOLD */
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
BIT(9));
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (board_is_k2g_gp())
env_set("board_name", "66AK2GGP\0");
+ else if (board_is_k2g_g1())
+ env_set("board_name", "66AK2GG1\0");
else if (board_is_k2g_ice())
env_set("board_name", "66AK2GIC\0");
#endif
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
#include "board.h"
/* K2G GP EVM DDR3 Configuration */
-struct ddr3_phy_config ddr3phy_800_2g = {
+static struct ddr3_phy_config ddr3phy_800_2g = {
.pllcr = 0x000DC000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.pir_v2 = 0x00000F81ul,
};
-struct ddr3_emif_config ddr3_800_2g = {
+static struct ddr3_phy_config ddr3phy_1066_2g = {
+ .pllcr = 0x000DC000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0,
+ .ptr3 = 0x0904111Dul,
+ .ptr4 = 0x0859A072ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x6D147744ul,
+ .dtpr1 = 0x32845A80ul,
+ .dtpr2 = 0x50023600ul,
+ .mr0 = 0x00001830ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000000ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F05159ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .datx8_2_mask = 0,
+ .datx8_2_val = 0,
+ .datx8_3_mask = 0,
+ .datx8_3_val = 0,
+ .datx8_4_mask = 0,
+ .datx8_4_val = ((1 << 0)),
+ .datx8_5_mask = DXEN_MASK,
+ .datx8_5_val = 0,
+ .datx8_6_mask = DXEN_MASK,
+ .datx8_6_val = 0,
+ .datx8_7_mask = DXEN_MASK,
+ .datx8_7_val = 0,
+ .datx8_8_mask = DXEN_MASK,
+ .datx8_8_val = 0,
+ .pir_v2 = 0x00000F81ul,
+};
+
+static struct ddr3_emif_config ddr3_800_2g = {
.sdcfg = 0x62005662ul,
.sdtim1 = 0x0A385033ul,
.sdtim2 = 0x00001CA5ul,
.sdrfc = 0x00000C34ul,
};
+static struct ddr3_emif_config ddr3_1066_2g = {
+ .sdcfg = 0x62005662ul,
+ .sdtim1 = 0x0E4C6843ul,
+ .sdtim2 = 0x00001CC6ul,
+ .sdtim3 = 0x323DFF32ul,
+ .sdtim4 = 0x533F08AFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001044ul,
+};
+
/* K2G ICE evm DDR3 Configuration */
-struct ddr3_phy_config ddr3phy_800_512mb = {
+static struct ddr3_phy_config ddr3phy_800_512mb = {
.pllcr = 0x000DC000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
.pir_v2 = 0x00000F81ul,
};
-struct ddr3_emif_config ddr3_800_512mb = {
+static struct ddr3_emif_config ddr3_800_512mb = {
.sdcfg = 0x62006662ul,
.sdtim1 = 0x0A385033ul,
.sdtim2 = 0x00001CA5ul,
{
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
-
- if (board_is_k2g_gp()) {
+ if (board_is_k2g_g1()) {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g);
+ } else if (board_is_k2g_gp()) {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
} else if (board_is_k2g_ice()) {
{
if (!board_ti_was_eeprom_read()) {
configure_pin_mux(k2g_generic_pin_cfg);
- } else if (board_is_k2g_gp()) {
+ } else if (board_is_k2g_gp() || board_is_k2g_g1()) {
configure_pin_mux(k2g_evm_pin_cfg);
} else if (board_is_k2g_ice()) {
configure_pin_mux(k2g_ice_evm_pin_cfg);
#include <common.h>
#include <i2c.h>
+#include <linux/compiler.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
/*#define DEBUG */
/* use Apalis GPIO1 to switch on VPGM, ON: 1 */
-static iomux_v3_cfg_t const pmic_prog_pads[] = {
+static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4)
};
return programmed;
}
-int pf0100_prog(void)
+#ifndef CONFIG_SPL_BUILD
+static int pf0100_prog(void)
{
unsigned char bus = 1;
unsigned char val;
return CMD_RET_SUCCESS;
}
-int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
+static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int ret;
"Program the OTP fuses on the PMIC PF0100",
""
);
+#endif
/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
unsigned pmic_init(void);
-/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
-int pf0100_prog(void);
-
#endif /* PF0100_H_ */
/*#define DEBUG */
/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
-static iomux_v3_cfg_t const pmic_prog_pads[] = {
+static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
};
return programmed;
}
-int pf0100_prog(void)
+#ifndef CONFIG_SPL_BUILD
+static int pf0100_prog(void)
{
unsigned char bus = 1;
unsigned char val;
return CMD_RET_SUCCESS;
}
-int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
+static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int ret;
"Program the OTP fuses on the PMIC PF0100",
""
);
+#endif
/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
unsigned pmic_init(void);
-/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
-int pf0100_prog(void);
-
#endif /* PF0100_H_ */
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
+ setup_qbman_portals();
#endif
print_lbc_regs();
return 0;
help
Enables the command "sdp" which is used to have U-Boot emulating the
Serial Download Protocol (SDP) via USB.
+config CMD_ROCKUSB
+ bool "rockusb"
+ depends on USB_FUNCTION_ROCKUSB
+ help
+ Rockusb protocol is widely used by Rockchip SoC based devices. It can
+ read/write info, image to/from devices. This enable rockusb command
+ support to communication with rockusb device. for more detail about
+ this command, please read doc/README.rockusb.
config CMD_USB_MASS_STORAGE
bool "UMS usb mass storage"
endmenu
+source "cmd/ti/Kconfig"
+
config CMD_BOOTSTAGE
bool "Enable the 'bootstage' command"
depends on BOOTSTAGE
config CMD_EXT2
bool "ext2 command support"
+ select FS_EXT4
help
Enables EXT2 FS command
config CMD_EXT4
bool "ext4 command support"
+ select FS_EXT4
help
Enables EXT4 FS command
config CMD_EXT4_WRITE
depends on CMD_EXT4
bool "ext4 write command support"
+ select EXT4_WRITE
help
Enables EXT4 FS write command
obj-$(CONFIG_CMD_REGINFO) += reginfo.o
obj-$(CONFIG_CMD_REISER) += reiser.o
obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
+obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o
obj-$(CONFIG_SANDBOX) += host.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_CMD_NVME) += nvme.o
obj-y += nvedit.o
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
+obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/
filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";")
return 0;
}
+#elif defined(CONFIG_RISCV)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ bd_t *bd = gd->bd;
+
+ print_num("arch_number", bd->bi_arch_number);
+ print_bi_boot_params(bd);
+ print_bi_dram(bd);
+ print_eth_ip_addr();
+ print_baudrate();
+
+ return 0;
+}
+
#elif defined(CONFIG_ARC)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
efi_obj_list_initalized = 1;
+ /* Initialize EFI driver uclass */
+ efi_driver_init();
+
efi_console_register();
#ifdef CONFIG_PARTITIONS
efi_disk_register();
/* Safe fdt location is at 128MB */
new_fdt_addr = fdt_ram_start + (128 * 1024 * 1024) + fdt_size;
- if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages,
+ if (efi_allocate_pages(1, EFI_RUNTIME_SERVICES_DATA, fdt_pages,
&new_fdt_addr) != EFI_SUCCESS) {
/* If we can't put it there, put it somewhere */
new_fdt_addr = (ulong)memalign(EFI_PAGE_SIZE, fdt_size);
- if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages,
+ if (efi_allocate_pages(1, EFI_RUNTIME_SERVICES_DATA, fdt_pages,
&new_fdt_addr) != EFI_SUCCESS) {
printf("ERROR: Failed to reserve space for FDT\n");
return NULL;
}
static efi_status_t efi_do_enter(
- void *image_handle, struct efi_system_table *st,
- asmlinkage ulong (*entry)(void *image_handle,
+ efi_handle_t image_handle, struct efi_system_table *st,
+ asmlinkage ulong (*entry)(efi_handle_t image_handle,
struct efi_system_table *st))
{
efi_status_t ret = EFI_LOAD_ERROR;
#ifdef CONFIG_ARM64
static efi_status_t efi_run_in_el2(asmlinkage ulong (*entry)(
- void *image_handle, struct efi_system_table *st),
- void *image_handle, struct efi_system_table *st)
+ efi_handle_t image_handle, struct efi_system_table *st),
+ efi_handle_t image_handle, struct efi_system_table *st)
{
/* Enable caches again */
dcache_enable();
struct efi_device_path *memdp = NULL;
ulong ret;
- ulong (*entry)(void *image_handle, struct efi_system_table *st)
+ ulong (*entry)(efi_handle_t image_handle, struct efi_system_table *st)
asmlinkage;
ulong fdt_pages, fdt_size, fdt_start, fdt_end;
const efi_guid_t fdt_guid = EFI_FDT_GUID;
(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
- printf("Tran Speed: %d\n", mmc->tran_speed);
+ printf("Bus Speed: %d\n", mmc->clock);
+#if CONFIG_IS_ENABLED(MMC_VERBOSE)
+ printf("Mode : %s\n", mmc_mode_name(mmc->selected_mode));
+ mmc_dump_capabilities("card capabilities", mmc->card_caps);
+ mmc_dump_capabilities("host capabilities", mmc->host_caps);
+#endif
printf("Rd Block Len: %d\n", mmc->read_bl_len);
printf("%s version %d.%d", IS_SD(mmc) ? "SD" : "MMC",
printf("Bus Width: %d-bit%s\n", mmc->bus_width,
mmc->ddr_mode ? " DDR" : "");
+#if CONFIG_IS_ENABLED(MMC_WRITE)
puts("Erase Group Size: ");
print_size(((u64)mmc->erase_grp_size) << 9, "\n");
+#endif
if (!IS_SD(mmc) && mmc->version >= MMC_VERSION_4_41) {
bool has_enh = (mmc->part_support & ENHNCD_SUPPORT) != 0;
bool usr_enh = has_enh && (mmc->part_attr & EXT_CSD_ENH_USR);
+#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
puts("HC WP Group Size: ");
print_size(((u64)mmc->hc_wp_grp_size) << 9, "\n");
+#endif
puts("User Capacity: ");
print_size(mmc->capacity_user, usr_enh ? " ENH" : "");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
+
+#if CONFIG_IS_ENABLED(MMC_WRITE)
static int do_mmc_write(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
+#endif
+
static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
return CMD_RET_SUCCESS;
}
+#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
static int parse_hwpart_user(struct mmc_hwpart_conf *pconf,
int argc, char * const argv[])
{
return CMD_RET_FAILURE;
}
}
+#endif
#ifdef CONFIG_SUPPORT_EMMC_BOOT
static int do_mmc_bootbus(cmd_tbl_t *cmdtp, int flag,
static cmd_tbl_t cmd_mmc[] = {
U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""),
U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""),
+#if CONFIG_IS_ENABLED(MMC_WRITE)
U_BOOT_CMD_MKENT(write, 4, 0, do_mmc_write, "", ""),
U_BOOT_CMD_MKENT(erase, 3, 0, do_mmc_erase, "", ""),
+#endif
U_BOOT_CMD_MKENT(rescan, 1, 1, do_mmc_rescan, "", ""),
U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""),
U_BOOT_CMD_MKENT(dev, 3, 0, do_mmc_dev, "", ""),
U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""),
+#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
U_BOOT_CMD_MKENT(hwpartition, 28, 0, do_mmc_hwpartition, "", ""),
+#endif
#ifdef CONFIG_SUPPORT_EMMC_BOOT
U_BOOT_CMD_MKENT(bootbus, 5, 0, do_mmc_bootbus, "", ""),
U_BOOT_CMD_MKENT(bootpart-resize, 4, 0, do_mmc_boot_resize, "", ""),
/********************************************************************
* eMMC services
********************************************************************/
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(MMC_WRITE)
static int mmc_burn_image(size_t image_size)
{
struct mmc *mmc;
}
U_BOOT_CMD(pmic, CONFIG_SYS_MAXARGS, 1, do_pmic,
- " operations",
+ "PMIC sub-system",
"list - list pmic devices\n"
"pmic dev [name] - show or [set] operating PMIC device\n"
"pmic dump - dump registers\n"
--- /dev/null
+/*
+ * Copyright (C) 2017 Eddie Cai <eddie.cai.linux@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <g_dnl.h>
+#include <usb.h>
+#include <asm/arch/f_rockusb.h>
+
+static int do_rockusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int controller_index, dev_index;
+ char *usb_controller;
+ char *devtype;
+ char *devnum;
+ int ret;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ usb_controller = argv[1];
+ controller_index = simple_strtoul(usb_controller, NULL, 0);
+
+ if (argc >= 4) {
+ devtype = argv[2];
+ devnum = argv[3];
+ } else {
+ return CMD_RET_USAGE;
+ }
+ dev_index = simple_strtoul(devnum, NULL, 0);
+ rockusb_dev_init(devtype, dev_index);
+
+ ret = board_usb_init(controller_index, USB_INIT_DEVICE);
+ if (ret) {
+ printf("USB init failed: %d\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ g_dnl_clear_detach();
+ ret = g_dnl_register("usb_dnl_rockusb");
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ if (!g_dnl_board_usb_cable_connected()) {
+ puts("\rUSB cable not detected, Command exit.\n");
+ ret = CMD_RET_FAILURE;
+ goto exit;
+ }
+
+ while (1) {
+ if (g_dnl_detach())
+ break;
+ if (ctrlc())
+ break;
+ usb_gadget_handle_interrupts(controller_index);
+ }
+ ret = CMD_RET_SUCCESS;
+
+exit:
+ g_dnl_unregister();
+ g_dnl_clear_detach();
+ board_usb_cleanup(controller_index, USB_INIT_DEVICE);
+
+ return ret;
+}
+
+U_BOOT_CMD(rockusb, 4, 1, do_rockusb,
+ "use the rockusb protocol",
+ "<USB_controller> <devtype> <dev[:part]> e.g. rockusb 0 mmc 0\n"
+);
--- /dev/null
+menu "TI specific command line interface"
+
+config CMD_DDR3
+ bool "command for verifying DDR features"
+ help
+ Support for testing ddr3 on TI platforms. This command
+ supports memory verification, memory comapre and ecc
+ verification if supported.
+
+endmenu
--- /dev/null
+# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj- += dummy.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_DDR3) += ddr3.o
+endif
--- /dev/null
+/*
+ * EMIF: DDR3 test commands
+ *
+ * Copyright (C) 2012-2017 Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/cache.h>
+#include <asm/emif.h>
+#include <common.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ARCH_KEYSTONE
+#include <asm/arch/ddr3.h>
+#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
+#define STACKSIZE (512 << 10) /* 512 KiB */
+
+#define DDR_REMAP_ADDR 0x80000000
+#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
+
+#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
+ STACKSIZE) >> 17) - 2)
+#endif
+
+#define DDR_TEST_BURST_SIZE 1024
+
+static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
+{
+ u32 index_start, value, index;
+
+ index_start = start_address;
+
+ while (1) {
+ /* Write a pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4)
+ __raw_writel(index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4) {
+ value = __raw_readl(index);
+ if (value != index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+
+ if (quick)
+ continue;
+
+ /* Write a pattern for complementary values */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4)
+ __raw_writel((u32)~index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4) {
+ value = __raw_readl(index);
+ if (value != ~index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+
+ /* Write a pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 2)
+ __raw_writew((u16)index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 2) {
+ value = __raw_readw(index);
+ if (value != (u16)index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readw(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+
+ /* Write a pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 1)
+ __raw_writeb((u8)index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 1) {
+ value = __raw_readb(index);
+ if (value != (u8)index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readb(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+ }
+
+ puts("ddr memory test PASSED!\n");
+ return 0;
+}
+
+static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
+{
+ u32 index, value, index2, value2;
+
+ for (index = address1, index2 = address2;
+ index < address1 + size;
+ index += 4, index2 += 4) {
+ value = __raw_readl(index);
+ value2 = __raw_readl(index2);
+
+ if (value != value2) {
+ printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
+ index, value, index2, value2);
+
+ return -1;
+ }
+ }
+
+ puts("ddr memory compare PASSED!\n");
+ return 0;
+}
+
+static void ddr_check_ecc_status(void)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 err_1b = readl(&emif->emif_1b_ecc_err_cnt);
+ u32 int_status = readl(&emif->emif_irqstatus_raw_sys);
+ int ecc_test = 0;
+ char *env;
+
+ env = env_get("ecc_test");
+ if (env)
+ ecc_test = simple_strtol(env, NULL, 0);
+
+ puts("ECC test Status:\n");
+ if (int_status & EMIF_INT_WR_ECC_ERR_SYS_MASK)
+ puts("\tECC test: DDR ECC write error interrupted\n");
+
+ if (int_status & EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK)
+ if (!ecc_test)
+ panic("\tECC test: DDR ECC 2-bit error interrupted");
+
+ if (int_status & EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK)
+ puts("\tECC test: DDR ECC 1-bit error interrupted\n");
+
+ if (err_1b)
+ printf("\tECC test: 1-bit ECC err count: 0x%x\n", err_1b);
+}
+
+static int ddr_memory_ecc_err(u32 addr, u32 ecc_err)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
+ u32 val1, val2, val3;
+
+ debug("Disabling D-Cache before ECC test\n");
+ dcache_disable();
+ invalidate_dcache_all();
+
+ puts("Testing DDR ECC:\n");
+ puts("\tECC test: Disabling DDR ECC ...\n");
+ writel(0, &emif->emif_ecc_ctrl_reg);
+
+ val1 = readl(addr);
+ val2 = val1 ^ ecc_err;
+ writel(val2, addr);
+
+ val3 = readl(addr);
+ printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
+ addr, val1, val2, ecc_err, val3);
+
+ puts("\tECC test: Enabling DDR ECC ...\n");
+#ifdef CONFIG_ARCH_KEYSTONE
+ ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
+ writel(ecc_ctrl, EMIF1_BASE + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+ ddr3_enable_ecc(EMIF1_BASE, 1);
+#else
+ writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg);
+#endif
+
+ val1 = readl(addr);
+ printf("\tECC test: addr 0x%x, read data 0x%x\n", addr, val1);
+
+ ddr_check_ecc_status();
+
+ debug("Enabling D-cache back after ECC test\n");
+ enable_caches();
+
+ return 0;
+}
+
+static int is_addr_valid(u32 addr)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 start_addr, end_addr, range, ecc_ctrl;
+
+#ifdef CONFIG_ARCH_KEYSTONE
+ ecc_ctrl = EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK;
+ range = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
+#else
+ ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
+ range = readl(&emif->emif_ecc_address_range_1);
+#endif
+
+ /* Check in ecc address range 1 */
+ if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) {
+ start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
+ + CONFIG_SYS_SDRAM_BASE;
+ end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK)
+ + 0xFFFF;
+ if ((addr >= start_addr) && (addr <= end_addr))
+ /* addr within ecc address range 1 */
+ return 1;
+ }
+
+ /* Check in ecc address range 2 */
+ if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) {
+ range = readl(&emif->emif_ecc_address_range_2);
+ start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
+ + CONFIG_SYS_SDRAM_BASE;
+ end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK)
+ + 0xFFFF;
+ if ((addr >= start_addr) && (addr <= end_addr))
+ /* addr within ecc address range 2 */
+ return 1;
+ }
+
+ return 0;
+}
+
+static int is_ecc_enabled(void)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
+
+ return (ecc_ctrl & EMIF_ECC_CTRL_REG_ECC_EN_MASK) &&
+ (ecc_ctrl & EMIF_ECC_REG_RMW_EN_MASK);
+}
+
+static int do_ddr_test(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ u32 start_addr, end_addr, size, ecc_err;
+
+ if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
+ if (!is_ecc_enabled()) {
+ puts("ECC not enabled. Please Enable ECC any try again\n");
+ return CMD_RET_FAILURE;
+ }
+
+ start_addr = simple_strtoul(argv[2], NULL, 16);
+ ecc_err = simple_strtoul(argv[3], NULL, 16);
+
+ if (!is_addr_valid(start_addr)) {
+ puts("Invalid address. Please enter ECC supported address!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ddr_memory_ecc_err(start_addr, ecc_err);
+ return 0;
+ }
+
+ if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
+ ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
+ return cmd_usage(cmdtp);
+
+ start_addr = simple_strtoul(argv[2], NULL, 16);
+ end_addr = simple_strtoul(argv[3], NULL, 16);
+
+ if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
+ (start_addr > (CONFIG_SYS_SDRAM_BASE +
+ get_effective_memsize() - 1)) ||
+ (end_addr < CONFIG_SYS_SDRAM_BASE) ||
+ (end_addr > (CONFIG_SYS_SDRAM_BASE +
+ get_effective_memsize() - 1)) || (start_addr >= end_addr)) {
+ puts("Invalid start or end address!\n");
+ return cmd_usage(cmdtp);
+ }
+
+ puts("Please wait ...\n");
+ if (argc == 5) {
+ size = simple_strtoul(argv[4], NULL, 16);
+ ddr_memory_compare(start_addr, end_addr, size);
+ } else {
+ ddr_memory_test(start_addr, end_addr, 0);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(ddr, 5, 1, do_ddr_test,
+ "DDR3 test",
+ "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
+ " address to end address\n"
+ "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
+ " compare DDR data of (size) bytes from start address to end\n"
+ " address\n"
+ "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
+ " in DDR data at <addr>, the command will read a 32-bit data\n"
+ " from <addr>, and write (data ^ bit_err) back to <addr>\n"
+);
config DISPLAY_CPUINFO
bool "Display information about the CPU during start up"
- default y if ARM || NIOS2 || X86 || XTENSA
+ default y if ARM || NIOS2 || X86 || XTENSA || M68K
help
Display information about the CPU that U-Boot is running on
when U-Boot starts up. The function print_cpuinfo() is called
obj-y += memsize.o
obj-y += stdio.o
+ifndef CONFIG_SPL_BUILD
# This option is not just y/n - it can have a numeric value
ifdef CONFIG_FASTBOOT_FLASH
obj-y += image-sparse.o
obj-y += fb_nand.o
endif
endif
+endif
ifdef CONFIG_CMD_EEPROM_LAYOUT
obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o
}
#endif
+#if defined(CONFIG_VID)
+__weak int init_func_vid(void)
+{
+ return 0;
+}
+#endif
+
#if defined(CONFIG_HARD_SPI)
static int init_func_spi(void)
{
gd->mon_len = (ulong)&_end - (ulong)_init;
#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
-#elif defined(CONFIG_NDS32) || defined(CONFIG_SH)
+#elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
#elif defined(CONFIG_SYS_MONITOR_BASE)
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
console_init_f, /* stage 1 init of console */
display_options, /* say that we are here */
display_text_info, /* show debugging info if required */
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \
- defined(CONFIG_X86)
+#if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
checkcpu,
#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
#if defined(CONFIG_SYS_I2C)
init_func_i2c,
#endif
+#if defined(CONFIG_VID) && !defined(CONFIG_SPL)
+ init_func_vid,
+#endif
#if defined(CONFIG_HARD_SPI)
init_func_spi,
#endif
{
#ifdef __ARM__
monitor_flash_len = _end - __image_copy_start;
-#elif defined(CONFIG_NDS32)
+#elif defined(CONFIG_NDS32) || defined(CONFIG_RISCV)
monitor_flash_len = (ulong)&_end - (ulong)&_start;
#elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2)
monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
ulong pram = 0;
char memsz[32];
-# ifdef CONFIG_PRAM
pram = env_get_ulong("pram", 10, CONFIG_PRAM);
-# endif
sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram));
env_set("mem", memsz);
#ifdef CONFIG_DM
initr_dm,
#endif
-#if defined(CONFIG_ARM) || defined(CONFIG_NDS32)
+#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV)
board_init, /* Setup chipselects */
#endif
/*
if (multi_hash()) {
struct hash_algo *algo;
- uint8_t output[HASH_MAX_DIGEST_SIZE];
+ u8 *output;
uint8_t vsum[HASH_MAX_DIGEST_SIZE];
void *buf;
return 1;
}
+ output = memalign(ARCH_DMA_MINALIGN,
+ sizeof(uint32_t) * HASH_MAX_DIGEST_SIZE);
+
buf = map_sysmem(addr, len);
algo->hash_func_ws(buf, len, output, algo->chunk_size);
unmap_sysmem(buf);
store_result(algo, output, *argv,
flags & HASH_FLAG_ENV);
}
+ unmap_sysmem(output);
+
}
/* Horrible code size hack for boards that just want crc32 */
/*
* Check subnode name, must be equal to "hash" or "signature".
* Multiple hash/signature nodes require unique unit node
- * names, e.g. hash@1, hash@2, signature@1, signature@2, etc.
+ * names, e.g. hash-1, hash-2, signature-1, signature-2, etc.
*/
name = fit_get_name(fit, noffset, NULL);
if (!strncmp(name, FIT_HASH_NODENAME, strlen(FIT_HASH_NODENAME))) {
/*
* Check subnode name, must be equal to "hash".
* Multiple hash nodes require unique unit node
- * names, e.g. hash@1, hash@2, etc.
+ * names, e.g. hash-1, hash-2, etc.
*/
if (!strncmp(name, FIT_HASH_NODENAME,
strlen(FIT_HASH_NODENAME))) {
*
* / o image-tree
* |-o images
- * | |-o fdt@1
- * | |-o fdt@2
+ * | |-o fdt-1
+ * | |-o fdt-2
* |
* |-o configurations
- * |-o config@1
- * | |-fdt = fdt@1
+ * |-o config-1
+ * | |-fdt = fdt-1
* |
- * |-o config@2
- * |-fdt = fdt@2
+ * |-o config-2
+ * |-fdt = fdt-2
*
* / o U-Boot fdt
* |-compatible = "foo,bar", "bim,bam"
/*
* Each node can generate one region for each sub-node. Allow for
- * 7 sub-nodes (hash@1, signature@1, etc.) and some extra.
+ * 7 sub-nodes (hash-1, signature-1, etc.) and some extra.
*/
max_regions = 20 + count * 7;
struct fdt_region fdt_regions[max_regions];
config SPL_SAVEENV
bool "Support save environment"
depends on SPL_ENV_SUPPORT
+ select SPL_MMC_WRITE if ENV_IS_IN_MMC
help
Enable save environment support in SPL after setenv. By default
the saveenv option is not provided in SPL, but some boards need
this option to build the drivers in drivers/mmc as part of an SPL
build.
+config SPL_MMC_WRITE
+ bool "MMC/SD/SDIO card support for write operations in SPL"
+ depends on SPL_MMC_SUPPORT
+ default n
+ help
+ Enable write access to MMC and SD Cards in SPL
+
+
config SPL_MPC8XXX_INIT_DDR_SUPPORT
bool "Support MPC8XXX DDR init"
help
CONFIG_SCSI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_B53_SWITCH=y
+CONFIG_B53_CPU_PORT=8
+CONFIG_B53_PHY_PORTS=0x1f
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200"
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_PHY_MICREL=y
CONFIG_BAUDRATE=38400
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_RSA=y
CONFIG_LZO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_HCD=y
+CONFIG_USB_AM35X=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_AM35X=y
# CONFIG_FAT_WRITE is not set
CONFIG_BCH=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
# CONFIG_CMD_MISC is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_MISC is not set
CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_MMC is not set
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_CALIMAIN=y
+CONFIG_DA850_LOWLEVEL=y
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_CMD_SF=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
# CONFIG_SPL_OF_LIBFDT is not set
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_CMD_SF=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
# CONFIG_SPL_OF_LIBFDT is not set
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_CMD_SF=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
# CONFIG_SPL_OF_LIBFDT is not set
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run legacy_bootcmd"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_AM35X=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
# CONFIG_FAT_WRITE is not set
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
# CONFIG_FAT_WRITE is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
+CONFIG_DA850_LOWLEVEL=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_PMIC_PM8916=y
CONFIG_MSM_SERIAL=y
CONFIG_SPMI_MSM=y
-CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_PSCI_RESET=y
+CONFIG_OF_SEPARATE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_TARGET_DRAGONBOARD820C=y
+CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
+CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
+CONFIG_USE_BOOTARGS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOOTARGS="console=ttyMSM0,115200n8"
+CONFIG_SYS_PROMPT="dragonboard820c => "
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTEFI=y
+CONFIG_EFI_LOADER=y
+CONFIG_CMD_BOOTEFI_HELLO=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PMIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_MSM_SERIAL=y
+CONFIG_SPMI_MSM=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_DM_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PM8916=y
+CONFIG_PM8916_GPIO=y
+CONFIG_CLK=y
+CONFIG_PSCI_RESET=y
+CONFIG_ENV_IS_IN_EXT4=y
+CONFIG_ENV_EXT4_INTERFACE="mmc"
+CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1"
+CONFIG_ENV_EXT4_FILE="/uboot.env"
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_FS_EXT4=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_STORAGE=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_DAVINCI_SPI=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_MISC is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
CONFIG_DISPLAY_ROCKCHIP_MIPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_BAUDRATE=38400
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_PANIC_HANG=y
CONFIG_SMC911X_32_BIT=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_SMC911X_32_BIT=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_BAUDRATE=38400
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_BAUDRATE=38400
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_DAVINCI_SPI=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_R_I2C_ENABLE=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-libretech-all-h3-cc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012A2G5RDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
+CONFIG_SPL_CRYPTO_SUPPORT=y
+CONFIG_SPL_HASH_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MVEBU_ARMADA_37XX=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MVEBU_ARMADA_37XX=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CMD_FS_GENERIC=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FS_EXT4=y
CONFIG_FS_FAT=y
CONFIG_OF_LIBFDT=y
CONFIG_TARGET_MX6SXSABRESD=y
# CONFIG_CMD_BMODE is not set
CONFIG_NXP_BOARD_REVISION=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_NXP_BOARD_REVISION=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HCD=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
# CONFIG_VGA_AS_SINGLE_DEVICE is not set
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_TARGET_NX25_AE250=y
+CONFIG_DEFAULT_DEVICE_TREE="ae250"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_NDS32=y
+CONFIG_FTSDC010=y
+CONFIG_DM_ETH=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_ATCSPI200_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATCPIT100_TIMER=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ADC=y
CONFIG_ADC_EXYNOS=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_S2MPS11=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_S2MPS11=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_OMAP3_BEAGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+# CONFIG_BLK is not set
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=1
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
+CONFIG_TWL4030_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="TI"
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_FAT_WRITE=y
+CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_BLK is not set
CONFIG_DM_I2C=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
+CONFIG_TWL4030_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="TI"
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_ETHER=y
CONFIG_BCH=y
+# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_SMC911X_32_BIT=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_BOOTDELAY=3
+CONFIG_LOGLEVEL=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_DAVINCI_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
+# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
+# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
+# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETHER=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETHER=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_FAT_WRITE=y
CONFIG_LIB_RAND=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_BAUDRATE=38400
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_ARCH_QEMU=y
+CONFIG_TARGET_QEMU_ARM_64BIT=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_OF_BOARD=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_BLK=y
+# CONFIG_MMC is not set
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_ARM=y
CONFIG_ARM_SMCCC=y
CONFIG_ARCH_QEMU=y
+CONFIG_TARGET_QEMU_ARM_32BIT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_MISC is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_DM_ETH=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_JFFS2=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_BAUDRATE=38400
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_SKSIMX6=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_BOOTDELAY=1
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SILENT_U_BOOT_ONLY=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
+CONFIG_TWL4030_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_DOS_PARTITION=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);"
CONFIG_CMD_UBI=y
CONFIG_ARM=y
CONFIG_STM32=y
+CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
CONFIG_CMD_IMLS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIMER=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_SYS_MALLOC_F_LEN=0xF00
+CONFIG_STM32F4=y
+CONFIG_TARGET_STM32F469_DISCOVERY=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
+CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD_NOR_FLASH=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_DNS=y
CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
-CONFIG_CLK=y
-CONFIG_DM_GPIO=y
-CONFIG_MISC=y
-CONFIG_STM32_RCC=y
-# CONFIG_MMC is not set
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_PINCTRL=y
# CONFIG_PINCTRL_FULL is not set
-CONFIG_PINCTRL_STM32=y
-CONFIG_RAM=y
-CONFIG_STM32_SDRAM=y
-CONFIG_DM_RESET=y
-CONFIG_STM32_RESET=y
-CONFIG_STM32X7_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_NETDEVICES=y
+CONFIG_SH_ETHER=y
CONFIG_BAUDRATE=38400
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
--- /dev/null
+NX25 is Andes CPU IP to adopt RISC-V architecture.
+
+Features
+========
+
+CPU Core
+ - 5-stage in-order execution pipeline
+ - Hardware Multiplier
+ - radix-2/radix-4/radix-16/radix-256/fast
+ - Hardware Divider
+ - Optional branch prediction
+ - Machine mode and optional user mode
+ - Optional performance monitoring
+
+ISA
+ - RV64I base integer instructions
+ - RVC for 16-bit compressed instructions
+ - RVM for multiplication and division instructions
+
+Memory subsystem
+ - I & D local memory
+ - Size: 4KB to 16MB
+ - Memory subsyetem soft-error protection
+ - Protection scheme: parity-checking or error-checking-and-correction (ECC)
+ - Automatic hardware error correction
+
+Bus
+ - Interface Protocol
+ - Synchronous AHB (32-bit/64-bit data-width), or
+ - Synchronous AXI4 (64-bit data-width)
+
+Power management
+ - Wait for interrupt (WFI) mode
+
+Debug
+ - Configurable number of breakpoints: 2/4/8
+ - External Debug Module
+ - AHB slave port
+ - External JTAG debug transport module
+
+Platform Level Interrupt Controller (PLIC)
+ - AHB slave port
+ - Configurable number of interrupts: 1-1023
+ - Configurable number of interrupt priorities: 3/7/15/63/127/255
+ - Configurable number of targets: 1-16
+ - Preempted interrupt priority stack
--- /dev/null
+Andes Technology SoC AE250
+===========================
+
+AE250 is the mainline SoC produced by Andes Technology using NX25 CPU core
+base on RISC-V architecture.
+
+AE250 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+NX25-AE250
+=========
+
+NX25-AE250 is the SoC with AE250 hardcore CPU.
+
+Configurations
+==============
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+ If you want to boot this system from SPI ROM and bypass e-bios (the
+ other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+ in "include/configs/nx25-ae250.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make nx25-ae250_defconfig` in u-boot root to build the image.
+
+Verification
+====================
+
+Target
+====================
+1. startup
+2. relocation
+3. timer driver
+4. uart driver
+5. mac driver
+6. mmc driver
+7. spi driver
+
+Steps
+====================
+1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
+2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
+3. Ping a server by mac driver
+4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
+5. Burn this u-boot image to spi rom by spi driver
+6. Re-boot u-boot from spi flash with power off and power on.
+
+Messages
+====================
+U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
+
+DRAM: 1 GiB
+MMC: mmc@f0e00000: 0
+SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+In: serial@f0300000
+Out: serial@f0300000
+Err: serial@f0300000
+Net:
+Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10
+eth0: mac@e0100000
+
+RISC-V # version
+U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)
+
+riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0
+GNU ld (GNU Binutils) 2.29
+
+RISC-V # setenv ipaddr 10.0.4.200 ;
+RISC-V # setenv serverip 10.0.4.97 ;
+RISC-V # ping 10.0.4.97 ;
+Using mac@e0100000 device
+host 10.0.4.97 is alive
+
+RISC-V # mmc rescan
+RISC-V # fatls mmc 0:1
+ 318907 u-boot-ae250-64.bin
+ 1252 hello_world_ae250_32.bin
+ 328787 u-boot-ae250-32.bin
+
+3 file(s), 0 dir(s)
+
+RISC-V # sf probe 0:0 50000000 0
+SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+
+RISC-V # sf test 0x100000 0x1000
+SPI flash test:
+0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
+1 check: 29 ticks, 137 KiB/s 1.096 Mbps
+2 write: 40 ticks, 100 KiB/s 0.800 Mbps
+3 read: 20 ticks, 200 KiB/s 1.600 Mbps
+Test passed
+0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
+1 check: 29 ticks, 137 KiB/s 1.096 Mbps
+2 write: 40 ticks, 100 KiB/s 0.800 Mbps
+3 read: 20 ticks, 200 KiB/s 1.600 Mbps
+
+RISC-V # fatload mmc 0:1 0x600000 u-boot-ae250-32.bin
+reading u-boot-ae250-32.bin
+328787 bytes read in 324 ms (990.2 KiB/s)
+
+RISC-V # sf erase 0x0 0x51000
+SF: 331776 bytes @ 0x0 Erased: OK
+
+RISC-V # sf write 0x600000 0x0 0x50453
+device 0 offset 0x0, size 0x50453
+SF: 328787 bytes @ 0x0 Written: OK
+
+RISC-V # crc32 0x600000 0x50453
+crc32 for 00600000 ... 00650452 ==> 692dc44a
+
+RISC-V # crc32 0x80000000 0x50453
+crc32 for 80000000 ... 80050452 ==> 692dc44a
+RISC-V #
+
+*** power-off and power-on, this U-Boot is booted from spi flash ***
+
+U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800)
+
+DRAM: 1 GiB
+MMC: mmc@f0e00000: 0
+SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+In: serial@f0300000
+Out: serial@f0300000
+Err: serial@f0300000
+Net:
+Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5
+eth0: mac@e0100000
+RISC-V #
+
+TODO
+====================
+
+Boot bbl and riscv-linux
mode or in read-write mode.
First, to enable support for both ext4 (and, automatically, ext2 as well),
-but without selecting the corresponding commands, use one of:
+but without selecting the corresponding commands, enable one of the following:
- #define CONFIG_FS_EXT4 (for read-only)
- #define CONFIG_EXT4_WRITE (for read-write)
+ CONFIG_FS_EXT4 (for read-only)
+ CONFIG_EXT4_WRITE (for read-write)
Next, to select the ext2-related commands:
use one or both of:
- #define CONFIG_CMD_EXT2
- #define CONFIG_CMD_EXT4
+ CONFIG_CMD_EXT2
+ CONFIG_CMD_EXT4
-Selecting either of the above automatically defines CONFIG_FS_EXT4 if it
-wasn't defined already.
+Selecting either of the above automatically selects CONFIG_FS_EXT4 if it
+wasn't enabled already.
-In addition, to get the write access command "ext4write", use:
+In addition, to get the write access command "ext4write", enable:
- #define CONFIG_CMD_EXT4_WRITE
+ CONFIG_CMD_EXT4_WRITE
-which automatically defines CONFIG_EXT4_WRITE if it wasn't defined
+which automatically selects CONFIG_EXT4_WRITE if it wasn't defined
already.
Also relevant are the generic filesystem commands, selected by:
- #define CONFIG_CMD_FS_GENERIC
+ CONFIG_CMD_FS_GENERIC
This does not automatically enable EXT4 support for you, you still need
to do that yourself.
1.2 Configuration settings for M54418TWR Development Board
CONFIG_MCF5441x -- define for all MCF5441x CPUs
CONFIG_M54418 -- define for all Freescale MCF54418 CPUs
-CONFIG_M54418TWR -- define for M54418TWR board
CONFIG_MCFUART -- define to use common CF Uart driver
CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
# SPDX-License-Identifier: GPL-2.0+
#
-U-Boot on QEMU's 'virt' machine on ARM
-======================================
+U-Boot on QEMU's 'virt' machine on ARM & AArch64
+================================================
QEMU for ARM supports a special 'virt' machine designed for emulation and
virtualization purposes. This document describes how to run U-Boot under it.
+Both 32-bit ARM and AArch64 are supported.
The 'virt' platform provides the following as the basic functionality:
- A generated device tree blob placed at the start of RAM
- A freely configurable amount of RAM, described by the DTB
- A PL011 serial port, discoverable via the DTB
- - An ARMv7 architected timer
+ - An ARMv7/ARMv8 architected timer
- PSCI for rebooting the system
- A generic ECAM-based PCI host controller, discoverable via the DTB
Building U-Boot
---------------
-Set the CROSS_COMPILE and ARCH=arm environment variables as usual, and run:
+Set the CROSS_COMPILE environment variable as usual, and run:
+- For ARM:
make qemu_arm_defconfig
make
+- For AArch64:
+ make qemu_arm64_defconfig
+ make
+
Running U-Boot
--------------
The minimal QEMU command line to get U-Boot up and running is:
+- For ARM:
qemu-system-arm -machine virt,highmem=off -bios u-boot.bin
+- For AArch64:
+ qemu-system-aarch64 -machine virt,highmem=off -cpu cortex-a57 -bios u-boot.bin
+
The 'highmem=off' parameter to the 'virt' machine is required for PCI to work
-in U-Boot.
+in U-Boot. Also, for some odd reason qemu-system-aarch64 needs to be explicitly
+told to use a 64-bit CPU or it will boot in 32-bit mode.
Additional peripherals that have been tested to work in both U-Boot and Linux
can be enabled with the following command line parameters:
--- /dev/null
+Rockusb (Rockchip USB protocol)
+=====================================================
+
+Overview
+--------
+
+Rockusb protocol is widely used by Rockchip SoC based devices. It can
+read/write info, image to/from devices. This document briefly describes how to
+use Rockusb for upgrading firmware (e.g. kernel, u-boot, rootfs, etc.).
+
+Tools
+--------
+There are many tools can support Rockusb protocol. rkdeveloptool
+(https://github.com/rockchip-linux/rkdeveloptool) is open source,
+It is maintained by Rockchip. People don't want to build from source
+can download from here
+(https://github.com/rockchip-linux/rkbin/blob/master/tools/rkdeveloptool)
+
+Usage
+--------
+The Usage of Rockusb command is:
+
+rockusb <USB_controller> <devtype> <dev[:part]>
+
+e.g. rockusb 0 mmc 0
+
+On your U-Boot console, type this command to enter rockusb mode.
+On your host PC. use lsusb command. you should see a usb device
+using 0x2207 as its USB verdor id.
+
+for more detail about the rkdeveloptool. please read the usage.
+
+rkdeveloptool -h
+
+use rkdeveloptool wl command to write lba. BeginSec is the lba on device
+you want to write.
+
+sudo rkdeveloptool wl <BeginSec> <File>
+
+to flash U-Boot image use below command. U-Boot binary is made by mkimage.
+see doc/README.rockchip for more detail about how to get U-Boot binary.
+
+sudo rkdeveloptool wl 64 <U-Boot binary>
+
+There are plenty of Rockusb command. but wl(write lba) and
+rd(reboot) command. These two command can let people flash
+image to device.
+
+To do
+-----
+* Fully support Rockusb protocol
Blackfin 0x00001000 0x00001000
NDS32 0x00300000 0x00300000
Nios II 0x02000000 0x02000000
+ RISC-V 0x00600000 0x00600000
For example, the "hello world" application may be loaded and
executed on a PowerPC board with the following commands:
#address-cells = <1>;
images {
- kernel@0 {
+ kernel {
description = "linux";
data = /incbin/("PATH/TO/YOUR/LINUX/DIR/arch/arm64/boot/Image.gz");
type = "kernel";
compression = "gzip";
load = <0x82080000>;
entry = <0x82080000>;
- hash@0 {
+ hash-1 {
algo = "sha256";
};
};
- fdt@0 {
+ fdt-1 {
description = "fdt";
data = /incbin/("PATH/TO/YOUR/LINUX/DIR/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dtb");
type = "flat_dt";
arch = "arm64";
compression = "none";
- hash@0 {
+ hash-1 {
algo = "sha256";
};
};
- ramdisk@0 {
+ ramdisk {
description = "ramdisk";
data = /incbin/("PATH/TO/YOUR/ROOTFS/DIR/rootfs.cpio");
type = "ramdisk";
arch = "arm64";
os = "linux";
compression = "none";
- hash@0 {
+ hash-1 {
algo = "sha256";
};
};
};
configurations {
- default = "config@0";
+ default = "config-1";
- config@0 {
+ config-1 {
description = "Configuration0";
- kernel = "kernel@0";
- fdt = "fdt@0";
- ramdisk = "ramdisk@0";
- signature@0 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ ramdisk = "ramdisk";
+ signature-1 {
algo = "sha256,rsa2048";
key-name-hint = "dev";
sign-images = "kernel", "fdt", "ramdisk";
---------------------------------------->8----------------------------------------
## Loading kernel from FIT Image at 84100000 ...
- Using 'config@0' configuration
+ Using 'config-1' configuration
Verifying Hash Integrity ... sha256,rsa2048:dev+ OK
- Trying 'kernel@0' kernel subimage
+ Trying 'kernel' kernel subimage
Description: linux
Created: 2017-10-20 14:32:29 UTC
Type: Kernel Image
Hash value: 82a37b7f11ae55f4e07aa25bf77e4067cb9dc1014d52d6cd4d588f92eee3aaad
Verifying Hash Integrity ... sha256+ OK
## Loading ramdisk from FIT Image at 84100000 ...
- Using 'config@0' configuration
- Trying 'ramdisk@0' ramdisk subimage
+ Using 'config-1' configuration
+ Trying 'ramdisk' ramdisk subimage
Description: ramdisk
Created: 2017-10-20 14:32:29 UTC
Type: RAMDisk Image
Hash value: 44980a2874154a2e31ed59222c9f8ea968867637f35c81e4107a984de7014deb
Verifying Hash Integrity ... sha256+ OK
## Loading fdt from FIT Image at 84100000 ...
- Using 'config@0' configuration
- Trying 'fdt@0' fdt subimage
+ Using 'config-1' configuration
+ Trying 'fdt-1' fdt subimage
Description: fdt
Created: 2017-10-20 14:32:29 UTC
Type: Flat Device Tree
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
description = "U-Boot mainline";
type = "kernel_noload";
arch = "arm";
compression = "none";
load = <0>;
entry = <0>;
- hash@2 {
+ hash-2 {
algo = "sha1";
};
};
- fdt@1{
+ fdt-1{
description = "rk3288-veryron-jerry.dtb";
data = /incbin/("../../b/chromebook_jerry/u-boot.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
- hash@1{
+ hash-1{
algo = "sha1";
};
};
};
configurations {
- default = "config@1";
- config@1 {
+ default = "config-1";
+ config-1 {
description = "Boot U-Boot";
- kernel = "kernel@1";
- fdt = "fdt@1";
+ kernel = "kernel";
+ fdt = "fdt-1";
};
};
};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
description = "U-Boot mainline";
type = "kernel_noload";
arch = "arm";
compression = "none";
load = <0>;
entry = <0>;
- hash@2 {
+ hash-2 {
algo = "sha1";
};
};
- fdt@1{
+ fdt-1{
description = "tegra124-nyan-big.dtb";
data = /incbin/("../.././b/nyan-big/u-boot.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
- hash@1{
+ hash-1{
algo = "sha1";
};
};
};
configurations {
- default = "config@1";
- config@1 {
+ default = "config-1";
+ config-1 {
description = "Boot U-Boot";
- kernel = "kernel@1";
- fdt = "fdt@1";
+ kernel = "kernel";
+ fdt = "fdt-1";
};
};
};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
data = /incbin/("Image.lzo");
type = "kernel";
arch = "arm";
compression = "lzo";
load = <0x80008000>;
entry = <0x80008000>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
- fdt@1 {
+ fdt-1 {
description = "beaglebone-black";
data = /incbin/("am335x-boneblack.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
- signature@1 {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ signature-1 {
algo = "sha1,rsa2048";
key-name-hint = "dev";
sign-images = "fdt", "kernel";
FIT description: Beaglebone black
Created: Sun Jun 1 12:50:30 2014
- Image 0 (kernel@1)
+ Image 0 (kernel)
Description: unavailable
Created: Sun Jun 1 12:50:30 2014
Type: Kernel Image
Entry Point: 0x80008000
Hash algo: sha1
Hash value: c94364646427e10f423837e559898ef02c97b988
- Image 1 (fdt@1)
+ Image 1 (fdt-1)
Description: beaglebone-black
Created: Sun Jun 1 12:50:30 2014
Type: Flat Device Tree
Architecture: ARM
Hash algo: sha1
Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d
- Default Configuration: 'conf@1'
- Configuration 0 (conf@1)
+ Default Configuration: 'conf-1'
+ Configuration 0 (conf-1)
Description: unavailable
- Kernel: kernel@1
- FDT: fdt@1
+ Kernel: kernel
+ FDT: fdt-1
Now am335x-boneblack-pubkey.dtb contains the public key and image.fit contains
Verifying Hash Integrity ... sha1,rsa2048:dev+
## Loading kernel from FIT Image at 7fc6ee469000 ...
- Using 'conf@1' configuration
+ Using 'conf-1' configuration
Verifying Hash Integrity ...
sha1,rsa2048:dev+
OK
- Trying 'kernel@1' kernel subimage
+ Trying 'kernel' kernel subimage
Description: unavailable
Created: Sun Jun 1 12:50:30 2014
Type: Kernel Image
Unimplemented compression type 4
## Loading fdt from FIT Image at 7fc6ee469000 ...
- Using 'conf@1' configuration
- Trying 'fdt@1' fdt subimage
+ Using 'conf-1' configuration
+ Trying 'fdt-1' fdt subimage
Description: beaglebone-black
Created: Sun Jun 1 12:50:30 2014
Type: Flat Device Tree
Loading Flat Device Tree ... OK
## Loading ramdisk from FIT Image at 7fc6ee469000 ...
- Using 'conf@1' configuration
+ Using 'conf-1' configuration
Could not find subimage node
Signature check OK
But it is fun to do this by hand, so you can load image.fit into a hex editor
like ghex, and change a byte in the kernel:
- $UOUT/tools/fit_info -f image.fit -n /images/kernel@1 -p data
-NAME: kernel@1
+ $UOUT/tools/fit_info -f image.fit -n /images/kernel -p data
+NAME: kernel
LEN: 7790938
OFF: 168
Verifying Hash Integrity ... sha1,rsa2048:dev+
## Loading kernel from FIT Image at 7f5a39571000 ...
- Using 'conf@1' configuration
+ Using 'conf-1' configuration
Verifying Hash Integrity ...
sha1,rsa2048:dev+
OK
- Trying 'kernel@1' kernel subimage
+ Trying 'kernel' kernel subimage
Description: unavailable
Created: Sun Jun 1 13:09:21 2014
Type: Kernel Image
Hash value: c94364646427e10f423837e559898ef02c97b988
Verifying Hash Integrity ...
sha1 error
-Bad hash value for 'hash@1' hash node in 'kernel@1' image node
+Bad hash value for 'hash-1' hash node in 'kernel' image node
Bad Data Hash
## Loading fdt from FIT Image at 7f5a39571000 ...
- Using 'conf@1' configuration
- Trying 'fdt@1' fdt subimage
+ Using 'conf-1' configuration
+ Trying 'fdt-1' fdt subimage
Description: beaglebone-black
Created: Sun Jun 1 13:09:21 2014
Type: Flat Device Tree
Loading Flat Device Tree ... OK
## Loading ramdisk from FIT Image at 7f5a39571000 ...
- Using 'conf@1' configuration
+ Using 'conf-1' configuration
Could not find subimage node
Signature check Bad (error 1)
configurations
fdtget -l image.fit /configurations
-conf@1
-fdtget -l image.fit /configurations/conf@1
-signature@1
+conf-1
+fdtget -l image.fit /configurations/conf-1
+signature-1
- fdtget -p image.fit /configurations/conf@1/signature@1
+ fdtget -p image.fit /configurations/conf-1/signature-1
hashed-strings
hashed-nodes
timestamp
key-name-hint
sign-images
- fdtget image.fit /configurations/conf@1/signature@1 hashed-nodes
-/ /configurations/conf@1 /images/fdt@1 /images/fdt@1/hash@1 /images/kernel@1 /images/kernel@1/hash@1
+ fdtget image.fit /configurations/conf-1/signature-1 hashed-nodes
+/ /configurations/conf-1 /images/fdt-1 /images/fdt-1/hash /images/kernel /images/kernel/hash-1
This gives us a bit of a look into the signature that mkimage added. Note you
can also use fdtdump to list the entire device tree.
Say we want to change the kernel that this configuration uses
-(/images/kernel@1). We could just put a new kernel in the image, but we will
+(/images/kernel). We could just put a new kernel in the image, but we will
need to change the hash to match. Let's simulate that by changing a byte of
the hash:
- fdtget -tx image.fit /images/kernel@1/hash@1 value
+ fdtget -tx image.fit /images/kernel/hash-1 value
c9436464 6427e10f 423837e5 59898ef0 2c97b988
- fdtput -tx image.fit /images/kernel@1/hash@1 value c9436464 6427e10f 423837e5 59898ef0 2c97b981
+ fdtput -tx image.fit /images/kernel/hash-1 value c9436464 6427e10f 423837e5 59898ef0 2c97b981
Now check it again:
configuration in any way. Try it with a fresh (valid) image if you like by
running the mkimage link again. Then:
- fdtput -p image.fit /configurations/conf@1/signature@2 value fred
+ fdtput -p image.fit /configurations/conf-1/signature-1 value fred
$UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
Verifying Hash Integrity ... -
sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
7824930 bytes read in 589 ms (12.7 MiB/s)
U-Boot# bootm 82000000
## Loading kernel from FIT Image at 82000000 ...
- Using 'conf@1' configuration
+ Using 'conf-1' configuration
Verifying Hash Integrity ... sha1,rsa2048:dev+ OK
- Trying 'kernel@1' kernel subimage
+ Trying 'kernel' kernel subimage
Description: unavailable
Created: 2014-06-01 19:32:54 UTC
Type: Kernel Image
Hash value: c94364646427e10f423837e559898ef02c97b988
Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 82000000 ...
- Using 'conf@1' configuration
- Trying 'fdt@1' fdt subimage
+ Using 'conf-1' configuration
+ Trying 'fdt-1' fdt subimage
Description: beaglebone-black
Created: 2014-06-01 19:32:54 UTC
Type: Flat Device Tree
Examples:
-- boot kernel "kernel@1" stored in a new uImage located at 200000:
-bootm 200000:kernel@1
+- boot kernel "kernel-1" stored in a new uImage located at 200000:
+bootm 200000:kernel-1
-- boot configuration "cfg@1" from a new uImage located at 200000:
-bootm 200000#cfg@1
+- boot configuration "cfg-1" from a new uImage located at 200000:
+bootm 200000#cfg-1
-- boot configuration "cfg@1" with extra "cfg@2" from a new uImage located
+- boot configuration "cfg-1" with extra "cfg-2" from a new uImage located
at 200000:
-bootm 200000#cfg@1#cfg@2
+bootm 200000#cfg-1#cfg-2
-- boot "kernel@1" from a new uImage at 200000 with initrd "ramdisk@2" found in
+- boot "kernel-1" from a new uImage at 200000 with initrd "ramdisk-2" found in
some other new uImage stored at address 800000:
-bootm 200000:kernel@1 800000:ramdisk@2
+bootm 200000:kernel-1 800000:ramdisk-2
-- boot "kernel@2" from a new uImage at 200000, with initrd "ramdisk@1" and FDT
- "fdt@1", both stored in some other new uImage located at 800000:
-bootm 200000:kernel@1 800000:ramdisk@1 800000:fdt@1
+- boot "kernel-2" from a new uImage at 200000, with initrd "ramdisk-1" and FDT
+ "fdt-1", both stored in some other new uImage located at 800000:
+bootm 200000:kernel-1 800000:ramdisk-1 800000:fdt-1
-- boot kernel "kernel@2" with initrd "ramdisk@2", both stored in a new uImage
+- boot kernel "kernel-2" with initrd "ramdisk-2", both stored in a new uImage
at address 200000, with a raw FDT blob stored at address 600000:
-bootm 200000:kernel@2 200000:ramdisk@2 600000
+bootm 200000:kernel-2 200000:ramdisk-2 600000
-- boot kernel "kernel@2" from new uImage at 200000 with FDT "fdt@1" from the
+- boot kernel "kernel-2" from new uImage at 200000 with FDT "fdt-1" from the
same new uImage:
-bootm 200000:kernel@2 - 200000:fdt@1
+bootm 200000:kernel-2 - 200000:fdt-1
Note on current image address
commands:
tftp 200000 /tftpboot/uImage
-bootm :kernel@1
+bootm :kernel-1
Last command is equivalent to:
-bootm 200000:kernel@1
+bootm 200000:kernel-1
tftp 200000 /tftpboot/uImage
-bootm 400000:kernel@1 :ramdisk@1
+bootm 400000:kernel-1 :ramdisk-1
Last command is equivalent to:
-bootm 400000:kernel@1 400000:ramdisk@1
+bootm 400000:kernel-1 400000:ramdisk-1
tftp 200000 /tftpboot/uImage
-bootm :kernel@1 400000:ramdisk@1 :fdt@1
+bootm :kernel-1 400000:ramdisk-1 :fdt-1
Last command is equivalent to:
-bootm 200000:kernel@1 400000:ramdisk@1 400000:fdt@1
+bootm 200000:kernel-1 400000:ramdisk-1 400000:fdt-1
$ mkimage -l kernel.itb
FIT description: Simple image with single Linux kernel
Created: Tue Mar 11 17:26:15 2008
- Image 0 (kernel@1)
+ Image 0 (kernel)
Description: Vanilla Linux kernel
Type: Kernel Image
Compression: gzip compressed
Hash value: 2ae2bb40
Hash algo: sha1
Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4
- Default Configuration: 'config@1'
- Configuration 0 (config@1)
+ Default Configuration: 'config-1'
+ Configuration 0 (config-1)
Description: Boot Linux kernel
- Kernel: kernel@1
+ Kernel: kernel
The resulting image file kernel.itb can be now transferred to the target,
FIT image found
FIT description: Simple image with single Linux kernel
Created: 2008-03-11 16:26:15 UTC
- Image 0 (kernel@1)
+ Image 0 (kernel)
Description: Vanilla Linux kernel
Type: Kernel Image
Compression: gzip compressed
Hash value: 2ae2bb40
Hash algo: sha1
Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4
- Default Configuration: 'config@1'
- Configuration 0 (config@1)
+ Default Configuration: 'config-1'
+ Configuration 0 (config-1)
Description: Boot Linux kernel
- Kernel: kernel@1
+ Kernel: kernel
=> bootm
## Booting kernel from FIT Image at 00900000 ...
- Using 'config@1' configuration
- Trying 'kernel@1' kernel subimage
+ Using 'config-1' configuration
+ Trying 'kernel' kernel subimage
Description: Vanilla Linux kernel
Type: Kernel Image
Compression: gzip compressed
$ mkimage -l kernel_fdt.itb
FIT description: Simple image with single Linux kernel and FDT blob
Created: Tue Mar 11 16:29:22 2008
- Image 0 (kernel@1)
+ Image 0 (kernel)
Description: Vanilla Linux kernel
Type: Kernel Image
Compression: gzip compressed
Hash value: 2c0cc807
Hash algo: sha1
Hash value: 264b59935470e42c418744f83935d44cdf59a3bb
- Image 1 (fdt@1)
+ Image 1 (fdt-1)
Description: Flattened Device Tree blob
Type: Flat Device Tree
Compression: uncompressed
Hash value: 0d655d71
Hash algo: sha1
Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def
- Default Configuration: 'conf@1'
- Configuration 0 (conf@1)
+ Default Configuration: 'conf-1'
+ Configuration 0 (conf-1)
Description: Boot Linux kernel with FDT blob
- Kernel: kernel@1
- FDT: fdt@1
+ Kernel: kernel
+ FDT: fdt-1
The resulting image file kernel_fdt.itb can be now transferred to the target,
FIT image found
FIT description: Simple image with single Linux kernel and FDT blob
Created: 2008-03-11 15:29:22 UTC
- Image 0 (kernel@1)
+ Image 0 (kernel)
Description: Vanilla Linux kernel
Type: Kernel Image
Compression: gzip compressed
Hash value: 2c0cc807
Hash algo: sha1
Hash value: 264b59935470e42c418744f83935d44cdf59a3bb
- Image 1 (fdt@1)
+ Image 1 (fdt-1)
Description: Flattened Device Tree blob
Type: Flat Device Tree
Compression: uncompressed
Hash value: 0d655d71
Hash algo: sha1
Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def
- Default Configuration: 'conf@1'
- Configuration 0 (conf@1)
+ Default Configuration: 'conf-1'
+ Configuration 0 (conf-1)
Description: Boot Linux kernel with FDT blob
- Kernel: kernel@1
- FDT: fdt@1
+ Kernel: kernel
+ FDT: fdt-1
=> bootm
## Booting kernel from FIT Image at 00900000 ...
- Using 'conf@1' configuration
- Trying 'kernel@1' kernel subimage
+ Using 'conf-1' configuration
+ Trying 'kernel' kernel subimage
Description: Vanilla Linux kernel
Type: Kernel Image
Compression: gzip compressed
Verifying Hash Integrity ... crc32+ sha1+ OK
Uncompressing Kernel Image ... OK
## Flattened Device Tree from FIT Image at 00900000
- Using 'conf@1' configuration
- Trying 'fdt@1' FDT blob subimage
+ Using 'conf-1' configuration
+ Trying 'fdt-1' FDT blob subimage
Description: Flattened Device Tree blob
Type: Flat Device Tree
Compression: uncompressed
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
description = "Vanilla Linux kernel";
data = /incbin/("./vmlinux.bin.gz");
type = "kernel";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
- hash@1 {
+ hash-1 {
algo = "crc32";
};
- hash@2 {
+ hash-2 {
algo = "sha1";
};
};
};
configurations {
- default = "config@1";
- config@1 {
+ default = "config-1";
+ config-1 {
description = "Boot Linux kernel";
- kernel = "kernel@1";
+ kernel = "kernel";
};
};
};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
description = "Vanilla Linux kernel";
data = /incbin/("./image.bin.lzo");
type = "kernel";
compression = "lzo";
load = <0x01000000>;
entry = <0x00000000>;
- hash@2 {
+ hash-2 {
algo = "sha1";
};
};
- setup@1 {
+ setup {
description = "Linux setup.bin";
data = /incbin/("./setup.bin");
type = "x86_setup";
compression = "none";
load = <0x00090000>;
entry = <0x00090000>;
- hash@2 {
+ hash-2 {
algo = "sha1";
};
};
};
configurations {
- default = "config@1";
- config@1 {
+ default = "config-1";
+ config-1 {
description = "Boot Linux kernel";
- kernel = "kernel@1";
- setup = "setup@1";
+ kernel = "kernel";
+ setup = "setup";
};
};
};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
description = "Vanilla Linux kernel";
data = /incbin/("./vmlinux.bin.gz");
type = "kernel";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
- hash@1 {
+ hash-1 {
algo = "crc32";
};
- hash@2 {
+ hash-2 {
algo = "sha1";
};
};
- fdt@1 {
+ fdt-1 {
description = "Flattened Device Tree blob";
data = /incbin/("./target.dtb");
type = "flat_dt";
arch = "ppc";
compression = "none";
- hash@1 {
+ hash-1 {
algo = "crc32";
};
- hash@2 {
+ hash-2 {
algo = "sha1";
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
+ default = "conf-1";
+ conf-1 {
description = "Boot Linux kernel with FDT blob";
- kernel = "kernel@1";
- fdt = "fdt@1";
+ kernel = "kernel";
+ fdt = "fdt-1";
};
};
};
#address-cells = <1>;
images {
- fdt@1 {
+ fdt-1 {
description = "zc706";
data = /incbin/("/tftpboot/devicetree.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
load = <0x10000000>;
- hash@1 {
+ hash-1 {
algo = "md5";
};
};
- fpga@1 {
+ fpga {
description = "FPGA";
data = /incbin/("/tftpboot/download.bit");
type = "fpga";
arch = "arm";
compression = "none";
load = <0x30000000>;
- hash@1 {
+ hash-1 {
algo = "md5";
};
};
- linux_kernel@1 {
+ linux_kernel {
description = "Linux";
data = /incbin/("/tftpboot/zImage");
type = "kernel";
compression = "none";
load = <0x8000>;
entry = <0x8000>;
- hash@1 {
+ hash-1 {
algo = "md5";
};
};
};
configurations {
- default = "config@2";
- config@1 {
+ default = "config-2";
+ config-1 {
description = "Linux";
- kernel = "linux_kernel@1";
- fdt = "fdt@1";
+ kernel = "linux_kernel";
+ fdt = "fdt-1";
};
- config@2 {
+ config-2 {
description = "Linux with fpga";
- kernel = "linux_kernel@1";
- fdt = "fdt@1";
- fpga = "fpga@1";
+ kernel = "linux_kernel";
+ fdt = "fdt-1";
+ fpga = "fpga";
};
};
};
#address-cells = <1>;
images {
- xen_kernel@1 {
+ xen_kernel {
description = "xen binary";
data = /incbin/("./xen");
type = "kernel";
compression = "none";
load = <0xa0000000>;
entry = <0xa0000000>;
- hash@1 {
+ hash-1 {
algo = "md5";
};
};
- fdt@1 {
+ fdt-1 {
description = "xexpress-ca15 tree blob";
data = /incbin/("./vexpress-v2p-ca15-tc1.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
load = <0xb0000000>;
- hash@1 {
+ hash-1 {
algo = "md5";
};
};
- fdt@2 {
+ fdt-2 {
description = "xexpress-ca15 tree blob";
data = /incbin/("./vexpress-v2p-ca15-tc1.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
load = <0xb0400000>;
- hash@1 {
+ hash-1 {
algo = "md5";
};
};
- linux_kernel@1 {
+ linux_kernel {
description = "Linux Image";
data = /incbin/("./Image");
type = "kernel";
compression = "none";
load = <0xa0000000>;
entry = <0xa0000000>;
- hash@1 {
+ hash-1 {
algo = "md5";
};
};
};
configurations {
- default = "config@2";
+ default = "config-2";
- config@1 {
+ config-1 {
description = "Just plain Linux";
- kernel = "linux_kernel@1";
- fdt = "fdt@1";
+ kernel = "linux_kernel";
+ fdt = "fdt-1";
};
- config@2 {
+ config-2 {
description = "Xen one loadable";
- kernel = "xen_kernel@1";
- fdt = "fdt@1";
- loadables = "linux_kernel@1";
+ kernel = "xen_kernel";
+ fdt = "fdt-1";
+ loadables = "linux_kernel";
};
- config@3 {
+ config-3 {
description = "Xen two loadables";
- kernel = "xen_kernel@1";
- fdt = "fdt@1";
- loadables = "linux_kernel@1", "fdt@2";
+ kernel = "xen_kernel";
+ fdt = "fdt-1";
+ loadables = "linux_kernel", "fdt-2";
};
};
};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel-1 {
description = "vanilla-2.6.23";
data = /incbin/("./vmlinux.bin.gz");
type = "kernel";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
- hash@1 {
+ hash-1 {
algo = "md5";
};
- hash@2 {
+ hash-2 {
algo = "sha1";
};
};
- kernel@2 {
+ kernel-2 {
description = "2.6.23-denx";
data = /incbin/("./2.6.23-denx.bin.gz");
type = "kernel";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
- kernel@3 {
+ kernel-3 {
description = "2.4.25-denx";
data = /incbin/("./2.4.25-denx.bin.gz");
type = "kernel";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
- hash@1 {
+ hash-1 {
algo = "md5";
};
};
- ramdisk@1 {
+ ramdisk-1 {
description = "eldk-4.2-ramdisk";
data = /incbin/("./eldk-4.2-ramdisk");
type = "ramdisk";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
- ramdisk@2 {
+ ramdisk-2 {
description = "eldk-3.1-ramdisk";
data = /incbin/("./eldk-3.1-ramdisk");
type = "ramdisk";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
- hash@1 {
+ hash-1 {
algo = "crc32";
};
};
- fdt@1 {
+ fdt-1 {
description = "tqm5200-fdt";
data = /incbin/("./tqm5200.dtb");
type = "flat_dt";
arch = "ppc";
compression = "none";
- hash@1 {
+ hash-1 {
algo = "crc32";
};
};
- fdt@2 {
+ fdt-2 {
description = "tqm5200s-fdt";
data = /incbin/("./tqm5200s.dtb");
type = "flat_dt";
arch = "ppc";
compression = "none";
load = <00700000>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
};
configurations {
- default = "config@1";
+ default = "config-1";
- config@1 {
+ config-1 {
description = "tqm5200 vanilla-2.6.23 configuration";
- kernel = "kernel@1";
- ramdisk = "ramdisk@1";
- fdt = "fdt@1";
+ kernel = "kernel-1";
+ ramdisk = "ramdisk-1";
+ fdt = "fdt-1";
};
- config@2 {
+ config-2 {
description = "tqm5200s denx-2.6.23 configuration";
- kernel = "kernel@2";
- ramdisk = "ramdisk@1";
- fdt = "fdt@2";
+ kernel = "kernel-2";
+ ramdisk = "ramdisk-1";
+ fdt = "fdt-2";
};
- config@3 {
+ config-3 {
description = "tqm5200s denx-2.4.25 configuration";
- kernel = "kernel@3";
- ramdisk = "ramdisk@2";
+ kernel = "kernel-3";
+ ramdisk = "ramdisk-2";
};
};
};
load = <0x40000>;
};
- fdt@1 {
+ fdt-1 {
description = "Pine64+ DT";
type = "flat_dt";
compression = "none";
arch = "arm64";
};
- fdt@2 {
+ fdt-2 {
description = "Pine64 DT";
type = "flat_dt";
compression = "none";
};
configurations {
- default = "config@1";
+ default = "config-1";
- config@1 {
+ config-1 {
description = "sun50i-a64-pine64-plus";
loadables = "uboot", "atf", "kernel", "initrd";
- fdt = "fdt@1";
+ fdt = "fdt-1";
};
- config@2 {
+ config-2 {
description = "sun50i-a64-pine64";
loadables = "uboot", "atf", "mgmt-firmware";
- fdt = "fdt@2";
+ fdt = "fdt-2";
};
};
};
/dts-v1/;
/ {
images {
- kernel@1 {
+ kernel {
data = /incbin/("./zImage");
type = "kernel";
arch = "arm";
load = <0x82000000>;
entry = <0x82000000>;
};
- fdt@1 {
+ fdt-1 {
data = /incbin/("./foo-reva.dtb");
type = "flat_dt";
arch = "arm";
};
- fdt@2 {
+ fdt-2 {
data = /incbin/("./foo-revb.dtb");
type = "flat_dt";
arch = "arm";
};
- fdt@3 {
+ fdt-3 {
data = /incbin/("./foo-reva-bar.dtb");
type = "flat_dt";
arch = "arm";
};
- fdt@4 {
+ fdt-4 {
data = /incbin/("./foo-revb-bar.dtb");
type = "flat_dt";
arch = "arm";
};
- fdt@5 {
+ fdt-5 {
data = /incbin/("./foo-revb-baz.dtb");
type = "flat_dt";
arch = "arm";
};
- fdt@6 {
+ fdt-6 {
data = /incbin/("./foo-revb-bar-baz.dtb");
type = "flat_dt";
arch = "arm";
configurations {
default = "foo-reva.dtb;
foo-reva.dtb {
- kernel = "kernel@1";
- fdt = "fdt@1";
+ kernel = "kernel";
+ fdt = "fdt-1";
};
foo-revb.dtb {
- kernel = "kernel@1";
- fdt = "fdt@2";
+ kernel = "kernel";
+ fdt = "fdt-2";
};
foo-reva-bar.dtb {
- kernel = "kernel@1";
- fdt = "fdt@3";
+ kernel = "kernel";
+ fdt = "fdt-3";
};
foo-revb-bar.dtb {
- kernel = "kernel@1";
- fdt = "fdt@4";
+ kernel = "kernel";
+ fdt = "fdt-4";
};
foo-revb-baz.dtb {
- kernel = "kernel@1";
- fdt = "fdt@5";
+ kernel = "kernel";
+ fdt = "fdt-5";
};
foo-revb-bar-baz.dtb {
- kernel = "kernel@1";
- fdt = "fdt@6";
+ kernel = "kernel";
+ fdt = "fdt-6";
};
};
};
/dts-v1/;
/ {
images {
- kernel@1 {
+ kernel {
data = /incbin/("./zImage");
type = "kernel";
arch = "arm";
load = <0x82000000>;
entry = <0x82000000>;
};
- fdt@1 {
+ fdt-1 {
data = /incbin/("./foo.dtb");
type = "flat_dt";
arch = "arm";
load = <0x87f00000>;
};
- fdt@2 {
+ fdt-2 {
data = /incbin/("./reva.dtbo");
type = "flat_dt";
arch = "arm";
load = <0x87fc0000>;
};
- fdt@3 {
+ fdt-3 {
data = /incbin/("./revb.dtbo");
type = "flat_dt";
arch = "arm";
load = <0x87fc0000>;
};
- fdt@4 {
+ fdt-4 {
data = /incbin/("./bar.dtbo");
type = "flat_dt";
arch = "arm";
load = <0x87fc0000>;
};
- fdt@5 {
+ fdt-5 {
data = /incbin/("./baz.dtbo");
type = "flat_dt";
arch = "arm";
configurations {
default = "foo-reva.dtb;
foo-reva.dtb {
- kernel = "kernel@1";
- fdt = "fdt@1", "fdt@2";
+ kernel = "kernel";
+ fdt = "fdt-1", "fdt-2";
};
foo-revb.dtb {
- kernel = "kernel@1";
- fdt = "fdt@1", "fdt@3";
+ kernel = "kernel";
+ fdt = "fdt-1", "fdt-3";
};
foo-reva-bar.dtb {
- kernel = "kernel@1";
- fdt = "fdt@1", "fdt@2", "fdt@4";
+ kernel = "kernel";
+ fdt = "fdt-1", "fdt-2", "fdt-4";
};
foo-revb-bar.dtb {
- kernel = "kernel@1";
- fdt = "fdt@1", "fdt@3", "fdt@4";
+ kernel = "kernel";
+ fdt = "fdt-1", "fdt-3", "fdt-4";
};
foo-revb-baz.dtb {
- kernel = "kernel@1";
- fdt = "fdt@1", "fdt@3", "fdt@5";
+ kernel = "kernel";
+ fdt = "fdt-1", "fdt-3", "fdt-5";
};
foo-revb-bar-baz.dtb {
- kernel = "kernel@1";
- fdt = "fdt@1", "fdt@3", "fdt@4", "fdt@5";
+ kernel = "kernel";
+ fdt = "fdt-1", "fdt-3", "fdt-4", "fdt-5";
};
bar {
- fdt = "fdt@4";
+ fdt = "fdt-4";
};
baz {
- fdt = "fdt@5";
+ fdt = "fdt-5";
};
};
};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
data = /incbin/("test-kernel.bin");
type = "kernel_noload";
arch = "sandbox";
load = <0x4>;
entry = <0x8>;
kernel-version = <1>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
- fdt@1 {
+ fdt-1 {
description = "snow";
data = /incbin/("sandbox-kernel.dtb");
type = "flat_dt";
arch = "sandbox";
compression = "none";
fdt-version = <1>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
- signature@1 {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ signature {
algo = "sha1,rsa2048";
key-name-hint = "dev";
sign-images = "fdt", "kernel";
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
data = /incbin/("test-kernel.bin");
type = "kernel_noload";
arch = "sandbox";
load = <0x4>;
entry = <0x8>;
kernel-version = <1>;
- signature@1 {
+ signature {
algo = "sha1,rsa2048";
key-name-hint = "dev";
};
};
- fdt@1 {
+ fdt-1 {
description = "snow";
data = /incbin/("sandbox-kernel.dtb");
type = "flat_dt";
arch = "sandbox";
compression = "none";
fdt-version = <1>;
- signature@1 {
+ signature {
algo = "sha1,rsa2048";
key-name-hint = "dev";
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
};
};
};
The following properties are required in the FIT's signature node(s) to
allow the signer to operate. These should be added to the .its file.
Signature nodes sit at the same level as hash nodes and are called
-signature@1, signature@2, etc.
+signature-1, signature-2, etc.
- algo: Algorithm name (e.g. "sha1,rsa2048")
- hashed-nodes: A list of nodes which were hashed by the signer. Each is
a string - the full path to node. A typical value might be:
- hashed-nodes = "/", "/configurations/conf@1", "/images/kernel@1",
- "/images/kernel@1/hash@1", "/images/fdt@1",
- "/images/fdt@1/hash@1";
+ hashed-nodes = "/", "/configurations/conf-1", "/images/kernel",
+ "/images/kernel/hash-1", "/images/fdt-1",
+ "/images/fdt-1/hash-1";
- hashed-strings: The start and size of the string region of the FIT that
was hashed
/ {
images {
- kernel@1 {
+ kernel-1 {
data = <data for kernel1>
- signature@1 {
+ signature-1 {
algo = "sha1,rsa2048";
value = <...kernel signature 1...>
};
};
- kernel@2 {
+ kernel-2 {
data = <data for kernel2>
- signature@1 {
+ signature-1 {
algo = "sha1,rsa2048";
value = <...kernel signature 2...>
};
};
- fdt@1 {
+ fdt-1 {
data = <data for fdt1>;
- signature@1 {
+ signature-1 {
algo = "sha1,rsa2048";
vaue = <...fdt signature 1...>
};
};
- fdt@2 {
+ fdt-2 {
data = <data for fdt2>;
- signature@1 {
+ signature-1 {
algo = "sha1,rsa2048";
vaue = <...fdt signature 2...>
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel-1";
+ fdt = "fdt-1";
};
- conf@1 {
- kernel = "kernel@2";
- fdt = "fdt@2";
+ conf-1 {
+ kernel = "kernel-2";
+ fdt = "fdt-2";
};
};
};
configuration 3 with kernel 1 and fdt 2:
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel-1";
+ fdt = "fdt-1";
};
- conf@1 {
- kernel = "kernel@2";
- fdt = "fdt@2";
+ conf-1 {
+ kernel = "kernel-2";
+ fdt = "fdt-2";
};
- conf@3 {
- kernel = "kernel@1";
- fdt = "fdt@2";
+ conf-3 {
+ kernel = "kernel-1";
+ fdt = "fdt-2";
};
};
/ {
images {
- kernel@1 {
+ kernel-1 {
data = <data for kernel1>
- hash@1 {
+ hash-1 {
algo = "sha1";
value = <...kernel hash 1...>
};
};
- kernel@2 {
+ kernel-2 {
data = <data for kernel2>
- hash@1 {
+ hash-1 {
algo = "sha1";
value = <...kernel hash 2...>
};
};
- fdt@1 {
+ fdt-1 {
data = <data for fdt1>;
- hash@1 {
+ hash-1 {
algo = "sha1";
value = <...fdt hash 1...>
};
};
- fdt@2 {
+ fdt-2 {
data = <data for fdt2>;
- hash@1 {
+ hash-1 {
algo = "sha1";
value = <...fdt hash 2...>
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
- signature@1 {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel-1";
+ fdt = "fdt-1";
+ signature-1 {
algo = "sha1,rsa2048";
value = <...conf 1 signature...>;
};
};
- conf@2 {
- kernel = "kernel@2";
- fdt = "fdt@2";
- signature@1 {
+ conf-2 {
+ kernel = "kernel-2";
+ fdt = "fdt-2";
+ signature-1 {
algo = "sha1,rsa2048";
value = <...conf 1 signature...>;
};
You can see that we have added hashes for all images (since they are no
longer signed), and a signature to each configuration. In the above example,
-mkimage will sign configurations/conf@1, the kernel and fdt that are
-pointed to by the configuration (/images/kernel@1, /images/kernel@1/hash@1,
-/images/fdt@1, /images/fdt@1/hash@1) and the root structure of the image
+mkimage will sign configurations/conf-1, the kernel and fdt that are
+pointed to by the configuration (/images/kernel-1, /images/kernel-1/hash-1,
+/images/fdt-1, /images/fdt-1/hash-1) and the root structure of the image
(so that it isn't possible to add or remove root nodes). The signature is
-written into /configurations/conf@1/signature@1/value. It can easily be
+written into /configurations/conf-1/signature-1/value. It can easily be
verified later even if the FIT has been signed with other keys in the
meantime.
|
o images
| |
- | o image@1 {...}
- | o image@2 {...}
+ | o image-1 {...}
+ | o image-2 {...}
| ...
|
o configurations
- |- default = "conf@1"
+ |- default = "conf-1"
|
- o conf@1 {...}
- o conf@2 {...}
+ o conf-1 {...}
+ o conf-2 {...}
...
This node is a container node for component sub-image nodes. Each sub-node of
the '/images' node should have the following layout:
- o image@1
+ o image-1
|- description = "component sub-image description"
|- data = /incbin/("path/to/data/file.bin")
|- type = "sub-image type name"
|- load = <00000000>
|- entry = <00000000>
|
- o hash@1 {...}
- o hash@2 {...}
+ o hash-1 {...}
+ o hash-2 {...}
...
Mandatory properties:
property of the root node. Mandatory for types: "standalone" and "kernel".
Optional nodes:
- - hash@1 : Each hash sub-node represents separate hash or checksum
+ - hash-1 : Each hash sub-node represents separate hash or checksum
calculated for node's data according to specified algorithm.
5) Hash nodes
-------------
-o hash@1
+o hash-1
|- algo = "hash or checksum algorithm name"
|- value = [hash or checksum value]
o configurations
|- default = "default configuration sub-node unit name"
|
- o config@1 {...}
- o config@2 {...}
+ o config-1 {...}
+ o config-2 {...}
...
Each configuration has the following structure:
-o config@1
+o config-1
|- description = "configuration description"
|- kernel = "kernel sub-node unit name"
|- ramdisk = "ramdisk sub-node unit name"
#address-cells = <1>;
images {
- update@1 {
+ update-1 {
description = "Linux kernel binary";
data = /incbin/("./vmlinux.bin.gz");
compression = "none";
type = "firmware";
load = <FF700000>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
- update@2 {
+ update-2 {
description = "Ramdisk image";
data = /incbin/("./ramdisk_image.gz");
compression = "none";
type = "firmware";
load = <FF8E0000>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
- update@3 {
+ update-3 {
description = "FDT blob";
data = /incbin/("./blob.fdt");
compression = "none";
type = "firmware";
load = <FFAC0000>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
#address-cells = <1>;
images {
- update@1 {
+ update-1 {
description = "U-Boot binary";
data = /incbin/("./u-boot.bin");
compression = "none";
type = "firmware";
load = <FFFC0000>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
$ dumpimage -l image.fit
FIT description: Simple image with single Linux kernel on x86
Created: Tue Oct 7 10:57:24 2014
- Image 0 (kernel@1)
+ Image 0 (kernel)
Description: Vanilla Linux kernel
Created: Tue Oct 7 10:57:24 2014
Type: Kernel Image
Entry Point: 0x00000000
Hash algo: sha1
Hash value: 446b5163ebfe0fb6ee20cbb7a8501b263cd92392
- Image 1 (setup@1)
+ Image 1 (setup)
Description: Linux setup.bin
Created: Tue Oct 7 10:57:24 2014
Type: x86 setup.bin
Data Size: 12912 Bytes = 12.61 kB = 0.01 MB
Hash algo: sha1
Hash value: a1f2099cf47ff9816236cd534c77af86e713faad
- Default Configuration: 'config@1'
- Configuration 0 (config@1)
+ Default Configuration: 'config-1'
+ Configuration 0 (config-1)
Description: Boot Linux kernel
- Kernel: kernel@1
+ Kernel: kernel
Booting the FIT
[IF_TYPE_HOST] = "host",
[IF_TYPE_SYSTEMACE] = "ace",
[IF_TYPE_NVME] = "nvme",
+ [IF_TYPE_EFI] = "efi",
};
static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
[IF_TYPE_SD] = UCLASS_INVALID,
[IF_TYPE_SATA] = UCLASS_AHCI,
[IF_TYPE_HOST] = UCLASS_ROOT,
- [IF_TYPE_NVME] = UCLASS_NVME,
[IF_TYPE_SYSTEMACE] = UCLASS_INVALID,
+ [IF_TYPE_NVME] = UCLASS_NVME,
+ [IF_TYPE_EFI] = UCLASS_EFI,
};
static enum if_type if_typename_to_iftype(const char *if_typename)
#
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
-obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
-obj-$(CONFIG_SANDBOX) += clk_sandbox.o
-obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
-obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
-obj-$(CONFIG_CLK_RENESAS) += renesas/
-obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
-obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
obj-y += tegra/
-obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
-obj-$(CONFIG_CLK_EXYNOS) += exynos/
+obj-$(CONFIG_ARCH_ASPEED) += aspeed/
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
+obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
-obj-$(CONFIG_ARCH_ASPEED) += aspeed/
+obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
+obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
+obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
+obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
* |-->| TUNNEL PLL |
* | --------------
* | |
- * | |-->|CGU_TUN_IDIV|----------->
+ * | |-->|CGU_TUN_IDIV_TUN|----------->
+ * | |-->|CGU_TUN_IDIV_ROM|----------->
+ * | |-->|CGU_TUN_IDIV_PWM|----------->
* |
* | ------------
* |-->| HDMI PLL |
DECLARE_GLOBAL_DATA_PTR;
#define CGU_ARC_IDIV 0x080
-#define CGU_TUN_IDIV 0x380
+#define CGU_TUN_IDIV_TUN 0x380
+#define CGU_TUN_IDIV_ROM 0x390
+#define CGU_TUN_IDIV_PWM 0x3A0
#define CGU_HDMI_IDIV_APB 0x480
#define CGU_SYS_IDIV_APB 0x180
#define CGU_SYS_IDIV_AXI 0x190
#define CREG_CORE_IF_CLK_DIV_1 0x0
#define CREG_CORE_IF_CLK_DIV_2 0x1
+#define MIN_PLL_RATE 100000000 /* 100 MHz */
#define PARENT_RATE 33333333 /* fixed clock - xtal */
-#define CGU_MAX_CLOCKS 24
+#define CGU_MAX_CLOCKS 26
+
+#define CGU_SYS_CLOCKS 16
+#define MAX_AXI_CLOCKS 4
+
+#define CGU_TUN_CLOCKS 3
+#define MAX_TUN_CLOCKS 6
+
+struct hsdk_tun_idiv_cfg {
+ u32 oft;
+ u8 val[MAX_TUN_CLOCKS];
+};
+
+struct hsdk_tun_clk_cfg {
+ const u32 clk_rate[MAX_TUN_CLOCKS];
+ const u32 pll_rate[MAX_TUN_CLOCKS];
+ const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
+};
+
+static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
+ { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
+ { 600000000, 600000000, 600000000, 600000000, 700000000, 600000000 }, {
+ { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
+ { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
+ { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } }
+ }
+};
+
+struct hsdk_sys_idiv_cfg {
+ u32 oft;
+ u8 val[MAX_AXI_CLOCKS];
+};
+
+struct hsdk_axi_clk_cfg {
+ const u32 clk_rate[MAX_AXI_CLOCKS];
+ const u32 pll_rate[MAX_AXI_CLOCKS];
+ const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
+};
+
+static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
+ { 200000000, 400000000, 600000000, 800000000 },
+ { 800000000, 800000000, 600000000, 800000000 }, {
+ { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
+ { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
+ { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
+ { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
+ { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
+ { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
+ { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
+ { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
+ { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
+ { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
+ { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
+ { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
+ { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
+ { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
+ { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
+ { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
+ }
+};
struct hsdk_pll_cfg {
u32 rate;
};
static ulong idiv_set(struct clk *, ulong);
+static ulong cpu_clk_set(struct clk *, ulong);
+static ulong axi_clk_set(struct clk *, ulong);
+static ulong tun_clk_set(struct clk *, ulong);
static ulong idiv_get(struct clk *);
static int idiv_off(struct clk *);
static ulong pll_set(struct clk *, ulong);
static const struct hsdk_cgu_clock_map clock_map[] = {
{ CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
- { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
{ CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
{ CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
- { CGU_TUN_PLL, 0, CGU_TUN_IDIV, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
{ CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
};
}
}
- pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE);
+ pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE);
return -EINVAL;
}
return parent_rate / div_factor;
}
+/* Special behavior: wen we set this clock we set both idiv and pll */
+static ulong cpu_clk_set(struct clk *sclk, ulong rate)
+{
+ ulong ret;
+
+ ret = pll_set(sclk, rate);
+ idiv_set(sclk, rate);
+
+ return ret;
+}
+
+/* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */
+static ulong axi_clk_set(struct clk *sclk, ulong rate)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong pll_rate;
+ int i, freq_idx = -1;
+ ulong ret = 0;
+
+ pll_rate = pll_get(sclk);
+
+ for (i = 0; i < MAX_AXI_CLOCKS; i++) {
+ if (axi_clk_cfg.clk_rate[i] == rate) {
+ freq_idx = i;
+ break;
+ }
+ }
+
+ if (freq_idx < 0) {
+ pr_err("axi clk: invalid rate=%ld Hz\n", rate);
+ return -EINVAL;
+ }
+
+ /* configure PLL before dividers */
+ if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
+ ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
+
+ /* configure SYS dividers */
+ for (i = 0; i < CGU_SYS_CLOCKS; i++) {
+ clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
+ hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);
+ }
+
+ /* configure PLL after dividers */
+ if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate)
+ ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
+
+ return ret;
+}
+
+static ulong tun_clk_set(struct clk *sclk, ulong rate)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong pll_rate;
+ int i, freq_idx = -1;
+ ulong ret = 0;
+
+ pll_rate = pll_get(sclk);
+
+ for (i = 0; i < MAX_TUN_CLOCKS; i++) {
+ if (tun_clk_cfg.clk_rate[i] == rate) {
+ freq_idx = i;
+ break;
+ }
+ }
+
+ if (freq_idx < 0) {
+ pr_err("tun clk: invalid rate=%ld Hz\n", rate);
+ return -EINVAL;
+ }
+
+ /* configure PLL before dividers */
+ if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate)
+ ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
+
+ /* configure SYS dividers */
+ for (i = 0; i < CGU_TUN_CLOCKS; i++) {
+ clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;
+ hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);
+ }
+
+ /* configure PLL after dividers */
+ if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate)
+ ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
+
+ return ret;
+}
+
static ulong idiv_set(struct clk *sclk, ulong rate)
{
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
}
if (div_factor & ~CGU_IDIV_MASK) {
- pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n",
+ pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
rate, parent_rate, div_factor, CGU_IDIV_MASK);
div_factor = CGU_IDIV_MASK;
}
if (div_factor == 0) {
- pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n",
+ pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
rate, parent_rate, div_factor);
div_factor = 1;
.id = UCLASS_CLK,
.of_match = hsdk_cgu_clk_id,
.probe = hsdk_cgu_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
+ .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
.ops = &hsdk_cgu_ops,
};
#include <dt-structs.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
+static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
{
- return (struct clk_ops *)dev->driver->ops;
+ return (const struct clk_ops *)dev->driver->ops;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
int ret;
struct ofnode_phandle_args args;
struct udevice *dev_clk;
- struct clk_ops *ops;
+ const struct clk_ops *ops;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
clk->dev = NULL;
ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
- index, &args);
+ index, &args);
if (ret) {
debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
__func__, ret);
int clk_request(struct udevice *dev, struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(dev);
+ const struct clk_ops *ops = clk_dev_ops(dev);
debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
int clk_free(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
ulong clk_get_rate(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
ulong clk_set_rate(struct clk *clk, ulong rate)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
int clk_enable(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
int clk_disable(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
#include <clk-uclass.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct clk_fixed_rate {
unsigned long fixed_rate;
};
static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- to_clk_fixed_rate(dev)->fixed_rate = dev_read_u32_default(dev,
- "clock-frequency", 0);
+ to_clk_fixed_rate(dev)->fixed_rate =
+ dev_read_u32_default(dev, "clock-frequency", 0);
#endif
return 0;
#include <asm/io.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_pwr.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
*/
#define RCC_APB2ENR_SYSCFGEN BIT(14)
+enum periph_clock {
+ SYSCFG_CLOCK_CFG,
+ TIMER2_CLOCK_CFG,
+ STMMAC_CLOCK_CFG,
+};
+
struct stm32_clk_info stm32f4_clk_info = {
/* 180 MHz */
.sys_pll_psc = {
#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <dm/of_access.h>
#include <dm/pinctrl.h>
#include <dm/platdata.h>
#include <dm/read.h>
bool device_is_compatible(struct udevice *dev, const char *compat)
{
const void *fdt = gd->fdt_blob;
+ ofnode node = dev_ofnode(dev);
- return !fdt_node_check_compatible(fdt, dev_of_offset(dev), compat);
+ if (ofnode_is_np(node))
+ return of_device_is_compatible(ofnode_to_np(node), compat, NULL, NULL);
+ else
+ return !fdt_node_check_compatible(fdt, ofnode_to_offset(node), compat);
}
bool of_machine_is_compatible(const char *compat)
&flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
- na = of_n_addr_cells(ofnode_to_np(node));
- return of_read_number(prop_val, na);
+
+ if (IS_ENABLED(CONFIG_OF_TRANSLATE)) {
+ return of_translate_address(ofnode_to_np(node), prop_val);
+ } else {
+ na = of_n_addr_cells(ofnode_to_np(node));
+ return of_read_number(prop_val, na);
+ }
} else {
return fdt_get_base_address(gd->fdt_blob,
ofnode_to_offset(node));
int ret;
ret = of_parse_phandle_with_args(ofnode_to_np(node),
- list_name, cells_name, index, &args);
+ list_name, cells_name, index,
+ &args);
if (ret)
return ret;
ofnode_from_of_phandle_args(&args, out_args);
int ret;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
- ofnode_to_offset(node), list_name, cells_name,
- cell_count, index, &args);
+ ofnode_to_offset(node),
+ list_name, cells_name,
+ cell_count, index, &args);
if (ret)
return ret;
ofnode_from_fdtdec_phandle_args(&args, out_args);
addr->phys_mid = fdt32_to_cpu(cell[1]);
addr->phys_lo = fdt32_to_cpu(cell[1]);
break;
- } else {
- cell += (FDT_PCI_ADDR_CELLS +
- FDT_PCI_SIZE_CELLS);
}
+
+ cell += (FDT_PCI_ADDR_CELLS +
+ FDT_PCI_SIZE_CELLS);
}
if (i == num) {
}
return 0;
- } else {
- ret = -EINVAL;
}
+ ret = -EINVAL;
+
fail:
debug("(not found)\n");
return ret;
return ofnode_read_resource(node, index, res);
}
+
+u64 ofnode_translate_address(ofnode node, const fdt32_t *in_addr)
+{
+ if (ofnode_is_np(node))
+ return of_translate_address(ofnode_to_np(node), in_addr);
+ else
+ return fdt_translate_address(gd->fdt_blob, ofnode_to_offset(node), in_addr);
+}
#include <mapmem.h>
#include <dm/of_access.h>
+int dev_read_u32(struct udevice *dev, const char *propname, u32 *outp)
+{
+ return ofnode_read_u32(dev_ofnode(dev), propname, outp);
+}
+
int dev_read_u32_default(struct udevice *dev, const char *propname, int def)
{
return ofnode_read_u32_default(dev_ofnode(dev), propname, def);
}
fdt_addr_t dev_read_addr_size(struct udevice *dev, const char *property,
- fdt_size_t *sizep)
+ fdt_size_t *sizep)
{
return ofnode_get_addr_size(dev_ofnode(dev), property, sizep);
}
}
int dev_read_stringlist_search(struct udevice *dev, const char *property,
- const char *string)
+ const char *string)
{
return ofnode_stringlist_search(dev_ofnode(dev), property, string);
}
}
int dev_read_phandle_with_args(struct udevice *dev, const char *list_name,
- const char *cells_name, int cell_count,
- int index,
- struct ofnode_phandle_args *out_args)
+ const char *cells_name, int cell_count,
+ int index, struct ofnode_phandle_args *out_args)
{
return ofnode_parse_phandle_with_args(dev_ofnode(dev), list_name,
cells_name, cell_count, index,
out_args);
}
+int dev_count_phandle_with_args(struct udevice *dev, const char *list_name,
+ const char *cells_name)
+{
+ return ofnode_count_phandle_with_args(dev_ofnode(dev), list_name,
+ cells_name);
+}
+
int dev_read_addr_cells(struct udevice *dev)
{
return ofnode_read_addr_cells(dev_ofnode(dev));
{
return ofnode_read_resource_byname(dev_ofnode(dev), name, res);
}
+
+u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr)
+{
+ return ofnode_translate_address(dev_ofnode(dev), in_addr);
+}
for (offset = fdt_first_subnode(blob, offset);
offset > 0;
offset = fdt_next_subnode(blob, offset)) {
+ /* "chosen" node isn't a device itself but may contain some: */
+ if (!strcmp(fdt_get_name(blob, offset, NULL), "chosen")) {
+ pr_debug("parsing subnodes of \"chosen\"\n");
+
+ err = dm_scan_fdt_node(parent, blob, offset,
+ pre_reloc_only);
+ if (err && !ret)
+ ret = err;
+ continue;
+ }
+
if (pre_reloc_only &&
!dm_fdt_pre_reloc(blob, offset))
continue;
#include <common.h>
#include <malloc.h>
+#include <memalign.h>
#include "jobdesc.h"
#include "desc.h"
#include "jr.h"
{
int ret = 0;
uint32_t *desc;
+ unsigned int size;
- desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
+ desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
if (!desc) {
debug("Not enough memory for descriptor allocation\n");
return -ENOMEM;
}
+ if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) ||
+ !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) {
+ puts("Error: Address arguments are not aligned\n");
+ return -EINVAL;
+ }
+
+ size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
+ flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size);
+
inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout,
driver_hash[algo].alg_type,
driver_hash[algo].digestsize,
0);
+ size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
+ flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+
ret = run_descriptor_jr(desc);
+ size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range((unsigned long)pout,
+ (unsigned long)pout + size);
+
free(desc);
return ret;
}
if (step == 2)
goto step2;
+ /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
+ ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+
if (regs->ddr_eor)
ddr_out32(&ddr->eor, regs->ddr_eor);
ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
- ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
#ifdef CONFIG_DEEP_SLEEP
if (is_warm_boot()) {
ddr_out32(&ddr->sdram_cfg_2,
extern u32 g_zpodt_ctrl;
extern u32 g_znodt_ctrl;
extern u32 g_dic;
-extern u32 g_odt_config;
+extern u32 g_odt_config_2cs;
+extern u32 g_odt_config_1cs;
extern u32 g_rtt_nom;
extern u8 debug_training_access;
SPEED_BIN_TWTR,
SPEED_BIN_TRTP,
SPEED_BIN_TWR,
- SPEED_BIN_TMOD
+ SPEED_BIN_TMOD,
+ SPEED_BIN_TXPDLL
};
#endif /* _DDR3_TOPOLOGY_DEF_H */
#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
+#define TIMES_9_TREFI_CYCLES 0x8
+
u32 window_mem_addr = 0;
u32 phy_reg0_val = 0;
u32 phy_reg1_val = 8;
enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
u32 data_read[MAX_INTERFACE_NUM];
struct hws_topology_map *tm = ddr3_get_topology_map();
+ u32 odt_config = g_odt_config_2cs;
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("cl_value 0x%x cwl_val 0x%x\n",
cl_value, cwl_val));
-
+ t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TWR),
+ t_ckclk);
data_value =
((cl_mask_table[cl_value] & 0x1) << 2) |
((cl_mask_table[cl_value] & 0xe) << 3);
(0x7 << 4) | (1 << 2)));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
- MR0_REG, twr_mask_table[t_wr + 1],
- 0xe00));
+ MR0_REG, twr_mask_table[t_wr + 1] << 9,
+ (0x7 << 9)));
+
/*
* MR1: Set RTT and DIC Design GL values
DUNIT_CONTROL_HIGH_REG,
(init_cntr_prm->msys_init << 7), (1 << 7)));
+ /* calculate number of CS (per interface) */
+ CHECK_STATUS(calc_cs_num
+ (dev_num, if_id, &cs_num));
timing = tm->interface_params[if_id].timing;
if (mode2_t != 0xff) {
/* Board topology map is forcing timing */
t2t = (timing == HWS_TIM_2T) ? 1 : 0;
} else {
- /* calculate number of CS (per interface) */
- CHECK_STATUS(calc_cs_num
- (dev_num, if_id, &cs_num));
t2t = (cs_num == 1) ? 0 : 1;
}
DDR_CONTROL_LOW_REG, t2t << 3,
0x3 << 3));
/* move the block to ddr3_tip_set_timing - start */
- t_pd = GET_MAX_VALUE(t_ckclk * 3,
- speed_bin_table(speed_bin_index,
- SPEED_BIN_TPD));
- t_pd = TIME_2_CLOCK_CYCLES(t_pd, t_ckclk);
- txpdll = GET_MAX_VALUE(t_ckclk * 10, 24);
+ t_pd = TIMES_9_TREFI_CYCLES;
+ txpdll = GET_MAX_VALUE(t_ckclk * 10,
+ speed_bin_table(speed_bin_index,
+ SPEED_BIN_TXPDLL));
txpdll = CEIL_DIVIDE((txpdll - 1), t_ckclk);
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
- DDR_TIMING_REG, txpdll << 4,
- 0x1f << 4));
+ DDR_TIMING_REG, txpdll << 4 | t_pd,
+ 0x1f << 4 | 0xf));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DDR_TIMING_REG, 0x28 << 9, 0x3f << 9));
(1 << 11)));
/* Set Active control for ODT write transactions */
+ if (cs_num == 1)
+ odt_config = g_odt_config_1cs;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_MULTICAST,
- PARAM_NOT_CARE, 0x1494, g_odt_config,
+ PARAM_NOT_CARE, 0x1494, odt_config,
MASK_ALL_BITS));
}
} else {
u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0,
bus_cnt = 0, t_hclk = 0, t_wr = 0,
refresh_interval_cnt = 0, cnt_id;
+ u32 t_ckclk;
u32 t_refi = 0, end_if, start_if;
u32 bus_index = 0;
int is_dll_off = 0;
/* adjust t_refi to new frequency */
t_refi = (tm->interface_params[if_id].interface_temp ==
- HWS_TEMP_HIGH) ? TREFI_LOW : TREFI_HIGH;
+ HWS_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW;
t_refi *= 1000; /*psec */
/* HCLK in[ps] */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id, DFS_REG,
(cwl_mask_table[cwl_value] << 12), 0x7000));
- t_wr = speed_bin_table(speed_bin_index, SPEED_BIN_TWR);
- t_wr = (t_wr / 1000);
+
+ t_ckclk = MEGA / freq_val[frequency];
+ t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TWR),
+ t_ckclk);
+
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id, DFS_REG,
(twr_mask_table[t_wr + 1] << 16), 0x70000));
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
if_id, ODT_TIMING_LOW,
val, 0xffff0));
- val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
if_id, ODT_TIMING_HI_REG,
val, 0xffff));
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
ODT_TIMING_LOW, val, 0xffff0));
- val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
ODT_TIMING_HI_REG, val, 0xffff));
if (odt_additional == 1) {
10,
10,
10,
- 1, /*5 */
- 2, /*6 */
- 3, /*7 */
+ 1, /*5*/
+ 2, /*6*/
+ 3, /*7*/
+ 4, /*8*/
10,
+ 5, /*10*/
10,
- 5, /*10 */
+ 6, /*12*/
10,
- 6, /*12 */
+ 7, /*14*/
10,
- 7, /*14 */
- 10,
- 0 /*16 */
+ 0 /*16*/
};
u8 cl_mask_table[] = {
case SPEED_BIN_TMOD:
result = 15000;
break;
+ case SPEED_BIN_TXPDLL:
+ result = 24000;
+ break;
default:
break;
}
#define VREF_MAX_INDEX 7
#define MAX_VALUE (1024 - 1)
#define MIN_VALUE (-MAX_VALUE)
-#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf)
+#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f)
u32 ck_delay = (u32)-1, ck_delay_16 = (u32)-1;
u32 ca_delay;
*/
int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
{
- u32 cs_num = 0, max_read_sample = 0, min_read_sample = 0;
+ u32 cs_num = 0, max_cs = 0, max_read_sample = 0, min_read_sample = 0x1f;
u32 data_read[MAX_INTERFACE_NUM] = { 0 };
u32 read_sample[MAX_CS_NUM];
u32 val;
data_read, MASK_ALL_BITS));
val = data_read[if_id];
- for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) {
+ max_cs = hws_ddr3_tip_max_cs_get();
+
+ for (cs_num = 0; cs_num < max_cs; cs_num++) {
read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
/* find maximum of read_samples */
if (read_sample[cs_num] >= max_read_sample) {
- if (read_sample[cs_num] == max_read_sample)
- max_phase = MIN_VALUE;
- else
+ if (read_sample[cs_num] == max_read_sample) {
+ /* search for max phase */;
+ } else {
max_read_sample = read_sample[cs_num];
+ max_phase = MIN_VALUE;
+ }
for (pup_index = 0;
pup_index < tm->num_of_bus_per_interface;
min_read_sample = read_sample[cs_num];
}
+ if (min_read_sample <= tm->interface_params[if_id].cas_l) {
+ min_read_sample = (int)tm->interface_params[if_id].cas_l;
+ }
+
min_read_sample = min_read_sample - 1;
max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
- if (min_read_sample >= 0xf)
- min_read_sample = 0xf;
if (max_read_sample >= 0x1f)
max_read_sample = 0x1f;
u32 g_znodt_data = 45; /* controller data - N ODT */
u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
u32 g_znodt_ctrl = 45; /* controller data - N ODT */
-u32 g_odt_config = 0x120012;
+u32 g_odt_config_2cs = 0x120012;
+u32 g_odt_config_1cs = 0x10000;
u32 g_rtt_nom = 0x44;
u32 g_dic = 0x2;
#define EDMA3_QEESR 0x108c
#define EDMA3_QSECR 0x1094
+#define EDMA_FILL_BUFFER_SIZE 512
+
struct ti_edma3_priv {
u32 base;
};
+static u8 edma_fill_buffer[EDMA_FILL_BUFFER_SIZE] __aligned(ARCH_DMA_MINALIGN);
+
/**
* qedma3_start - start qdma on a channel
* @base: base address of edma
}
void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
- void *dst, void *src, size_t len)
+ void *dst, void *src, size_t len, size_t s_len)
{
struct edma3_slot_config slot;
struct edma3_channel_config edma_channel;
unsigned int addr = (unsigned int) (dst);
unsigned int max_acnt = 0x7FFFU;
- if (len > max_acnt) {
+ if (len > s_len) {
+ b_cnt_value = (len / s_len);
+ rem_bytes = (len % s_len);
+ a_cnt_value = s_len;
+ } else if (len > max_acnt) {
b_cnt_value = (len / max_acnt);
rem_bytes = (len % max_acnt);
a_cnt_value = max_acnt;
slot.acnt = a_cnt_value;
slot.bcnt = b_cnt_value;
slot.ccnt = 1;
- slot.src_bidx = a_cnt_value;
+ if (len == s_len)
+ slot.src_bidx = a_cnt_value;
+ else
+ slot.src_bidx = 0;
slot.dst_bidx = a_cnt_value;
slot.src_cidx = 0;
slot.dst_cidx = 0;
if (rem_bytes != 0) {
slot.opt = 0;
- slot.src =
- (b_cnt_value * max_acnt) + ((unsigned int) src);
+ if (len == s_len)
+ slot.src =
+ (b_cnt_value * max_acnt) + ((unsigned int) src);
+ else
+ slot.src = (unsigned int) src;
slot.acnt = rem_bytes;
slot.bcnt = 1;
slot.ccnt = 1;
}
}
+void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+ void *dst, u8 val, size_t len)
+{
+ int xfer_len;
+ int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535;
+
+ memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer));
+
+ while (len) {
+ xfer_len = len;
+ if (xfer_len > max_xfer)
+ xfer_len = max_xfer;
+
+ __edma3_transfer(edma3_base_addr, edma_slot_num, dst,
+ edma_fill_buffer, xfer_len,
+ EDMA_FILL_BUFFER_SIZE);
+ len -= xfer_len;
+ dst += xfer_len;
+ }
+}
+
#ifndef CONFIG_DMA
void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
void *dst, void *src, size_t len)
{
- __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len);
+ __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len);
+}
+
+void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+ void *dst, u8 val, size_t len)
+{
+ __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len);
}
#else
switch (direction) {
case DMA_MEM_TO_MEM:
- __edma3_transfer(priv->base, 1, dst, src, len);
+ __edma3_transfer(priv->base, 1, dst, src, len, len);
break;
default:
pr_err("Transfer type not implemented in DMA driver\n");
obj-$(CONFIG_TCA642X) += tca642x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
-obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o
obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o
obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
return (int)val;
}
-#ifdef CONFIG_CMD_PCA953X
+#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_SPL_BUILD)
/*
* Display pca953x information
*/
return 0;
}
-cmd_tbl_t cmd_pca953x[] = {
+static cmd_tbl_t cmd_pca953x[] = {
U_BOOT_CMD_MKENT(device, 3, 0, (void *)PCA953X_CMD_DEVICE, "", ""),
U_BOOT_CMD_MKENT(output, 4, 0, (void *)PCA953X_CMD_OUTPUT, "", ""),
U_BOOT_CMD_MKENT(input, 3, 0, (void *)PCA953X_CMD_INPUT, "", ""),
U_BOOT_CMD_MKENT(info, 2, 0, (void *)PCA953X_CMD_INFO, "", ""),
};
-int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
int ret = CMD_RET_USAGE, val;
#define REG_STATUS_VAL_MASK 0x1
/* MODE_CTL */
-#define REG_CTL 0x40
+#define REG_CTL 0x40
#define REG_CTL_MODE_MASK 0x70
#define REG_CTL_MODE_INPUT 0x00
#define REG_CTL_MODE_INOUT 0x20
return -ENODEV;
reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
- if (reg != 0x5)
+ if (reg != 0x5 && reg != 0x1)
return -ENODEV;
return 0;
static const struct udevice_id pm8916_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
+ { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
{ }
};
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->gpio_count = 2;
+ uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
if (uc_priv->bank_name == NULL)
uc_priv->bank_name = "pm8916_key";
static const struct udevice_id pm8941_pwrkey_ids[] = {
{ .compatible = "qcom,pm8916-pwrkey" },
+ { .compatible = "qcom,pm8994-pwrkey" },
{ }
};
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * Copyright 2015 ATS Advanced Telematics Systems GmbH
- * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const unsigned long io_base[] = {
- STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
- STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
- STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-#define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15)
-#define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
- x->pupd > 2 || x->speed > 3)
-
-int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
- const struct stm32_gpio_ctl *ctl)
-{
- struct stm32_gpio_regs *gpio_regs;
- u32 i;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
- if (CHECK_CTL(ctl)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
- i = (dsc->pin & 0x07) * 4;
- clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
-
- i = dsc->pin * 2;
-
- clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
- clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
- clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
- clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
-
- rv = 0;
-out:
- return rv;
-}
-
-int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
-{
- struct stm32_gpio_regs *gpio_regs;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
- if (state)
- writel(1 << dsc->pin, &gpio_regs->bsrr);
- else
- writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
-
- rv = 0;
-out:
- return rv;
-}
-
-int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
-{
- struct stm32_gpio_regs *gpio_regs;
- int rv;
-
- if (CHECK_DSC(dsc)) {
- rv = -EINVAL;
- goto out;
- }
-
- gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
- rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
-out:
- return rv;
-}
-
-/* Common GPIO API */
-
-int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
- return 0;
-}
-
-int gpio_direction_input(unsigned gpio)
-{
- struct stm32_gpio_dsc dsc;
- struct stm32_gpio_ctl ctl;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
- ctl.af = STM32_GPIO_AF0;
- ctl.mode = STM32_GPIO_MODE_IN;
- ctl.otype = STM32_GPIO_OTYPE_PP;
- ctl.pupd = STM32_GPIO_PUPD_NO;
- ctl.speed = STM32_GPIO_SPEED_50M;
-
- return stm32_gpio_config(&dsc, &ctl);
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- struct stm32_gpio_dsc dsc;
- struct stm32_gpio_ctl ctl;
- int res;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
- ctl.af = STM32_GPIO_AF0;
- ctl.mode = STM32_GPIO_MODE_OUT;
- ctl.pupd = STM32_GPIO_PUPD_NO;
- ctl.speed = STM32_GPIO_SPEED_50M;
-
- res = stm32_gpio_config(&dsc, &ctl);
- if (res < 0)
- goto out;
- res = stm32_gpout_set(&dsc, value);
-out:
- return res;
-}
-
-int gpio_get_value(unsigned gpio)
-{
- struct stm32_gpio_dsc dsc;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
-
- return stm32_gpin_get(&dsc);
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
- struct stm32_gpio_dsc dsc;
-
- dsc.port = stm32_gpio_to_port(gpio);
- dsc.pin = stm32_gpio_to_pin(gpio);
-
- return stm32_gpout_set(&dsc, value);
-}
return ret;
}
-#ifdef CONFIG_CMD_TCA642X
+#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_SPL_BUILD)
/*
* Display tca642x information
*/
return 0;
}
-cmd_tbl_t cmd_tca642x[] = {
+static cmd_tbl_t cmd_tca642x[] = {
U_BOOT_CMD_MKENT(device, 3, 0, (void *)TCA642X_CMD_DEVICE, "", ""),
U_BOOT_CMD_MKENT(output, 4, 0, (void *)TCA642X_CMD_OUTPUT, "", ""),
U_BOOT_CMD_MKENT(input, 3, 0, (void *)TCA642X_CMD_INPUT, "", ""),
U_BOOT_CMD_MKENT(info, 2, 0, (void *)TCA642X_CMD_INFO, "", ""),
};
-int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR;
int ret = CMD_RET_USAGE, val;
int i;
regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
- clock_rate = imx_get_i2cclk(bus->seq + 4);
+ clock_rate = imx_get_i2cclk(bus->seq);
if (!clock_rate)
return -EPERM;
i2c_bus->bus = bus;
/* power up i2c resource */
- ret = init_i2c_power(bus->seq + 4);
+ ret = init_i2c_power(bus->seq);
if (ret) {
debug("init_i2c_power err = %d\n", ret);
return ret;
}
- /* Enable clk, only i2c4-7 can be handled by A7 core */
- ret = enable_i2c_clk(1, bus->seq + 4);
+ /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
+ ret = enable_i2c_clk(1, bus->seq);
if (ret < 0)
return ret;
ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
"sda-gpios", 0, &i2c_bus->sda_gpio,
GPIOD_IS_OUT);
- if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) |
- !dm_gpio_is_valid(&i2c_bus->scl_gpio) |
- ret | ret2) {
+ if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
+ !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
+ ret || ret2) {
dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
return -EINVAL;
}
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
+obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
--- /dev/null
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#ifdef CONFIG_PPC
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#endif
+#include <fsl_qbman.h>
+
+#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
+#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
+void setup_qbman_portals(void)
+{
+ void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
+ CONFIG_SYS_BMAN_SWP_ISDR_REG;
+ void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
+ CONFIG_SYS_QMAN_SWP_ISDR_REG;
+#ifdef CONFIG_PPC
+ struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+
+ /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+ out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+ out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+#endif
+#ifdef CONFIG_FSL_CORENET
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+ u8 sdest = qp_info[i].sdest;
+ u16 fliodn = qp_info[i].fliodn;
+ u16 dliodn = qp_info[i].dliodn;
+ u16 liodn_off = qp_info[i].liodn_offset;
+
+ out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
+ dliodn);
+ /* set frame liodn */
+ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
+ }
+#endif
+
+ /* Change default state of BMan ISDR portals to all 1s */
+ inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
+ CONFIG_SYS_BMAN_SP_CINH_SIZE);
+ inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
+ CONFIG_SYS_QMAN_SP_CINH_SIZE);
+}
+
+void inhibit_portals(void __iomem *addr, int max_portals,
+ int arch_max_portals, int portal_cinh_size)
+{
+ u32 val;
+ int i;
+
+ /* arch_max_portals is the maximum based on memory size. This includes
+ * the reserved memory in the SoC. max_portals the number of physical
+ * portals in the SoC
+ */
+ if (max_portals > arch_max_portals) {
+ printf("ERROR: portal config error\n");
+ max_portals = arch_max_portals;
+ }
+
+ for (i = 0; i < max_portals; i++) {
+ out_be32(addr, -1);
+ val = in_be32(addr);
+ if (!val) {
+ printf("ERROR: Stopped after %d portals\n", i);
+ return;
+ }
+ addr += portal_cinh_size;
+ }
+ debug("Cleared %d portals\n", i);
+}
+
+#ifdef CONFIG_PPC
+static int fdt_qportal(void *blob, int off, int id, char *name,
+ enum fsl_dpaa_dev dev, int create)
+{
+ int childoff, dev_off, ret = 0;
+ u32 dev_handle;
+#ifdef CONFIG_FSL_CORENET
+ int num;
+ u32 liodns[2];
+#endif
+
+ childoff = fdt_subnode_offset(blob, off, name);
+ if (create) {
+ char handle[64], *p;
+
+ strncpy(handle, name, sizeof(handle));
+ p = strchr(handle, '@');
+ if (!strncmp(name, "fman", 4)) {
+ *p = *(p + 1);
+ p++;
+ }
+ *p = '\0';
+
+ dev_off = fdt_path_offset(blob, handle);
+ /* skip this node if alias is not found */
+ if (dev_off == -FDT_ERR_BADPATH)
+ return 0;
+ if (dev_off < 0)
+ return dev_off;
+
+ if (childoff <= 0)
+ childoff = fdt_add_subnode(blob, off, name);
+
+ /* need to update the dev_off after adding a subnode */
+ dev_off = fdt_path_offset(blob, handle);
+ if (dev_off < 0)
+ return dev_off;
+
+ if (childoff > 0) {
+ dev_handle = fdt_get_phandle(blob, dev_off);
+ if (dev_handle <= 0) {
+ dev_handle = fdt_alloc_phandle(blob);
+ ret = fdt_set_phandle(blob, dev_off,
+ dev_handle);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = fdt_setprop(blob, childoff, "dev-handle",
+ &dev_handle, sizeof(dev_handle));
+ if (ret < 0)
+ return ret;
+
+#ifdef CONFIG_FSL_CORENET
+ num = get_dpaa_liodn(dev, &liodns[0], id);
+ ret = fdt_setprop(blob, childoff, "fsl,liodn",
+ &liodns[0], sizeof(u32) * num);
+ if (!strncmp(name, "pme", 3)) {
+ u32 pme_rev1, pme_rev2;
+ ccsr_pme_t *pme_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+
+ pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
+ pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
+ ret = fdt_setprop(blob, childoff,
+ "fsl,pme-rev1", &pme_rev1,
+ sizeof(u32));
+ if (ret < 0)
+ return ret;
+ ret = fdt_setprop(blob, childoff,
+ "fsl,pme-rev2", &pme_rev2,
+ sizeof(u32));
+ }
+#endif
+ } else {
+ return childoff;
+ }
+ } else {
+ if (childoff > 0)
+ ret = fdt_del_node(blob, childoff);
+ }
+
+ return ret;
+}
+#endif /* CONFIG_PPC */
+
+void fdt_fixup_qportals(void *blob)
+{
+ int off, err;
+ unsigned int maj, min;
+ unsigned int ip_cfg;
+ struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+ u32 rev_1 = in_be32(&qman->ip_rev_1);
+ u32 rev_2 = in_be32(&qman->ip_rev_2);
+ char compat[64];
+ int compat_len;
+
+ maj = (rev_1 >> 8) & 0xff;
+ min = rev_1 & 0xff;
+ ip_cfg = rev_2 & 0xff;
+
+ compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
+ compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
+ while (off != -FDT_ERR_NOTFOUND) {
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+ u32 liodns[2];
+#endif
+ const int *ci = fdt_getprop(blob, off, "cell-index", &err);
+ int i;
+
+ if (!ci)
+ goto err;
+
+ i = *ci;
+#ifdef CONFIG_SYS_DPAA_FMAN
+ int j;
+#endif
+
+#endif /* CONFIG_PPC */
+ err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+ if (err < 0)
+ goto err;
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+ liodns[0] = qp_info[i].dliodn;
+ liodns[1] = qp_info[i].fliodn;
+ err = fdt_setprop(blob, off, "fsl,liodn",
+ &liodns, sizeof(u32) * 2);
+ if (err < 0)
+ goto err;
+#endif
+
+ i++;
+
+ err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
+ IS_E_PROCESSOR(get_svr()));
+ if (err < 0)
+ goto err;
+
+#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_DPAA_PME
+ err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
+ if (err < 0)
+ goto err;
+#else
+ fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
+#endif
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+ char name[] = "fman@0";
+
+ name[sizeof(name) - 2] = '0' + j;
+ err = fdt_qportal(blob, off, i, name,
+ FSL_HW_PORTAL_FMAN1 + j, 1);
+ if (err < 0)
+ goto err;
+ }
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+ err = fdt_qportal(blob, off, i, "rman@0",
+ FSL_HW_PORTAL_RMAN, 1);
+ if (err < 0)
+ goto err;
+#endif
+#endif /* CONFIG_PPC */
+
+err:
+ if (err < 0) {
+ printf("ERROR: unable to create props for %s: %s\n",
+ fdt_get_name(blob, off, NULL),
+ fdt_strerror(err));
+ return;
+ }
+
+ off = fdt_node_offset_by_compatible(blob, off,
+ "fsl,qman-portal");
+ }
+}
+
+void fdt_fixup_bportals(void *blob)
+{
+ int off, err;
+ unsigned int maj, min;
+ unsigned int ip_cfg;
+ struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
+ u32 rev_1 = in_be32(&bman->ip_rev_1);
+ u32 rev_2 = in_be32(&bman->ip_rev_2);
+ char compat[64];
+ int compat_len;
+
+ maj = (rev_1 >> 8) & 0xff;
+ min = rev_1 & 0xff;
+
+ ip_cfg = rev_2 & 0xff;
+
+ compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
+ compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
+ while (off != -FDT_ERR_NOTFOUND) {
+ err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+ if (err < 0) {
+ printf("ERROR: unable to create props for %s: %s\n",
+ fdt_get_name(blob, off, NULL),
+ fdt_strerror(err));
+ return;
+ }
+
+ off = fdt_node_offset_by_compatible(blob, off,
+ "fsl,bman-portal");
+ }
+}
static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
const char *caller)
{
+#ifdef CONFIG_MX7ULP
+ u32 val;
+ int ret;
+
+ /* Only bank 0 and 1 are redundancy mode, others are ECC mode */
+ if (bank != 0 && bank != 1) {
+ ret = fuse_sense(bank, word, &val);
+ if (ret)
+ return ret;
+
+ if (val != 0) {
+ printf("mxc_ocotp: The word has been programmed, no more write\n");
+ return -EPERM;
+ }
+ }
+#endif
+
return prepare_access(regs, bank, word, true, caller);
}
If you want MMC/SD/SDIO support, you should say Y here and
also to your specific host controller driver.
+config MMC_WRITE
+ bool "support for MMC/SD write operations"
+ depends on MMC
+ default y
+ help
+ Enable write access to MMC and SD Cards
+
+config MMC_BROKEN_CD
+ bool "Poll for broken card detection case"
+ help
+ If card detection feature is broken, just poll to detect.
+
config DM_MMC
bool "Enable MMC controllers using Driver Model"
depends on DM
If you have an ARM(R) platform with a Multimedia Card slot,
say Y or M here.
+config MMC_QUIRKS
+ bool "Enable quirks"
+ default y
+ help
+ Some cards and hosts may sometimes behave unexpectedly (quirks).
+ This option enable workarounds to handle those quirks. Some of them
+ are enabled by default, other may require additionnal flags or are
+ enabled by the host driver.
+
+config MMC_HW_PARTITIONING
+ bool "Support for HW partitioning command(eMMC)"
+ default y
+ help
+ This adds a command and an API to do hardware partitioning on eMMC
+ devices.
+
+config MMC_IO_VOLTAGE
+ bool "Support IO voltage configuration"
+ help
+ IO voltage configuration allows selecting the voltage level of the IO
+ lines (not the level of main supply). This is required for UHS
+ support. For eMMC this not mandatory, but not enabling this option may
+ prevent the driver of using the faster modes.
+
+config SPL_MMC_IO_VOLTAGE
+ bool "Support IO voltage configuration in SPL"
+ default n
+ help
+ IO voltage configuration allows selecting the voltage level of the IO
+ lines (not the level of main supply). This is required for UHS
+ support. For eMMC this not mandatory, but not enabling this option may
+ prevent the driver of using the faster modes.
+
+config MMC_UHS_SUPPORT
+ bool "enable UHS support"
+ depends on MMC_IO_VOLTAGE
+ help
+ The Ultra High Speed (UHS) bus is available on some SDHC and SDXC
+ cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
+ frequency can go up to 208MHz (SDR104)
+
+config SPL_MMC_UHS_SUPPORT
+ bool "enable UHS support in SPL"
+ depends on SPL_MMC_IO_VOLTAGE
+ help
+ The Ultra High Speed (UHS) bus is available on some SDHC and SDXC
+ cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
+ frequency can go up to 208MHz (SDR104)
+
+config MMC_HS200_SUPPORT
+ bool "enable HS200 support"
+ help
+ The HS200 mode is support by some eMMC. The bus frequency is up to
+ 200MHz. This mode requires tuning the IO.
+
+
+config SPL_MMC_HS200_SUPPORT
+ bool "enable HS200 support in SPL"
+ help
+ The HS200 mode is support by some eMMC. The bus frequency is up to
+ 200MHz. This mode requires tuning the IO.
+
+config MMC_VERBOSE
+ bool "Output more information about the MMC"
+ default y
+ help
+ Enable the output of more information about the card such as the
+ operating mode.
+
config SPL_MMC_TINY
bool "Tiny MMC framework in SPL"
help
obj-y += mmc.o
obj-$(CONFIG_$(SPL_)DM_MMC) += mmc-uclass.o
+obj-$(CONFIG_$(SPL_)MMC_WRITE) += mmc_write.o
ifndef CONFIG_$(SPL_)BLK
obj-y += mmc_legacy.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
-obj-$(CONFIG_SPL_SAVEENV) += mmc_write.o
-else
-obj-y += mmc_write.o
endif
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
if (host->dev_index > 4) {
printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
+ free(priv);
return -EINVAL;
}
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
printf("DWMMC%d: Can't get base address\n", host->dev_index);
+ free(priv);
return -EINVAL;
}
host->ioaddr = (void *)base;
if (err) {
printf("DWMMC%d: Can't get sdr-timings for devider\n",
host->dev_index);
+ free(priv);
return -EINVAL;
}
static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
#ifdef ARCH_MXC
+#ifdef CONFIG_MX53
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+ int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
+#else
int pre_div = 1;
+#endif
#else
int pre_div = 2;
#endif
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
- struct fsl_esdhc *regs = priv->esdhc_regs;
int sdhc_clk = priv->sdhc_clk;
uint clk;
esdhc_write32(®s->clktunectrlstatus, 0x0);
/* Put VEND_SPEC to default value */
- esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
+ if (priv->vs18_enable)
+ esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
+ ESDHC_VENDORSPEC_VSELECT));
+ else
+ esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
/* Disable DLL_CTRL delay line */
esdhc_write32(®s->dllctrl, 0x0);
#endif
/* Set the initial clock speed */
- mmc_set_clock(mmc, 400000);
+ mmc_set_clock(mmc, 400000, false);
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
/* Set timout to the maximum value */
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
- if (priv->vs18_enable)
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-
return 0;
}
cmdr, cmdr & 0x3F, arg, status, msg);
}
+static inline void mci_set_blklen(atmel_mci_t *mci, int blklen)
+{
+ unsigned int version = atmel_mci_get_version(mci);
+
+ blklen &= 0xfffc;
+
+ /* MCI IP version >= 0x200 has blkr */
+ if (version >= 0x200)
+ writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->blkr)),
+ &mci->blkr);
+ else
+ writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->mr)), &mci->mr);
+}
+
/* Setup for MCI Clock and Block Size */
#ifdef CONFIG_DM_MMC
static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen)
priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2);
else
priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2;
- blklen &= 0xfffc;
mr = MMCI_BF(CLKDIV, clkdiv);
*/
if (version >= 0x500)
mr |= MMCI_BF(CLKODD, clkodd);
- else
- mr |= MMCI_BF(BLKLEN, blklen);
writel(mr, &mci->mr);
- /* MCI IP version >= 0x200 has blkr */
- if (version >= 0x200)
- writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
+ mci_set_blklen(mci, blklen);
if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
writel(MMCI_BIT(HSMODE), &mci->cfg);
{
struct atmel_mci_plat *plat = dev_get_platdata(dev);
struct atmel_mci_priv *priv = dev_get_priv(dev);
- struct mmc *mmc = mmc_get_mmc_dev(dev);
atmel_mci_t *mci = plat->mci;
#else
static int
/* Figure out the transfer arguments */
cmdr = mci_encode_cmd(cmd, data, &error_flags);
+ mci_set_blklen(mci, data->blocksize);
+
/* For multi blocks read/write, set the block register */
if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
- writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
- &mci->blkr);
+ writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
+ &mci->blkr);
/* Send the command */
writel(cmd->cmdarg, &mci->argr);
if (data) {
u32 word_count, block_count;
u32* ioptr;
- u32 sys_blocksize, dummy, i;
+ u32 i;
u32 (*mci_data_op)
(atmel_mci_t *mci, u32* data, u32 error_flags);
if (data->flags & MMC_DATA_READ) {
mci_data_op = mci_data_read;
- sys_blocksize = mmc->read_bl_len;
ioptr = (u32*)data->dest;
} else {
mci_data_op = mci_data_write;
- sys_blocksize = mmc->write_bl_len;
ioptr = (u32*)data->src;
}
1, cnt, 0);
}
#endif
-#ifdef DEBUG
- if (!status && word_count < (sys_blocksize / 4))
- printf("filling rest of block...\n");
-#endif
- /* fill the rest of a full block */
- while (!status && word_count < (sys_blocksize / 4)) {
- status = mci_data_op(mci, &dummy,
- error_flags);
- word_count++;
- }
if (status) {
dump_cmd(cmdr, cmd->cmdarg, status,
"Data Transfer Failed");
mmc->priv = pdata;
upriv->mmc = mmc;
- mmc_set_clock(mmc, cfg->f_min);
+ mmc_set_clock(mmc, cfg->f_min, false);
/* reset all status bits */
meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
-#include <dm/root.h>
#include "mmc_private.h"
DECLARE_GLOBAL_DATA_PTR;
return dm_mmc_set_ios(mmc->dev);
}
+void dm_mmc_send_init_stream(struct udevice *dev)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (ops->send_init_stream)
+ ops->send_init_stream(dev);
+}
+
+void mmc_send_init_stream(struct mmc *mmc)
+{
+ dm_mmc_send_init_stream(mmc->dev);
+}
+
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (!ops->wait_dat0)
+ return -ENOSYS;
+ return ops->wait_dat0(dev, state, timeout);
+}
+
+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
+{
+ return dm_mmc_wait_dat0(mmc->dev, state, timeout);
+}
+#endif
+
int dm_mmc_get_wp(struct udevice *dev)
{
struct dm_mmc_ops *ops = mmc_get_ops(dev);
return dm_mmc_get_cd(mmc->dev);
}
+#ifdef MMC_SUPPORTS_TUNING
+int dm_mmc_execute_tuning(struct udevice *dev, uint opcode)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (!ops->execute_tuning)
+ return -ENOSYS;
+ return ops->execute_tuning(dev, opcode);
+}
+
+int mmc_execute_tuning(struct mmc *mmc, uint opcode)
+{
+ return dm_mmc_execute_tuning(mmc->dev, opcode);
+}
+#endif
+
+int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg)
+{
+ int val;
+
+ val = dev_read_u32_default(dev, "bus-width", 1);
+
+ switch (val) {
+ case 0x8:
+ cfg->host_caps |= MMC_MODE_8BIT;
+ /* fall through */
+ case 0x4:
+ cfg->host_caps |= MMC_MODE_4BIT;
+ /* fall through */
+ case 0x1:
+ cfg->host_caps |= MMC_MODE_1BIT;
+ break;
+ default:
+ dev_err(dev, "Invalid \"bus-width\" value %u!\n", val);
+ return -EINVAL;
+ }
+
+ /* f_max is obtained from the optional "max-frequency" property */
+ dev_read_u32(dev, "max-frequency", &cfg->f_max);
+
+ if (dev_read_bool(dev, "cap-sd-highspeed"))
+ cfg->host_caps |= MMC_CAP(SD_HS);
+ if (dev_read_bool(dev, "cap-mmc-highspeed"))
+ cfg->host_caps |= MMC_CAP(MMC_HS);
+ if (dev_read_bool(dev, "sd-uhs-sdr12"))
+ cfg->host_caps |= MMC_CAP(UHS_SDR12);
+ if (dev_read_bool(dev, "sd-uhs-sdr25"))
+ cfg->host_caps |= MMC_CAP(UHS_SDR25);
+ if (dev_read_bool(dev, "sd-uhs-sdr50"))
+ cfg->host_caps |= MMC_CAP(UHS_SDR50);
+ if (dev_read_bool(dev, "sd-uhs-sdr104"))
+ cfg->host_caps |= MMC_CAP(UHS_SDR104);
+ if (dev_read_bool(dev, "sd-uhs-ddr50"))
+ cfg->host_caps |= MMC_CAP(UHS_DDR50);
+ if (dev_read_bool(dev, "mmc-ddr-1_8v"))
+ cfg->host_caps |= MMC_CAP(MMC_DDR_52);
+ if (dev_read_bool(dev, "mmc-ddr-1_2v"))
+ cfg->host_caps |= MMC_CAP(MMC_DDR_52);
+ if (dev_read_bool(dev, "mmc-hs200-1_8v"))
+ cfg->host_caps |= MMC_CAP(MMC_HS_200);
+ if (dev_read_bool(dev, "mmc-hs200-1_2v"))
+ cfg->host_caps |= MMC_CAP(MMC_HS_200);
+
+ return 0;
+}
+
struct mmc *mmc_get_mmc_dev(struct udevice *dev)
{
struct mmc_uclass_priv *upriv;
static const struct blk_ops mmc_blk_ops = {
.read = mmc_bread,
-#ifndef CONFIG_SPL_BUILD
+#if CONFIG_IS_ENABLED(MMC_WRITE)
.write = mmc_bwrite,
.erase = mmc_berase,
#endif
#include <div64.h>
#include "mmc_private.h"
-static const unsigned int sd_au_size[] = {
- 0, SZ_16K / 512, SZ_32K / 512,
- SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
- SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
- SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
- SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
-};
+static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
+static int mmc_power_cycle(struct mmc *mmc);
+static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
#if CONFIG_IS_ENABLED(MMC_TINY)
static struct mmc mmc_static;
#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
+
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
+{
+ return -ENOSYS;
+}
+#endif
+
__weak int board_mmc_getwp(struct mmc *mmc)
{
return -1;
}
#endif
+#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
+const char *mmc_mode_name(enum bus_mode mode)
+{
+ static const char *const names[] = {
+ [MMC_LEGACY] = "MMC legacy",
+ [SD_LEGACY] = "SD Legacy",
+ [MMC_HS] = "MMC High Speed (26MHz)",
+ [SD_HS] = "SD High Speed (50MHz)",
+ [UHS_SDR12] = "UHS SDR12 (25MHz)",
+ [UHS_SDR25] = "UHS SDR25 (50MHz)",
+ [UHS_SDR50] = "UHS SDR50 (100MHz)",
+ [UHS_SDR104] = "UHS SDR104 (208MHz)",
+ [UHS_DDR50] = "UHS DDR50 (50MHz)",
+ [MMC_HS_52] = "MMC High Speed (52MHz)",
+ [MMC_DDR_52] = "MMC DDR52 (52MHz)",
+ [MMC_HS_200] = "HS200 (200MHz)",
+ };
+
+ if (mode >= MMC_MODES_END)
+ return "Unknown mode";
+ else
+ return names[mode];
+}
+#endif
+
+static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
+{
+ static const int freqs[] = {
+ [SD_LEGACY] = 25000000,
+ [MMC_HS] = 26000000,
+ [SD_HS] = 50000000,
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ [UHS_SDR12] = 25000000,
+ [UHS_SDR25] = 50000000,
+ [UHS_SDR50] = 100000000,
+ [UHS_DDR50] = 50000000,
+#ifdef MMC_SUPPORTS_TUNING
+ [UHS_SDR104] = 208000000,
+#endif
+#endif
+ [MMC_HS_52] = 52000000,
+ [MMC_DDR_52] = 52000000,
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ [MMC_HS_200] = 200000000,
+#endif
+ };
+
+ if (mode == MMC_LEGACY)
+ return mmc->legacy_speed;
+ else if (mode >= MMC_MODES_END)
+ return 0;
+ else
+ return freqs[mode];
+}
+
+static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
+{
+ mmc->selected_mode = mode;
+ mmc->tran_speed = mmc_mode2freq(mmc, mode);
+ mmc->ddr_mode = mmc_is_mode_ddr(mode);
+ debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
+ mmc->tran_speed / 1000000);
+ return 0;
+}
+
#if !CONFIG_IS_ENABLED(DM_MMC)
int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
(cmd.response[0] & MMC_STATUS_CURR_STATE) !=
MMC_STATE_PRG)
break;
- else if (cmd.response[0] & MMC_STATUS_MASK) {
+
+ if (cmd.response[0] & MMC_STATUS_MASK) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("Status Error: 0x%08X\n",
- cmd.response[0]);
+ pr_err("Status Error: 0x%08X\n",
+ cmd.response[0]);
#endif
return -ECOMM;
}
mmc_trace_state(mmc, &cmd);
if (timeout <= 0) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("Timeout waiting card ready\n");
+ pr_err("Timeout waiting card ready\n");
#endif
return -ETIMEDOUT;
}
int mmc_set_blocklen(struct mmc *mmc, int len)
{
struct mmc_cmd cmd;
+ int err;
if (mmc->ddr_mode)
return 0;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
- return mmc_send_cmd(mmc, &cmd, NULL);
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+#ifdef CONFIG_MMC_QUIRKS
+ if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
+ int retries = 4;
+ /*
+ * It has been seen that SET_BLOCKLEN may fail on the first
+ * attempt, let's try a few more time
+ */
+ do {
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (!err)
+ break;
+ } while (retries--);
+ }
+#endif
+
+ return err;
+}
+
+#ifdef MMC_SUPPORTS_TUNING
+static const u8 tuning_blk_pattern_4bit[] = {
+ 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
+ 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
+ 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
+ 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
+ 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
+ 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
+ 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
+ 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
+};
+
+static const u8 tuning_blk_pattern_8bit[] = {
+ 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
+ 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
+ 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
+ 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
+ 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
+ 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
+ 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
+ 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
+ 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
+ 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
+ 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
+ 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
+ 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
+ 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
+ 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
+};
+
+int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
+{
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+ const u8 *tuning_block_pattern;
+ int size, err;
+
+ if (mmc->bus_width == 8) {
+ tuning_block_pattern = tuning_blk_pattern_8bit;
+ size = sizeof(tuning_blk_pattern_8bit);
+ } else if (mmc->bus_width == 4) {
+ tuning_block_pattern = tuning_blk_pattern_4bit;
+ size = sizeof(tuning_blk_pattern_4bit);
+ } else {
+ return -EINVAL;
+ }
+
+ ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
+
+ cmd.cmdidx = opcode;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1;
+
+ data.dest = (void *)data_buf;
+ data.blocks = 1;
+ data.blocksize = size;
+ data.flags = MMC_DATA_READ;
+
+ err = mmc_send_cmd(mmc, &cmd, &data);
+ if (err)
+ return err;
+
+ if (memcmp(data_buf, tuning_block_pattern, size))
+ return -EIO;
+
+ return 0;
}
+#endif
static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
lbaint_t blkcnt)
cmd.resp_type = MMC_RSP_R1b;
if (mmc_send_cmd(mmc, &cmd, NULL)) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("mmc fail to send stop cmd\n");
+ pr_err("mmc fail to send stop cmd\n");
#endif
return 0;
}
if ((start + blkcnt) > block_dev->lba) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
- start + blkcnt, block_dev->lba);
+ pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
+ start + blkcnt, block_dev->lba);
#endif
return 0;
}
return 0;
}
-static int sd_send_op_cond(struct mmc *mmc)
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
+{
+ struct mmc_cmd cmd;
+ int err = 0;
+
+ /*
+ * Send CMD11 only if the request is to switch the card to
+ * 1.8V signalling.
+ */
+ if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
+ return mmc_set_signal_voltage(mmc, signal_voltage);
+
+ cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
+
+ if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
+ return -EIO;
+
+ /*
+ * The card should drive cmd and dat[0:3] low immediately
+ * after the response of cmd11, but wait 100 us to be sure
+ */
+ err = mmc_wait_dat0(mmc, 0, 100);
+ if (err == -ENOSYS)
+ udelay(100);
+ else if (err)
+ return -ETIMEDOUT;
+
+ /*
+ * During a signal voltage level switch, the clock must be gated
+ * for 5 ms according to the SD spec
+ */
+ mmc_set_clock(mmc, mmc->clock, true);
+
+ err = mmc_set_signal_voltage(mmc, signal_voltage);
+ if (err)
+ return err;
+
+ /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
+ mdelay(10);
+ mmc_set_clock(mmc, mmc->clock, false);
+
+ /*
+ * Failure to switch is indicated by the card holding
+ * dat[0:3] low. Wait for at least 1 ms according to spec
+ */
+ err = mmc_wait_dat0(mmc, 1, 1000);
+ if (err == -ENOSYS)
+ udelay(1000);
+ else if (err)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+#endif
+
+static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
{
int timeout = 1000;
int err;
if (mmc->version == SD_VERSION_2)
cmd.cmdarg |= OCR_HCS;
+ if (uhs_en)
+ cmd.cmdarg |= OCR_S18R;
+
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
mmc->ocr = cmd.response[0];
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
+ == 0x41000000) {
+ err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
+ if (err)
+ return err;
+ }
+#endif
+
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
mmc->rca = 0;
}
-static int mmc_change_freq(struct mmc *mmc)
+static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
{
- ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
- char cardtype;
int err;
+ int speed_bits;
- mmc->card_caps = 0;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
- if (mmc_host_is_spi(mmc))
- return 0;
+ switch (mode) {
+ case MMC_HS:
+ case MMC_HS_52:
+ case MMC_DDR_52:
+ speed_bits = EXT_CSD_TIMING_HS;
+ break;
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ case MMC_HS_200:
+ speed_bits = EXT_CSD_TIMING_HS200;
+ break;
+#endif
+ case MMC_LEGACY:
+ speed_bits = EXT_CSD_TIMING_LEGACY;
+ break;
+ default:
+ return -EINVAL;
+ }
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
+ speed_bits);
+ if (err)
+ return err;
- /* Only version 4 supports high-speed */
- if (mmc->version < MMC_VERSION_4)
- return 0;
+ if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
+ /* Now check to see that it worked */
+ err = mmc_send_ext_csd(mmc, test_csd);
+ if (err)
+ return err;
- mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
+ /* No high-speed support */
+ if (!test_csd[EXT_CSD_HS_TIMING])
+ return -ENOTSUPP;
+ }
- err = mmc_send_ext_csd(mmc, ext_csd);
+ return 0;
+}
- if (err)
- return err;
+static int mmc_get_capabilities(struct mmc *mmc)
+{
+ u8 *ext_csd = mmc->ext_csd;
+ char cardtype;
- cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
+ mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
+ if (mmc_host_is_spi(mmc))
+ return 0;
- if (err)
- return err;
+ /* Only version 4 supports high-speed */
+ if (mmc->version < MMC_VERSION_4)
+ return 0;
- /* Now check to see that it worked */
- err = mmc_send_ext_csd(mmc, ext_csd);
+ if (!ext_csd) {
+ pr_err("No ext_csd found!\n"); /* this should enver happen */
+ return -ENOTSUPP;
+ }
- if (err)
- return err;
+ mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
- /* No high-speed support */
- if (!ext_csd[EXT_CSD_HS_TIMING])
- return 0;
+ cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
+ mmc->cardtype = cardtype;
- /* High Speed is set, there are two types: 52MHz and 26MHz */
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
+ EXT_CSD_CARD_TYPE_HS200_1_8V)) {
+ mmc->card_caps |= MMC_MODE_HS200;
+ }
+#endif
if (cardtype & EXT_CSD_CARD_TYPE_52) {
- if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
+ if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
mmc->card_caps |= MMC_MODE_DDR_52MHz;
- mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
- } else {
- mmc->card_caps |= MMC_MODE_HS;
+ mmc->card_caps |= MMC_MODE_HS_52MHz;
}
+ if (cardtype & EXT_CSD_CARD_TYPE_26)
+ mmc->card_caps |= MMC_MODE_HS;
return 0;
}
return 0;
}
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
+{
+ int forbidden = 0;
+ bool change = false;
+
+ if (part_num & PART_ACCESS_MASK)
+ forbidden = MMC_CAP(MMC_HS_200);
+
+ if (MMC_CAP(mmc->selected_mode) & forbidden) {
+ debug("selected mode (%s) is forbidden for part %d\n",
+ mmc_mode_name(mmc->selected_mode), part_num);
+ change = true;
+ } else if (mmc->selected_mode != mmc->best_mode) {
+ debug("selected mode is not optimal\n");
+ change = true;
+ }
+
+ if (change)
+ return mmc_select_mode_and_width(mmc,
+ mmc->card_caps & ~forbidden);
+
+ return 0;
+}
+#else
+static inline int mmc_boot_part_access_chk(struct mmc *mmc,
+ unsigned int part_num)
+{
+ return 0;
+}
+#endif
+
int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
{
int ret;
+ ret = mmc_boot_part_access_chk(mmc, part_num);
+ if (ret)
+ return ret;
+
ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
(mmc->part_config & ~PART_ACCESS_MASK)
| (part_num & PART_ACCESS_MASK));
return ret;
}
+#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
int mmc_hwpart_config(struct mmc *mmc,
const struct mmc_hwpart_conf *conf,
enum mmc_hwpart_conf_mode mode)
return -EINVAL;
if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
- printf("eMMC >= 4.4 required for enhanced user data area\n");
+ pr_err("eMMC >= 4.4 required for enhanced user data area\n");
return -EMEDIUMTYPE;
}
if (!(mmc->part_support & PART_SUPPORT)) {
- printf("Card does not support partitioning\n");
+ pr_err("Card does not support partitioning\n");
return -EMEDIUMTYPE;
}
if (!mmc->hc_wp_grp_size) {
- printf("Card does not define HC WP group size\n");
+ pr_err("Card does not define HC WP group size\n");
return -EMEDIUMTYPE;
}
if (conf->user.enh_size) {
if (conf->user.enh_size % mmc->hc_wp_grp_size ||
conf->user.enh_start % mmc->hc_wp_grp_size) {
- printf("User data enhanced area not HC WP group "
+ pr_err("User data enhanced area not HC WP group "
"size aligned\n");
return -EINVAL;
}
for (pidx = 0; pidx < 4; pidx++) {
if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
- printf("GP%i partition not HC WP group size "
+ pr_err("GP%i partition not HC WP group size "
"aligned\n", pidx+1);
return -EINVAL;
}
}
if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
- printf("Card does not support enhanced attribute\n");
+ pr_err("Card does not support enhanced attribute\n");
return -EMEDIUMTYPE;
}
(ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
if (tot_enh_size_mult > max_enh_size_mult) {
- printf("Total enhanced size exceeds maximum (%u > %u)\n",
+ pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
tot_enh_size_mult, max_enh_size_mult);
return -EMEDIUMTYPE;
}
if (ext_csd[EXT_CSD_PARTITION_SETTING] &
EXT_CSD_PARTITION_SETTING_COMPLETED) {
- printf("Card already partitioned\n");
+ pr_err("Card already partitioned\n");
return -EPERM;
}
return 0;
}
+#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
int mmc_getcd(struct mmc *mmc)
}
-static int sd_change_freq(struct mmc *mmc)
+static int sd_get_capabilities(struct mmc *mmc)
{
int err;
struct mmc_cmd cmd;
- ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
- ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
+ ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
+ ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
struct mmc_data data;
int timeout;
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ u32 sd3_bus_mode;
+#endif
- mmc->card_caps = 0;
+ mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
if (mmc_host_is_spi(mmc))
return 0;
}
/* If high-speed isn't supported, we return */
- if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
- return 0;
+ if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
+ mmc->card_caps |= MMC_CAP(SD_HS);
- /*
- * If the host doesn't support SD_HIGHSPEED, do not switch card to
- * HIGHSPEED mode even if the card support SD_HIGHSPPED.
- * This can avoid furthur problem when the card runs in different
- * mode between the host.
- */
- if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
- (mmc->cfg->host_caps & MMC_MODE_HS)))
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ /* Version before 3.0 don't support UHS modes */
+ if (mmc->version < SD_VERSION_3)
return 0;
- err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
+ sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
+ if (sd3_bus_mode & SD_MODE_UHS_SDR104)
+ mmc->card_caps |= MMC_CAP(UHS_SDR104);
+ if (sd3_bus_mode & SD_MODE_UHS_SDR50)
+ mmc->card_caps |= MMC_CAP(UHS_SDR50);
+ if (sd3_bus_mode & SD_MODE_UHS_SDR25)
+ mmc->card_caps |= MMC_CAP(UHS_SDR25);
+ if (sd3_bus_mode & SD_MODE_UHS_SDR12)
+ mmc->card_caps |= MMC_CAP(UHS_SDR12);
+ if (sd3_bus_mode & SD_MODE_UHS_DDR50)
+ mmc->card_caps |= MMC_CAP(UHS_DDR50);
+#endif
+
+ return 0;
+}
+
+static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
+{
+ int err;
+
+ ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
+ int speed;
+
+ switch (mode) {
+ case SD_LEGACY:
+ speed = UHS_SDR12_BUS_SPEED;
+ break;
+ case SD_HS:
+ speed = HIGH_SPEED_BUS_SPEED;
+ break;
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ case UHS_SDR12:
+ speed = UHS_SDR12_BUS_SPEED;
+ break;
+ case UHS_SDR25:
+ speed = UHS_SDR25_BUS_SPEED;
+ break;
+ case UHS_SDR50:
+ speed = UHS_SDR50_BUS_SPEED;
+ break;
+ case UHS_DDR50:
+ speed = UHS_DDR50_BUS_SPEED;
+ break;
+ case UHS_SDR104:
+ speed = UHS_SDR104_BUS_SPEED;
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+
+ err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
+ if (err)
+ return err;
+
+ if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
+ return -ENOTSUPP;
+
+ return 0;
+}
+
+int sd_select_bus_width(struct mmc *mmc, int w)
+{
+ int err;
+ struct mmc_cmd cmd;
+
+ if ((w != 4) && (w != 1))
+ return -EINVAL;
+
+ cmd.cmdidx = MMC_CMD_APP_CMD;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = mmc->rca << 16;
+ err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
- if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
- mmc->card_caps |= MMC_MODE_HS;
+ cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
+ cmd.resp_type = MMC_RSP_R1;
+ if (w == 4)
+ cmd.cmdarg = 2;
+ else if (w == 1)
+ cmd.cmdarg = 0;
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
return 0;
}
+#if CONFIG_IS_ENABLED(MMC_WRITE)
static int sd_read_ssr(struct mmc *mmc)
{
+ static const unsigned int sd_au_size[] = {
+ 0, SZ_16K / 512, SZ_32K / 512,
+ SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
+ SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
+ SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
+ SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
+ SZ_64M / 512,
+ };
int err, i;
struct mmc_cmd cmd;
ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
return 0;
}
-
+#endif
/* frequency bases */
/* divided by 10 to be nice to platforms without floating point */
static const int fbase[] = {
80,
};
+static inline int bus_width(uint cap)
+{
+ if (cap == MMC_MODE_8BIT)
+ return 8;
+ if (cap == MMC_MODE_4BIT)
+ return 4;
+ if (cap == MMC_MODE_1BIT)
+ return 1;
+ pr_warn("invalid bus witdh capability 0x%x\n", cap);
+ return 0;
+}
+
#if !CONFIG_IS_ENABLED(DM_MMC)
-static void mmc_set_ios(struct mmc *mmc)
+#ifdef MMC_SUPPORTS_TUNING
+static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
+{
+ return -ENOTSUPP;
+}
+#endif
+
+static void mmc_send_init_stream(struct mmc *mmc)
+{
+}
+
+static int mmc_set_ios(struct mmc *mmc)
{
+ int ret = 0;
+
if (mmc->cfg->ops->set_ios)
- mmc->cfg->ops->set_ios(mmc);
+ ret = mmc->cfg->ops->set_ios(mmc);
+
+ return ret;
}
#endif
-void mmc_set_clock(struct mmc *mmc, uint clock)
+int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
{
- if (clock > mmc->cfg->f_max)
- clock = mmc->cfg->f_max;
+ if (!disable) {
+ if (clock > mmc->cfg->f_max)
+ clock = mmc->cfg->f_max;
- if (clock < mmc->cfg->f_min)
- clock = mmc->cfg->f_min;
+ if (clock < mmc->cfg->f_min)
+ clock = mmc->cfg->f_min;
+ }
mmc->clock = clock;
+ mmc->clk_disable = disable;
- mmc_set_ios(mmc);
+ return mmc_set_ios(mmc);
}
-static void mmc_set_bus_width(struct mmc *mmc, uint width)
+static int mmc_set_bus_width(struct mmc *mmc, uint width)
{
mmc->bus_width = width;
- mmc_set_ios(mmc);
+ return mmc_set_ios(mmc);
}
-static int mmc_startup(struct mmc *mmc)
+#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
+/*
+ * helper function to display the capabilities in a human
+ * friendly manner. The capabilities include bus width and
+ * supported modes.
+ */
+void mmc_dump_capabilities(const char *text, uint caps)
{
- int err, i;
- uint mult, freq;
- u64 cmult, csize, capacity;
- struct mmc_cmd cmd;
- ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
- ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
- bool has_parts = false;
- bool part_completed;
- struct blk_desc *bdesc;
-
-#ifdef CONFIG_MMC_SPI_CRC_ON
- if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
- cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
- cmd.resp_type = MMC_RSP_R1;
- cmd.cmdarg = 1;
- err = mmc_send_cmd(mmc, &cmd, NULL);
-
- if (err)
- return err;
- }
+ enum bus_mode mode;
+
+ printf("%s: widths [", text);
+ if (caps & MMC_MODE_8BIT)
+ printf("8, ");
+ if (caps & MMC_MODE_4BIT)
+ printf("4, ");
+ if (caps & MMC_MODE_1BIT)
+ printf("1, ");
+ printf("\b\b] modes [");
+ for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
+ if (MMC_CAP(mode) & caps)
+ printf("%s, ", mmc_mode_name(mode));
+ printf("\b\b]\n");
+}
+#endif
+
+struct mode_width_tuning {
+ enum bus_mode mode;
+ uint widths;
+#ifdef MMC_SUPPORTS_TUNING
+ uint tuning;
+#endif
+};
+
+#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
+int mmc_voltage_to_mv(enum mmc_voltage voltage)
+{
+ switch (voltage) {
+ case MMC_SIGNAL_VOLTAGE_000: return 0;
+ case MMC_SIGNAL_VOLTAGE_330: return 3300;
+ case MMC_SIGNAL_VOLTAGE_180: return 1800;
+ case MMC_SIGNAL_VOLTAGE_120: return 1200;
+ }
+ return -EINVAL;
+}
+
+static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
+{
+ int err;
+
+ if (mmc->signal_voltage == signal_voltage)
+ return 0;
+
+ mmc->signal_voltage = signal_voltage;
+ err = mmc_set_ios(mmc);
+ if (err)
+ debug("unable to set voltage (err %d)\n", err);
+
+ return err;
+}
+#else
+static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
+{
+ return 0;
+}
+#endif
+
+static const struct mode_width_tuning sd_modes_by_pref[] = {
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+#ifdef MMC_SUPPORTS_TUNING
+ {
+ .mode = UHS_SDR104,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ .tuning = MMC_CMD_SEND_TUNING_BLOCK
+ },
+#endif
+ {
+ .mode = UHS_SDR50,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+ {
+ .mode = UHS_DDR50,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+ {
+ .mode = UHS_SDR25,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+#endif
+ {
+ .mode = SD_HS,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ {
+ .mode = UHS_SDR12,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+#endif
+ {
+ .mode = SD_LEGACY,
+ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+ }
+};
+
+#define for_each_sd_mode_by_pref(caps, mwt) \
+ for (mwt = sd_modes_by_pref;\
+ mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
+ mwt++) \
+ if (caps & MMC_CAP(mwt->mode))
+
+static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
+{
+ int err;
+ uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
+ const struct mode_width_tuning *mwt;
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
+#else
+ bool uhs_en = false;
+#endif
+ uint caps;
+
+#ifdef DEBUG
+ mmc_dump_capabilities("sd card", card_caps);
+ mmc_dump_capabilities("host", mmc->host_caps);
+#endif
+
+ /* Restrict card's capabilities by what the host can do */
+ caps = card_caps & mmc->host_caps;
+
+ if (!uhs_en)
+ caps &= ~UHS_CAPS;
+
+ for_each_sd_mode_by_pref(caps, mwt) {
+ uint *w;
+
+ for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
+ if (*w & caps & mwt->widths) {
+ debug("trying mode %s width %d (at %d MHz)\n",
+ mmc_mode_name(mwt->mode),
+ bus_width(*w),
+ mmc_mode2freq(mmc, mwt->mode) / 1000000);
+
+ /* configure the bus width (card + host) */
+ err = sd_select_bus_width(mmc, bus_width(*w));
+ if (err)
+ goto error;
+ mmc_set_bus_width(mmc, bus_width(*w));
+
+ /* configure the bus mode (card) */
+ err = sd_set_card_speed(mmc, mwt->mode);
+ if (err)
+ goto error;
+
+ /* configure the bus mode (host) */
+ mmc_select_mode(mmc, mwt->mode);
+ mmc_set_clock(mmc, mmc->tran_speed, false);
+
+#ifdef MMC_SUPPORTS_TUNING
+ /* execute tuning if needed */
+ if (mwt->tuning && !mmc_host_is_spi(mmc)) {
+ err = mmc_execute_tuning(mmc,
+ mwt->tuning);
+ if (err) {
+ debug("tuning failed\n");
+ goto error;
+ }
+ }
+#endif
+
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+ err = sd_read_ssr(mmc);
+ if (!err)
+ pr_warn("unable to read ssr\n");
+#endif
+ if (!err)
+ return 0;
+
+error:
+ /* revert to a safer bus speed */
+ mmc_select_mode(mmc, SD_LEGACY);
+ mmc_set_clock(mmc, mmc->tran_speed, false);
+ }
+ }
+ }
+
+ printf("unable to select a mode\n");
+ return -ENOTSUPP;
+}
+
+/*
+ * read the compare the part of ext csd that is constant.
+ * This can be used to check that the transfer is working
+ * as expected.
+ */
+static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
+{
+ int err;
+ const u8 *ext_csd = mmc->ext_csd;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
+
+ if (mmc->version < MMC_VERSION_4)
+ return 0;
+
+ err = mmc_send_ext_csd(mmc, test_csd);
+ if (err)
+ return err;
+
+ /* Only compare read only fields */
+ if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
+ == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
+ ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
+ == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
+ ext_csd[EXT_CSD_REV]
+ == test_csd[EXT_CSD_REV] &&
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
+ == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
+ memcmp(&ext_csd[EXT_CSD_SEC_CNT],
+ &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
+ return 0;
+
+ return -EBADMSG;
+}
+
+#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
+static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
+ uint32_t allowed_mask)
+{
+ u32 card_mask = 0;
+
+ switch (mode) {
+ case MMC_HS_200:
+ if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
+ card_mask |= MMC_SIGNAL_VOLTAGE_180;
+ if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
+ card_mask |= MMC_SIGNAL_VOLTAGE_120;
+ break;
+ case MMC_DDR_52:
+ if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
+ card_mask |= MMC_SIGNAL_VOLTAGE_330 |
+ MMC_SIGNAL_VOLTAGE_180;
+ if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
+ card_mask |= MMC_SIGNAL_VOLTAGE_120;
+ break;
+ default:
+ card_mask |= MMC_SIGNAL_VOLTAGE_330;
+ break;
+ }
+
+ while (card_mask & allowed_mask) {
+ enum mmc_voltage best_match;
+
+ best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
+ if (!mmc_set_signal_voltage(mmc, best_match))
+ return 0;
+
+ allowed_mask &= ~best_match;
+ }
+
+ return -ENOTSUPP;
+}
+#else
+static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
+ uint32_t allowed_mask)
+{
+ return 0;
+}
+#endif
+
+static const struct mode_width_tuning mmc_modes_by_pref[] = {
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+ {
+ .mode = MMC_HS_200,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
+ .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
+ },
+#endif
+ {
+ .mode = MMC_DDR_52,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
+ },
+ {
+ .mode = MMC_HS_52,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+ {
+ .mode = MMC_HS,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
+ },
+ {
+ .mode = MMC_LEGACY,
+ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
+ }
+};
+
+#define for_each_mmc_mode_by_pref(caps, mwt) \
+ for (mwt = mmc_modes_by_pref;\
+ mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
+ mwt++) \
+ if (caps & MMC_CAP(mwt->mode))
+
+static const struct ext_csd_bus_width {
+ uint cap;
+ bool is_ddr;
+ uint ext_csd_bits;
+} ext_csd_bus_width[] = {
+ {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
+ {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
+ {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
+ {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
+ {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
+};
+
+#define for_each_supported_width(caps, ddr, ecbv) \
+ for (ecbv = ext_csd_bus_width;\
+ ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
+ ecbv++) \
+ if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
+
+static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
+{
+ int err;
+ const struct mode_width_tuning *mwt;
+ const struct ext_csd_bus_width *ecbw;
+
+#ifdef DEBUG
+ mmc_dump_capabilities("mmc", card_caps);
+ mmc_dump_capabilities("host", mmc->host_caps);
+#endif
+
+ /* Restrict card's capabilities by what the host can do */
+ card_caps &= mmc->host_caps;
+
+ /* Only version 4 of MMC supports wider bus widths */
+ if (mmc->version < MMC_VERSION_4)
+ return 0;
+
+ if (!mmc->ext_csd) {
+ debug("No ext_csd found!\n"); /* this should enver happen */
+ return -ENOTSUPP;
+ }
+
+ mmc_set_clock(mmc, mmc->legacy_speed, false);
+
+ for_each_mmc_mode_by_pref(card_caps, mwt) {
+ for_each_supported_width(card_caps & mwt->widths,
+ mmc_is_mode_ddr(mwt->mode), ecbw) {
+ enum mmc_voltage old_voltage;
+ debug("trying mode %s width %d (at %d MHz)\n",
+ mmc_mode_name(mwt->mode),
+ bus_width(ecbw->cap),
+ mmc_mode2freq(mmc, mwt->mode) / 1000000);
+ old_voltage = mmc->signal_voltage;
+ err = mmc_set_lowest_voltage(mmc, mwt->mode,
+ MMC_ALL_SIGNAL_VOLTAGE);
+ if (err)
+ continue;
+
+ /* configure the bus width (card + host) */
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH,
+ ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
+ if (err)
+ goto error;
+ mmc_set_bus_width(mmc, bus_width(ecbw->cap));
+
+ /* configure the bus speed (card) */
+ err = mmc_set_card_speed(mmc, mwt->mode);
+ if (err)
+ goto error;
+
+ /*
+ * configure the bus width AND the ddr mode (card)
+ * The host side will be taken care of in the next step
+ */
+ if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH,
+ ecbw->ext_csd_bits);
+ if (err)
+ goto error;
+ }
+
+ /* configure the bus mode (host) */
+ mmc_select_mode(mmc, mwt->mode);
+ mmc_set_clock(mmc, mmc->tran_speed, false);
+#ifdef MMC_SUPPORTS_TUNING
+
+ /* execute tuning if needed */
+ if (mwt->tuning) {
+ err = mmc_execute_tuning(mmc, mwt->tuning);
+ if (err) {
+ debug("tuning failed\n");
+ goto error;
+ }
+ }
+#endif
+
+ /* do a transfer to check the configuration */
+ err = mmc_read_and_compare_ext_csd(mmc);
+ if (!err)
+ return 0;
+error:
+ mmc_set_signal_voltage(mmc, old_voltage);
+ /* if an error occured, revert to a safer bus mode */
+ mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
+ mmc_select_mode(mmc, MMC_LEGACY);
+ mmc_set_bus_width(mmc, 1);
+ }
+ }
+
+ pr_err("unable to select a mode\n");
+
+ return -ENOTSUPP;
+}
+
+static int mmc_startup_v4(struct mmc *mmc)
+{
+ int err, i;
+ u64 capacity;
+ bool has_parts = false;
+ bool part_completed;
+ static const u32 mmc_versions[] = {
+ MMC_VERSION_4,
+ MMC_VERSION_4_1,
+ MMC_VERSION_4_2,
+ MMC_VERSION_4_3,
+ MMC_VERSION_4_41,
+ MMC_VERSION_4_5,
+ MMC_VERSION_5_0,
+ MMC_VERSION_5_1
+ };
+
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+
+ if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
+ return 0;
+
+ /* check ext_csd version and capacity */
+ err = mmc_send_ext_csd(mmc, ext_csd);
+ if (err)
+ goto error;
+
+ /* store the ext csd for future reference */
+ if (!mmc->ext_csd)
+ mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
+ if (!mmc->ext_csd)
+ return -ENOMEM;
+ memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
+
+ if (ext_csd[EXT_CSD_REV] > ARRAY_SIZE(mmc_versions))
+ return -EINVAL;
+
+ mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
+
+ if (mmc->version >= MMC_VERSION_4_2) {
+ /*
+ * According to the JEDEC Standard, the value of
+ * ext_csd's capacity is valid if the value is more
+ * than 2GB
+ */
+ capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
+ | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
+ | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
+ | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
+ capacity *= MMC_MAX_BLOCK_LEN;
+ if ((capacity >> 20) > 2 * 1024)
+ mmc->capacity_user = capacity;
+ }
+
+ /* The partition data may be non-zero but it is only
+ * effective if PARTITION_SETTING_COMPLETED is set in
+ * EXT_CSD, so ignore any data if this bit is not set,
+ * except for enabling the high-capacity group size
+ * definition (see below).
+ */
+ part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
+ EXT_CSD_PARTITION_SETTING_COMPLETED);
+
+ /* store the partition info of emmc */
+ mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
+ if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
+ ext_csd[EXT_CSD_BOOT_MULT])
+ mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
+ if (part_completed &&
+ (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
+ mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
+
+ mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
+
+ mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
+
+ for (i = 0; i < 4; i++) {
+ int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
+ uint mult = (ext_csd[idx + 2] << 16) +
+ (ext_csd[idx + 1] << 8) + ext_csd[idx];
+ if (mult)
+ has_parts = true;
+ if (!part_completed)
+ continue;
+ mmc->capacity_gp[i] = mult;
+ mmc->capacity_gp[i] *=
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
+ mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+ mmc->capacity_gp[i] <<= 19;
+ }
+
+#ifndef CONFIG_SPL_BUILD
+ if (part_completed) {
+ mmc->enh_user_size =
+ (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
+ (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
+ ext_csd[EXT_CSD_ENH_SIZE_MULT];
+ mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
+ mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+ mmc->enh_user_size <<= 19;
+ mmc->enh_user_start =
+ (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
+ (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
+ (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
+ ext_csd[EXT_CSD_ENH_START_ADDR];
+ if (mmc->high_capacity)
+ mmc->enh_user_start <<= 9;
+ }
+#endif
+
+ /*
+ * Host needs to enable ERASE_GRP_DEF bit if device is
+ * partitioned. This bit will be lost every time after a reset
+ * or power off. This will affect erase size.
+ */
+ if (part_completed)
+ has_parts = true;
+ if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
+ (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
+ has_parts = true;
+ if (has_parts) {
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_ERASE_GROUP_DEF, 1);
+
+ if (err)
+ goto error;
+
+ ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
+ }
+
+ if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+ /* Read out group size from ext_csd */
+ mmc->erase_grp_size =
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
+#endif
+ /*
+ * if high capacity and partition setting completed
+ * SEC_COUNT is valid even if it is smaller than 2 GiB
+ * JEDEC Standard JESD84-B45, 6.2.4
+ */
+ if (mmc->high_capacity && part_completed) {
+ capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
+ (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
+ (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
+ (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
+ capacity *= MMC_MAX_BLOCK_LEN;
+ mmc->capacity_user = capacity;
+ }
+ }
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+ else {
+ /* Calculate the group size from the csd value. */
+ int erase_gsz, erase_gmul;
+
+ erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
+ erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
+ mmc->erase_grp_size = (erase_gsz + 1)
+ * (erase_gmul + 1);
+ }
+#endif
+#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
+ mmc->hc_wp_grp_size = 1024
+ * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
+ * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+#endif
+
+ mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
+
+ return 0;
+error:
+ if (mmc->ext_csd) {
+ free(mmc->ext_csd);
+ mmc->ext_csd = NULL;
+ }
+ return err;
+}
+
+static int mmc_startup(struct mmc *mmc)
+{
+ int err, i;
+ uint mult, freq;
+ u64 cmult, csize;
+ struct mmc_cmd cmd;
+ struct blk_desc *bdesc;
+
+#ifdef CONFIG_MMC_SPI_CRC_ON
+ if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
+ cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 1;
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
+ }
#endif
/* Put the Card in Identify Mode */
err = mmc_send_cmd(mmc, &cmd, NULL);
+#ifdef CONFIG_MMC_QUIRKS
+ if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
+ int retries = 4;
+ /*
+ * It has been seen that SEND_CID may fail on the first
+ * attempt, let's try a few more time
+ */
+ do {
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (!err)
+ break;
+ } while (retries--);
+ }
+#endif
+
if (err)
return err;
freq = fbase[(cmd.response[0] & 0x7)];
mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
- mmc->tran_speed = freq * mult;
+ mmc->legacy_speed = freq * mult;
+ mmc_select_mode(mmc, MMC_LEGACY);
mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
+#if CONFIG_IS_ENABLED(MMC_WRITE)
if (IS_SD(mmc))
mmc->write_bl_len = mmc->read_bl_len;
else
mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
+#endif
if (mmc->high_capacity) {
csize = (mmc->csd[1] & 0x3f) << 16
if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+#if CONFIG_IS_ENABLED(MMC_WRITE)
if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
+#endif
if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
cmd.cmdidx = MMC_CMD_SET_DSR;
cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
cmd.resp_type = MMC_RSP_NONE;
if (mmc_send_cmd(mmc, &cmd, NULL))
- printf("MMC: SET_DSR failed\n");
+ pr_warn("MMC: SET_DSR failed\n");
}
/* Select the card, and put it into Transfer Mode */
/*
* For SD, its erase group is always one sector
*/
+#if CONFIG_IS_ENABLED(MMC_WRITE)
mmc->erase_grp_size = 1;
+#endif
mmc->part_config = MMCPART_NOAVAILABLE;
- if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
- /* check ext_csd version and capacity */
- err = mmc_send_ext_csd(mmc, ext_csd);
- if (err)
- return err;
- if (ext_csd[EXT_CSD_REV] >= 2) {
- /*
- * According to the JEDEC Standard, the value of
- * ext_csd's capacity is valid if the value is more
- * than 2GB
- */
- capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
- | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
- | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
- | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
- capacity *= MMC_MAX_BLOCK_LEN;
- if ((capacity >> 20) > 2 * 1024)
- mmc->capacity_user = capacity;
- }
-
- switch (ext_csd[EXT_CSD_REV]) {
- case 1:
- mmc->version = MMC_VERSION_4_1;
- break;
- case 2:
- mmc->version = MMC_VERSION_4_2;
- break;
- case 3:
- mmc->version = MMC_VERSION_4_3;
- break;
- case 5:
- mmc->version = MMC_VERSION_4_41;
- break;
- case 6:
- mmc->version = MMC_VERSION_4_5;
- break;
- case 7:
- mmc->version = MMC_VERSION_5_0;
- break;
- case 8:
- mmc->version = MMC_VERSION_5_1;
- break;
- }
-
- /* The partition data may be non-zero but it is only
- * effective if PARTITION_SETTING_COMPLETED is set in
- * EXT_CSD, so ignore any data if this bit is not set,
- * except for enabling the high-capacity group size
- * definition (see below). */
- part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
- EXT_CSD_PARTITION_SETTING_COMPLETED);
-
- /* store the partition info of emmc */
- mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
- if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
- ext_csd[EXT_CSD_BOOT_MULT])
- mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
- if (part_completed &&
- (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
- mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
-
- mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
-
- mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
-
- for (i = 0; i < 4; i++) {
- int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
- uint mult = (ext_csd[idx + 2] << 16) +
- (ext_csd[idx + 1] << 8) + ext_csd[idx];
- if (mult)
- has_parts = true;
- if (!part_completed)
- continue;
- mmc->capacity_gp[i] = mult;
- mmc->capacity_gp[i] *=
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
- mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
- mmc->capacity_gp[i] <<= 19;
- }
-
- if (part_completed) {
- mmc->enh_user_size =
- (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
- (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
- ext_csd[EXT_CSD_ENH_SIZE_MULT];
- mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
- mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
- mmc->enh_user_size <<= 19;
- mmc->enh_user_start =
- (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
- (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
- (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
- ext_csd[EXT_CSD_ENH_START_ADDR];
- if (mmc->high_capacity)
- mmc->enh_user_start <<= 9;
- }
-
- /*
- * Host needs to enable ERASE_GRP_DEF bit if device is
- * partitioned. This bit will be lost every time after a reset
- * or power off. This will affect erase size.
- */
- if (part_completed)
- has_parts = true;
- if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
- (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
- has_parts = true;
- if (has_parts) {
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_ERASE_GROUP_DEF, 1);
-
- if (err)
- return err;
- else
- ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
- }
-
- if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
- /* Read out group size from ext_csd */
- mmc->erase_grp_size =
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
- /*
- * if high capacity and partition setting completed
- * SEC_COUNT is valid even if it is smaller than 2 GiB
- * JEDEC Standard JESD84-B45, 6.2.4
- */
- if (mmc->high_capacity && part_completed) {
- capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
- (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
- (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
- (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
- capacity *= MMC_MAX_BLOCK_LEN;
- mmc->capacity_user = capacity;
- }
- } else {
- /* Calculate the group size from the csd value. */
- int erase_gsz, erase_gmul;
- erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
- erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
- mmc->erase_grp_size = (erase_gsz + 1)
- * (erase_gmul + 1);
- }
-
- mmc->hc_wp_grp_size = 1024
- * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
- * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
-
- mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
- }
- err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
+ err = mmc_startup_v4(mmc);
if (err)
return err;
- if (IS_SD(mmc))
- err = sd_change_freq(mmc);
- else
- err = mmc_change_freq(mmc);
-
+ err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
if (err)
return err;
- /* Restrict card's capabilities by what the host can do */
- mmc->card_caps &= mmc->cfg->host_caps;
-
if (IS_SD(mmc)) {
- if (mmc->card_caps & MMC_MODE_4BIT) {
- cmd.cmdidx = MMC_CMD_APP_CMD;
- cmd.resp_type = MMC_RSP_R1;
- cmd.cmdarg = mmc->rca << 16;
-
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err)
- return err;
-
- cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
- cmd.resp_type = MMC_RSP_R1;
- cmd.cmdarg = 2;
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err)
- return err;
-
- mmc_set_bus_width(mmc, 4);
- }
-
- err = sd_read_ssr(mmc);
+ err = sd_get_capabilities(mmc);
if (err)
return err;
-
- if (mmc->card_caps & MMC_MODE_HS)
- mmc->tran_speed = 50000000;
- else
- mmc->tran_speed = 25000000;
- } else if (mmc->version >= MMC_VERSION_4) {
- /* Only version 4 of MMC supports wider bus widths */
- int idx;
-
- /* An array of possible bus widths in order of preference */
- static unsigned ext_csd_bits[] = {
- EXT_CSD_DDR_BUS_WIDTH_8,
- EXT_CSD_DDR_BUS_WIDTH_4,
- EXT_CSD_BUS_WIDTH_8,
- EXT_CSD_BUS_WIDTH_4,
- EXT_CSD_BUS_WIDTH_1,
- };
-
- /* An array to map CSD bus widths to host cap bits */
- static unsigned ext_to_hostcaps[] = {
- [EXT_CSD_DDR_BUS_WIDTH_4] =
- MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
- [EXT_CSD_DDR_BUS_WIDTH_8] =
- MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
- [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
- [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
- };
-
- /* An array to map chosen bus width to an integer */
- static unsigned widths[] = {
- 8, 4, 8, 4, 1,
- };
-
- for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
- unsigned int extw = ext_csd_bits[idx];
- unsigned int caps = ext_to_hostcaps[extw];
-
- /*
- * If the bus width is still not changed,
- * don't try to set the default again.
- * Otherwise, recover from switch attempts
- * by switching to 1-bit bus width.
- */
- if (extw == EXT_CSD_BUS_WIDTH_1 &&
- mmc->bus_width == 1) {
- err = 0;
- break;
- }
-
- /*
- * Check to make sure the card and controller support
- * these capabilities
- */
- if ((mmc->card_caps & caps) != caps)
- continue;
-
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_BUS_WIDTH, extw);
-
- if (err)
- continue;
-
- mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
- mmc_set_bus_width(mmc, widths[idx]);
-
- err = mmc_send_ext_csd(mmc, test_csd);
-
- if (err)
- continue;
-
- /* Only compare read only fields */
- if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
- == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
- ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
- == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
- ext_csd[EXT_CSD_REV]
- == test_csd[EXT_CSD_REV] &&
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
- == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
- memcmp(&ext_csd[EXT_CSD_SEC_CNT],
- &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
- break;
- else
- err = -EBADMSG;
- }
-
+ err = sd_select_mode_and_width(mmc, mmc->card_caps);
+ } else {
+ err = mmc_get_capabilities(mmc);
if (err)
return err;
-
- if (mmc->card_caps & MMC_MODE_HS) {
- if (mmc->card_caps & MMC_MODE_HS_52MHz)
- mmc->tran_speed = 52000000;
- else
- mmc->tran_speed = 26000000;
- }
+ mmc_select_mode_and_width(mmc, mmc->card_caps);
}
- mmc_set_clock(mmc, mmc->tran_speed);
+ if (err)
+ return err;
+
+ mmc->best_mode = mmc->selected_mode;
/* Fix the block length for DDR mode */
if (mmc->ddr_mode) {
mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+#if CONFIG_IS_ENABLED(MMC_WRITE)
mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
+#endif
}
/* fill in device description */
static int mmc_power_init(struct mmc *mmc)
{
#if CONFIG_IS_ENABLED(DM_MMC)
-#if defined(CONFIG_DM_REGULATOR) && !defined(CONFIG_SPL_BUILD)
- struct udevice *vmmc_supply;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
int ret;
ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
- &vmmc_supply);
- if (ret) {
+ &mmc->vmmc_supply);
+ if (ret)
debug("%s: No vmmc supply\n", mmc->dev->name);
- return 0;
- }
- ret = regulator_set_enable(vmmc_supply, true);
- if (ret) {
- puts("Error enabling VMMC supply\n");
- return ret;
- }
+ ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
+ &mmc->vqmmc_supply);
+ if (ret)
+ debug("%s: No vqmmc supply\n", mmc->dev->name);
#endif
#else /* !CONFIG_DM_MMC */
/*
return 0;
}
+/*
+ * put the host in the initial state:
+ * - turn on Vdd (card power supply)
+ * - configure the bus width and clock to minimal values
+ */
+static void mmc_set_initial_state(struct mmc *mmc)
+{
+ int err;
+
+ /* First try to set 3.3V. If it fails set to 1.8V */
+ err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
+ if (err != 0)
+ err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
+ if (err != 0)
+ pr_warn("mmc: failed to set signal voltage\n");
+
+ mmc_select_mode(mmc, MMC_LEGACY);
+ mmc_set_bus_width(mmc, 1);
+ mmc_set_clock(mmc, 0, false);
+}
+
+static int mmc_power_on(struct mmc *mmc)
+{
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vmmc_supply) {
+ int ret = regulator_set_enable(mmc->vmmc_supply, true);
+
+ if (ret) {
+ puts("Error enabling VMMC supply\n");
+ return ret;
+ }
+ }
+#endif
+ return 0;
+}
+
+static int mmc_power_off(struct mmc *mmc)
+{
+ mmc_set_clock(mmc, 0, true);
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vmmc_supply) {
+ int ret = regulator_set_enable(mmc->vmmc_supply, false);
+
+ if (ret) {
+ debug("Error disabling VMMC supply\n");
+ return ret;
+ }
+ }
+#endif
+ return 0;
+}
+
+static int mmc_power_cycle(struct mmc *mmc)
+{
+ int ret;
+
+ ret = mmc_power_off(mmc);
+ if (ret)
+ return ret;
+ /*
+ * SD spec recommends at least 1ms of delay. Let's wait for 2ms
+ * to be on the safer side.
+ */
+ udelay(2000);
+ return mmc_power_on(mmc);
+}
+
int mmc_start_init(struct mmc *mmc)
{
bool no_card;
+ bool uhs_en = supports_uhs(mmc->cfg->host_caps);
int err;
+ /*
+ * all hosts are capable of 1 bit bus-width and able to use the legacy
+ * timings.
+ */
+ mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
+ MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
+
+#if !defined(CONFIG_MMC_BROKEN_CD)
/* we pretend there's no card when init is NULL */
no_card = mmc_getcd(mmc) == 0;
+#else
+ no_card = 0;
+#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
no_card = no_card || (mmc->cfg->ops->init == NULL);
#endif
if (err)
return err;
+#ifdef CONFIG_MMC_QUIRKS
+ mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
+ MMC_QUIRK_RETRY_SEND_CID;
+#endif
+
+ err = mmc_power_cycle(mmc);
+ if (err) {
+ /*
+ * if power cycling is not supported, we should not try
+ * to use the UHS modes, because we wouldn't be able to
+ * recover from an error during the UHS initialization.
+ */
+ debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
+ uhs_en = false;
+ mmc->host_caps &= ~UHS_CAPS;
+ err = mmc_power_on(mmc);
+ }
+ if (err)
+ return err;
+
#if CONFIG_IS_ENABLED(DM_MMC)
/* The device has already been probed ready for use */
#else
return err;
#endif
mmc->ddr_mode = 0;
- mmc_set_bus_width(mmc, 1);
- mmc_set_clock(mmc, 1);
+
+retry:
+ mmc_set_initial_state(mmc);
+ mmc_send_init_stream(mmc);
/* Reset the Card */
err = mmc_go_idle(mmc);
err = mmc_send_if_cond(mmc);
/* Now try to get the SD card's operating condition */
- err = sd_send_op_cond(mmc);
+ err = sd_send_op_cond(mmc, uhs_en);
+ if (err && uhs_en) {
+ uhs_en = false;
+ mmc_power_cycle(mmc);
+ goto retry;
+ }
/* If the command timed out, we check for an MMC card */
if (err == -ETIMEDOUT) {
if (err) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("Card did not respond to voltage select!\n");
+ pr_err("Card did not respond to voltage select!\n");
#endif
return -EOPNOTSUPP;
}
uclass_foreach_dev(dev, uc) {
ret = device_probe(dev);
if (ret)
- printf("%s - probe failed: %d\n", dev->name, ret);
+ pr_err("%s - probe failed: %d\n", dev->name, ret);
}
return 0;
void *dst);
#endif
-#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV))
+#if CONFIG_IS_ENABLED(MMC_WRITE)
#if CONFIG_IS_ENABLED(BLK)
ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt);
#endif
-#else /* CONFIG_SPL_BUILD and CONFIG_SPL_SAVEENV is not defined */
+#else /* CONFIG_SPL_MMC_WRITE is not defined */
/* declare dummies to reduce code size. */
#include <config.h>
#include <common.h>
#include <malloc.h>
+#include <memalign.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
-#include <twl4030.h>
-#include <twl6030.h>
+#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
#include <palmas.h>
+#endif
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#if !defined(CONFIG_SOC_KEYSTONE)
#define SYSCTL_SRC (1 << 25)
#define SYSCTL_SRD (1 << 26)
-struct omap2_mmc_platform_config {
- u32 reg_offset;
-};
-
struct omap_hsmmc_data {
struct hsmmc *base_addr;
#if !CONFIG_IS_ENABLED(DM_MMC)
int wp_gpio;
#endif
#endif
+ u8 controller_flags;
+#ifndef CONFIG_OMAP34XX
+ struct omap_hsmmc_adma_desc *adma_desc_table;
+ uint desc_slot;
+#endif
+};
+
+#ifndef CONFIG_OMAP34XX
+struct omap_hsmmc_adma_desc {
+ u8 attr;
+ u8 reserved;
+ u16 len;
+ u32 addr;
};
+#define ADMA_MAX_LEN 63488
+
+/* Decriptor table defines */
+#define ADMA_DESC_ATTR_VALID BIT(0)
+#define ADMA_DESC_ATTR_END BIT(1)
+#define ADMA_DESC_ATTR_INT BIT(2)
+#define ADMA_DESC_ATTR_ACT1 BIT(4)
+#define ADMA_DESC_ATTR_ACT2 BIT(5)
+
+#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
+#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
+#endif
+
/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS 1000
+/* DMA transfers can take a long time if a lot a data is transferred.
+ * The timeout must take in account the amount of data. Let's assume
+ * that the time will never exceed 333 ms per MB (in other word we assume
+ * that the bandwidth is always above 3MB/s).
+ */
+#define DMA_TIMEOUT_PER_MB 333
+#define OMAP_HSMMC_USE_ADMA BIT(2)
+
static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
unsigned int siz);
return -ETIMEDOUT;
}
}
+#ifndef CONFIG_OMAP34XX
+ reg_val = readl(&mmc_base->hl_hwinfo);
+ if (reg_val & MADMA_EN)
+ priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
+#endif
writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
&mmc_base->capa);
dsor = 240;
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
- (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+ (ICE_STOP | DTO_15THDTO));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
- IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
- &mmc_base->ie);
+ IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
+ IE_CC, &mmc_base->ie);
mmc_init_stream(mmc_base);
}
}
}
+
+#ifndef CONFIG_OMAP34XX
+static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
+{
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ struct omap_hsmmc_adma_desc *desc;
+ u8 attr;
+
+ desc = &priv->adma_desc_table[priv->desc_slot];
+
+ attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
+ if (!end)
+ priv->desc_slot++;
+ else
+ attr |= ADMA_DESC_ATTR_END;
+
+ desc->len = len;
+ desc->addr = (u32)buf;
+ desc->reserved = 0;
+ desc->attr = attr;
+}
+
+static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
+ struct mmc_data *data)
+{
+ uint total_len = data->blocksize * data->blocks;
+ uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ int i = desc_count;
+ char *buf;
+
+ priv->desc_slot = 0;
+ priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
+ memalign(ARCH_DMA_MINALIGN, desc_count *
+ sizeof(struct omap_hsmmc_adma_desc));
+
+ if (data->flags & MMC_DATA_READ)
+ buf = data->dest;
+ else
+ buf = (char *)data->src;
+
+ while (--i) {
+ omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
+ buf += ADMA_MAX_LEN;
+ total_len -= ADMA_MAX_LEN;
+ }
+
+ omap_hsmmc_adma_desc(mmc, buf, total_len, true);
+
+ flush_dcache_range((long)priv->adma_desc_table,
+ (long)priv->adma_desc_table +
+ ROUND(desc_count *
+ sizeof(struct omap_hsmmc_adma_desc),
+ ARCH_DMA_MINALIGN));
+}
+
+static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
+{
+ struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ u32 val;
+ char *buf;
+
+ mmc_base = priv->base_addr;
+ omap_hsmmc_prepare_adma_table(mmc, data);
+
+ if (data->flags & MMC_DATA_READ)
+ buf = data->dest;
+ else
+ buf = (char *)data->src;
+
+ val = readl(&mmc_base->hctl);
+ val |= DMA_SELECT;
+ writel(val, &mmc_base->hctl);
+
+ val = readl(&mmc_base->con);
+ val |= DMA_MASTER;
+ writel(val, &mmc_base->con);
+
+ writel((u32)priv->adma_desc_table, &mmc_base->admasal);
+
+ flush_dcache_range((u32)buf,
+ (u32)buf +
+ ROUND(data->blocksize * data->blocks,
+ ARCH_DMA_MINALIGN));
+}
+
+static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
+{
+ struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ u32 val;
+
+ mmc_base = priv->base_addr;
+
+ val = readl(&mmc_base->con);
+ val &= ~DMA_MASTER;
+ writel(val, &mmc_base->con);
+
+ val = readl(&mmc_base->hctl);
+ val &= ~DMA_SELECT;
+ writel(val, &mmc_base->hctl);
+
+ kfree(priv->adma_desc_table);
+}
+#else
+#define omap_hsmmc_adma_desc
+#define omap_hsmmc_prepare_adma_table
+#define omap_hsmmc_prepare_data
+#define omap_hsmmc_dma_cleanup
+#endif
+
#if !CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
struct mmc_data *data)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
+#ifndef CONFIG_OMAP34XX
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct mmc *mmc = upriv->mmc;
+#endif
#endif
struct hsmmc *mmc_base;
unsigned int flags, mmc_stat;
ulong start;
mmc_base = priv->base_addr;
+
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ return 0;
+
start = get_timer(0);
while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
if (get_timer(0) - start > MAX_RETRY_MS) {
/* enable default flags */
flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
- MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
+ MSBS_SGLEBLK);
+ flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
if (cmd->resp_type & MMC_RSP_CRC)
flags |= CCCE_CHECK;
if (data) {
if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
- flags |= (MSBS_MULTIBLK | BCE_ENABLE);
+ flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
data->blocksize = 512;
writel(data->blocksize | (data->blocks << 16),
&mmc_base->blk);
flags |= (DP_DATA | DDIR_READ);
else
flags |= (DP_DATA | DDIR_WRITE);
+
+#ifndef CONFIG_OMAP34XX
+ if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
+ !mmc_is_tuning_cmd(cmd->cmdidx)) {
+ omap_hsmmc_prepare_data(mmc, data);
+ flags |= DE_ENABLE;
+ }
+#endif
}
writel(cmd->cmdarg, &mmc_base->arg);
start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
- if (get_timer(0) - start > MAX_RETRY_MS) {
+ if (get_timer(start) > MAX_RETRY_MS) {
printf("%s : timeout: No status update\n", __func__);
return -ETIMEDOUT;
}
}
}
+#ifndef CONFIG_OMAP34XX
+ if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
+ !mmc_is_tuning_cmd(cmd->cmdidx)) {
+ u32 sz_mb, timeout;
+
+ if (mmc_stat & IE_ADMAE) {
+ omap_hsmmc_dma_cleanup(mmc);
+ return -EIO;
+ }
+
+ sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
+ timeout = sz_mb * DMA_TIMEOUT_PER_MB;
+ if (timeout < MAX_RETRY_MS)
+ timeout = MAX_RETRY_MS;
+
+ start = get_timer(0);
+ do {
+ mmc_stat = readl(&mmc_base->stat);
+ if (mmc_stat & TC_MASK) {
+ writel(readl(&mmc_base->stat) | TC_MASK,
+ &mmc_base->stat);
+ break;
+ }
+ if (get_timer(start) > timeout) {
+ printf("%s : DMA timeout: No status update\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ } while (1);
+
+ omap_hsmmc_dma_cleanup(mmc);
+ return 0;
+ }
+#endif
+
if (data && (data->flags & MMC_DATA_READ)) {
mmc_read_data(mmc_base, data->dest,
data->blocksize * data->blocks);
}
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
- (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+ (ICE_STOP | DTO_15THDTO));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_config *cfg = &plat->cfg;
- struct omap2_mmc_platform_config *data =
- (struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int val;
plat->base_addr = map_physmem(devfdt_get_addr(dev),
sizeof(struct hsmmc *),
- MAP_NOCACHE) + data->reg_offset;
+ MAP_NOCACHE);
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
val = fdtdec_get_int(fdt, node, "bus-width", -1);
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
- .reg_offset = 0,
-};
-
-static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
- .reg_offset = 0x100,
-};
-
-static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
- .reg_offset = 0x100,
-};
-
static const struct udevice_id omap_hsmmc_ids[] = {
- {
- .compatible = "ti,omap3-hsmmc",
- .data = (ulong)&omap3_mmc_pdata
- },
- {
- .compatible = "ti,omap4-hsmmc",
- .data = (ulong)&omap4_mmc_pdata
- },
- {
- .compatible = "ti,am33xx-hsmmc",
- .data = (ulong)&am33xx_mmc_pdata
- },
+ { .compatible = "ti,omap3-hsmmc" },
+ { .compatible = "ti,omap4-hsmmc" },
+ { .compatible = "ti,am33xx-hsmmc" },
{ }
};
#endif
cmd->response[1] = 10 << 16; /* 1 << block_len */
break;
case SD_CMD_SWITCH_FUNC: {
+ if (!data)
+ break;
u32 *resp = (u32 *)data->dest;
-
resp[7] = cpu_to_be32(SD_HIGHSPEED_BUSY);
+ if ((cmd->cmdarg & 0xF) == UHS_SDR12_BUS_SPEED)
+ resp[4] = (cmd->cmdarg & 0xF) << 24;
break;
}
case MMC_CMD_READ_SINGLE_BLOCK:
#include <common.h>
#include <dm.h>
+#include <linux/bitfield.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/sizes.h>
#define SDHCI_CDNS_HRS04_ACK BIT(26)
#define SDHCI_CDNS_HRS04_RD BIT(25)
#define SDHCI_CDNS_HRS04_WR BIT(24)
-#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16
-#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
-#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
+#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
+#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
+#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
-#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8
-#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f
-#define SDHCI_CDNS_HRS06_MODE_MASK 0x7
+#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
+#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
#define SDHCI_CDNS_HRS06_MODE_SD 0x0
#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
+/*
+ * The tuned val register is 6 bit-wide, but not the whole of the range is
+ * available. The range 0-42 seems to be available (then 43 wraps around to 0)
+ * but I am not quite sure if it is official. Use only 0 to 39 for safety.
+ */
+#define SDHCI_CDNS_MAX_TUNING_LOOP 40
+
struct sdhci_cdns_plat {
struct mmc_config cfg;
struct mmc mmc;
u32 tmp;
int ret;
- tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
- (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
+ tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
+ FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
writel(tmp, reg);
tmp |= SDHCI_CDNS_HRS04_WR;
* The mode should be decided by MMC_TIMING_* like Linux, but
* U-Boot does not support timing. Use the clock frequency instead.
*/
- if (clock <= 26000000)
+ if (clock <= 26000000) {
mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
- else if (clock <= 52000000) {
+ } else if (clock <= 52000000) {
if (mmc->ddr_mode)
mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
else
mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
} else {
- /*
- * REVISIT:
- * The IP supports HS200/HS400, revisit once U-Boot support it
- */
- printf("unsupported frequency %d\n", clock);
- return;
+ if (mmc->ddr_mode)
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
+ else
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
}
tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
- tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK;
- tmp |= mode;
+ tmp &= ~SDHCI_CDNS_HRS06_MODE;
+ tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
}
.set_control_reg = sdhci_cdns_set_control_reg,
};
+static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
+ unsigned int val)
+{
+ void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
+ u32 tmp;
+
+ if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
+ return -EINVAL;
+
+ tmp = readl(reg);
+ tmp &= ~SDHCI_CDNS_HRS06_TUNE;
+ tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
+ tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
+ writel(tmp, reg);
+
+ return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
+ 1);
+}
+
+static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
+ unsigned int opcode)
+{
+ struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
+ struct mmc *mmc = &plat->mmc;
+ int cur_streak = 0;
+ int max_streak = 0;
+ int end_of_streak = 0;
+ int i;
+
+ /*
+ * This handler only implements the eMMC tuning that is specific to
+ * this controller. The tuning for SD timing should be handled by the
+ * SDHCI core.
+ */
+ if (!IS_MMC(mmc))
+ return -ENOTSUPP;
+
+ if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
+ return -EINVAL;
+
+ for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
+ if (sdhci_cdns_set_tune_val(plat, i) ||
+ mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
+ cur_streak = 0;
+ } else { /* good */
+ cur_streak++;
+ if (cur_streak > max_streak) {
+ max_streak = cur_streak;
+ end_of_streak = i;
+ }
+ }
+ }
+
+ if (!max_streak) {
+ dev_err(dev, "no tuning point found\n");
+ return -EIO;
+ }
+
+ return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
+}
+
+static struct dm_mmc_ops sdhci_cdns_mmc_ops;
+
static int sdhci_cdns_bind(struct udevice *dev)
{
struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
host->ops = &sdhci_cdns_ops;
host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
+ sdhci_cdns_mmc_ops = sdhci_ops;
+#ifdef MMC_SUPPORTS_TUNING
+ sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
+#endif
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
if (ret)
.probe = sdhci_cdns_probe,
.priv_auto_alloc_size = sizeof(struct sdhci_host),
.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
- .ops = &sdhci_ops,
+ .ops = &sdhci_cdns_mmc_ops,
};
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
- printf("%s: Error detected in status(0x%X)!\n",
- __func__, stat);
+ pr_debug("%s: Error detected in status(0x%X)!\n",
+ __func__, stat);
return -EIO;
}
if (!transfer_done && (stat & rdy)) {
/* Timeout unit - ms */
static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
- sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
/* We shouldn't wait for data inihibit for stop commands, even
udelay(1000);
}
+ sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
+
mask = SDHCI_INT_RESPONSE;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = SDHCI_CMD_RESP_NONE;
flags |= SDHCI_CMD_DATA;
/* Set Transfer mode regarding to data flag */
- if (data != 0) {
+ if (data) {
sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
mode = SDHCI_TRNS_BLK_CNT_EN;
trans_bytes = data->blocks * data->blocksize;
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDHCI_SDMA
- if (data != 0) {
+ if (data) {
trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
flush_cache(start_addr, trans_bytes);
}
if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
cfg->voltages |= host->voltages;
- cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+ cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
/* Since Host Controller Version3.0 */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
This MAC is present in Andestech SoCs.
config MVNETA
- bool "Marvell Armada 385 network interface support"
- depends on ARMADA_XP || ARMADA_38X
+ bool "Marvell Armada XP/385/3700 network interface support"
+ depends on ARMADA_XP || ARMADA_38X || ARMADA_3700
select PHYLIB
help
This driver supports the network interface units in the
- Marvell ARMADA XP and 38X SoCs
+ Marvell ARMADA XP, ARMADA 38X and ARMADA 3700 SoCs
config MVPP2
bool "Marvell Armada 375/7K/8K network interface support"
GEM (Gigabit Ethernet MAC) found in some ARM SoC devices.
Say Y to include support for the MACB/GEM chip.
+config MACB_ZYNQ
+ bool "Cadence MACB/GEM Ethernet Interface for Xilinx Zynq"
+ depends on MACB
+ help
+ The Cadence MACB ethernet interface was used on Zynq platform.
+ Say Y to enable support for the MACB/GEM in Zynq chip.
+
config PCH_GBE
bool "Intel Platform Controller Hub EG20T GMAC driver"
depends on DM_ETH && DM_PCI
It can be found in H3/A64/A83T based SoCs and compatible with both
External and Internal PHYs.
+config SH_ETHER
+ bool "Renesas SH Ethernet MAC"
+ select PHYLIB
+ help
+ This driver supports the Ethernet for Renesas SH and ARM SoCs.
+
config XILINX_AXIEMAC
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB
The PHY does not have a RXERR line (RMII only).
(so program the FEC to ignore it).
+config SYS_DPAA_QBMAN
+ bool "Device tree fixup for QBMan on freescale SOCs"
+ depends on (ARM || PPC) && !SPL_BUILD
+ default y if ARCH_B4860 || \
+ ARCH_B4420 || \
+ ARCH_P1023 || \
+ ARCH_P2041 || \
+ ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4240 || \
+ ARCH_T4160 || \
+ ARCH_P4080 || \
+ ARCH_P3041 || \
+ ARCH_P5040 || \
+ ARCH_P5020 || \
+ ARCH_LS1043A || \
+ ARCH_LS1046A
+ help
+ QBman fixups to allow deep sleep in DPAA 1 SOCs
+
endif # NETDEVICES
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
#include <pci.h>
#include <linux/compiler.h>
#include <linux/err.h>
+#include <linux/kernel.h>
#include <asm/io.h>
#include <power/regulator.h>
#include "designware.h"
return 0;
}
+#define ETH_ZLEN 60
+
static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
{
struct eth_dma_regs *dma_p = priv->dma_regs_p;
return -EPERM;
}
+ length = max(length, ETH_ZLEN);
+
memcpy((void *)data_start, packet, length);
/* Flush data to be sent */
u32 iobase = pdata->iobase;
ulong ioaddr;
int ret;
+#ifdef CONFIG_CLK
+ int i, err, clock_nb;
+
+ priv->clock_count = 0;
+ clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
+ if (clock_nb > 0) {
+ priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
+ GFP_KERNEL);
+ if (!priv->clocks)
+ return -ENOMEM;
+
+ for (i = 0; i < clock_nb; i++) {
+ err = clk_get_by_index(dev, i, &priv->clocks[i]);
+ if (err < 0)
+ break;
+
+ err = clk_enable(&priv->clocks[i]);
+ if (err) {
+ pr_err("failed to enable clock %d\n", i);
+ clk_free(&priv->clocks[i]);
+ goto clk_err;
+ }
+ priv->clock_count++;
+ }
+ } else if (clock_nb != -ENOENT) {
+ pr_err("failed to get clock phandle(%d)\n", clock_nb);
+ return clock_nb;
+ }
+#endif
#if defined(CONFIG_DM_REGULATOR)
struct udevice *phy_supply;
debug("%s, ret=%d\n", __func__, ret);
return ret;
+
+#ifdef CONFIG_CLK
+clk_err:
+ ret = clk_release_all(priv->clocks, priv->clock_count);
+ if (ret)
+ pr_err("failed to disable all clocks\n");
+
+ return err;
+#endif
}
static int designware_eth_remove(struct udevice *dev)
mdio_unregister(priv->bus);
mdio_free(priv->bus);
+#ifdef CONFIG_CLK
+ return clk_release_all(priv->clocks, priv->clock_count);
+#else
return 0;
+#endif
}
const struct eth_ops designware_eth_ops = {
#ifdef CONFIG_DM_GPIO
struct gpio_desc reset_gpio;
#endif
+#ifdef CONFIG_CLK
+ struct clk *clocks; /* clock list */
+ int clock_count; /* number of clock in clock list */
+#endif
struct phy_device *phydev;
struct mii_dev *bus;
#define MACB_TX_TIMEOUT 1000
#define MACB_AUTONEG_TIMEOUT 5000000
+#ifdef CONFIG_MACB_ZYNQ
+/* INCR4 AHB bursts */
+#define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
+/* Use full configured addressable space (8 Kb) */
+#define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
+/* Use full configured addressable space (4 Kb) */
+#define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
+/* Set RXBUF with use of 128 byte */
+#define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
+#define MACB_ZYNQ_GEM_DMACR_INIT \
+ (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
+ MACB_ZYNQ_GEM_DMACR_RXSIZE | \
+ MACB_ZYNQ_GEM_DMACR_TXSIZE | \
+ MACB_ZYNQ_GEM_DMACR_RXBUF)
+#endif
+
struct macb_dma_desc {
u32 addr;
u32 ctrl;
phy_id = macb_mdio_read(macb, MII_PHYSID1);
if (phy_id != 0xffff) {
printf("%s: PHY present at %d\n", name, i);
- return 1;
+ return 0;
}
}
/* PHY isn't up to snuff */
printf("%s: PHY not found\n", name);
+ return -ENODEV;
+}
+
+/**
+ * macb_linkspd_cb - Linkspeed change callback function
+ * @regs: Base Register of MACB devices
+ * @speed: Linkspeed
+ * Returns 0 when operation success and negative errno number
+ * when operation failed.
+ */
+int __weak macb_linkspd_cb(void *regs, unsigned int speed)
+{
return 0;
}
u32 ncfgr;
u16 phy_id, status, adv, lpa;
int media, speed, duplex;
+ int ret;
int i;
arch_get_mdio_control(name);
/* Auto-detect phy_addr */
- if (!macb_phy_find(macb, name))
- return 0;
+ ret = macb_phy_find(macb, name);
+ if (ret)
+ return ret;
/* Check if the PHY is up to snuff... */
phy_id = macb_mdio_read(macb, MII_PHYSID1);
if (phy_id == 0xffff) {
printf("%s: No PHY present\n", name);
- return 0;
+ return -ENODEV;
}
#ifdef CONFIG_PHYLIB
if (!(status & BMSR_LSTATUS)) {
printf("%s: link down (status: 0x%04x)\n",
name, status);
- return 0;
+ return -ENETDOWN;
}
/* First check for GMAC and that it is GiB capable */
macb_writel(macb, NCFGR, ncfgr);
- return 1;
+ ret = macb_linkspd_cb(macb->regs, _1000BASET);
+ if (ret)
+ return ret;
+
+ return 0;
}
}
ncfgr = macb_readl(macb, NCFGR);
ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
- if (speed)
+ if (speed) {
ncfgr |= MACB_BIT(SPD);
+ ret = macb_linkspd_cb(macb->regs, _100BASET);
+ } else {
+ ret = macb_linkspd_cb(macb->regs, _10BASET);
+ }
+
+ if (ret)
+ return ret;
+
if (duplex)
ncfgr |= MACB_BIT(FD);
macb_writel(macb, NCFGR, ncfgr);
- return 1;
+ return 0;
}
static int gmac_init_multi_queues(struct macb_device *macb)
struct macb_device *macb = dev_get_priv(dev);
#endif
unsigned long paddr;
+ int ret;
int i;
/*
macb->tx_tail = 0;
macb->next_rx_tail = 0;
+#ifdef CONFIG_MACB_ZYNQ
+ macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
+#endif
+
macb_writel(macb, RBQP, macb->rx_ring_dma);
macb_writel(macb, TBQP, macb->tx_ring_dma);
}
#ifdef CONFIG_DM_ETH
- if (!macb_phy_init(dev, name))
+ ret = macb_phy_init(dev, name);
#else
- if (!macb_phy_init(macb, name))
+ ret = macb_phy_init(macb, name);
#endif
- return -1;
+ if (ret)
+ return ret;
/* Enable TX and RX */
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
if (ret)
return -EINVAL;
+ /*
+ * Zynq clock driver didn't support for enable or disable
+ * clock. Hence, clk_enable() didn't apply for Zynq
+ */
+#ifndef CONFIG_MACB_ZYNQ
ret = clk_enable(&clk);
if (ret)
return ret;
+#endif
clk_rate = clk_get_rate(&clk);
if (!clk_rate)
return 0;
}
+/**
+ * macb_late_eth_ofdata_to_platdata
+ * @dev: udevice struct
+ * Returns 0 when operation success and negative errno number
+ * when operation failed.
+ */
+int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ return 0;
+}
+
static int macb_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
pdata->iobase = devfdt_get_addr(dev);
- return 0;
+
+ return macb_late_eth_ofdata_to_platdata(dev);
}
static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d3-gem" },
{ .compatible = "atmel,sama5d4-gem" },
+ { .compatible = "cdns,zynq-gem" },
{ }
};
#define MACB_NCFGR 0x0004
#define MACB_NSR 0x0008
#define GEM_UR 0x000c
+#define MACB_DMACFG 0x0010
#define MACB_TSR 0x0014
#define MACB_RBQP 0x0018
#define MACB_TBQP 0x001c
*/
*packetp = data;
- mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
+ /*
+ * Only mark one descriptor as free
+ * since only one was processed
+ */
+ mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
}
return rx_bytes;
len = sizeof(input_buffer) - input_size;
end = input_offset + input_size;
- if (end > sizeof(input_buffer))
+ if (end >= sizeof(input_buffer))
end -= sizeof(input_buffer);
chunk = len;
- if (end + len > sizeof(input_buffer)) {
+ /* Check if packet will wrap in input_buffer */
+ if (end + len >= sizeof(input_buffer)) {
chunk = sizeof(input_buffer) - end;
+ /* Copy the second part of the pkt to start of input_buffer */
memcpy(input_buffer, pkt + chunk, len - chunk);
}
+ /* Copy first (or only) part of pkt after end of current valid input*/
memcpy(input_buffer + end, pkt, chunk);
input_size += len;
if PHYLIB
+config B53_SWITCH
+ bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
+ help
+ Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
+ This currently supports BCM53125 and similar models.
+
+if B53_SWITCH
+
+config B53_CPU_PORT
+ int "CPU port"
+ default 8
+
+config B53_PHY_PORTS
+ hex "Bitmask of PHY ports"
+
+endif # B53_SWITCH
+
config MV88E61XX_SWITCH
bool "Marvel MV88E61xx Ethernet switch PHY support."
#
obj-$(CONFIG_BITBANGMII) += miiphybb.o
+obj-$(CONFIG_B53_SWITCH) += b53.o
obj-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o
obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o
static int ar8021_config(struct phy_device *phydev)
{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
--- /dev/null
+/*
+ * Copyright (C) 2017
+ * Broadcom
+ * Florian Fainelli <f.fainelli@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * PHY driver for Broadcom BCM53xx (roboswitch) Ethernet switches.
+ *
+ * This driver configures the b53 for basic use as a PHY. The switch supports
+ * vendor tags and VLAN configuration that can affect the switching decisions.
+ * This driver uses a simple configuration in which all ports are only allowed
+ * to send frames to the CPU port and receive frames from the CPU port this
+ * providing port isolation (no cross talk).
+ *
+ * The configuration determines which PHY ports to activate using the
+ * CONFIG_B53_PHY_PORTS bitmask. Set bit N will active port N and so on.
+ *
+ * This driver was written primarily for the Lamobo R1 platform using a BCM53152
+ * switch but the BCM53xx being largely register compatible, extending it to
+ * cover other switches would be trivial.
+ */
+
+#include <common.h>
+
+#include <errno.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+/* Pseudo-PHY address (non configurable) to access internal registers */
+#define BRCM_PSEUDO_PHY_ADDR 30
+
+/* Maximum number of ports possible */
+#define B53_N_PORTS 9
+
+#define B53_CTRL_PAGE 0x00 /* Control */
+#define B53_MGMT_PAGE 0x02 /* Management Mode */
+/* Port VLAN Page */
+#define B53_PVLAN_PAGE 0x31
+
+/* Control Page registers */
+#define B53_PORT_CTRL(i) (0x00 + (i))
+#define PORT_CTRL_RX_DISABLE BIT(0)
+#define PORT_CTRL_TX_DISABLE BIT(1)
+#define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
+#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
+#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
+
+/* Switch Mode Control Register (8 bit) */
+#define B53_SWITCH_MODE 0x0b
+#define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
+#define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
+
+/* IMP Port state override register (8 bit) */
+#define B53_PORT_OVERRIDE_CTRL 0x0e
+#define PORT_OVERRIDE_LINK BIT(0)
+#define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
+#define PORT_OVERRIDE_SPEED_S 2
+#define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
+#define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
+#define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
+/* BCM5325 only */
+#define PORT_OVERRIDE_RV_MII_25 BIT(4)
+#define PORT_OVERRIDE_RX_FLOW BIT(4)
+#define PORT_OVERRIDE_TX_FLOW BIT(5)
+/* BCM5301X only, requires setting 1000M */
+#define PORT_OVERRIDE_SPEED_2000M BIT(6)
+#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
+
+#define B53_RGMII_CTRL_IMP 0x60
+#define RGMII_CTRL_ENABLE_GMII BIT(7)
+#define RGMII_CTRL_TIMING_SEL BIT(2)
+#define RGMII_CTRL_DLL_RXC BIT(1)
+#define RGMII_CTRL_DLL_TXC BIT(0)
+
+/* Switch control (8 bit) */
+#define B53_SWITCH_CTRL 0x22
+#define B53_MII_DUMB_FWDG_EN BIT(6)
+
+/* Software reset register (8 bit) */
+#define B53_SOFTRESET 0x79
+#define SW_RST BIT(7)
+#define EN_CH_RST BIT(6)
+#define EN_SW_RST BIT(4)
+
+/* Fast Aging Control register (8 bit) */
+#define B53_FAST_AGE_CTRL 0x88
+#define FAST_AGE_STATIC BIT(0)
+#define FAST_AGE_DYNAMIC BIT(1)
+#define FAST_AGE_PORT BIT(2)
+#define FAST_AGE_VLAN BIT(3)
+#define FAST_AGE_STP BIT(4)
+#define FAST_AGE_MC BIT(5)
+#define FAST_AGE_DONE BIT(7)
+
+/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
+#define B53_PVLAN_PORT_MASK(i) ((i) * 2)
+
+/* MII registers */
+#define REG_MII_PAGE 0x10 /* MII Page register */
+#define REG_MII_ADDR 0x11 /* MII Address register */
+#define REG_MII_DATA0 0x18 /* MII Data register 0 */
+#define REG_MII_DATA1 0x19 /* MII Data register 1 */
+#define REG_MII_DATA2 0x1a /* MII Data register 2 */
+#define REG_MII_DATA3 0x1b /* MII Data register 3 */
+
+#define REG_MII_PAGE_ENABLE BIT(0)
+#define REG_MII_ADDR_WRITE BIT(0)
+#define REG_MII_ADDR_READ BIT(1)
+
+struct b53_device {
+ struct mii_dev *bus;
+ unsigned int cpu_port;
+};
+
+static int b53_mdio_op(struct mii_dev *bus, u8 page, u8 reg, u16 op)
+{
+ int ret;
+ int i;
+ u16 v;
+
+ /* set page number */
+ v = (page << 8) | REG_MII_PAGE_ENABLE;
+ ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_PAGE, v);
+ if (ret)
+ return ret;
+
+ /* set register address */
+ v = (reg << 8) | op;
+ ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_ADDR, v);
+ if (ret)
+ return ret;
+
+ /* check if operation completed */
+ for (i = 0; i < 5; ++i) {
+ v = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_ADDR);
+ if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ)))
+ break;
+
+ udelay(100);
+ }
+
+ if (i == 5)
+ return -EIO;
+
+ return 0;
+}
+
+static int b53_mdio_read8(struct mii_dev *bus, u8 page, u8 reg, u8 *val)
+{
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0) & 0xff;
+
+ return 0;
+}
+
+static int b53_mdio_read16(struct mii_dev *bus, u8 page, u8 reg, u16 *val)
+{
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0);
+
+ return 0;
+}
+
+static int b53_mdio_read32(struct mii_dev *bus, u8 page, u8 reg, u32 *val)
+{
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0);
+ *val |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA1) << 16;
+
+ return 0;
+}
+
+static int b53_mdio_read48(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
+{
+ u64 temp = 0;
+ int i;
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ for (i = 2; i >= 0; i--) {
+ temp <<= 16;
+ temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i);
+ }
+
+ *val = temp;
+
+ return 0;
+}
+
+static int b53_mdio_read64(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
+{
+ u64 temp = 0;
+ int i;
+ int ret;
+
+ ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
+ if (ret)
+ return ret;
+
+ for (i = 3; i >= 0; i--) {
+ temp <<= 16;
+ temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i);
+ }
+
+ *val = temp;
+
+ return 0;
+}
+
+static int b53_mdio_write8(struct mii_dev *bus, u8 page, u8 reg, u8 value)
+{
+ int ret;
+
+ ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0, value);
+ if (ret)
+ return ret;
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static int b53_mdio_write16(struct mii_dev *bus, u8 page, u8 reg,
+ u16 value)
+{
+ int ret;
+
+ ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
+ REG_MII_DATA0, value);
+ if (ret)
+ return ret;
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static int b53_mdio_write32(struct mii_dev *bus, u8 page, u8 reg,
+ u32 value)
+{
+ unsigned int i;
+ u32 temp = value;
+
+ for (i = 0; i < 2; i++) {
+ int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
+ MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i, temp & 0xffff);
+ if (ret)
+ return ret;
+ temp >>= 16;
+ }
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static int b53_mdio_write48(struct mii_dev *bus, u8 page, u8 reg,
+ u64 value)
+{
+ unsigned int i;
+ u64 temp = value;
+
+ for (i = 0; i < 3; i++) {
+ int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
+ MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i, temp & 0xffff);
+ if (ret)
+ return ret;
+ temp >>= 16;
+ }
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static int b53_mdio_write64(struct mii_dev *bus, u8 page, u8 reg,
+ u64 value)
+{
+ unsigned int i;
+ u64 temp = value;
+
+ for (i = 0; i < 4; i++) {
+ int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
+ MDIO_DEVAD_NONE,
+ REG_MII_DATA0 + i, temp & 0xffff);
+ if (ret)
+ return ret;
+ temp >>= 16;
+ }
+
+ return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
+}
+
+static inline int b53_read8(struct b53_device *dev, u8 page,
+ u8 reg, u8 *value)
+{
+ return b53_mdio_read8(dev->bus, page, reg, value);
+}
+
+static inline int b53_read16(struct b53_device *dev, u8 page,
+ u8 reg, u16 *value)
+{
+ return b53_mdio_read16(dev->bus, page, reg, value);
+}
+
+static inline int b53_read32(struct b53_device *dev, u8 page,
+ u8 reg, u32 *value)
+{
+ return b53_mdio_read32(dev->bus, page, reg, value);
+}
+
+static inline int b53_read48(struct b53_device *dev, u8 page,
+ u8 reg, u64 *value)
+{
+ return b53_mdio_read48(dev->bus, page, reg, value);
+}
+
+static inline int b53_read64(struct b53_device *dev, u8 page,
+ u8 reg, u64 *value)
+{
+ return b53_mdio_read64(dev->bus, page, reg, value);
+}
+
+static inline int b53_write8(struct b53_device *dev, u8 page,
+ u8 reg, u8 value)
+{
+ return b53_mdio_write8(dev->bus, page, reg, value);
+}
+
+static inline int b53_write16(struct b53_device *dev, u8 page,
+ u8 reg, u16 value)
+{
+ return b53_mdio_write16(dev->bus, page, reg, value);
+}
+
+static inline int b53_write32(struct b53_device *dev, u8 page,
+ u8 reg, u32 value)
+{
+ return b53_mdio_write32(dev->bus, page, reg, value);
+}
+
+static inline int b53_write48(struct b53_device *dev, u8 page,
+ u8 reg, u64 value)
+{
+ return b53_mdio_write48(dev->bus, page, reg, value);
+}
+
+static inline int b53_write64(struct b53_device *dev, u8 page,
+ u8 reg, u64 value)
+{
+ return b53_mdio_write64(dev->bus, page, reg, value);
+}
+
+static int b53_flush_arl(struct b53_device *dev, u8 mask)
+{
+ unsigned int i;
+
+ b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
+ FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
+
+ for (i = 0; i < 10; i++) {
+ u8 fast_age_ctrl;
+
+ b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
+ &fast_age_ctrl);
+
+ if (!(fast_age_ctrl & FAST_AGE_DONE))
+ goto out;
+
+ mdelay(1);
+ }
+
+ return -ETIMEDOUT;
+out:
+ /* Only age dynamic entries (default behavior) */
+ b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
+ return 0;
+}
+
+static int b53_switch_reset(struct phy_device *phydev)
+{
+ struct b53_device *dev = phydev->priv;
+ unsigned int timeout = 1000;
+ u8 mgmt;
+ u8 reg;
+
+ b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
+ reg |= SW_RST | EN_SW_RST | EN_CH_RST;
+ b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
+
+ do {
+ b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
+ if (!(reg & SW_RST))
+ break;
+
+ mdelay(1);
+ } while (timeout-- > 0);
+
+ if (timeout == 0)
+ return -ETIMEDOUT;
+
+ b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
+
+ if (!(mgmt & SM_SW_FWD_EN)) {
+ mgmt &= ~SM_SW_FWD_MODE;
+ mgmt |= SM_SW_FWD_EN;
+
+ b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
+ b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
+
+ if (!(mgmt & SM_SW_FWD_EN)) {
+ printf("Failed to enable switch!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Include IMP port in dumb forwarding mode when no tagging protocol
+ * is configured
+ */
+ b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
+ mgmt |= B53_MII_DUMB_FWDG_EN;
+ b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
+
+ return b53_flush_arl(dev, FAST_AGE_STATIC);
+}
+
+static void b53_enable_cpu_port(struct phy_device *phydev)
+{
+ struct b53_device *dev = phydev->priv;
+ u8 port_ctrl;
+
+ port_ctrl = PORT_CTRL_RX_BCST_EN |
+ PORT_CTRL_RX_MCST_EN |
+ PORT_CTRL_RX_UCST_EN;
+ b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(dev->cpu_port), port_ctrl);
+
+ port_ctrl = PORT_OVERRIDE_EN | PORT_OVERRIDE_LINK |
+ PORT_OVERRIDE_FULL_DUPLEX | PORT_OVERRIDE_SPEED_1000M;
+ b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, port_ctrl);
+
+ b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_IMP, &port_ctrl);
+}
+
+static void b53_imp_vlan_setup(struct b53_device *dev, int cpu_port)
+{
+ unsigned int port;
+ u16 pvlan;
+
+ /* Enable the IMP port to be in the same VLAN as the other ports
+ * on a per-port basis such that we only have Port i and IMP in
+ * the same VLAN.
+ */
+ for (port = 0; port < B53_N_PORTS; port++) {
+ if (!((1 << port) & CONFIG_B53_PHY_PORTS))
+ continue;
+
+ b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
+ &pvlan);
+ pvlan |= BIT(cpu_port);
+ b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
+ pvlan);
+ }
+}
+
+static int b53_port_enable(struct phy_device *phydev, unsigned int port)
+{
+ struct b53_device *dev = phydev->priv;
+ unsigned int cpu_port = dev->cpu_port;
+ u16 pvlan;
+
+ /* Clear the Rx and Tx disable bits and set to no spanning tree */
+ b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
+
+ /* Set this port, and only this one to be in the default VLAN */
+ b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
+ pvlan &= ~0x1ff;
+ pvlan |= BIT(port);
+ b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
+
+ b53_imp_vlan_setup(dev, cpu_port);
+
+ return 0;
+}
+
+static int b53_switch_init(struct phy_device *phydev)
+{
+ static int init;
+ int ret;
+
+ if (init)
+ return 0;
+
+ ret = b53_switch_reset(phydev);
+ if (ret < 0)
+ return ret;
+
+ b53_enable_cpu_port(phydev);
+
+ init = 1;
+
+ return 0;
+}
+
+static int b53_probe(struct phy_device *phydev)
+{
+ struct b53_device *dev;
+ int ret;
+
+ dev = malloc(sizeof(*dev));
+ if (!dev)
+ return -ENOMEM;
+
+ memset(dev, 0, sizeof(*dev));
+
+ phydev->priv = dev;
+ dev->bus = phydev->bus;
+ dev->cpu_port = CONFIG_B53_CPU_PORT;
+
+ ret = b53_switch_reset(phydev);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int b53_phy_config(struct phy_device *phydev)
+{
+ unsigned int port;
+ int res;
+
+ res = b53_switch_init(phydev);
+ if (res < 0)
+ return res;
+
+ for (port = 0; port < B53_N_PORTS; port++) {
+ if (!((1 << port) & CONFIG_B53_PHY_PORTS))
+ continue;
+
+ res = b53_port_enable(phydev, port);
+ if (res < 0) {
+ printf("Error enabling port %i\n", port);
+ continue;
+ }
+
+ res = genphy_config_aneg(phydev);
+ if (res < 0) {
+ printf("Error setting PHY %i autoneg\n", port);
+ continue;
+ }
+
+ res = 0;
+ }
+
+ return res;
+}
+
+static int b53_phy_startup(struct phy_device *phydev)
+{
+ unsigned int port;
+ int res;
+
+ for (port = 0; port < B53_N_PORTS; port++) {
+ if (!((1 << port) & CONFIG_B53_PHY_PORTS))
+ continue;
+
+ phydev->addr = port;
+
+ res = genphy_startup(phydev);
+ if (res < 0)
+ continue;
+ else
+ break;
+ }
+
+ /* Since we are connected directly to the switch, hardcode the link
+ * parameters to match those of the CPU port configured in
+ * b53_enable_cpu_port, we cannot be dependent on the user-facing port
+ * settings (e.g: 100Mbits/sec would not work here)
+ */
+ phydev->speed = 1000;
+ phydev->duplex = 1;
+ phydev->link = 1;
+
+ return 0;
+}
+
+static struct phy_driver b53_driver = {
+ .name = "Broadcom BCM53125",
+ .uid = 0x03625c00,
+ .mask = 0xfffffc00,
+ .features = PHY_GBIT_FEATURES,
+ .probe = b53_probe,
+ .config = b53_phy_config,
+ .startup = b53_phy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_b53_init(void)
+{
+ phy_register(&b53_driver);
+
+ return 0;
+}
+
+int do_b53_reg_read(const char *name, int argc, char * const argv[])
+{
+ u8 page, offset, width;
+ struct mii_dev *bus;
+ int ret = -EINVAL;
+ u64 value64 = 0;
+ u32 value32 = 0;
+ u16 value16 = 0;
+ u8 value8 = 0;
+
+ bus = miiphy_get_dev_by_name(name);
+ if (!bus) {
+ printf("unable to find MDIO bus: %s\n", name);
+ return ret;
+ }
+
+ page = simple_strtoul(argv[1], NULL, 16);
+ offset = simple_strtoul(argv[2], NULL, 16);
+ width = simple_strtoul(argv[3], NULL, 10);
+
+ switch (width) {
+ case 8:
+ ret = b53_mdio_read8(bus, page, offset, &value8);
+ printf("page=0x%02x, offset=0x%02x, value=0x%02x\n",
+ page, offset, value8);
+ break;
+ case 16:
+ ret = b53_mdio_read16(bus, page, offset, &value16);
+ printf("page=0x%02x, offset=0x%02x, value=0x%04x\n",
+ page, offset, value16);
+ break;
+ case 32:
+ ret = b53_mdio_read32(bus, page, offset, &value32);
+ printf("page=0x%02x, offset=0x%02x, value=0x%08x\n",
+ page, offset, value32);
+ break;
+ case 48:
+ ret = b53_mdio_read48(bus, page, offset, &value64);
+ printf("page=0x%02x, offset=0x%02x, value=0x%012llx\n",
+ page, offset, value64);
+ break;
+ case 64:
+ ret = b53_mdio_read48(bus, page, offset, &value64);
+ printf("page=0x%02x, offset=0x%02x, value=0x%016llx\n",
+ page, offset, value64);
+ break;
+ default:
+ printf("Unsupported width: %d\n", width);
+ break;
+ }
+
+ return ret;
+}
+
+int do_b53_reg_write(const char *name, int argc, char * const argv[])
+{
+ u8 page, offset, width;
+ struct mii_dev *bus;
+ int ret = -EINVAL;
+ u64 value64 = 0;
+ u32 value = 0;
+
+ bus = miiphy_get_dev_by_name(name);
+ if (!bus) {
+ printf("unable to find MDIO bus: %s\n", name);
+ return ret;
+ }
+
+ page = simple_strtoul(argv[1], NULL, 16);
+ offset = simple_strtoul(argv[2], NULL, 16);
+ width = simple_strtoul(argv[3], NULL, 10);
+ if (width == 48 || width == 64)
+ value64 = simple_strtoull(argv[4], NULL, 16);
+ else
+ value = simple_strtoul(argv[4], NULL, 16);
+
+ switch (width) {
+ case 8:
+ ret = b53_mdio_write8(bus, page, offset, value & 0xff);
+ break;
+ case 16:
+ ret = b53_mdio_write16(bus, page, offset, value);
+ break;
+ case 32:
+ ret = b53_mdio_write32(bus, page, offset, value);
+ break;
+ case 48:
+ ret = b53_mdio_write48(bus, page, offset, value64);
+ break;
+ case 64:
+ ret = b53_mdio_write64(bus, page, offset, value64);
+ break;
+ default:
+ printf("Unsupported width: %d\n", width);
+ break;
+ }
+
+ return ret;
+}
+
+int do_b53_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *cmd, *mdioname;
+ int ret = 0;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ cmd = argv[1];
+ --argc;
+ ++argv;
+
+ if (!strcmp(cmd, "write")) {
+ if (argc < 4)
+ return cmd_usage(cmdtp);
+ mdioname = argv[1];
+ --argc;
+ ++argv;
+ ret = do_b53_reg_write(mdioname, argc, argv);
+ } else if (!strcmp(cmd, "read")) {
+ if (argc < 5)
+ return cmd_usage(cmdtp);
+ mdioname = argv[1];
+ --argc;
+ ++argv;
+ ret = do_b53_reg_read(mdioname, argc, argv);
+ } else {
+ return cmd_usage(cmdtp);
+ }
+
+ return ret;
+}
+
+U_BOOT_CMD(b53_reg, 7, 1, do_b53_reg,
+ "Broadcom B53 switch register access",
+ "write mdioname page (hex) offset (hex) width (dec) value (hex)\n"
+ "read mdioname page (hex) offset (hex) width (dec)\n"
+ );
#define MIIM_88E151x_MODE_SGMII 1
#define MIIM_88E151x_RESET_OFFS 15
+static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
+ int devaddr, int regnum)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
+ int val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
+
+ return val;
+}
+
+static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr,
+ int devaddr, int regnum, u16 val)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
+ phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
+
+ return 0;
+}
+
/* Marvell 88E1011S */
static int m88e1011s_config(struct phy_device *phydev)
{
.config = &m88e1510_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
+ .readext = &m88e1xxx_phy_extread,
+ .writeext = &m88e1xxx_phy_extwrite,
};
/*
.config = &m88e1518_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
+ .readext = &m88e1xxx_phy_extread,
+ .writeext = &m88e1xxx_phy_extwrite,
};
static struct phy_driver M88E1310_driver = {
*/
int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
{
- short rdreg; /* register working value */
+ unsigned short rdreg; /* register working value */
int v;
int j; /* counter */
struct bb_miiphy_bus *bus;
int phy_init(void)
{
+#ifdef CONFIG_B53_SWITCH
+ phy_b53_init();
+#endif
#ifdef CONFIG_MV88E61XX_SWITCH
phy_mv88e61xx_init();
#endif
#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
- flush_dcache_range((u32)addr, (u32)(addr + len - 1))
+ flush_dcache_range((u32)addr, \
+ (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
#else
#define flush_cache_wback(...)
#endif
/* packet must be a 4 byte boundary */
if ((int)packet & 3) {
- printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n"
+ printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
, __func__);
ret = -EFAULT;
goto err;
flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
/* Restart the transmitter if disabled */
- if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
- sh_eth_write(eth, EDTRR_TRNS, EDTRR);
+ if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
+ sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
/* Wait until packet is transmitted */
timeout = TIMEOUT_CNT;
}
/* Restart the receiver if disabled */
- if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
- sh_eth_write(eth, EDRRR_R, EDRRR);
+ if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
+ sh_eth_write(port_info, EDRRR_R, EDRRR);
return len;
}
static int sh_eth_reset(struct sh_eth_dev *eth)
{
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
- sh_eth_write(eth, EDSR_ENALL, EDSR);
+ sh_eth_write(port_info, EDSR_ENALL, EDSR);
/* Perform a software reset and wait for it to complete */
- sh_eth_write(eth, EDMR_SRST, EDMR);
+ sh_eth_write(port_info, EDMR_SRST, EDMR);
for (i = 0; i < TIMEOUT_CNT; i++) {
- if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
+ if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
break;
udelay(1000);
}
return ret;
#else
- sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
+ sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
udelay(3000);
- sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
return 0;
#endif
goto err;
}
- flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
+ flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base =
cur_tx_desc--;
cur_tx_desc->td0 |= TD_TDLE;
- /* Point the controller to the tx descriptor list. Must use physical
- addresses */
- sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
+ /*
+ * Point the controller to the tx descriptor list. Must use physical
+ * addresses
+ */
+ sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
- sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
- sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
- sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
+ sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
+ sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
+ sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
#endif
err:
static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
{
- int port = eth->port, i , ret = 0;
+ int port = eth->port, i, ret = 0;
u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
struct sh_eth_info *port_info = ð->port_info[port];
struct rx_desc_s *cur_rx_desc;
i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
cur_rx_desc->rd0 = RD_RACT;
cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
- cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
+ cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
}
/* Mark the end of the descriptors */
cur_rx_desc->rd0 |= RD_RDLE;
/* Point the controller to the rx descriptor list */
- sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
+ sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
- sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
- sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
- sh_eth_write(eth, RDFFR_RDLF, RDFFR);
+ sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
+ sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
+ sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
#endif
return ret;
return ret;
}
-static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
+static int sh_eth_config(struct sh_eth_dev *eth)
{
int port = eth->port, ret = 0;
u32 val;
struct phy_device *phy;
/* Configure e-dmac registers */
- sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
+ sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
(EMDR_DESC | EDMR_EL), EDMR);
- sh_eth_write(eth, 0, EESIPR);
- sh_eth_write(eth, 0, TRSCER);
- sh_eth_write(eth, 0, TFTR);
- sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
- sh_eth_write(eth, RMCR_RST, RMCR);
+ sh_eth_write(port_info, 0, EESIPR);
+ sh_eth_write(port_info, 0, TRSCER);
+ sh_eth_write(port_info, 0, TFTR);
+ sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
+ sh_eth_write(port_info, RMCR_RST, RMCR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
- sh_eth_write(eth, 0, RPADIR);
+ sh_eth_write(port_info, 0, RPADIR);
#endif
- sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
+ sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
/* Configure e-mac registers */
- sh_eth_write(eth, 0, ECSIPR);
+ sh_eth_write(port_info, 0, ECSIPR);
/* Set Mac address */
val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
dev->enetaddr[2] << 8 | dev->enetaddr[3];
- sh_eth_write(eth, val, MAHR);
+ sh_eth_write(port_info, val, MAHR);
val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
- sh_eth_write(eth, val, MALR);
+ sh_eth_write(port_info, val, MALR);
- sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
+ sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
- sh_eth_write(eth, 0, PIPR);
+ sh_eth_write(port_info, 0, PIPR);
#endif
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
- sh_eth_write(eth, APR_AP, APR);
- sh_eth_write(eth, MPR_MP, MPR);
- sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
+ sh_eth_write(port_info, APR_AP, APR);
+ sh_eth_write(port_info, MPR_MP, MPR);
+ sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
#endif
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
- sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
+ sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
- sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
+ sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
if (phy->speed == 100) {
printf(SHETHER_NAME ": 100Base/");
#if defined(SH_ETH_TYPE_GETHER)
- sh_eth_write(eth, GECMR_100B, GECMR);
+ sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
- sh_eth_write(eth, 1, RTRATE);
+ sh_eth_write(port_info, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
defined(CONFIG_R8A7794)
} else if (phy->speed == 10) {
printf(SHETHER_NAME ": 10Base/");
#if defined(SH_ETH_TYPE_GETHER)
- sh_eth_write(eth, GECMR_10B, GECMR);
+ sh_eth_write(port_info, GECMR_10B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
- sh_eth_write(eth, 0, RTRATE);
+ sh_eth_write(port_info, 0, RTRATE);
#endif
}
#if defined(SH_ETH_TYPE_GETHER)
else if (phy->speed == 1000) {
printf(SHETHER_NAME ": 1000Base/");
- sh_eth_write(eth, GECMR_1000B, GECMR);
+ sh_eth_write(port_info, GECMR_1000B, GECMR);
}
#endif
/* Check if full duplex mode is supported by the phy */
if (phy->duplex) {
printf("Full\n");
- sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
+ sh_eth_write(port_info,
+ val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
ECMR);
} else {
printf("Half\n");
- sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
+ sh_eth_write(port_info,
+ val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
+ ECMR);
}
return ret;
static void sh_eth_start(struct sh_eth_dev *eth)
{
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
/*
* Enable the e-dmac receiver only. The transmitter will be enabled when
* we have something to transmit
*/
- sh_eth_write(eth, EDRRR_R, EDRRR);
+ sh_eth_write(port_info, EDRRR_R, EDRRR);
}
static void sh_eth_stop(struct sh_eth_dev *eth)
{
- sh_eth_write(eth, ~EDRRR_R, EDRRR);
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
+ sh_eth_write(port_info, ~EDRRR_R, EDRRR);
}
int sh_eth_init(struct eth_device *dev, bd_t *bd)
if (ret)
goto err;
- ret = sh_eth_config(eth, bd);
+ ret = sh_eth_config(eth);
if (ret)
goto err_config;
void sh_eth_halt(struct eth_device *dev)
{
struct sh_eth_dev *eth = dev->priv;
+
sh_eth_stop(eth);
}
int ret = 0;
struct sh_eth_dev *eth = NULL;
struct eth_device *dev = NULL;
+ struct mii_dev *mdiodev;
eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
if (!eth) {
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
+ eth->port_info[eth->port].iobase =
+ (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
dev->priv = (void *)eth;
dev->iobase = 0;
eth_register(dev);
bb_miiphy_buses[0].priv = eth;
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
+ mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
+ ret = mdio_register(mdiodev);
+ if (ret < 0)
+ return ret;
if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
puts("Please set MAC address\n");
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
- sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
+ sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
return 0;
}
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
- sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
+ sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
return 0;
}
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
if (v)
- sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
else
- sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
return 0;
}
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
- *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
+ *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
return 0;
}
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
if (v)
- sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
else
- sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
return 0;
}
.delay = sh_eth_bb_delay,
}
};
+
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
#endif
#elif defined(CONFIG_ARM)
-#define inl readl
+#ifndef inl
+#define inl readl
#define outl writel
+#endif
#define ADDR_TO_PHY(addr) ((int)(addr))
#define ADDR_TO_P2(addr) (addr)
#endif /* defined(CONFIG_SH) */
u8 phy_addr;
struct eth_device *dev;
struct phy_device *phydev;
+ void __iomem *iobase;
};
struct sh_eth_dev {
[RMII_MII] = 0x0790,
};
-#if defined(SH_ETH_TYPE_RZ)
-static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
- [EDSR] = 0x0000,
- [EDMR] = 0x0400,
- [EDTRR] = 0x0408,
- [EDRRR] = 0x0410,
- [EESR] = 0x0428,
- [EESIPR] = 0x0430,
- [TDLAR] = 0x0010,
- [TDFAR] = 0x0014,
- [TDFXR] = 0x0018,
- [TDFFR] = 0x001c,
- [RDLAR] = 0x0030,
- [RDFAR] = 0x0034,
- [RDFXR] = 0x0038,
- [RDFFR] = 0x003c,
- [TRSCER] = 0x0438,
- [RMFCR] = 0x0440,
- [TFTR] = 0x0448,
- [FDR] = 0x0450,
- [RMCR] = 0x0458,
- [RPADIR] = 0x0460,
- [FCFTR] = 0x0468,
- [CSMR] = 0x04E4,
-
- [ECMR] = 0x0500,
- [ECSR] = 0x0510,
- [ECSIPR] = 0x0518,
- [PSR] = 0x0528,
- [PIPR] = 0x052c,
- [RFLR] = 0x0508,
- [APR] = 0x0554,
- [MPR] = 0x0558,
- [PFTCR] = 0x055c,
- [PFRCR] = 0x0560,
- [TPAUSER] = 0x0564,
- [GECMR] = 0x05b0,
- [BCULR] = 0x05b4,
- [MAHR] = 0x05c0,
- [MALR] = 0x05c8,
- [TROCR] = 0x0700,
- [CDCR] = 0x0708,
- [LCCR] = 0x0710,
- [CEFCR] = 0x0740,
- [FRECR] = 0x0748,
- [TSFRCR] = 0x0750,
- [TLFRCR] = 0x0758,
- [RFCR] = 0x0760,
- [CERCR] = 0x0768,
- [CEECR] = 0x0770,
- [MAFCR] = 0x0778,
- [RMII_MII] = 0x0790,
-};
-#endif
-
static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[ECMR] = 0x0100,
[RFLR] = 0x0108,
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
};
-static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
+static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
int enum_index)
{
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
const u16 *reg_offset = sh_eth_offset_gigabit;
#elif defined(SH_ETH_TYPE_ETHER)
const u16 *reg_offset = sh_eth_offset_fast_sh4;
-#elif defined(SH_ETH_TYPE_RZ)
- const u16 *reg_offset = sh_eth_offset_rz;
#else
#error
#endif
- return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
+ return (unsigned long)port->iobase + reg_offset[enum_index];
}
-static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
+static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
int enum_index)
{
- outl(data, sh_eth_reg_addr(eth, enum_index));
+ outl(data, sh_eth_reg_addr(port, enum_index));
}
-static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
+static inline unsigned long sh_eth_read(struct sh_eth_info *port,
int enum_index)
{
- return inl(sh_eth_reg_addr(eth, enum_index));
+ return inl(sh_eth_reg_addr(port, enum_index));
}
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
-obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
__weak int imx6_pcie_toggle_power(void)
{
#ifdef CONFIG_PCIE_IMX_POWER_GPIO
+ gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
mdelay(20);
gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
mdelay(20);
+ gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
#endif
return 0;
}
* state due to being previously used in U-Boot.
*/
#ifdef CONFIG_PCIE_IMX_PERST_GPIO
+ gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
mdelay(20);
gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
mdelay(20);
+ gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
#else
puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
#endif
imx_pcie_regions_setup();
+ /*
+ * By default, the subordinate is set equally to the secondary
+ * bus (0x01) when the RC boots.
+ * This means that theoretically, only bus 1 is reachable from the RC.
+ * Force the PCIe RC subordinate to 0xff, otherwise no downstream
+ * devices will be detected if the enumeration is applied strictly.
+ */
+ tmp = readl(MX6_DBI_ADDR + 0x18);
+ tmp |= (0xff << 16);
+ writel(tmp, MX6_DBI_ADDR + 0x18);
+
/*
* FIXME: Force the PCIe RC to Gen1 operation
* The RC must be forced into Gen1 mode before bringing the link
+++ /dev/null
-/*
- * (C) Copyright 2004 Tundra Semiconductor Corp.
- * Alex Bounine <alexandreb@tundra.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * PCI initialisation for the Tsi108 EMU board.
- */
-
-#include <config.h>
-
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <tsi108.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-struct pci_controller local_hose;
-
-void tsi108_clear_pci_error (void)
-{
- u32 err_stat, err_addr, pci_stat;
-
- /*
- * Quietly clear errors signalled as result of PCI/X configuration read
- * requests.
- */
- /* Read PB Error Log Registers */
- err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_ERRCS);
- err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_AERR);
- if (err_stat & PB_ERRCS_ES) {
- /* Clear PCI/X bus errors if applicable */
- if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) {
- /* Clear error flag */
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_ERRCS) =
- PB_ERRCS_ES;
-
- /* Clear read error reported in PB_ISR */
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PB_REG_OFFSET + PB_ISR) =
- PB_ISR_PBS_RD_ERR;
-
- /* Clear errors reported by PCI CSR (Normally Master Abort) */
- pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET +
- PCI_CSR);
- *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET + PCI_CSR) =
- pci_stat;
-
- *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET +
- PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
- }
- }
-
- return;
-}
-
-unsigned int __get_pci_config_dword (u32 addr)
-{
- unsigned int retval;
-
- __asm__ __volatile__ (" lwbrx %0,0,%1\n"
- "1: eieio\n"
- "2:\n"
- ".section .fixup,\"ax\"\n"
- "3: li %0,-1\n"
- " b 2b\n"
- ".section __ex_table,\"a\"\n"
- " .align 2\n"
- " .long 1b,3b\n"
- ".section .text.__get_pci_config_dword"
- : "=r"(retval) : "r"(addr));
-
- return (retval);
-}
-
-static int tsi108_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
-{
- dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
- dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
- *value = __get_pci_config_dword(dev);
- if (0xFFFFFFFF == *value)
- tsi108_clear_pci_error ();
- return 0;
-}
-
-static int tsi108_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
-{
- dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
- dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
-
- out_le32 ((volatile unsigned *)dev, value);
-
- return 0;
-}
-
-void pci_init_board (void)
-{
- struct pci_controller *hose = (struct pci_controller *)&local_hose;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- pci_set_region (hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region (hose->regions + 1,
- CONFIG_SYS_PCI_MEM_BUS,
- CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (hose->regions + 2,
- CONFIG_SYS_PCI_IO_BUS,
- CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
- hose->region_count = 3;
-
- pci_set_ops (hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- tsi108_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- tsi108_write_config_dword);
-
- pci_register_hose (hose);
-
- hose->last_busno = pci_hose_scan (hose);
-
- debug ("Done PCI initialization\n");
- return;
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(local_hose.first_busno);
- tmp[1] = cpu_to_be32(local_hose.last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
- }
- }
-}
-#endif /* CONFIG_OF_LIBFDT */
if ARCH_MVEBU
config PINCTRL_ARMADA_37XX
- depends on ARMADA_3700
+ depends on ARMADA_3700 && PINCTRL_FULL
bool "Armada 37xx pin control driver"
help
Support pin multiplexing and pin configuration control on
Marvell's Armada-37xx SoC.
config PINCTRL_ARMADA_8K
- depends on ARMADA_8K
+ depends on ARMADA_8K && PINCTRL_FULL
bool "Armada 7k/8k pin control driver"
help
Support pin multiplexing and pin configuration control on
};
static const struct udevice_id stm32_pinctrl_ids[] = {
+ { .compatible = "st,stm32f429-pinctrl" },
+ { .compatible = "st,stm32f469-pinctrl" },
{ .compatible = "st,stm32f746-pinctrl" },
{ .compatible = "st,stm32h743-pinctrl" },
{ }
DECLARE_GLOBAL_DATA_PTR;
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = S2MPS11_OF_LDO_PREFIX, .driver = S2MPS11_LDO_DRIVER },
+ { .prefix = S2MPS11_OF_BUCK_PREFIX, .driver = S2MPS11_BUCK_DRIVER },
+ { },
+};
+
static int s2mps11_reg_count(struct udevice *dev)
{
return S2MPS11_REG_COUNT;
return ret;
}
+static int s2mps11_probe(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ regulators_node = dev_read_subnode(dev, "voltage-regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found!", __func__,
+ dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+
+ return 0;
+}
+
static struct dm_pmic_ops s2mps11_ops = {
.reg_count = s2mps11_reg_count,
.read = s2mps11_read,
.id = UCLASS_PMIC,
.of_match = s2mps11_ids,
.ops = &s2mps11_ops,
+ .probe = s2mps11_probe,
};
return 0;
}
-static void pmic_show_info(struct pmic *p)
-{
- printf("PMIC: %s\n", p->name);
-}
-
-static int pmic_dump(struct pmic *p)
-{
- int i, ret;
- u32 val;
-
- if (!p) {
- puts("Wrong PMIC name!\n");
- return -ENODEV;
- }
-
- pmic_show_info(p);
- for (i = 0; i < p->number_of_regs; i++) {
- ret = pmic_reg_read(p, i, &val);
- if (ret)
- puts("PMIC: Registers dump failed\n");
-
- if (!(i % 8))
- printf("\n0x%02x: ", i);
-
- printf("%08x ", val);
- }
- puts("\n");
- return 0;
-}
-
struct pmic *pmic_alloc(void)
{
struct pmic *p;
return NULL;
}
-const char *power_get_interface(int interface)
+#ifndef CONFIG_SPL_BUILD
+static int pmic_dump(struct pmic *p)
+{
+ int i, ret;
+ u32 val;
+
+ if (!p) {
+ puts("Wrong PMIC name!\n");
+ return -ENODEV;
+ }
+
+ printf("PMIC: %s\n", p->name);
+ for (i = 0; i < p->number_of_regs; i++) {
+ ret = pmic_reg_read(p, i, &val);
+ if (ret)
+ puts("PMIC: Registers dump failed\n");
+
+ if (!(i % 8))
+ printf("\n0x%02x: ", i);
+
+ printf("%08x ", val);
+ }
+ puts("\n");
+ return 0;
+}
+
+static const char *power_get_interface(int interface)
{
const char *power_interface[] = {"I2C", "SPI", "|+|-|"};
return power_interface[interface];
}
}
-int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 ret, reg, val;
char *cmd, *name;
"pmic name bat state - write register\n"
"pmic name bat charge - write register\n"
);
+#endif
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
+config DM_REGULATOR_S2MPS11
+ bool "Enable driver for S2MPS11 regulator"
+ depends on DM_REGULATOR && PMIC_S2MPS11
+ ---help---
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR S2MPS11.
+ The driver implements get/set api for: value and enable.
+
config REGULATOR_S5M8767
bool "Enable support for S5M8767 regulator"
depends on DM_REGULATOR && PMIC_S5M8767
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o
+obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
--- /dev/null
+/*
+ * Copyright (C) 2018 Samsung Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/s2mps11.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MODE(_id, _val, _name) { \
+ .id = _id, \
+ .register_value = _val, \
+ .name = _name, \
+}
+
+/* BUCK : 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 */
+static struct dm_regulator_mode s2mps11_buck_modes[] = {
+ MODE(OP_OFF, S2MPS11_BUCK_MODE_OFF, "OFF"),
+ MODE(OP_STANDBY, S2MPS11_BUCK_MODE_STANDBY, "ON/OFF"),
+ MODE(OP_ON, S2MPS11_BUCK_MODE_STANDBY, "ON"),
+};
+
+static struct dm_regulator_mode s2mps11_ldo_modes[] = {
+ MODE(OP_OFF, S2MPS11_LDO_MODE_OFF, "OFF"),
+ MODE(OP_STANDBY, S2MPS11_LDO_MODE_STANDBY, "ON/OFF"),
+ MODE(OP_STANDBY_LPM, S2MPS11_LDO_MODE_STANDBY_LPM, "ON/LPM"),
+ MODE(OP_ON, S2MPS11_LDO_MODE_ON, "ON"),
+};
+
+static const char s2mps11_buck_ctrl[] = {
+ 0xff, 0x25, 0x27, 0x29, 0x2b, 0x2d, 0x33, 0x35, 0x37, 0x39, 0x3b
+};
+
+static const char s2mps11_buck_out[] = {
+ 0xff, 0x26, 0x28, 0x2a, 0x2c, 0x2f, 0x34, 0x36, 0x38, 0x3a, 0x3c
+};
+
+static int s2mps11_buck_hex2volt(int buck, int hex)
+{
+ unsigned int uV = 0;
+
+ if (hex < 0)
+ goto bad;
+
+ switch (buck) {
+ case 7:
+ case 8:
+ case 10:
+ if (hex > S2MPS11_BUCK7_8_10_VOLT_MAX_HEX)
+ goto bad;
+
+ uV = hex * S2MPS11_BUCK_HSTEP + S2MPS11_BUCK_UV_HMIN;
+ break;
+ case 9:
+ if (hex > S2MPS11_BUCK9_VOLT_MAX_HEX)
+ goto bad;
+ uV = hex * S2MPS11_BUCK9_STEP * 2 + S2MPS11_BUCK9_UV_MIN;
+ break;
+ default:
+ if (buck == 5 && hex > S2MPS11_BUCK5_VOLT_MAX_HEX)
+ goto bad;
+ else if (buck != 5 && hex > S2MPS11_BUCK_VOLT_MAX_HEX)
+ goto bad;
+
+ uV = hex * S2MPS11_BUCK_LSTEP + S2MPS11_BUCK_UV_MIN;
+ break;
+ }
+
+ return uV;
+bad:
+ pr_err("Value: %#x is wrong for BUCK%d", hex, buck);
+ return -EINVAL;
+}
+
+static int s2mps11_buck_volt2hex(int buck, int uV)
+{
+ int hex;
+
+ switch (buck) {
+ case 7:
+ case 8:
+ case 10:
+ hex = (uV - S2MPS11_BUCK_UV_HMIN) / S2MPS11_BUCK_HSTEP;
+ if (hex > S2MPS11_BUCK7_8_10_VOLT_MAX_HEX)
+ goto bad;
+
+ break;
+ case 9:
+ hex = (uV - S2MPS11_BUCK9_UV_MIN) / S2MPS11_BUCK9_STEP;
+ if (hex > S2MPS11_BUCK9_VOLT_MAX_HEX)
+ goto bad;
+ break;
+ default:
+ hex = (uV - S2MPS11_BUCK_UV_MIN) / S2MPS11_BUCK_LSTEP;
+ if (buck == 5 && hex > S2MPS11_BUCK5_VOLT_MAX_HEX)
+ goto bad;
+ else if (buck != 5 && hex > S2MPS11_BUCK_VOLT_MAX_HEX)
+ goto bad;
+ break;
+ };
+
+ if (hex >= 0)
+ return hex;
+
+bad:
+ pr_err("Value: %d uV is wrong for BUCK%d", uV, buck);
+ return -EINVAL;
+}
+
+static int s2mps11_buck_val(struct udevice *dev, int op, int *uV)
+{
+ int hex, buck, ret;
+ u32 mask, addr;
+ u8 val;
+
+ buck = dev->driver_data;
+ if (buck < 1 || buck > S2MPS11_BUCK_NUM) {
+ pr_err("Wrong buck number: %d\n", buck);
+ return -EINVAL;
+ }
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ addr = s2mps11_buck_out[buck];
+
+ switch (buck) {
+ case 9:
+ mask = S2MPS11_BUCK9_VOLT_MASK;
+ break;
+ default:
+ mask = S2MPS11_BUCK_VOLT_MASK;
+ break;
+ }
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ val &= mask;
+ ret = s2mps11_buck_hex2volt(buck, val);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+ return 0;
+ }
+
+ hex = s2mps11_buck_volt2hex(buck, *uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~mask;
+ val |= hex;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_buck_mode(struct udevice *dev, int op, int *opmode)
+{
+ unsigned int addr, mode;
+ unsigned char val;
+ int buck, ret;
+
+ buck = dev->driver_data;
+ if (buck < 1 || buck > S2MPS11_BUCK_NUM) {
+ pr_err("Wrong buck number: %d\n", buck);
+ return -EINVAL;
+ }
+
+ addr = s2mps11_buck_ctrl[buck];
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ val &= (S2MPS11_BUCK_MODE_MASK << S2MPS11_BUCK_MODE_SHIFT);
+ switch (val) {
+ case S2MPS11_BUCK_MODE_OFF:
+ *opmode = OP_OFF;
+ break;
+ case S2MPS11_BUCK_MODE_STANDBY:
+ *opmode = OP_STANDBY;
+ break;
+ case S2MPS11_BUCK_MODE_ON:
+ *opmode = OP_ON;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ switch (*opmode) {
+ case OP_OFF:
+ mode = S2MPS11_BUCK_MODE_OFF;
+ break;
+ case OP_STANDBY:
+ mode = S2MPS11_BUCK_MODE_STANDBY;
+ break;
+ case OP_ON:
+ mode = S2MPS11_BUCK_MODE_ON;
+ break;
+ default:
+ pr_err("Wrong mode: %d for buck: %d\n", *opmode, buck);
+ return -EINVAL;
+ }
+
+ val &= ~(S2MPS11_BUCK_MODE_MASK << S2MPS11_BUCK_MODE_SHIFT);
+ val |= mode;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret, on_off;
+
+ if (op == PMIC_OP_GET) {
+ ret = s2mps11_buck_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ switch (on_off) {
+ case OP_OFF:
+ *enable = false;
+ break;
+ case OP_ON:
+ *enable = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ on_off = OP_ON;
+ else
+ on_off = OP_OFF;
+
+ ret = s2mps11_buck_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int buck_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = s2mps11_buck_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+ return uV;
+}
+
+static int buck_set_value(struct udevice *dev, int uV)
+{
+ return s2mps11_buck_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int buck_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = s2mps11_buck_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+ return enable;
+}
+
+static int buck_set_enable(struct udevice *dev, bool enable)
+{
+ return s2mps11_buck_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int buck_get_mode(struct udevice *dev)
+{
+ int mode;
+ int ret;
+
+ ret = s2mps11_buck_mode(dev, PMIC_OP_GET, &mode);
+ if (ret)
+ return ret;
+
+ return mode;
+}
+
+static int buck_set_mode(struct udevice *dev, int mode)
+{
+ return s2mps11_buck_mode(dev, PMIC_OP_SET, &mode);
+}
+
+static int s2mps11_buck_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+ uc_pdata->mode = s2mps11_buck_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(s2mps11_buck_modes);
+
+ return 0;
+}
+
+static const struct dm_regulator_ops s2mps11_buck_ops = {
+ .get_value = buck_get_value,
+ .set_value = buck_set_value,
+ .get_enable = buck_get_enable,
+ .set_enable = buck_set_enable,
+ .get_mode = buck_get_mode,
+ .set_mode = buck_set_mode,
+};
+
+U_BOOT_DRIVER(s2mps11_buck) = {
+ .name = S2MPS11_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &s2mps11_buck_ops,
+ .probe = s2mps11_buck_probe,
+};
+
+static int s2mps11_ldo_hex2volt(int ldo, int hex)
+{
+ unsigned int uV = 0;
+
+ if (hex > S2MPS11_LDO_VOLT_MAX_HEX) {
+ pr_err("Value: %#x is wrong for LDO%d", hex, ldo);
+ return -EINVAL;
+ }
+
+ switch (ldo) {
+ case 1:
+ case 6:
+ case 11:
+ case 22:
+ case 23:
+ uV = hex * S2MPS11_LDO_STEP + S2MPS11_LDO_UV_MIN;
+ break;
+ default:
+ uV = hex * S2MPS11_LDO_STEP * 2 + S2MPS11_LDO_UV_MIN;
+ break;
+ }
+
+ return uV;
+}
+
+static int s2mps11_ldo_volt2hex(int ldo, int uV)
+{
+ int hex = 0;
+
+ switch (ldo) {
+ case 1:
+ case 6:
+ case 11:
+ case 22:
+ case 23:
+ hex = (uV - S2MPS11_LDO_UV_MIN) / S2MPS11_LDO_STEP;
+ break;
+ default:
+ hex = (uV - S2MPS11_LDO_UV_MIN) / (S2MPS11_LDO_STEP * 2);
+ break;
+ }
+
+ if (hex >= 0 && hex <= S2MPS11_LDO_VOLT_MAX_HEX)
+ return hex;
+
+ pr_err("Value: %d uV is wrong for LDO%d", uV, ldo);
+ return -EINVAL;
+
+ return 0;
+}
+
+static int s2mps11_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int addr;
+ unsigned char val;
+ int hex, ldo, ret;
+
+ ldo = dev->driver_data;
+ if (ldo < 1 || ldo > S2MPS11_LDO_NUM) {
+ pr_err("Wrong ldo number: %d\n", ldo);
+ return -EINVAL;
+ }
+
+ addr = S2MPS11_REG_L1CTRL + ldo - 1;
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+ val &= S2MPS11_LDO_VOLT_MASK;
+ ret = s2mps11_ldo_hex2volt(ldo, val);
+ if (ret < 0)
+ return ret;
+
+ *uV = ret;
+ return 0;
+ }
+
+ hex = s2mps11_ldo_volt2hex(ldo, *uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~S2MPS11_LDO_VOLT_MASK;
+ val |= hex;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_ldo_mode(struct udevice *dev, int op, int *opmode)
+{
+ unsigned int addr, mode;
+ unsigned char val;
+ int ldo, ret;
+
+ ldo = dev->driver_data;
+ if (ldo < 1 || ldo > S2MPS11_LDO_NUM) {
+ pr_err("Wrong ldo number: %d\n", ldo);
+ return -EINVAL;
+ }
+ addr = S2MPS11_REG_L1CTRL + ldo - 1;
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ val &= (S2MPS11_LDO_MODE_MASK << S2MPS11_LDO_MODE_SHIFT);
+ switch (val) {
+ case S2MPS11_LDO_MODE_OFF:
+ *opmode = OP_OFF;
+ break;
+ case S2MPS11_LDO_MODE_STANDBY:
+ *opmode = OP_STANDBY;
+ break;
+ case S2MPS11_LDO_MODE_STANDBY_LPM:
+ *opmode = OP_STANDBY_LPM;
+ break;
+ case S2MPS11_LDO_MODE_ON:
+ *opmode = OP_ON;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ switch (*opmode) {
+ case OP_OFF:
+ mode = S2MPS11_LDO_MODE_OFF;
+ break;
+ case OP_STANDBY:
+ mode = S2MPS11_LDO_MODE_STANDBY;
+ break;
+ case OP_STANDBY_LPM:
+ mode = S2MPS11_LDO_MODE_STANDBY_LPM;
+ break;
+ case OP_ON:
+ mode = S2MPS11_LDO_MODE_ON;
+ break;
+ default:
+ pr_err("Wrong mode: %d for ldo: %d\n", *opmode, ldo);
+ return -EINVAL;
+ }
+
+ val &= ~(S2MPS11_LDO_MODE_MASK << S2MPS11_LDO_MODE_SHIFT);
+ val |= mode;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_ldo_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret, on_off;
+
+ if (op == PMIC_OP_GET) {
+ ret = s2mps11_ldo_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ switch (on_off) {
+ case OP_OFF:
+ *enable = false;
+ break;
+ case OP_ON:
+ *enable = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ on_off = OP_ON;
+ else
+ on_off = OP_OFF;
+
+ ret = s2mps11_ldo_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = s2mps11_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return s2mps11_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int ldo_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = s2mps11_ldo_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+ return enable;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ return s2mps11_ldo_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int ldo_get_mode(struct udevice *dev)
+{
+ int mode, ret;
+
+ ret = s2mps11_ldo_mode(dev, PMIC_OP_GET, &mode);
+ if (ret)
+ return ret;
+ return mode;
+}
+
+static int ldo_set_mode(struct udevice *dev, int mode)
+{
+ return s2mps11_ldo_mode(dev, PMIC_OP_SET, &mode);
+}
+
+static int s2mps11_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+ uc_pdata->mode = s2mps11_ldo_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(s2mps11_ldo_modes);
+
+ return 0;
+}
+
+static const struct dm_regulator_ops s2mps11_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+ .get_mode = ldo_get_mode,
+ .set_mode = ldo_set_mode,
+};
+
+U_BOOT_DRIVER(s2mps11_ldo) = {
+ .name = S2MPS11_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &s2mps11_ldo_ops,
+ .probe = s2mps11_ldo_probe,
+};
#include <ram.h>
#include <asm/io.h>
+#define MEM_MODE_MASK GENMASK(2, 0)
+#define NOT_FOUND 0xff
+
DECLARE_GLOBAL_DATA_PTR;
struct stm32_fmc_regs {
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
struct bank_params *bank_params;
+ struct ofnode_phandle_args args;
+ u32 *syscfg_base;
+ u32 mem_remap;
ofnode bank_node;
char *bank_name;
u8 bank = 0;
+ int ret;
+
+ mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
+ if (mem_remap != NOT_FOUND) {
+ ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ &args);
+ if (ret) {
+ debug("%s: can't find syscon device (%d)\n", __func__,
+ ret);
+ return ret;
+ }
+
+ syscfg_base = (u32 *)ofnode_get_addr(args.node);
+
+ /* set memory mapping selection */
+ clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
+ } else {
+ debug("%s: cannot find st,mem_remap property\n", __func__);
+ }
dev_for_each_subnode(bank_node, dev) {
/* extract the bank index from DT */
on STiH410 SoC. This is a basic implementation, it supports
following baudrate 9600, 19200, 38400, 57600 and 115200.
-config STM32X7_SERIAL
+config STM32_SERIAL
bool "STMicroelectronics STM32 SoCs on-chip UART"
depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
help
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o
obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
-obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
+obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
lpuart_read32(plat->flags, &base->data, &val);
- if (plat->devtype & DEV_MX7ULP) {
- lpuart_read32(plat->flags, &base->stat, &stat);
- if (stat & STAT_OR)
- lpuart_write32(plat->flags, &base->stat, STAT_OR);
- }
+ lpuart_read32(plat->flags, &base->stat, &stat);
+ if (stat & STAT_OR)
+ lpuart_write32(plat->flags, &base->stat, STAT_OR);
return val & 0x3ff;
}
struct lpuart_fsl_reg32 *base = plat->reg;
u32 stat;
- if (plat->devtype & DEV_MX7ULP) {
- if (c == '\n')
- serial_putc('\r');
- }
+ if (c == '\n')
+ serial_putc('\r');
while (true) {
lpuart_read32(plat->flags, &base->stat, &stat);
lpuart_write32(plat->flags, &base->match, 0);
- if (plat->devtype & DEV_MX7ULP) {
+ if (plat->devtype == DEV_MX7ULP) {
_lpuart32_serial_setbrg_7ulp(plat, gd->baudrate);
} else {
/* provide data bits, parity, stop bit, etc */
struct lpuart_serial_platdata *plat = dev->platdata;
if (is_lpuart32(dev)) {
- if (plat->devtype & DEV_MX7ULP)
+ if (plat->devtype == DEV_MX7ULP)
_lpuart32_serial_setbrg_7ulp(plat, baudrate);
else
_lpuart32_serial_setbrg(plat, baudrate);
/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <asm/io.h>
#include <serial.h>
#include <asm/arch/stm32.h>
-#include <dm/platform_data/serial_stm32.h>
-
-struct stm32_usart {
- u32 sr;
- u32 dr;
- u32 brr;
- u32 cr1;
- u32 cr2;
- u32 cr3;
- u32 gtpr;
-};
-
-#define USART_CR1_RE (1 << 2)
-#define USART_CR1_TE (1 << 3)
-#define USART_CR1_UE (1 << 13)
-
-#define USART_SR_FLAG_RXNE (1 << 5)
-#define USART_SR_FLAG_TXE (1 << 7)
-
-#define USART_BRR_F_MASK 0xF
-#define USART_BRR_M_SHIFT 4
-#define USART_BRR_M_MASK 0xFFF0
+#include "serial_stm32.h"
DECLARE_GLOBAL_DATA_PTR;
static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
- u32 clock, int_div, frac_div, tmp;
-
- if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE)
- clock = clock_get(CLOCK_APB1);
- else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE)
- clock = clock_get(CLOCK_APB2);
- else
- return -EINVAL;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
+ u32 int_div, mantissa, fraction, oversampling;
+
+ int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
+
+ if (int_div < 16) {
+ oversampling = 8;
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
+ } else {
+ oversampling = 16;
+ clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
+ }
+
+ mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
+ fraction = int_div % oversampling;
- int_div = (25 * clock) / (4 * baudrate);
- tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK;
- frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT));
- tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK;
- writel(tmp, &usart->brr);
+ writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
return 0;
}
static int stm32_serial_getc(struct udevice *dev)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
- if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
+ if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
return -EAGAIN;
- return readl(&usart->dr);
+ return readl(base + RDR_OFFSET(stm32f4));
}
static int stm32_serial_putc(struct udevice *dev, const char c)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
- if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
+ if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
return -EAGAIN;
- writel(c, &usart->dr);
+ writel(c, base + TDR_OFFSET(stm32f4));
return 0;
}
static int stm32_serial_pending(struct udevice *dev, bool input)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
if (input)
- return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
+ return readl(base + ISR_OFFSET(stm32f4)) &
+ USART_SR_FLAG_RXNE ? 1 : 0;
else
- return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
+ return readl(base + ISR_OFFSET(stm32f4)) &
+ USART_SR_FLAG_TXE ? 0 : 1;
}
static int stm32_serial_probe(struct udevice *dev)
{
- struct stm32_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
- setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ struct clk clk;
+ fdt_addr_t base = plat->base;
+ int ret;
+ bool stm32f4;
+ u8 uart_enable_bit;
+
+ plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
+ stm32f4 = plat->uart_info->stm32f4;
+ uart_enable_bit = plat->uart_info->uart_enable_bit;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
+ plat->clock_rate = clk_get_rate(&clk);
+ if (plat->clock_rate < 0) {
+ clk_disable(&clk);
+ return plat->clock_rate;
+ };
+
+ /* Disable uart-> disable overrun-> enable uart */
+ clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
+ if (plat->uart_info->has_overrun_disable)
+ setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
+ if (plat->uart_info->has_fifo)
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
+
+ return 0;
+}
+
+static const struct udevice_id stm32_serial_id[] = {
+ { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
+ { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
+ { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
+ {}
+};
+
+static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+
+ plat->base = devfdt_get_addr(dev);
+ if (plat->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
return 0;
}
U_BOOT_DRIVER(serial_stm32) = {
.name = "serial_stm32",
.id = UCLASS_SERIAL,
+ .of_match = of_match_ptr(stm32_serial_id),
+ .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
+ .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
.ops = &stm32_serial_ops,
.probe = stm32_serial_probe,
.flags = DM_FLAG_PRE_RELOC,
--- /dev/null
+/*
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SERIAL_STM32_
+#define _SERIAL_STM32_
+
+#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
+#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
+#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
+#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
+/*
+ * STM32F4 has one Data Register (DR) for received or transmitted
+ * data, so map Receive Data Register (RDR) and Transmit Data
+ * Register (TDR) at the same offset
+ */
+#define RDR_OFFSET(x) (x ? 0x04 : 0x24)
+#define TDR_OFFSET(x) (x ? 0x04 : 0x28)
+
+struct stm32_uart_info {
+ u8 uart_enable_bit; /* UART_CR1_UE */
+ bool stm32f4; /* true for STM32F4, false otherwise */
+ bool has_overrun_disable;
+ bool has_fifo;
+};
+
+struct stm32_uart_info stm32f4_info = {
+ .stm32f4 = true,
+ .uart_enable_bit = 13,
+ .has_overrun_disable = false,
+ .has_fifo = false,
+};
+
+struct stm32_uart_info stm32f7_info = {
+ .uart_enable_bit = 0,
+ .stm32f4 = false,
+ .has_overrun_disable = true,
+ .has_fifo = false,
+};
+
+struct stm32_uart_info stm32h7_info = {
+ .uart_enable_bit = 0,
+ .stm32f4 = false,
+ .has_overrun_disable = true,
+ .has_fifo = true,
+};
+
+/* Information about a serial port */
+struct stm32x7_serial_platdata {
+ fdt_addr_t base; /* address of registers in physical memory */
+ struct stm32_uart_info *uart_info;
+ unsigned long int clock_rate;
+};
+
+#define USART_CR1_FIFOEN BIT(29)
+#define USART_CR1_OVER8 BIT(15)
+#define USART_CR1_TE BIT(3)
+#define USART_CR1_RE BIT(2)
+
+#define USART_CR3_OVRDIS BIT(12)
+
+#define USART_SR_FLAG_RXNE BIT(5)
+#define USART_SR_FLAG_TXE BIT(7)
+
+#define USART_BRR_F_MASK GENMASK(7, 0)
+#define USART_BRR_M_SHIFT 4
+#define USART_BRR_M_MASK GENMASK(15, 4)
+
+#endif
+++ /dev/null
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <serial.h>
-#include <asm/arch/stm32.h>
-#include "serial_stm32x7.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
- u32 int_div, mantissa, fraction, oversampling;
-
- int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
-
- if (int_div < 16) {
- oversampling = 8;
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
- } else {
- oversampling = 16;
- clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
- }
-
- mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
- fraction = int_div % oversampling;
-
- writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
-
- return 0;
-}
-
-static int stm32_serial_getc(struct udevice *dev)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
-
- if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
- return -EAGAIN;
-
- return readl(base + RDR_OFFSET(stm32f4));
-}
-
-static int stm32_serial_putc(struct udevice *dev, const char c)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
-
- if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
- return -EAGAIN;
-
- writel(c, base + TDR_OFFSET(stm32f4));
-
- return 0;
-}
-
-static int stm32_serial_pending(struct udevice *dev, bool input)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
-
- if (input)
- return readl(base + ISR_OFFSET(stm32f4)) &
- USART_SR_FLAG_RXNE ? 1 : 0;
- else
- return readl(base + ISR_OFFSET(stm32f4)) &
- USART_SR_FLAG_TXE ? 0 : 1;
-}
-
-static int stm32_serial_probe(struct udevice *dev)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- struct clk clk;
- fdt_addr_t base = plat->base;
- int ret;
- bool stm32f4;
- u8 uart_enable_bit;
-
- plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
- stm32f4 = plat->uart_info->stm32f4;
- uart_enable_bit = plat->uart_info->uart_enable_bit;
-
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0)
- return ret;
-
- ret = clk_enable(&clk);
- if (ret) {
- dev_err(dev, "failed to enable clock\n");
- return ret;
- }
-
- plat->clock_rate = clk_get_rate(&clk);
- if (plat->clock_rate < 0) {
- clk_disable(&clk);
- return plat->clock_rate;
- };
-
- /* Disable uart-> disable overrun-> enable uart */
- clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
- BIT(uart_enable_bit));
- if (plat->uart_info->has_overrun_disable)
- setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
- if (plat->uart_info->has_fifo)
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
- BIT(uart_enable_bit));
-
- return 0;
-}
-
-static const struct udevice_id stm32_serial_id[] = {
- { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
- { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
- { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
- {}
-};
-
-static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
-
- plat->base = devfdt_get_addr(dev);
- if (plat->base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- return 0;
-}
-
-static const struct dm_serial_ops stm32_serial_ops = {
- .putc = stm32_serial_putc,
- .pending = stm32_serial_pending,
- .getc = stm32_serial_getc,
- .setbrg = stm32_serial_setbrg,
-};
-
-U_BOOT_DRIVER(serial_stm32) = {
- .name = "serial_stm32x7",
- .id = UCLASS_SERIAL,
- .of_match = of_match_ptr(stm32_serial_id),
- .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
- .ops = &stm32_serial_ops,
- .probe = stm32_serial_probe,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SERIAL_STM32_X7_
-#define _SERIAL_STM32_X7_
-
-#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
-#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
-#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
-#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
-/*
- * STM32F4 has one Data Register (DR) for received or transmitted
- * data, so map Receive Data Register (RDR) and Transmit Data
- * Register (TDR) at the same offset
- */
-#define RDR_OFFSET(x) (x ? 0x04 : 0x24)
-#define TDR_OFFSET(x) (x ? 0x04 : 0x28)
-
-struct stm32_uart_info {
- u8 uart_enable_bit; /* UART_CR1_UE */
- bool stm32f4; /* true for STM32F4, false otherwise */
- bool has_overrun_disable;
- bool has_fifo;
-};
-
-struct stm32_uart_info stm32f4_info = {
- .stm32f4 = true,
- .uart_enable_bit = 13,
- .has_overrun_disable = false,
- .has_fifo = false,
-};
-
-struct stm32_uart_info stm32f7_info = {
- .uart_enable_bit = 0,
- .stm32f4 = false,
- .has_overrun_disable = true,
- .has_fifo = false,
-};
-
-struct stm32_uart_info stm32h7_info = {
- .uart_enable_bit = 0,
- .stm32f4 = false,
- .has_overrun_disable = true,
- .has_fifo = true,
-};
-
-/* Information about a serial port */
-struct stm32x7_serial_platdata {
- fdt_addr_t base; /* address of registers in physical memory */
- struct stm32_uart_info *uart_info;
- unsigned long int clock_rate;
-};
-
-#define USART_CR1_FIFOEN BIT(29)
-#define USART_CR1_OVER8 BIT(15)
-#define USART_CR1_TE BIT(3)
-#define USART_CR1_RE BIT(2)
-
-#define USART_CR3_OVRDIS BIT(12)
-
-#define USART_SR_FLAG_RXNE BIT(5)
-#define USART_SR_FLAG_TXE BIT(7)
-
-#define USART_BRR_F_MASK GENMASK(7, 0)
-#define USART_BRR_M_SHIFT 4
-#define USART_BRR_M_MASK GENMASK(15, 4)
-
-#endif
used to access the SPI flash on AE3XX and AE250 platforms embedding
this Andestech IP core.
+config DAVINCI_SPI
+ bool "Davinci & Keystone SPI driver"
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE
+ help
+ Enable the Davinci SPI driver
+
config TI_QSPI
bool "TI QSPI driver"
help
DECLARE_GLOBAL_DATA_PTR;
#define RX_BUFFER_SIZE 0x80
-#ifdef CONFIG_MX6SX
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
#define TX_BUFFER_SIZE 0x200
#else
#define TX_BUFFER_SIZE 0x40
INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#endif
-#ifdef CONFIG_MX6SX
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
/*
* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
* So, Use IDATSZ in IPCR to determine the size and here set 0.
qspi->slave.max_write_size = TX_BUFFER_SIZE;
mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr);
+
+ /* Set endianness to LE for i.mx */
+ if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
+ mcr_val = QSPI_MCR_END_CFD_LE;
+
qspi_write32(qspi->priv.flags, ®s->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
(mcr_val & QSPI_MCR_END_CFD_MASK));
}
mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
+
+ /* Set endianness to LE for i.mx */
+ if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
+ mcr_val = QSPI_MCR_END_CFD_LE;
+
qspi_write32(priv->flags, &priv->regs->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
(mcr_val & QSPI_MCR_END_CFD_MASK));
static const struct udevice_id fsl_qspi_ids[] = {
{ .compatible = "fsl,vf610-qspi" },
{ .compatible = "fsl,imx6sx-qspi" },
+ { .compatible = "fsl,imx6ul-qspi" },
+ { .compatible = "fsl,imx7d-qspi" },
{ }
};
DECLARE_GLOBAL_DATA_PTR;
+/* PMIC Arbiter configuration registers */
+#define PMIC_ARB_VERSION 0x0000
+#define PMIC_ARB_VERSION_V2_MIN 0x20010000
+
#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
struct udevice *parent = dev->parent;
struct msm_spmi_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
+ u32 hw_ver;
+ bool is_v1;
int i;
priv->arb_chnl = devfdt_get_addr(dev);
dev_of_offset(parent), node, "reg", 1, NULL, false);
priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
dev_of_offset(parent), node, "reg", 2, NULL, false);
+
+ hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800);
+ is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
+
+ dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver);
+
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
priv->spmi_core == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
-
obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
-obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
+++ /dev/null
-/*
- * Qualcomm APQ8016 reset controller driver
- *
- * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <sysreset.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- phys_addr_t addr = devfdt_get_addr(dev);
- if (!addr)
- return -EINVAL;
- writel(0, addr);
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops msm_sysreset_ops = {
- .request = msm_sysreset_request,
-};
-
-static const struct udevice_id msm_sysreset_ids[] = {
- { .compatible = "qcom,pshold" },
- { }
-};
-
-U_BOOT_DRIVER(msm_reset) = {
- .name = "msm_sysreset",
- .id = UCLASS_SYSRESET,
- .of_match = msm_sysreset_ids,
- .ops = &msm_sysreset_ops,
-};
source "drivers/usb/dwc3/Kconfig"
+source "drivers/usb/musb/Kconfig"
+
source "drivers/usb/musb-new/Kconfig"
source "drivers/usb/emul/Kconfig"
+source "drivers/usb/phy/Kconfig"
+
source "drivers/usb/ulpi/Kconfig"
comment "USB peripherals"
allows to download images into memory and execute (jump to) them
using the same protocol as implemented by the i.MX family's boot ROM.
+config USB_FUNCTION_ROCKUSB
+ bool "Enable USB rockusb gadget"
+ help
+ Rockusb protocol is widely used by Rockchip SoC based devices. It can
+ read/write info, image to/from devices. This enables the USB part of
+ the rockusb gadget.for more detail about Rockusb protocol, please see
+ doc/README.rockusb
+
endif # USB_GADGET_DOWNLOAD
config USB_ETHER
obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o
obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o
obj-$(CONFIG_USB_FUNCTION_SDP) += f_sdp.o
+obj-$(CONFIG_USB_FUNCTION_ROCKUSB) += f_rockusb.o
endif
endif
ifdef CONFIG_USB_ETHER
--- /dev/null
+/*
+ * (C) Copyright 2017
+ *
+ * Eddie Cai <eddie.cai.linux@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linux/compiler.h>
+#include <version.h>
+#include <g_dnl.h>
+#include <asm/arch/f_rockusb.h>
+
+static inline struct f_rockusb *func_to_rockusb(struct usb_function *f)
+{
+ return container_of(f, struct f_rockusb, usb_function);
+}
+
+static struct usb_endpoint_descriptor fs_ep_in = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor fs_ep_out = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor hs_ep_in = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor hs_ep_out = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(512),
+};
+
+static struct usb_interface_descriptor interface_desc = {
+ .bLength = USB_DT_INTERFACE_SIZE,
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bInterfaceNumber = 0x00,
+ .bAlternateSetting = 0x00,
+ .bNumEndpoints = 0x02,
+ .bInterfaceClass = ROCKUSB_INTERFACE_CLASS,
+ .bInterfaceSubClass = ROCKUSB_INTERFACE_SUB_CLASS,
+ .bInterfaceProtocol = ROCKUSB_INTERFACE_PROTOCOL,
+};
+
+static struct usb_descriptor_header *rkusb_fs_function[] = {
+ (struct usb_descriptor_header *)&interface_desc,
+ (struct usb_descriptor_header *)&fs_ep_in,
+ (struct usb_descriptor_header *)&fs_ep_out,
+};
+
+static struct usb_descriptor_header *rkusb_hs_function[] = {
+ (struct usb_descriptor_header *)&interface_desc,
+ (struct usb_descriptor_header *)&hs_ep_in,
+ (struct usb_descriptor_header *)&hs_ep_out,
+ NULL,
+};
+
+static const char rkusb_name[] = "Rockchip Rockusb";
+
+static struct usb_string rkusb_string_defs[] = {
+ [0].s = rkusb_name,
+ { } /* end of list */
+};
+
+static struct usb_gadget_strings stringtab_rkusb = {
+ .language = 0x0409, /* en-us */
+ .strings = rkusb_string_defs,
+};
+
+static struct usb_gadget_strings *rkusb_strings[] = {
+ &stringtab_rkusb,
+ NULL,
+};
+
+static struct f_rockusb *rockusb_func;
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req);
+static int rockusb_tx_write_csw(u32 tag, int residue, u8 status, int size);
+
+struct f_rockusb *get_rkusb(void)
+{
+ struct f_rockusb *f_rkusb = rockusb_func;
+
+ if (!f_rkusb) {
+ f_rkusb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_rkusb));
+ if (!f_rkusb)
+ return 0;
+
+ rockusb_func = f_rkusb;
+ memset(f_rkusb, 0, sizeof(*f_rkusb));
+ }
+
+ if (!f_rkusb->buf_head) {
+ f_rkusb->buf_head = memalign(CONFIG_SYS_CACHELINE_SIZE,
+ RKUSB_BUF_SIZE);
+ if (!f_rkusb->buf_head)
+ return 0;
+
+ f_rkusb->buf = f_rkusb->buf_head;
+ memset(f_rkusb->buf_head, 0, RKUSB_BUF_SIZE);
+ }
+ return f_rkusb;
+}
+
+static struct usb_endpoint_descriptor *rkusb_ep_desc(
+struct usb_gadget *g,
+struct usb_endpoint_descriptor *fs,
+struct usb_endpoint_descriptor *hs)
+{
+ if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+ return hs;
+ return fs;
+}
+
+static void rockusb_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ int status = req->status;
+
+ if (!status)
+ return;
+ debug("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual);
+}
+
+/* config the rockusb device*/
+static int rockusb_bind(struct usb_configuration *c, struct usb_function *f)
+{
+ int id;
+ struct usb_gadget *gadget = c->cdev->gadget;
+ struct f_rockusb *f_rkusb = func_to_rockusb(f);
+ const char *s;
+
+ id = usb_interface_id(c, f);
+ if (id < 0)
+ return id;
+ interface_desc.bInterfaceNumber = id;
+
+ id = usb_string_id(c->cdev);
+ if (id < 0)
+ return id;
+
+ rkusb_string_defs[0].id = id;
+ interface_desc.iInterface = id;
+
+ f_rkusb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in);
+ if (!f_rkusb->in_ep)
+ return -ENODEV;
+ f_rkusb->in_ep->driver_data = c->cdev;
+
+ f_rkusb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out);
+ if (!f_rkusb->out_ep)
+ return -ENODEV;
+ f_rkusb->out_ep->driver_data = c->cdev;
+
+ f->descriptors = rkusb_fs_function;
+
+ if (gadget_is_dualspeed(gadget)) {
+ hs_ep_in.bEndpointAddress = fs_ep_in.bEndpointAddress;
+ hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
+ f->hs_descriptors = rkusb_hs_function;
+ }
+
+ s = env_get("serial#");
+ if (s)
+ g_dnl_set_serialnumber((char *)s);
+
+ return 0;
+}
+
+static void rockusb_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+ /* clear the configuration*/
+ memset(rockusb_func, 0, sizeof(*rockusb_func));
+}
+
+static void rockusb_disable(struct usb_function *f)
+{
+ struct f_rockusb *f_rkusb = func_to_rockusb(f);
+
+ usb_ep_disable(f_rkusb->out_ep);
+ usb_ep_disable(f_rkusb->in_ep);
+
+ if (f_rkusb->out_req) {
+ free(f_rkusb->out_req->buf);
+ usb_ep_free_request(f_rkusb->out_ep, f_rkusb->out_req);
+ f_rkusb->out_req = NULL;
+ }
+ if (f_rkusb->in_req) {
+ free(f_rkusb->in_req->buf);
+ usb_ep_free_request(f_rkusb->in_ep, f_rkusb->in_req);
+ f_rkusb->in_req = NULL;
+ }
+ if (f_rkusb->buf_head) {
+ free(f_rkusb->buf_head);
+ f_rkusb->buf_head = NULL;
+ f_rkusb->buf = NULL;
+ }
+}
+
+static struct usb_request *rockusb_start_ep(struct usb_ep *ep)
+{
+ struct usb_request *req;
+
+ req = usb_ep_alloc_request(ep, 0);
+ if (!req)
+ return NULL;
+
+ req->length = EP_BUFFER_SIZE;
+ req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE);
+ if (!req->buf) {
+ usb_ep_free_request(ep, req);
+ return NULL;
+ }
+ memset(req->buf, 0, req->length);
+
+ return req;
+}
+
+static int rockusb_set_alt(struct usb_function *f, unsigned int interface,
+ unsigned int alt)
+{
+ int ret;
+ struct usb_composite_dev *cdev = f->config->cdev;
+ struct usb_gadget *gadget = cdev->gadget;
+ struct f_rockusb *f_rkusb = func_to_rockusb(f);
+ const struct usb_endpoint_descriptor *d;
+
+ debug("%s: func: %s intf: %d alt: %d\n",
+ __func__, f->name, interface, alt);
+
+ d = rkusb_ep_desc(gadget, &fs_ep_out, &hs_ep_out);
+ ret = usb_ep_enable(f_rkusb->out_ep, d);
+ if (ret) {
+ printf("failed to enable out ep\n");
+ return ret;
+ }
+
+ f_rkusb->out_req = rockusb_start_ep(f_rkusb->out_ep);
+ if (!f_rkusb->out_req) {
+ printf("failed to alloc out req\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ f_rkusb->out_req->complete = rx_handler_command;
+
+ d = rkusb_ep_desc(gadget, &fs_ep_in, &hs_ep_in);
+ ret = usb_ep_enable(f_rkusb->in_ep, d);
+ if (ret) {
+ printf("failed to enable in ep\n");
+ goto err;
+ }
+
+ f_rkusb->in_req = rockusb_start_ep(f_rkusb->in_ep);
+ if (!f_rkusb->in_req) {
+ printf("failed alloc req in\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ f_rkusb->in_req->complete = rockusb_complete;
+
+ ret = usb_ep_queue(f_rkusb->out_ep, f_rkusb->out_req, 0);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ rockusb_disable(f);
+ return ret;
+}
+
+static int rockusb_add(struct usb_configuration *c)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+ int status;
+
+ debug("%s: cdev: 0x%p\n", __func__, c->cdev);
+
+ f_rkusb->usb_function.name = "f_rockusb";
+ f_rkusb->usb_function.bind = rockusb_bind;
+ f_rkusb->usb_function.unbind = rockusb_unbind;
+ f_rkusb->usb_function.set_alt = rockusb_set_alt;
+ f_rkusb->usb_function.disable = rockusb_disable;
+ f_rkusb->usb_function.strings = rkusb_strings;
+
+ status = usb_add_function(c, &f_rkusb->usb_function);
+ if (status) {
+ free(f_rkusb);
+ rockusb_func = f_rkusb;
+ }
+ return status;
+}
+
+void rockusb_dev_init(char *dev_type, int dev_index)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+
+ f_rkusb->dev_type = dev_type;
+ f_rkusb->dev_index = dev_index;
+}
+
+DECLARE_GADGET_BIND_CALLBACK(usb_dnl_rockusb, rockusb_add);
+
+static int rockusb_tx_write(const char *buffer, unsigned int buffer_size)
+{
+ struct usb_request *in_req = rockusb_func->in_req;
+ int ret;
+
+ memcpy(in_req->buf, buffer, buffer_size);
+ in_req->length = buffer_size;
+ usb_ep_dequeue(rockusb_func->in_ep, in_req);
+ ret = usb_ep_queue(rockusb_func->in_ep, in_req, 0);
+ if (ret)
+ printf("Error %d on queue\n", ret);
+ return 0;
+}
+
+static int rockusb_tx_write_str(const char *buffer)
+{
+ return rockusb_tx_write(buffer, strlen(buffer));
+}
+
+#ifdef DEBUG
+static void printcbw(char *buf)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+
+ memcpy((char *)cbw, buf, USB_BULK_CB_WRAP_LEN);
+
+ debug("cbw: signature:%x\n", cbw->signature);
+ debug("cbw: tag=%x\n", cbw->tag);
+ debug("cbw: data_transfer_length=%d\n", cbw->data_transfer_length);
+ debug("cbw: flags=%x\n", cbw->flags);
+ debug("cbw: lun=%d\n", cbw->lun);
+ debug("cbw: length=%d\n", cbw->length);
+ debug("cbw: ucOperCode=%x\n", cbw->CDB[0]);
+ debug("cbw: ucReserved=%x\n", cbw->CDB[1]);
+ debug("cbw: dwAddress:%x %x %x %x\n", cbw->CDB[5], cbw->CDB[4],
+ cbw->CDB[3], cbw->CDB[2]);
+ debug("cbw: ucReserved2=%x\n", cbw->CDB[6]);
+ debug("cbw: uslength:%x %x\n", cbw->CDB[8], cbw->CDB[7]);
+}
+
+static void printcsw(char *buf)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct bulk_cs_wrap, csw,
+ sizeof(struct bulk_cs_wrap));
+ memcpy((char *)csw, buf, USB_BULK_CS_WRAP_LEN);
+ debug("csw: signature:%x\n", csw->signature);
+ debug("csw: tag:%x\n", csw->tag);
+ debug("csw: residue:%x\n", csw->residue);
+ debug("csw: status:%x\n", csw->status);
+}
+#endif
+
+static int rockusb_tx_write_csw(u32 tag, int residue, u8 status, int size)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct bulk_cs_wrap, csw,
+ sizeof(struct bulk_cs_wrap));
+ csw->signature = cpu_to_le32(USB_BULK_CS_SIG);
+ csw->tag = tag;
+ csw->residue = cpu_to_be32(residue);
+ csw->status = status;
+#ifdef DEBUG
+ printcsw((char *)&csw);
+#endif
+ return rockusb_tx_write((char *)csw, size);
+}
+
+static unsigned int rx_bytes_expected(struct usb_ep *ep)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+ int rx_remain = f_rkusb->dl_size - f_rkusb->dl_bytes;
+ unsigned int rem;
+ unsigned int maxpacket = ep->maxpacket;
+
+ if (rx_remain <= 0)
+ return 0;
+ else if (rx_remain > EP_BUFFER_SIZE)
+ return EP_BUFFER_SIZE;
+
+ rem = rx_remain % maxpacket;
+ if (rem > 0)
+ rx_remain = rx_remain + (maxpacket - rem);
+
+ return rx_remain;
+}
+
+/* usb_request complete call back to handle down load image */
+static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+ unsigned int transfer_size = 0;
+ const unsigned char *buffer = req->buf;
+ unsigned int buffer_size = req->actual;
+
+ transfer_size = f_rkusb->dl_size - f_rkusb->dl_bytes;
+ if (!f_rkusb->desc) {
+ char *type = f_rkusb->dev_type;
+ int index = f_rkusb->dev_index;
+
+ f_rkusb->desc = blk_get_dev(type, index);
+ if (!f_rkusb->desc ||
+ f_rkusb->desc->type == DEV_TYPE_UNKNOWN) {
+ puts("invalid mmc device\n");
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+ }
+
+ if (req->status != 0) {
+ printf("Bad status: %d\n", req->status);
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+
+ if (buffer_size < transfer_size)
+ transfer_size = buffer_size;
+
+ memcpy((void *)f_rkusb->buf, buffer, transfer_size);
+ f_rkusb->dl_bytes += transfer_size;
+ int blks = 0, blkcnt = transfer_size / 512;
+
+ debug("dl %x bytes, %x blks, write lba %x, dl_size:%x, dl_bytes:%x, ",
+ transfer_size, blkcnt, f_rkusb->lba, f_rkusb->dl_size,
+ f_rkusb->dl_bytes);
+ blks = blk_dwrite(f_rkusb->desc, f_rkusb->lba, blkcnt, f_rkusb->buf);
+ if (blks != blkcnt) {
+ printf("failed writing to device %s: %d\n", f_rkusb->dev_type,
+ f_rkusb->dev_index);
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+ f_rkusb->lba += blkcnt;
+
+ /* Check if transfer is done */
+ if (f_rkusb->dl_bytes >= f_rkusb->dl_size) {
+ req->complete = rx_handler_command;
+ req->length = EP_BUFFER_SIZE;
+ f_rkusb->buf = f_rkusb->buf_head;
+ printf("transfer 0x%x bytes done\n", f_rkusb->dl_size);
+ f_rkusb->dl_size = 0;
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_GOOD,
+ USB_BULK_CS_WRAP_LEN);
+ } else {
+ req->length = rx_bytes_expected(ep);
+ if (f_rkusb->buf == f_rkusb->buf_head)
+ f_rkusb->buf = f_rkusb->buf_head + EP_BUFFER_SIZE;
+ else
+ f_rkusb->buf = f_rkusb->buf_head;
+
+ debug("remain %x bytes, %x sectors\n", req->length,
+ req->length / 512);
+ }
+
+ req->actual = 0;
+ usb_ep_queue(ep, req, 0);
+}
+
+static void cb_test_unit_ready(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length,
+ CSW_GOOD, USB_BULK_CS_WRAP_LEN);
+}
+
+static void cb_read_storage_id(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ char emmc_id[] = "EMMC ";
+
+ printf("read storage id\n");
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ rockusb_tx_write_str(emmc_id);
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD,
+ USB_BULK_CS_WRAP_LEN);
+}
+
+static void cb_write_lba(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ struct f_rockusb *f_rkusb = get_rkusb();
+ int sector_count;
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ sector_count = (int)get_unaligned_be16(&cbw->CDB[7]);
+ f_rkusb->lba = get_unaligned_be32(&cbw->CDB[2]);
+ f_rkusb->dl_size = sector_count * 512;
+ f_rkusb->dl_bytes = 0;
+ f_rkusb->tag = cbw->tag;
+ debug("require write %x bytes, %x sectors to lba %x\n",
+ f_rkusb->dl_size, sector_count, f_rkusb->lba);
+
+ if (f_rkusb->dl_size == 0) {
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length,
+ CSW_FAIL, USB_BULK_CS_WRAP_LEN);
+ } else {
+ req->complete = rx_handler_dl_image;
+ req->length = rx_bytes_expected(ep);
+ }
+}
+
+void __weak rkusb_set_reboot_flag(int flag)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+
+ printf("rockkusb set reboot flag: %d\n", f_rkusb->reboot_flag);
+}
+
+static void compl_do_reset(struct usb_ep *ep, struct usb_request *req)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+
+ rkusb_set_reboot_flag(f_rkusb->reboot_flag);
+ do_reset(NULL, 0, 0, NULL);
+}
+
+static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ struct f_rockusb *f_rkusb = get_rkusb();
+
+ f_rkusb->reboot_flag = 0;
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ f_rkusb->reboot_flag = cbw->CDB[1];
+ rockusb_func->in_req->complete = compl_do_reset;
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD,
+ USB_BULK_CS_WRAP_LEN);
+}
+
+static void cb_not_support(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ printf("Rockusb command %x not support yet\n", cbw->CDB[0]);
+ rockusb_tx_write_csw(cbw->tag, 0, CSW_FAIL, USB_BULK_CS_WRAP_LEN);
+}
+
+static const struct cmd_dispatch_info cmd_dispatch_info[] = {
+ {
+ .cmd = K_FW_TEST_UNIT_READY,
+ .cb = cb_test_unit_ready,
+ },
+ {
+ .cmd = K_FW_READ_FLASH_ID,
+ .cb = cb_read_storage_id,
+ },
+ {
+ .cmd = K_FW_SET_DEVICE_ID,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_TEST_BAD_BLOCK,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_READ_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_WRITE_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_ERASE_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_WRITE_SPARE,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_READ_SPARE,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_ERASE_10_FORCE,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_GET_VERSION,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_LBA_READ_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_LBA_WRITE_10,
+ .cb = cb_write_lba,
+ },
+ {
+ .cmd = K_FW_ERASE_SYS_DISK,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SDRAM_READ_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SDRAM_WRITE_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SDRAM_EXECUTE,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_READ_FLASH_INFO,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_GET_CHIP_VER,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_LOW_FORMAT,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SET_RESET_FLAG,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SPI_READ_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SPI_WRITE_10,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_SESSION,
+ .cb = cb_not_support,
+ },
+ {
+ .cmd = K_FW_RESET,
+ .cb = cb_reboot,
+ },
+};
+
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
+{
+ void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL;
+
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ char *cmdbuf = req->buf;
+ int i;
+
+ if (req->status || req->length == 0)
+ return;
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+#ifdef DEBUG
+ printcbw(req->buf);
+#endif
+
+ for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) {
+ if (cmd_dispatch_info[i].cmd == cbw->CDB[0]) {
+ func_cb = cmd_dispatch_info[i].cb;
+ break;
+ }
+ }
+
+ if (!func_cb) {
+ printf("unknown command: %s\n", (char *)req->buf);
+ rockusb_tx_write_str("FAILunknown command");
+ } else {
+ if (req->actual < req->length) {
+ u8 *buf = (u8 *)req->buf;
+
+ buf[req->actual] = 0;
+ func_cb(ep, req);
+ } else {
+ puts("buffer overflow\n");
+ rockusb_tx_write_str("FAILbuffer overflow");
+ }
+ }
+
+ *cmdbuf = '\0';
+ req->actual = 0;
+ usb_ep_queue(ep, req, 0);
+}
---help---
Enables support for generic EHCI controller.
+config USB_EHCI_FSL
+ bool "Support for FSL on-chip EHCI USB controller"
+ default n
+ select CONFIG_EHCI_HCD_INIT_AFTER_RESET
+ ---help---
+ Enables support for the on-chip EHCI controller on FSL chips.
endif # USB_EHCI_HCD
config USB_OHCI_HCD
ehci = (struct usb_ehci *)priv->hcd_base;
hccr = (struct ehci_hccr *)(&ehci->caplength);
hcor = (struct ehci_hcor *)
- ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
return -ENXIO;
- debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
- (u32)hccr, (u32)hcor,
- (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
+ (void *)hccr, (void *)hcor,
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
}
speed USB controller based on the Mentor Graphics
silicon IP.
+config USB_MUSB_OMAP2PLUS
+ tristate "OMAP2430 and onwards"
+ depends on ARCH_OMAP2PLUS
+
+config USB_MUSB_AM35X
+ bool "AM35x"
+
+config USB_MUSB_DSPS
+ bool "TI DSPS platforms"
+
if USB_MUSB_HOST || USB_MUSB_GADGET
config USB_MUSB_PIC32
used on almost all sunxi boards.
endif
+
+config USB_MUSB_PIO_ONLY
+ bool "Disable DMA (always use PIO)"
+ default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS || USB_MUSB_DSPS || USB_MUSB_SUNXI
+ help
+ All data is copied between memory and FIFO by the CPU.
+ DMA controllers are ignored.
{
struct musb_host_data *host = dev_get_priv(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+ void *base = dev_read_addr_ptr(dev);
int ret;
+ if (!base)
+ return -EINVAL;
+
priv->desc_before_addr = true;
#ifdef CONFIG_USB_MUSB_HOST
- host->host = musb_init_controller(&musb_plat, NULL,
- (void *)SUNXI_USB0_BASE);
+ host->host = musb_init_controller(&musb_plat, NULL, base);
if (!host->host)
return -EIO;
if (!ret)
printf("Allwinner mUSB OTG (Host)\n");
#else
- ret = musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
+ ret = musb_register(&musb_plat, NULL, base);
if (!ret)
printf("Allwinner mUSB OTG (Peripheral)\n");
#endif
--- /dev/null
+#
+# (C) Copyright 2017
+# Adam Ford, Logic PD, aford173@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+comment "Legacy MUSB Support"
+
+config USB_MUSB_HCD
+ bool "Legacy MUSB Host Controller"
+
+config USB_MUSB_UDC
+ bool "Legacy USB Device Controller"
+
+config USB_DAVINCI
+ bool "Legacy MUSB DaVinci"
+
+config USB_OMAP3
+ bool "Legacy MUSB OMAP3 / OMAP4"
+ depends on ARCH_OMAP2PLUS
+
+config USB_DA8XX
+ bool "Legacy MUSB DA8xx/OMAP-L1x"
+ depends on ARCH_DAVINCI
+
+config USB_AM35X
+ bool"Legacy MUSB AM35x"
+ depends on ARCH_OMAP2PLUS && !USB_OMAP3
--- /dev/null
+#
+# (C) Copyright 2017
+# Adam Ford, Logic PD, aford173@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+comment "USB Phy"
+
+config TWL4030_USB
+ bool "TWL4030 PHY"
+
+config OMAP_USB_PHY
+ bool "OMAP PHY"
+
+config ROCKCHIP_USB2_PHY
+ bool "Rockchip USB2 PHY"
/*
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
*
* minimal framebuffer driver for TI's AM335x SoC to be compatible with
* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include <lcd.h>
#include "am335x-fb.h"
#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
#endif
+#define LCDC_FMAX 200000000
/* LCD Control Register */
#define LCD_CLK_DIVISOR(x) ((x) << 8)
};
static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
+
DECLARE_GLOBAL_DATA_PTR;
int lcd_get_size(int *line_length)
{
u32 raster_ctrl = 0;
- if (0 == gd->fb_base) {
+ struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+ struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
+ unsigned int m, n, d, best_d = 2;
+ int err = 0, err_r = 0;
+
+ if (gd->fb_base == 0) {
printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
return -1;
}
- if (0 == panel) {
+ if (panel == NULL) {
printf("ERROR: missing ptr to am335x_lcdpanel!\n");
return -1;
}
return -1;
}
+ /* check given clock-frequency */
+ if (panel->pxl_clk > (LCDC_FMAX / 2)) {
+ pr_err("am335x-fb: requested pxl-clk: %d not supported!\n",
+ panel->pxl_clk);
+ return -1;
+ }
+
debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
panel->hactive, panel->vactive, panel->bpp,
panel->hfp, panel->hbp, panel->hsw);
- debug("vfp=%d,vbp=%d,vsw=%d / clk-div=%d)\n",
- panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk_div);
+ debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n",
+ panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk);
debug("using frambuffer at 0x%08x with size %d.\n",
(unsigned int)gd->fb_base, FBSIZE(panel));
+ /* setup display pll for requested clock frequency */
+ err = panel->pxl_clk;
+ err_r = err;
+
+ for (d = 2; d < 255; d++) {
+ for (m = 2; m < 2047; m++) {
+ if ((V_OSCK * m) < (panel->pxl_clk * d))
+ continue;
+ n = (V_OSCK * m) / (panel->pxl_clk * d);
+ if (n > 127)
+ break;
+ if (((V_OSCK * m) / n) > LCDC_FMAX)
+ break;
+
+ err = abs((V_OSCK * m) / n / d - panel->pxl_clk);
+ if (err < err_r) {
+ err_r = err;
+ dpll_disp.m = m;
+ dpll_disp.n = n;
+ best_d = d;
+ }
+ }
+ }
+ debug("%s: PLL: best error %d Hz (M %d, N %d, DISP %d)\n",
+ __func__, err_r, dpll_disp.m, dpll_disp.n, best_d);
+ do_setup_dpll(&dpll_disp_regs, &dpll_disp);
+
+ /* clock source for LCDC from dispPLL M2 */
+ writel(0x0, &cmdpll->clklcdcpixelclk);
+
/* palette default entry */
memset((void *)gd->fb_base, 0, 0x20);
*(unsigned int *)gd->fb_base = 0x4000;
gd->fb_base += 0x20;
/* turn ON display through powercontrol function if accessible */
- if (0 != panel->panel_power_ctrl)
+ if (panel->panel_power_ctrl != NULL)
panel->panel_power_ctrl(1);
debug("am335x-fb: wait for stable power ...\n");
mdelay(panel->pup_delay);
lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
lcdhw->raster_ctrl = 0;
- lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
+ lcdhw->ctrl = LCD_CLK_DIVISOR(best_d) | LCD_RASTER_MODE;
lcdhw->lcddma_fb0_base = gd->fb_base;
lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
lcdhw->lcddma_fb1_base = gd->fb_base;
/*
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
unsigned int vfp; /* Vertical front porch */
unsigned int vbp; /* Vertical back porch */
unsigned int vsw; /* Vertical Sync Pulse Width */
- unsigned int pxl_clk_div; /* Pixel clock divider*/
+ unsigned int pxl_clk; /* Pixel clock */
unsigned int pol; /* polarity of sync, clock signals */
unsigned int pup_delay; /*
* time in ms after power on to
config ENV_IS_IN_FAT
bool "Environment is in a FAT filesystem"
depends on !CHAIN_OF_TRUST
+ select FS_FAT
select FAT_WRITE
help
Define this if you want to use the FAT file system for the environment.
- - CONFIG_FAT_WRITE:
- This must be enabled. Otherwise it cannot save the environment file.
+config ENV_IS_IN_EXT4
+ bool "Environment is in a EXT4 filesystem"
+ depends on !CHAIN_OF_TRUST
+ select EXT4_WRITE
+ help
+ Define this if you want to use the EXT4 file system for the environment.
config ENV_IS_IN_FLASH
bool "Environment in flash memory"
It's a string of the FAT file name. This file use to store the
environment.
+config ENV_EXT4_INTERFACE
+ string "Name of the block device for the environment"
+ depends on ENV_IS_IN_EXT4
+ help
+ Define this to a string that is the name of the block device.
+
+config ENV_EXT4_DEVICE_AND_PART
+ string "Device and partition for where to store the environemt in EXT4"
+ depends on ENV_IS_IN_EXT4
+ help
+ Define this to a string to specify the partition of the device. It can
+ be as following:
+
+ "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
+ - "D:P": device D partition P. Error occurs if device D has no
+ partition table.
+ - "D:0": device D.
+ - "D" or "D:": device D partition 1 if device D has partition
+ table, or the whole device D if has no partition
+ table.
+ - "D:auto": first partition in device D with bootable flag set.
+ If none, first valid partition in device D. If no
+ partition table then means device D.
+
+config ENV_EXT4_FILE
+ string "Name of the EXT4 file to use for the environemnt"
+ depends on ENV_IS_IN_EXT4
+ default "uboot.env"
+ help
+ It's a string of the EXT4 file name. This file use to store the
+ environment (explicit path to the file)
+
if ARCH_SUNXI
config ENV_OFFSET
return ENVL_EEPROM;
else if IS_ENABLED(CONFIG_ENV_IS_IN_FAT)
return ENVL_FAT;
+ else if IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)
+ return ENVL_EXT4;
else if IS_ENABLED(CONFIG_ENV_IS_IN_FLASH)
return ENVL_FLASH;
else if IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
if (err)
return err;
- part = blk_get_device_part_str(EXT4_ENV_INTERFACE,
- EXT4_ENV_DEVICE_AND_PART,
- &dev_desc, &info, 1);
+ part = blk_get_device_part_str(CONFIG_ENV_EXT4_INTERFACE,
+ CONFIG_ENV_EXT4_DEVICE_AND_PART,
+ &dev_desc, &info, 1);
if (part < 0)
return 1;
if (!ext4fs_mount(info.size)) {
printf("\n** Unable to use %s %s for saveenv **\n",
- EXT4_ENV_INTERFACE, EXT4_ENV_DEVICE_AND_PART);
+ CONFIG_ENV_EXT4_INTERFACE,
+ CONFIG_ENV_EXT4_DEVICE_AND_PART);
return 1;
}
- err = ext4fs_write(EXT4_ENV_FILE, (void *)&env_new, sizeof(env_t));
+ err = ext4fs_write(CONFIG_ENV_EXT4_FILE, (void *)&env_new,
+ sizeof(env_t));
ext4fs_close();
if (err == -1) {
printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
+ CONFIG_ENV_EXT4_FILE, CONFIG_ENV_EXT4_INTERFACE, dev,
+ part);
return 1;
}
int err;
loff_t off;
- part = blk_get_device_part_str(EXT4_ENV_INTERFACE,
- EXT4_ENV_DEVICE_AND_PART,
- &dev_desc, &info, 1);
+ part = blk_get_device_part_str(CONFIG_ENV_EXT4_INTERFACE,
+ CONFIG_ENV_EXT4_DEVICE_AND_PART,
+ &dev_desc, &info, 1);
if (part < 0)
goto err_env_relocate;
if (!ext4fs_mount(info.size)) {
printf("\n** Unable to use %s %s for loading the env **\n",
- EXT4_ENV_INTERFACE, EXT4_ENV_DEVICE_AND_PART);
+ CONFIG_ENV_EXT4_INTERFACE,
+ CONFIG_ENV_EXT4_DEVICE_AND_PART);
goto err_env_relocate;
}
- err = ext4_read_file(EXT4_ENV_FILE, buf, 0, CONFIG_ENV_SIZE, &off);
+ err = ext4_read_file(CONFIG_ENV_EXT4_FILE, buf, 0, CONFIG_ENV_SIZE,
+ &off);
ext4fs_close();
if (err == -1) {
printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
+ CONFIG_ENV_EXT4_FILE, CONFIG_ENV_EXT4_INTERFACE, dev,
+ part);
goto err_env_relocate;
}
#ifndef CONFIG_SPL_BUILD
#define CMD_SAVEENV
+#define INITENV
#endif
#ifdef CONFIG_ENV_OFFSET_REDUND
}
#endif
+#if defined(INITENV) && defined(CONFIG_ENV_ADDR)
+static int env_sf_init(void)
+{
+ env_t *env_ptr = (env_t *)(CONFIG_ENV_ADDR);
+
+ if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
+ gd->env_addr = (ulong)&(env_ptr->data);
+ gd->env_valid = 1;
+ } else {
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+ }
+
+ return 0;
+}
+#endif
+
U_BOOT_ENV_LOCATION(sf) = {
.location = ENVL_SPI_FLASH,
ENV_NAME("SPI Flash")
#ifdef CMD_SAVEENV
.save = env_save_ptr(env_sf_save),
#endif
+#if defined(INITENV) && defined(CONFIG_ENV_ADDR)
+ .init = env_sf_init,
+#endif
};
# SPDX-License-Identifier: GPL-2.0+
#
+# Provide symbol API_BUILD to signal that the API example is being built.
+KBUILD_CPPFLAGS += -DAPI_BUILD
+
ifeq ($(ARCH),powerpc)
LOAD_ADDR = 0x40000
endif
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SECTIONS
+{
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .data : {
+ __global_pointer$ = . + 0x800;
+ *(.data)
+ }
+
+ . = ALIGN(4);
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ __bss_end = .;
+
+ . = ALIGN(4);
+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+ _end = .;
+}
" lwi $r16, [$r16 + (%1)]\n" \
" jr $r16\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16");
+#elif defined(CONFIG_RISCV)
+/*
+ * t7 holds the pointer to the global_data. gp is call clobbered.
+ */
+#define EXPORT_FUNC(f, a, x, ...) \
+ asm volatile ( \
+" .globl " #x "\n" \
+#x ":\n" \
+" lw x19, %0(gp)\n" \
+" lw x19, %1(x19)\n" \
+" jr x19\n" \
+ : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "x19");
#elif defined(CONFIG_ARC)
/*
* r25 holds the pointer to the global_data. r10 is call clobbered.
+config FS_EXT4
+ bool "Enable ext4 filesystem support"
+ help
+ This provides support for reading images from the ext4 filesystem.
+ ext4 is a widely used general-purpose filesystem for Linux.
+ You can also enable CMD_EXT4 to get access to ext4 commands.
+
+config EXT4_WRITE
+ bool "Enable ext4 filesystem write support"
+ depends on FS_EXT4
+ help
+ This provides support for creating and writing new files to an
+ existing ext4 filesystem partition.
existing FAT filesystem partition.
config FS_FAT_MAX_CLUSTSIZE
- int "Set maximum possible clusersize"
+ int "Set maximum possible clustersize"
default 65536
depends on FS_FAT
help
#include <linux/compiler.h>
#include <linux/ctype.h>
-#ifdef CONFIG_SUPPORT_VFAT
-static const int vfat_enabled = 1;
-#else
-static const int vfat_enabled = 0;
-#endif
-
/*
* Convert a string to lowercase. Converts at most 'len' characters,
* 'len' may be larger than the length of 'str' if 'str' is NULL
return -1;
}
- if (vfat_enabled)
- debug("VFAT Support enabled\n");
-
debug("FAT%d, fat_sect: %d, fatlength: %d\n",
mydata->fatsize, mydata->fat_sect, mydata->fatlength);
debug("Rootdir begins at cluster: %d, sector: %d, offset: %x\n"
continue;
if (dent->attr & ATTR_VOLUME) {
- if (vfat_enabled &&
- (dent->attr & ATTR_VFAT) == ATTR_VFAT &&
+ if ((dent->attr & ATTR_VFAT) == ATTR_VFAT &&
(dent->name[0] & LAST_LONG_ENTRY_MASK)) {
dent = extract_vfat_name(itr);
if (!dent)
if (ret)
goto out_free_both;
- printf("reading %s\n", filename);
+ debug("reading %s\n", filename);
ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread);
out_free_both:
continue;
}
if ((dentptr->attr & ATTR_VOLUME)) {
- if (vfat_enabled &&
- (dentptr->attr & ATTR_VFAT) &&
+ if ((dentptr->attr & ATTR_VFAT) &&
(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
get_long_file_name(mydata, curclust,
get_dentfromdir_block,
get_name(dentptr, s_name);
- if (strcmp(filename, s_name)
- && strcmp(filename, l_name)) {
+ if (strncasecmp(filename, s_name, sizeof(s_name)) &&
+ strncasecmp(filename, l_name, sizeof(l_name))) {
debug("Mismatch: |%s|%s|\n",
s_name, l_name);
dentptr++;
/* If we requested a specific number of bytes, check we got it */
if (ret == 0 && len && *actread != len)
- printf("** %s shorter than offset + len **\n", filename);
+ debug("** %s shorter than offset + len **\n", filename);
fs_close();
return ret;
IF_TYPE_HOST,
IF_TYPE_SYSTEMACE,
IF_TYPE_NVME,
+ IF_TYPE_EFI,
IF_TYPE_COUNT, /* Number of interface types */
};
int misc_init_f (void);
int misc_init_r (void);
+#if defined(CONFIG_VID)
+int init_func_vid(void);
+#endif
/* common/exports.c */
void jumptable_init(void);
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
-#if defined(CONFIG_ENV_IS_IN_FAT) && !defined(CONFIG_FS_FAT)
-#define CONFIG_FS_FAT
-#endif
-
-#if (defined(CONFIG_CMD_EXT4) || defined(CONFIG_CMD_EXT2)) && \
- !defined(CONFIG_FS_EXT4)
-#define CONFIG_FS_EXT4
-#endif
-
-#if defined(CONFIG_CMD_EXT4_WRITE) && !defined(CONFIG_EXT4_WRITE)
-#define CONFIG_EXT4_WRITE
-#endif
-
/* Rather than repeat this expression each time, add a define for it */
#if defined(CONFIG_IDE) || \
defined(CONFIG_SATA) || \
defined(CONFIG_MMC) || \
defined(CONFIG_NVME) || \
defined(CONFIG_SYSTEMACE) || \
+ (defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)) || \
defined(CONFIG_SANDBOX)
#define HAVE_BLOCK_DEVICE
#endif
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_M52277EVB /* M52277EVB board */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#ifndef _M5253DEMO_H
#define _M5253DEMO_H
-#define CONFIG_M5253DEMO /* define board type */
-
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#ifndef _M5253EVBE_H
#define _M5253EVBE_H
-#define CONFIG_M5253EVBE /* define board type */
-
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_M5275EVB /* define board type */
#define CONFIG_MCFTMR
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_M54418TWR /* M54418TWR board */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC834x 1 /* MPC834x family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
- || defined(CONFIG_USB_STORAGE)
- #define CONFIG_SUPPORT_VFAT
-#endif
-
-#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
-#endif
-
/* Watchdog */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define __MIGO_R_H
#define CONFIG_CPU_SH7722 1
-#define CONFIG_MIGO_R 1
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_LOADADDR 1000000
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_FSL_PCIE_RESET
+#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 18
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 18
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 50
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 50
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC834x 1 /* MPC834x specific */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_TQM834X 1 /* TQM834X board specific */
#define CONFIG_SYS_TEXT_BASE 0x80000000
/*
* CPU and Board Configuration Options
*/
-#define CONFIG_ADP_AG101P
-
#define CONFIG_USE_INTERRUPT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SPI_FLASH_QUAD
/* SH Ether */
-#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
/* settings we don;t want on this board */
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
-#undef CONFIG_CMD_EXT4
-#undef CONFIG_CMD_EXT4_WRITE
#undef CONFIG_CMD_SPI
#define CONFIG_CMD_CACHE
* Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
* Enable CONFIG_USB_MUSB_UDC for Device functionalities.
*/
-#define CONFIG_USB_AM35X 1
-#define CONFIG_USB_MUSB_HCD 1
#ifdef CONFIG_USB_AM35X
* Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard
* Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
*/
-#define CONFIG_USB_MUSB_AM35X
-#define CONFIG_USB_MUSB_PIO_ONLY
#ifdef CONFIG_USB_MUSB_AM35X
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
#endif
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB3PHY1_HOST
/* SATA */
#ifndef __AMCORE_CONFIG_H
#define __AMCORE_CONFIG_H
-#define CONFIG_AMCORE
#define CONFIG_HOSTNAME AMCORE
#define CONFIG_MCFTMR
#define __AP325RXA_H
#define CONFIG_CPU_SH7723 1
-#define CONFIG_AP325RXA 1
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define __AP_SH4A_4A_H
#define CONFIG_CPU_SH7734 1
-#define CONFIG_AP_SH4A_4A 1
#define CONFIG_400MHZ_MODE 1
#define CONFIG_SYS_TEXT_BASE 0x8BFC0000
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Ether */
-#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
#define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_SUPPORT_VFAT
/*
* Ethernet (on SOC imx FEC)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
/* SH Ether */
-#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x0
#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
#define CONFIG_ARMADA100 1 /* SOC Family Name */
#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
-#define CONFIG_MACH_ASPENITE /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
#error No card type defined!
#endif
-#define CONFIG_ASTRO5373L /* define board type */
-
/* Command line configuration */
/*
* CONFIG_RAM defines if u-boot is loaded via BDM (or started from
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN SZ_2M
-#define CONFIG_SYS_BOOTM_LEN SZ_32M
+#define CONFIG_SYS_BOOTM_LEN SZ_128M
#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#endif /* CONFIG_NAND */
/* USB configuration */
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
#else
#error "no storage for Environment defined!"
#endif
-/*
- * Common filesystems support. When we have removable storage we
- * enabled a number of useful commands and support.
- */
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_FS_EXT4
-#define CONFIG_EXT4_WRITE
-#endif /* CONFIG_MMC, ... */
#endif /* ! __CONFIG_BRPPT1_H__ */
#define CONFIG_INITRD_TAG
/* USB configuration */
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_CALIMAIN
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_TEXT_BASE 0x60000000
-#define CONFIG_DA850_LOWLEVEL
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_HW_WATCHDOG
/* NAND: SPL related configs */
/* USB configuration */
-#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB3PHY1_HOST
/* USB Networking options */
*/
#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
-/* Partition support */
-
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_ENV_OFFSET (768 * 1024)
#ifndef CONFIG_SPL_BUILD
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdtfile=undefined\0" \
"stdin=serial,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0" \
"fi;" \
"run setupnandboot;" \
"run nandboot;\0" \
+ "findfdt="\
+ "if test $board_name = Utilite && test $board_rev = MX6Q ; then " \
+ "setenv fdtfile imx6q-utilite-pro.dtb; fi; " \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine dtb to use; fi; \0" \
BOOTENV
#define CONFIG_PREBOOT "usb start;sf probe"
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-/* USB */
-#define CONFIG_USB_OMAP3
-#define CONFIG_USB_MUSB_UDC
-#define CONFIG_TWL4030_USB
-
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
115200}
/* USB */
-#define CONFIG_USB_MUSB_AM35X
#ifndef CONFIG_USB_MUSB_AM35X
-#define CONFIG_USB_OMAP3
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
-#else /* !CONFIG_USB_MUSB_AM35X */
-#define CONFIG_USB_MUSB_PIO_ONLY
#endif /* CONFIG_USB_MUSB_AM35X */
/* commands to include */
/* USB support */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
/* SPI Flash support */
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_CYRUS
-
#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
#error Must call Cyrus CONFIG with a specific CPU enabled.
#endif
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_DA8XX_GPIO
#define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
-#define CONFIG_DA850_LOWLEVEL
#else
#define CONFIG_SYS_TEXT_BASE 0xc1080000
#endif
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_CLOCKS
#endif
-#ifndef CONFIG_DRIVER_TI_EMAC
-#endif
-
#ifdef CONFIG_USE_NAND
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif
-#ifdef CONFIG_USE_SPIFLASH
-#endif
-
#if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_SYS_ALT_MEMTEST
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-/* Partition support */
-
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* Partition support */
-
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_MVEBU
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_DOCKSTAR /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB2PHY2_HOST
/* SATA */
#define CONFIG_SYS_TEXT_BASE 0x80080000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
-#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* UART */
"initrd_high=0xffffffffffffffff\0" \
"linux_image=Image\0" \
"kernel_addr_r=0x81000000\0"\
- "fdtfile=apq8016-sbc.dtb\0" \
+ "fdtfile=qcom/apq8016-sbc.dtb\0" \
"fdt_addr_r=0x83000000\0"\
"ramdisk_addr_r=0x84000000\0"\
"scriptaddr=0x90000000\0"\
--- /dev/null
+/*
+ * Board configuration file for Dragonboard 410C
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIGS_DRAGONBOARD820C_H
+#define __CONFIGS_DRAGONBOARD820C_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-apq8096.h>
+
+#define CONFIG_MISC_INIT_R /* To stop autoboot */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define PHYS_SDRAM_SIZE 0xC0000000
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE 0x60000000
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE 0x5ea4ffff
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_TEXT_BASE 0x80080000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define CONFIG_SYS_LDSCRIPT "board/qualcomm/dragonboard820c/u-boot.lds"
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 19000000
+
+/* Partition table support */
+#define HAVE_BLOCK_DEVICE
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#include <config_distro_bootcmd.h>
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x95000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "linux_image=uImage\0" \
+ "kernel_addr_r=0x95000000\0"\
+ "fdtfile=qcom/apq8096-db820c.dtb\0" \
+ "fdt_addr_r=0x93000000\0"\
+ "ramdisk_addr_r=0x91000000\0"\
+ "scriptaddr=0x90000000\0"\
+ "pxefile_addr_r=0x90100000\0"\
+ BOOTENV
+
+#define CONFIG_ENV_SIZE 0x4000
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 64
+
+#endif
#endif
/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
-#define CONFIG_SUPPORT_VFAT
#define CONFIG_SYS_MVFS
/*
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#include "tam3517-common.h"
-#undef CONFIG_USB_OMAP3
-
/* Our console port is port3 */
#undef CONFIG_CONS_INDEX
#undef CONFIG_SYS_NS16550_COM1
*/
#define CONFIG_CPU_SH7724 1
-#define CONFIG_ECOVEC 1
#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_SH_I2C_CLOCK 41666666
/* Ether */
-#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
#define CONFIG_PHY_SMSC 1
#define CONFIG_MARVELL 1
#define CONFIG_FEROCEON 1 /* CPU Core subversion */
#define CONFIG_88F5182 1 /* SOC Name */
-#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
#include <asm/arch/orion5x.h>
/*
*/
#ifdef CONFIG_CMD_USB
#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
-#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/*
#define __ESPT_H
#define CONFIG_CPU_SH7763 1
-#define CONFIG_ESPT 1
#define __LITTLE_ENDIAN 1
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_SYS_TMU_CLK_DIV 4
/* Ether */
-#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
#define CONFIG_BITBANGMII
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_GOFLEXHOME /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
#define CONFIG_SH_QSPI
/* SH Ether */
-#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */
-#define CONFIG_SUPPORT_VFAT
-
#endif /* __CONFIG_GPLUGD_H */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_MACH_GURUPLUG /* Machine type */
/*
* Standard filesystems
/* SD/MMC configuration */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FS_EXT4
-
/* Command line configuration */
#define CONFIG_MTD_PARTITIONS
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN SZ_2M
-#define CONFIG_SYS_BOOTM_LEN SZ_32M
+#define CONFIG_SYS_BOOTM_LEN SZ_128M
#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
*/
#define CONFIG_MPC831x
#define CONFIG_MPC8313
-#define CONFIG_IDS8313
#define CONFIG_FSL_ELBC
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
"findfdt="\
"if test $board_name = 66AK2GGP; then " \
"setenv name_fdt keystone-k2g-evm.dtb; " \
+ "else if test $board_name = 66AK2GG1; then " \
+ "setenv name_fdt keystone-k2g-evm.dtb; " \
"else if test $board_name = 66AK2GIC; then " \
"setenv name_fdt keystone-k2g-ice.dtb; " \
"else if test $name_fdt = undefined; then " \
"echo WARNING: Could not determine device tree to use;"\
- "fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
+ "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
"name_mon=skern-k2g.bin\0" \
"name_ubi=k2g-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2g-evm.gph\0" \
#endif
/* SPL SPI Loader Configuration */
-#define CONFIG_SPL_TEXT_BASE 0x0c080000
+#define CONFIG_SPL_TEXT_BASE 0x0c0a0000
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_2K
* USB gadget
*/
-#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_MUSB_OMAP2PLUS
-
/*
* Environment
*/
#define CONFIG_MARVELL
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CONFIG_SH_QSPI
/* SH Ether */
-#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_QSPI
/* SH Ether */
-#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 50000000
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012A2G5RDB_H__
+#define __LS1012A2G5RDB_H__
+
+#include "ls1012a_common.h"
+
+/* PFE Ethernet */
+#ifdef CONFIG_FSL_PFE
+#define EMAC1_PHY_ADDR 0x2
+#define EMAC2_PHY_ADDR 0x1
+#define CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_AQUANTIA
+#endif
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_NET_MULTI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x00f00000\0" \
+ "kernel_addr=0x01000000\0" \
+ "kernelheader_addr=0x800000\0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernelheader_size=0x40000\0" \
+ "console=ttyS0,115200\0" \
+ BOOTENV \
+ "boot_scripts=ls1012ardb_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1012ardb_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;" \
+ "\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0" \
+ "installer=load mmc 0:2 $load_addr " \
+ "/flex_installer_arm64.itb; " \
+ "bootm $load_addr#$board\0" \
+ "qspi_bootcmd=echo Trying load from qspi..;" \
+ "sf probe && sf read $load_addr " \
+ "$kernel_addr $kernel_size; env exists secureboot " \
+ "&& sf read $kernelheader_addr_r $kernelheader_addr " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#endif
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A2G5RDB_H__ */
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#include <config_distro_defaults.h>
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
+ func(SCSI, scsi, 0) \
func(MMC, mmc, 0) \
func(USB, usb, 0)
#include <config_distro_bootcmd.h>
#define CONFIG_SF_DEFAULT_BUS 1
#define CONFIG_SF_DEFAULT_CS 0
-/*
-* USB
-*/
-/* EHCI Support - disbaled by default */
-/*#define CONFIG_HAS_FSL_DR_USB*/
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_PCIE1 /* PCIE controller 1 */
#endif
#endif
-/*
- * USB
- */
-/* EHCI Support - disbaled by default */
-/*#define CONFIG_HAS_FSL_DR_USB*/
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
/*
* Video
*/
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-/*
- * USB
- */
-
-/*
- * EHCI Support - disbaled by default as
- * there is no signal coming out of soc on
- * this board for this controller. However,
- * the silicon still has this controller,
- * and anyone can use this controller by
- * taking signals out on their board.
- */
-
-/*#define CONFIG_HAS_FSL_DR_USB*/
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_PCI_SCAN_SHOW
#endif
+/* SATA */
+#ifndef SPL_NO_SATA
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
/* Command line configuration */
/* MMC */
#endif
#endif
-#ifndef SPL_NO_QBMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
-#endif
-
/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN
#include <config_distro_defaults.h>
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
+ func(SCSI, scsi, 0) \
func(MMC, mmc, 0) \
func(USB, usb, 0)
#include <config_distro_bootcmd.h>
#define CFG_LPUART_EN 0x2
#endif
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/*
* IFC Definitions
*/
#endif
#endif
-/* SATA */
-#ifndef SPL_NO_SATA
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
#ifndef SPL_NO_MISC
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT)
#ifndef __LS1088_COMMON_H
#define __LS1088_COMMON_H
+/* SPL build */
+#ifdef CONFIG_SPL_BUILD
+#define SPL_NO_BOARDINFO
+#define SPL_NO_QIXIS
+#define SPL_NO_PCI
+#define SPL_NO_ENV
+#define SPL_NO_RTC
+#define SPL_NO_USB
+#define SPL_NO_SATA
+#define SPL_NO_QSPI
+#define SPL_NO_IFC
+#undef CONFIG_DISPLAY_CPUINFO
+#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_SUPPORT_RAW_INITRD
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
+#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \
+ CONFIG_ENV_OFFSET)
+#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
/* IFC */
#define CONFIG_FSL_IFC
+#endif
/*
* During booting, IFC is mapped at the region of 0x30000000.
/* #define CONFIG_DISPLAY_CPUINFO */
+#ifndef SPL_NO_ENV
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#endif
+#endif
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
+#ifndef SPL_NO_ENV
#define CONFIG_CMDLINE_EDITING 1
+#endif
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 64 /* max command args */
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN 0x100000
+#endif /* ifdef CONFIG_SECURE_BOOT */
+
#endif
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
#define QIXIS_LBMAP_DFLTBANK 0x0e
#define QIXIS_LBMAP_ALTBANK 0x2e
#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_EMMC 0x00
+#define QIXIS_LBMAP_IFC 0x00
#define QIXIS_LBMAP_SD_QSPI 0x0e
#define QIXIS_LBMAP_QSPI 0x0e
+#define QIXIS_RCW_SRC_IFC 0x25
#define QIXIS_RCW_SRC_SD 0x40
+#define QIXIS_RCW_SRC_EMMC 0x41
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_CTL_RESET 0x41
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH5 0xD
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define I2C_SVDD_MONITOR_ADDR 0x4F
+
+#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed for LS1088AQDS */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+
+#define PWM_CHANNEL0 0x0
+
/*
* RTC configuration
*/
#include "ls1088a_common.h"
+#ifndef SPL_NO_BOARDINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
+#endif
#define CONFIG_MISC_INIT_R
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
#endif
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_QIXIS_I2C_ACCESS
+#endif
#define SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#endif
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif
#endif
+
+#ifndef SPL_NO_IFC
#define CONFIG_NAND_FSL_IFC
+#endif
+
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#ifndef SPL_NO_QIXIS
#define CONFIG_FSL_QIXIS
+#endif
+
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_BRDCFG4_OFFSET 0x54
#define QIXIS_LBMAP_SWITCH 2
#define QIXIS_QMAP_MASK 0xe0
#define QIXIS_QMAP_SHIFT 5
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x20
#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_EMMC 0x00
#define QIXIS_LBMAP_SD_QSPI 0x00
#define QIXIS_LBMAP_QSPI 0x00
#define QIXIS_RCW_SRC_SD 0x40
+#define QIXIS_RCW_SRC_EMMC 0x41
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define I2C_SVDD_MONITOR_ADDR 0x4F
+
+#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed for LS1088ARDB */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+
+#define PWM_CHANNEL0 0x0
+
/*
* I2C bus multiplexer
*/
#define I2C_RETIMER_ADDR 0x18
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH5 0xD
+
+#ifndef SPL_NO_RTC
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#define CONFIG_CMD_DATE
+#endif
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#ifndef SPL_NO_QSPI
/* QSPI device */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_QSPI
#define FSL_QSPI_FLASH_SIZE (1 << 26)
#define FSL_QSPI_FLASH_NUM 2
#endif
+#endif
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_FSL_MEMAC
+#ifndef SPL_NO_ENV
/* Initial environment variables */
#if defined(CONFIG_QSPI_BOOT)
#define MC_INIT_CMD \
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE
#endif
+#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
+#ifndef SPL_NO_ENV
#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>
func(SCSI, scsi, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
+#endif
#include <asm/fsl_secure_boot.h>
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFC000000
/* CPU and platform */
#define CONFIG_CPU_SH7720 1
-#define CONFIG_MPR2 1
#define CONFIG_DISPLAY_BOARDINFO
#define __MS7720SE_H
#define CONFIG_CPU_SH7720 1
-#define CONFIG_MS7720SE 1
#define CONFIG_BOOTFILE "/boot/zImage"
#define CONFIG_LOADADDR 0x8E000000
#define __MS7722SE_H
#define CONFIG_CPU_SH7722 1
-#define CONFIG_MS7722SE 1
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_CPU_SH7750 1
/* #define CONFIG_CPU_SH7751 1 */
/* #define CONFIG_CPU_TYPE_R 1 */
-#define CONFIG_MS7750SE 1
#define __LITTLE_ENDIAN__ 1
#define CONFIG_DISPLAY_BOARDINFO
#ifdef CONFIG_CMD_SF
#endif
-/*
- * Common USB/EHCI configuration
- */
-#if defined(CONFIG_CMD_USB) && !defined(CONFIG_DM)
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_CMD_USB */
-
/*
* File system
*/
/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SUPPORT_VFAT
+#include <config_distro_defaults.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(SCSI, scsi, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x4d00000\0" \
+ "pxefile_addr_r=0x4e00000\0" \
+ "fdt_addr_r=0x4f00000\0" \
+ "kernel_addr_r=0x5000000\0" \
+ "ramdisk_addr_r=0x8000000\0" \
+ BOOTENV
#endif /* _CONFIG_MVEBU_ARMADA_37XX_H */
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SUPPORT_VFAT
-
/*
* PCI configuration
*/
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
-/* U-Boot commands */
-
-/* Filesystem support */
-#define CONFIG_FS_EXT4
-
/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0x1f
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* I2C Configs */
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_MII
#endif
#endif
-#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_ENV_OFFSET (14 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SOFT_SPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 40000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM 1
+#define FSL_QSPI_FLASH_SIZE SZ_32M
+#endif
+
#endif
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/*
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
-/* USB */
-#define CONFIG_USB_MUSB_UDC
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_OMAP3
-#define CONFIG_TWL4030_USB
-
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USBD_VENDORID 0x0421
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_SEPARATE
+#define CONFIG_OF_EMBED
+#endif
+#else
+#define CONFIG_SYS_TEXT_BASE 0x80000000
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+/*
+ * Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * max number of command args
+ */
+#define CONFIG_SYS_MAXARGS 16
+
+/*
+ * Boot Argument Buffer Size
+ */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
+ */
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1 \
+ (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
+#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#endif
+#define CONFIG_SYS_NS16550_CLK 19660800
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_FTSDC010_NUMBER 1
+#define CONFIG_FTSDC010_SDIO
+
+/* Init Stack Pointer */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Load address and memory test area should agree with
+ * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
+
+/*
+ * memtest works on 512 MB in DRAM
+ */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
+
+/* environments */
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SECT_SIZE 0x1000
+#define CONFIG_ENV_OVERWRITE
+
+/* SPI FLASH */
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
+/* Increase max gunzip size */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
+#endif /* __CONFIG_H */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#include <configs/ti_omap3_common.h>
+
/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs. We use this rather than the inherited defines from
- * ti_armv7_common.h for backwards compatibility.
+ * We are only ever GP parts and will utilize all of the "downloaded image"
+ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
*/
-#define CONFIG_SYS_TEXT_BASE 0x80100000
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE 0x40200000
-#include <configs/ti_omap3_common.h>
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_MISC_INIT_R
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
-#define CONFIG_REVISION_TAG 1
+/* NAND */
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
+/* NAND: SPL falcon mode configs */
+#if defined(CONFIG_SPL_OS_BOOT)
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#endif /* CONFIG_SPL_OS_BOOT */
+#endif /* CONFIG_NAND */
-/* Status LED */
-
-/* Enable Multi Bus support for I2C */
-#define CONFIG_I2C_MULTI_BUS 1
-
-/* Probe all devices */
-#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
-
-/* USB */
-#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_TWL4030_USB 1
+/* MUSB */
+#define CONFIG_USB_OMAP3
/* USB EHCI */
-
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
-/* commands to include */
-
-#define CONFIG_VIDEO_OMAP3 /* DSS Support */
+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_LED 1
+/* DSS Support */
+#define CONFIG_VIDEO_OMAP3
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
- /* devices */
+/* TWL4030 LED Support */
+#define CONFIG_TWL4030_LED
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
"run bootscript; " \
"else " \
"if run loadimage; then " \
+ "run loadfdt;" \
"run mmcboot;" \
"fi;" \
"fi; " \
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "kernel_addr_r=0x80200000\0" \
- "rdaddr=0x81000000\0" \
- "initrd_addr_r=0x81000000\0" \
+ DEFAULT_LINUX_BOOT_ENV \
"fdt_high=0xffffffff\0" \
- "fdtaddr=0x80f80000\0" \
- "fdt_addr_r=0x80f80000\0" \
"usbtty=cdc_acm\0" \
"bootfile=uImage\0" \
"ramdisk=ramdisk.gz\0" \
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
"nandroot=ubi0:rootfs ubi.mtd=4\0" \
"nandrootfstype=ubifs\0" \
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0" \
"loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcboot=echo Booting from mmc ...; " \
+ "mmcboot=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
"run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
+ "bootm ${loadaddr} - ${fdtaddr}\0" \
+ "mmcbootz=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
"run mmcargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"userbutton_nonxm=gpio input 7;\0" \
BOOTENV
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_ADDR 0x260000
-
-/* Defines for SPL */
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#endif
-
#endif /* __CONFIG_H */
#endif /* CONFIG_NAND */
/* MUSB */
-#define CONFIG_USB_OMAP3
-#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_USB_MUSB_PIO_ONLY
/* USB EHCI */
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
#define MEM_LAYOUT_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) && defined(CONFIG_CMD_UBI)
+/* NAND boot with uImage from NAND 'kernel' partition */
#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"run nandboot\0"
-
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
#devtypel #instance " "
-#endif /* CONFIG_NAND */
+/* NAND boot with zImage from UBIFS '/boot/zImage' */
+#define BOOTENV_DEV_UBIFS_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "run nandbootubifs\0"
+#define BOOTENV_DEV_NAME_UBIFS_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+#endif /* CONFIG_NAND && CONFIG_CMD_UBI */
+
+/* MMC boot with uImage from MMC 0:2 '/boot/uImage' */
#define BOOTENV_DEV_UIMAGE_MMC(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"setenv mmcdev " #instance"; " \
"run mmcboot\0"
-
#define BOOTENV_DEV_NAME_UIMAGE_MMC(devtypeu, devtypel, instance) \
#devtypel #instance " "
+/* MMC boot with zImage from MMC 0:2 '/boot/zImage' */
#define BOOTENV_DEV_ZIMAGE_MMC(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"setenv mmcdev " #instance"; " \
"run mmcbootz\0"
-
#define BOOTENV_DEV_NAME_ZIMAGE_MMC(devtypeu, devtypel, instance) \
#devtypel #instance " "
func(MMC, mmc, 0) \
func(ZIMAGE_MMC, zimage_mmc, 0) \
func(UIMAGE_MMC, uimage_mmc, 0) \
+ func(UBIFS_NAND, ubifs_nand, 0) \
func(NAND, nand, 0)
#include <config_distro_bootcmd.h>
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"fdt_high=0xffffffff\0" \
+ "bootdir=/boot\0" \
"bootenv=uEnv.txt\0" \
"optargs=\0" \
"mmcdev=0\0" \
+ "mmcpart=2\0" \
"console=ttyO0,115200n8\0" \
"mmcargs=setenv bootargs console=${console} " \
"${mtdparts} " \
"root=ubi0:rootfs rw ubi.mtd=rootfs noinitrd " \
"rootfstype=ubifs rootwait\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "ext4bootenv=ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
- "mmcbootenv=" \
- "mmc dev ${mmcdev}; " \
- "if mmc rescan && run loadbootenv; then " \
- "run importbootenv; " \
+ "mmcbootenv=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "run loadbootenv && run importbootenv; " \
+ "run ext4bootenv && run importbootenv; " \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...; " \
"run uenvcmd; " \
"fi; " \
"fi\0" \
"loaduimage=setenv bootfile uImage; " \
- "fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadzimage=setenv bootfile zImage; " \
- "fatload mmc ${mmcdev} ${loadaddr} zImage\0" \
- "loaddtb=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+ "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loaddtb=ext4load mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "loadubizimage=setenv bootfile zImage; " \
+ "ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadubidtb=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcboot=run mmcbootenv; " \
"if run loaduimage && run loaddtb; then " \
- "echo Booting ${bootfile} from mmc ...; " \
+ "echo Booting ${bootdir}/${bootfile} from mmc ${mmcdev}:${mmcpart} ...; " \
"run mmcargs; " \
"bootm ${loadaddr} - ${fdtaddr}; " \
"fi\0" \
"mmcbootz=run mmcbootenv; " \
"if run loadzimage && run loaddtb; then " \
- "echo Booting ${bootfile} from mmc ...; " \
+ "echo Booting ${bootdir}/${bootfile} from mmc ${mmcdev}:${mmcpart} ...; " \
"run mmcargs; " \
- "bootz ${loadaddr} - ${fdtaddr};" \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
"fi\0" \
- "nandboot=echo Booting uImage from nand ...; " \
- "run nandargs; " \
+ "nandboot=" \
"nand read ${loadaddr} kernel; " \
"nand read ${fdtaddr} dtb; " \
+ "echo Booting uImage from NAND MTD 'kernel' partition ...; " \
+ "run nandargs; " \
"bootm ${loadaddr} - ${fdtaddr}\0" \
+ "nandbootubifs=" \
+ "ubi part rootfs; " \
+ "ubifsmount ubi0:rootfs; " \
+ "if run loadubizimage && run loadubidtb; then " \
+ "echo Booting ${bootdir}/${bootfile} from NAND ubi0:rootfs ...; " \
+ "run nandargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "fi\0" \
BOOTENV
#endif /* __CONFIG_H */
#define GPIO_IGEP00X0_BOARD_DETECTION 28
#define GPIO_IGEP00X0_REVISION_DETECTION 129
-/* USB */
-#define CONFIG_USB_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-#define CONFIG_TWL4030_USB 1
-
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
/* Hardware drivers */
-#define CONFIG_USB_OMAP3
-
/* I2C */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
-/* USB */
-#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_USB_MUSB_PIO_ONLY
-
-/* TWL4030 */
-#define CONFIG_TWL4030_USB
-
/* Board NAND Info. */
#ifdef CONFIG_NAND
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
* Hardware drivers
*/
-/* USB */
-#define CONFIG_USB_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-#define CONFIG_TWL4030_USB 1
-
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
*/
#define CONFIG_MACH_OMAPL138_LCDK
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 30000000
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_OPENRD_BASE /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
/* PCI host support */
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
+ "ramdisk_addr_r\0" \
+ "kernel_addr_r_align=00200000\0" \
+ "kernel_addr_r_offset=00080000\0" \
+ "kernel_addr_r_size=02000000\0" \
+ "kernel_addr_r_aliases=loadaddr\0" \
+ "fdt_addr_r_align=00200000\0" \
+ "fdt_addr_r_offset=00000000\0" \
+ "fdt_addr_r_size=00200000\0" \
+ "scriptaddr_align=00200000\0" \
+ "scriptaddr_offset=00000000\0" \
+ "scriptaddr_size=00200000\0" \
+ "pxefile_addr_r_align=00200000\0" \
+ "pxefile_addr_r_offset=00000000\0" \
+ "pxefile_addr_r_size=00200000\0" \
+ "ramdisk_addr_r_align=00200000\0" \
+ "ramdisk_addr_r_offset=00000000\0" \
+ "ramdisk_addr_r_size=02000000\0"
+
#include "tegra-common-post.h"
/* Crystal is 38.4MHz. clk_m runs at half that rate */
#define COUNTER_FREQUENCY 19200000
+#undef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS (1024 + 2)
+
#endif
/*
* USB configuration
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
* board schematic and physical port wired to each. Then for host we
* add mass storage support.
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
/*--------------------------------------------------
* USB Configuration
*/
-#define CONFIG_USB_MUSB_PIO_ONLY
-
-/*-----------------------------------------------------------------------
- * File System Configuration
- */
-/* FAT FS */
-#define CONFIG_SUPPORT_VFAT
-
-/* EXT4 FS */
-#define CONFIG_FS_EXT4
/* -------------------------------------------------
* Environment
#define CONFIG_NR_DRAM_BANKS 2
/* SYS */
-#define CONFIG_SYS_BOOTM_LEN 0x1400000
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_SYS_INIT_SP_ADDR 0x200000
#define CONFIG_SYS_LOAD_ADDR 0x800000
#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (0x780 * 512) /* env_mmc_blknum */
#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */
-#define CONFIG_FAT_WRITE
#define CONFIG_ENV_VARS_UBOOT_CONFIG
/* Monitor Command Prompt */
#define CONFIG_SPI_FLASH_QUAD
/* SH Ether */
-#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define __R0P7734_H
#define CONFIG_CPU_SH7734 1
-#define CONFIG_R0P7734 1
#define CONFIG_400MHZ_MODE 1
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Ether */
-#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
#define CONFIG_PHY_SMSC 1
#define __CONFIG_H
#define CONFIG_CPU_SH7751 1
-#define CONFIG_CPU_SH_TYPE_R 1
-#define CONFIG_R2DPLUS 1
#define __LITTLE_ENDIAN__ 1
#define CONFIG_DISPLAY_BOARDINFO
#include <asm/arch/rmobile.h>
-/* Support File sytems */
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-#define CONFIG_EXT4_WRITE
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* boot option */
#define CONFIG_SUPPORT_RAW_INITRD
-/* Support File sytems */
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-#define CONFIG_EXT4_WRITE
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* MMC/SD IP block */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#ifndef CONFIG_SPL_BUILD
/* usb otg */
-#define CONFIG_ROCKCHIP_USB2_PHY
/* usb host support */
#define ENV_MEM_LAYOUT_SETTINGS \
#ifndef CONFIG_SPL_BUILD
/* usb otg */
-#define CONFIG_ROCKCHIP_USB2_PHY
/* usb mass storage */
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* MMC/SD IP block */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define __RSK7203_H
#define CONFIG_CPU_SH7203 1
-#define CONFIG_RSK7203 1
#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
#define __RSK7264_H
#define CONFIG_CPU_SH7264 1
-#define CONFIG_RSK7264 1
#define CONFIG_DISPLAY_BOARDINFO
#define __RSK7269_H
#define CONFIG_CPU_SH7269 1
-#define CONFIG_RSK7269 1
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5P 1 /* which is in a S5P Family */
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
-#define CONFIG_MACH_GONI 1 /* working with Goni */
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_SAMSUNG_ONENAND 1
#define CONFIG_SYS_ONENAND_BASE 0xB0000000
-/* write support for filesystems */
-#define CONFIG_EXT4_WRITE
-
-/* GPT */
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
#define CONFIG_LMB
-#define CONFIG_FS_EXT4
-#define CONFIG_EXT4_WRITE
#define CONFIG_HOST_MAX_DEVICES 4
/*
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC834x 1 /* MPC834x family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
#define CONFIG_SYS_TEXT_BASE 0xFF800000
/*
* High Level Configuration Options
*/
-#define CONFIG_SBC8548 1 /* SBC8548 board specific */
/*
* If you want to boot from the SODIMM flash, instead of the soldered
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define __SH7752EVB_H
#define CONFIG_CPU_SH7752 1
-#define CONFIG_SH7752EVB 1
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* Ether */
-#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 18
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define __SH7753EVB_H
#define CONFIG_CPU_SH7753 1
-#define CONFIG_SH7753EVB 1
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* Ether */
-#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 18
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define __SH7757LCR_H
#define CONFIG_CPU_SH7757 1
-#define CONFIG_SH7757LCR 1
#define CONFIG_SH7757LCR_DDR_ECC 1
#define CONFIG_SYS_TEXT_BASE 0x8ef80000
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* Ether */
-#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define __SH7763RDP_H
#define CONFIG_CPU_SH7763 1
-#define CONFIG_SH7763RDP 1
#define __LITTLE_ENDIAN 1
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
/* Ether */
-#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
#define CONFIG_BITBANGMII
#define __SH7785LCR_H
#define CONFIG_CPU_SH7785 1
-#define CONFIG_SH7785LCR 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootdevice=0:1\0" \
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
/*
* Commands configuration
/*
* USB configuration
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_SPI_FLASH_QUAD
/* SH Ether */
-#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
--- /dev/null
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#ifndef __SKSIMX6_CONFIG_H
+#define __SKSIMX6_CONFIG_H
+
+#include <config_distro_defaults.h>
+
+#include "mx6_common.h"
+#include "imx6_spl.h"
+
+/* Thermal */
+#define CONFIG_IMX_THERMAL
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
+
+/* Ethernet */
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0x01
+
+#define CONFIG_MII
+#define CONFIG_PHY_MICREL_KSZ9021
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* Filesystem support */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "addcons=setenv bootargs ${bootargs} " \
+ "console=${console},${baudrate}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off\0" \
+ "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \
+ "bootcmd=run mmcboot\0" \
+ "bootfile=uImage\0" \
+ "bootimage=uImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_addr_r=0x18000000\0" \
+ "fdt_file=imx6dl-sks-cts.dtb\0" \
+ "fdt_high=0xffffffff\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "miscargs=quiet\0" \
+ "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \
+ "mmcboot=if run mmcload;then " \
+ "run mmcargs addcons addmisc;" \
+ "bootm;fi\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p1\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \
+ "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \
+ "run nfsargs addip addcons addmisc;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs " \
+ "nfsroot=${serverip}:${nfsroot},v3 panic=1\0"
+
+#endif
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
115200 }
-/*
- * USB gadget
- */
-
-#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_TWL4030_USB
-
/*
* Environment
*/
* Configuration of the external SDRAM memory
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_RAM_SIZE (8 << 20)
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
#define CONFIG_SYS_RAM_BASE 0xD0000000
#define CONFIG_RED_LED 110
#define CONFIG_GREEN_LED 109
-#define CONFIG_STM32_GPIO
#define CONFIG_STM32_FLASH
-#define CONFIG_STM32_SERIAL
#define CONFIG_STM32_HSE_HZ 8000000
--- /dev/null
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_STM32F4DISCOVERY
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_FLASH_BASE 0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_RAM_FREQ_DIV 2
+#define CONFIG_SYS_RAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
+#define CONFIG_SYS_LOAD_ADDR 0x00400000
+#define CONFIG_LOADADDR 0x00400000
+
+#define CONFIG_SYS_MAX_FLASH_SECT 12
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE (128 << 10)
+#define CONFIG_ENV_SIZE (8 << 10)
+
+#define CONFIG_STM32_FLASH
+
+#define CONFIG_STM32_HSE_HZ 8000000
+#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
+#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE 1024
+
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+
+#define CONFIG_BOOTCOMMAND \
+ "run boot_sd"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32f469-disco.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000"
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#endif /* __CONFIG_H */
#ifndef __STMARK2_CONFIG_H
#define __STMARK2_CONFIG_H
-#define CONFIG_STMARK2
#define CONFIG_HOSTNAME stmark2
#define CONFIG_MCFUART
#define CONFIG_SPI_FLASH_QUAD
/* SH Ether */
-#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif
-#ifdef CONFIG_USB_MUSB_SUNXI
-#define CONFIG_USB_MUSB_PIO_ONLY
-#endif
-
#ifdef CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#endif
#ifdef CONFIG_CMD_I2C
#endif
-/* remove partitions/filesystems */
-#ifdef CONFIG_FS_EXT4
-#undef CONFIG_FS_EXT4
-#endif
-
/* remove USB */
#ifdef CONFIG_USB_EHCI_TEGRA
#undef CONFIG_USB_EHCI_TEGRA
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+#ifndef CONFIG_ARM64
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+#endif
+#ifndef CONFIG_ARM64
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
+#endif
/* Misc utility code */
#define CONFIG_BOUNCE_BUFFER
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_STACKBASE 0x82800000 /* 40MB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x80108000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
-#define CONFIG_SPL_STACK 0x800ffffc
-
#endif
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_STACKBASE 0x82800000 /* 40MB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x80108000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
-#define CONFIG_SPL_STACK 0x800ffffc
-
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* PCIe support */
#ifdef CONFIG_CMD_PCI
#ifndef CONFIG_SPL_BUILD
#endif
/* SPI Configuration */
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
"${bootdir}/${fit_bootfile}\0" \
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
- "burn_uboot_spi=sf probe; sf erase 0 0x90000; " \
+ "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
"sf write ${loadaddr} 0 ${filesize}\0" \
"burn_uboot_nand=nand erase 0 0x100000; " \
"nand write ${loadaddr} 0 ${filesize}\0" \
#endif
/* USB */
-#define CONFIG_USB_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
* Commands
*/
#if defined(CONFIG_CMD_USB)
-#define CONFIG_SUPPORT_VFAT
/*
* USB/EHCI
#define CONFIG_E300 1
#define CONFIG_MPC831x 1
#define CONFIG_MPC8313 1
-#define CONFIG_VE8313 1
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfe000000
#define CONFIG_USB_EHCI_SPEAR
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-/* Filesystem support (for USB key) */
-#define CONFIG_SUPPORT_VFAT
-
-
/*
* U-Boot Environment placing definitions.
*/
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SUPPORT_VFAT
-
/*-----------------------------------------------------------------------
* Command line configuration.
*/
/*
* High Level Configuration Options
*/
-#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
/*
* High Level Configuration Options
*/
-#define CONFIG_XPEDITE5200 1
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
/*
* High Level Configuration Options
*/
-#define CONFIG_XPEDITE550X 1
#define CONFIG_SYS_BOARD_NAME "XPedite5500"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/* SDRAM */
# define DFU_ALT_INFO
#endif
-#if defined(CONFIG_MMC_SDHCI_ZYNQ) || defined(CONFIG_ZYNQ_USB)
-# define CONFIG_SUPPORT_VFAT
-#endif
-
#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
#define CONFIG_SYS_I2C_ZYNQ
#endif
ofnode_valid(node); \
node = ofnode_next_subnode(node))
+/**
+ * ofnode_translate_address() - Tranlate a device-tree address
+ *
+ * Translate an address from the device-tree into a CPU physical address. This
+ * function walks up the tree and applies the various bus mappings along the
+ * way.
+ *
+ * @ofnode: Device tree node giving the context in which to translate the
+ * address
+ * @in_addr: pointer to the address to translate
+ * @return the translated address; OF_BAD_ADDR on error
+ */
+u64 ofnode_translate_address(ofnode node, const fdt32_t *in_addr);
#endif
/**
* Generic pin configuration paramters
*
+ * enum pin_config_param - possible pin configuration parameters
+ * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
+ * weakly drives the last value on a tristate bus, also known as a "bus
+ * holder", "bus keeper" or "repeater". This allows another device on the
+ * bus to change the value by driving the bus high or low and switching to
+ * tristate. The argument is ignored.
* @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
* transition from say pull-up to pull-down implies that you disable
* pull-up in the process, this setting disables all biasing.
* if for example some other pin is going to drive the signal connected
* to it for a while. Pins used for input are usually always high
* impedance.
- * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
- * weakly drives the last value on a tristate bus, also known as a "bus
- * holder", "bus keeper" or "repeater". This allows another device on the
- * bus to change the value by driving the bus high or low and switching to
- * tristate. The argument is ignored.
- * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
- * impedance to VDD). If the argument is != 0 pull-up is enabled,
- * if it is 0, pull-up is total, i.e. the pin is connected to VDD.
* @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
* impedance to GROUND). If the argument is != 0 pull-down is enabled,
* if it is 0, pull-down is total, i.e. the pin is connected to GROUND.
* If the argument is != 0 pull up/down is enabled, if it is 0, the
* configuration is ignored. The proper way to disable it is to use
* @PIN_CONFIG_BIAS_DISABLE.
- * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
- * low, this is the most typical case and is typically achieved with two
- * active transistors on the output. Setting this config will enable
- * push-pull mode, the argument is ignored.
+ * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
+ * impedance to VDD). If the argument is != 0 pull-up is enabled,
+ * if it is 0, pull-up is total, i.e. the pin is connected to VDD.
* @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
* collector) which means it is usually wired with other output ports
* which are then pulled up with an external resistor. Setting this
* @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
* (open emitter). Setting this config will enable open source mode, the
* argument is ignored.
+ * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
+ * low, this is the most typical case and is typically achieved with two
+ * active transistors on the output. Setting this config will enable
+ * push-pull mode, the argument is ignored.
* @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current
* passed as argument. The argument is in mA.
+ * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
+ * which means it will wait for signals to settle when reading inputs. The
+ * argument gives the debounce time in usecs. Setting the
+ * argument to zero turns debouncing off.
* @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does not
* affect the pin's ability to drive output. 1 enables input, 0 disables
* input.
- * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
- * If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
- * schmitt-trigger mode is disabled.
* @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
* schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
* the threshold value is given on a custom format as argument when
* setting pins to this mode.
- * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
- * which means it will wait for signals to settle when reading inputs. The
- * argument gives the debounce time in usecs. Setting the
- * argument to zero turns debouncing off.
+ * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
+ * If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
+ * schmitt-trigger mode is disabled.
+ * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
+ * operation, if several modes of operation are supported these can be
+ * passed in the argument on a custom form, else just use argument 1
+ * to indicate low power mode, argument 0 turns low power mode off.
+ * @PIN_CONFIG_OUTPUT_ENABLE: this will enable the pin's output mode
+ * without driving a value there. For most platforms this reduces to
+ * enable the output buffers and then let the pin controller current
+ * configuration (eg. the currently selected mux function) drive values on
+ * the line. Use argument 1 to enable output mode, argument 0 to disable
+ * it.
+ * @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a
+ * value on the line. Use argument 1 to indicate high level, argument 0 to
+ * indicate low level. (Please see Documentation/driver-api/pinctl.rst,
+ * section "GPIO mode pitfalls" for a discussion around this parameter.)
* @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
* supplies, the argument to this parameter (on a custom format) tells
* the driver which alternative power source to use.
+ * @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state.
* @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
* this parameter (on a custom format) tells the driver which alternative
* slew rate to use.
- * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
- * operation, if several modes of operation are supported these can be
- * passed in the argument on a custom form, else just use argument 1
- * to indicate low power mode, argument 0 turns low power mode off.
- * @PIN_CONFIG_OUTPUT: this will configure the pin as an output. Use argument
- * 1 to indicate high level, argument 0 to indicate low level. (Please
- * see Documentation/pinctrl.txt, section "GPIO mode pitfalls" for a
- * discussion around this parameter.)
+ * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs)
+ * or latch delay (on outputs) this parameter (in a custom format)
+ * specifies the clock skew or latch delay. It typically controls how
+ * many double inverters are put in front of the line.
* @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
* you need to pass in custom configurations to the pin controller, use
* PIN_CONFIG_END+1 as the base offset.
+ * @PIN_CONFIG_MAX: this is the maximum configuration value that can be
+ * presented using the packed format.
*/
-#define PIN_CONFIG_BIAS_DISABLE 0
-#define PIN_CONFIG_BIAS_HIGH_IMPEDANCE 1
-#define PIN_CONFIG_BIAS_BUS_HOLD 2
-#define PIN_CONFIG_BIAS_PULL_UP 3
-#define PIN_CONFIG_BIAS_PULL_DOWN 4
-#define PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 5
-#define PIN_CONFIG_DRIVE_PUSH_PULL 6
-#define PIN_CONFIG_DRIVE_OPEN_DRAIN 7
-#define PIN_CONFIG_DRIVE_OPEN_SOURCE 8
-#define PIN_CONFIG_DRIVE_STRENGTH 9
-#define PIN_CONFIG_INPUT_ENABLE 10
-#define PIN_CONFIG_INPUT_SCHMITT_ENABLE 11
-#define PIN_CONFIG_INPUT_SCHMITT 12
-#define PIN_CONFIG_INPUT_DEBOUNCE 13
-#define PIN_CONFIG_POWER_SOURCE 14
-#define PIN_CONFIG_SLEW_RATE 15
-#define PIN_CONFIG_LOW_POWER_MODE 16
-#define PIN_CONFIG_OUTPUT 17
-#define PIN_CONFIG_END 0x7FFF
+enum pin_config_param {
+ PIN_CONFIG_BIAS_BUS_HOLD,
+ PIN_CONFIG_BIAS_DISABLE,
+ PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+ PIN_CONFIG_BIAS_PULL_DOWN,
+ PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
+ PIN_CONFIG_BIAS_PULL_UP,
+ PIN_CONFIG_DRIVE_OPEN_DRAIN,
+ PIN_CONFIG_DRIVE_OPEN_SOURCE,
+ PIN_CONFIG_DRIVE_PUSH_PULL,
+ PIN_CONFIG_DRIVE_STRENGTH,
+ PIN_CONFIG_INPUT_DEBOUNCE,
+ PIN_CONFIG_INPUT_ENABLE,
+ PIN_CONFIG_INPUT_SCHMITT,
+ PIN_CONFIG_INPUT_SCHMITT_ENABLE,
+ PIN_CONFIG_LOW_POWER_MODE,
+ PIN_CONFIG_OUTPUT_ENABLE,
+ PIN_CONFIG_OUTPUT,
+ PIN_CONFIG_POWER_SOURCE,
+ PIN_CONFIG_SLEEP_HARDWARE_STATE,
+ PIN_CONFIG_SLEW_RATE,
+ PIN_CONFIG_SKEW_DELAY,
+ PIN_CONFIG_END = 0x7F,
+ PIN_CONFIG_MAX = 0xFF,
+};
#if CONFIG_IS_ENABLED(PINCTRL_GENERIC)
/**
}
#ifndef CONFIG_DM_DEV_READ_INLINE
+/**
+ * dev_read_u32() - read a 32-bit integer from a device's DT property
+ *
+ * @dev: device to read DT property from
+ * @propname: name of the property to read from
+ * @outp: place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int dev_read_u32(struct udevice *dev, const char *propname, u32 *outp);
+
/**
* dev_read_u32_default() - read a 32-bit integer from a device's DT property
*
int dev_read_resource_byname(struct udevice *dev, const char *name,
struct resource *res);
+/**
+ * dev_translate_address() - Tranlate a device-tree address
+ *
+ * Translate an address from the device-tree into a CPU physical address. This
+ * function walks up the tree and applies the various bus mappings along the
+ * way.
+ *
+ * @dev: device giving the context in which to translate the address
+ * @in_addr: pointer to the address to translate
+ * @return the translated address; OF_BAD_ADDR on error
+ */
+u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr);
#else /* CONFIG_DM_DEV_READ_INLINE is enabled */
+static inline int dev_read_u32(struct udevice *dev,
+ const char *propname, u32 *outp)
+{
+ return ofnode_read_u32(dev_ofnode(dev), propname, outp);
+}
+
static inline int dev_read_u32_default(struct udevice *dev,
const char *propname, int def)
{
return ofnode_read_resource_byname(dev_ofnode(dev), name, res);
}
+static inline u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr)
+{
+ return ofnode_translate_address(dev_ofnode(dev), in_addr);
+}
+
#endif /* CONFIG_DM_DEV_READ_INLINE */
/**
UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
UCLASS_DMA, /* Direct Memory Access */
+ UCLASS_EFI, /* EFI managed devices */
UCLASS_ETH, /* Ethernet device */
UCLASS_GPIO, /* Bank of general-purpose I/O pins */
UCLASS_FIRMWARE, /* Firmware */
* then this will be automatically allocated.
* @per_child_auto_alloc_size: Each child device (of a parent in this
* uclass) can hold parent data for the device/uclass. This value is only
- * used as a falback if this member is 0 in the driver.
+ * used as a fallback if this member is 0 in the driver.
* @per_child_platdata_auto_alloc_size: A bus likes to store information about
* its children. If non-zero this is the size of this data, to be allocated
* in the child device's parent_platdata pointer. This value is only used as
- * a falback if this member is 0 in the driver.
+ * a fallback if this member is 0 in the driver.
* @ops: Uclass operations, providing the consistent interface to devices
* within the uclass.
* @flags: Flags for this uclass (DM_UC_...)
#define CLK_SYS_UART_REF 18
#define CLK_SYS_EBI_REF 19
#define CLK_TUN_PLL 20
-#define CLK_TUN 21
-#define CLK_HDMI_PLL 22
-#define CLK_HDMI 23
+#define CLK_TUN_TUN 21
+#define CLK_TUN_ROM 22
+#define CLK_TUN_PWM 23
+#define CLK_HDMI_PLL 24
+#define CLK_HDMI 25
#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
--- /dev/null
+/*
+ * This header provides constants for pca9532 LED bindings.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _DT_BINDINGS_LEDS_PCA9532_H
+#define _DT_BINDINGS_LEDS_PCA9532_H
+
+#define PCA9532_TYPE_NONE 0
+#define PCA9532_TYPE_LED 1
+#define PCA9532_TYPE_N2100_BEEP 2
+#define PCA9532_TYPE_GPIO 3
+#define PCA9532_LED_TIMER2 4
+
+#endif /* _DT_BINDINGS_LEDS_PCA9532_H */
/* Timing = value +1 cycles */
#define TMRD_1 (1 - 1)
#define TMRD_2 (2 - 1)
+#define TMRD_3 (3 - 1)
#define TXSR_1 (1 - 1)
#define TXSR_6 (6 - 1)
+#define TXSR_7 (7 - 1)
#define TRAS_1 (1 - 1)
#define TRAS_4 (4 - 1)
#define TRC_6 (6 - 1)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the STM32F4 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H
+#define _DT_BINDINGS_MFD_STM32F4_RCC_H
+
+/* AHB1 */
+#define STM32F4_RCC_AHB1_GPIOA 0
+#define STM32F4_RCC_AHB1_GPIOB 1
+#define STM32F4_RCC_AHB1_GPIOC 2
+#define STM32F4_RCC_AHB1_GPIOD 3
+#define STM32F4_RCC_AHB1_GPIOE 4
+#define STM32F4_RCC_AHB1_GPIOF 5
+#define STM32F4_RCC_AHB1_GPIOG 6
+#define STM32F4_RCC_AHB1_GPIOH 7
+#define STM32F4_RCC_AHB1_GPIOI 8
+#define STM32F4_RCC_AHB1_GPIOJ 9
+#define STM32F4_RCC_AHB1_GPIOK 10
+#define STM32F4_RCC_AHB1_CRC 12
+#define STM32F4_RCC_AHB1_BKPSRAM 18
+#define STM32F4_RCC_AHB1_CCMDATARAM 20
+#define STM32F4_RCC_AHB1_DMA1 21
+#define STM32F4_RCC_AHB1_DMA2 22
+#define STM32F4_RCC_AHB1_DMA2D 23
+#define STM32F4_RCC_AHB1_ETHMAC 25
+#define STM32F4_RCC_AHB1_ETHMACTX 26
+#define STM32F4_RCC_AHB1_ETHMACRX 27
+#define STM32F4_RCC_AHB1_ETHMACPTP 28
+#define STM32F4_RCC_AHB1_OTGHS 29
+#define STM32F4_RCC_AHB1_OTGHSULPI 30
+
+#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
+
+/* AHB2 */
+#define STM32F4_RCC_AHB2_DCMI 0
+#define STM32F4_RCC_AHB2_CRYP 4
+#define STM32F4_RCC_AHB2_HASH 5
+#define STM32F4_RCC_AHB2_RNG 6
+#define STM32F4_RCC_AHB2_OTGFS 7
+
+#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F4_RCC_AHB3_FMC 0
+#define STM32F4_RCC_AHB3_QSPI 1
+
+#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F4_RCC_APB1_TIM2 0
+#define STM32F4_RCC_APB1_TIM3 1
+#define STM32F4_RCC_APB1_TIM4 2
+#define STM32F4_RCC_APB1_TIM5 3
+#define STM32F4_RCC_APB1_TIM6 4
+#define STM32F4_RCC_APB1_TIM7 5
+#define STM32F4_RCC_APB1_TIM12 6
+#define STM32F4_RCC_APB1_TIM13 7
+#define STM32F4_RCC_APB1_TIM14 8
+#define STM32F4_RCC_APB1_WWDG 11
+#define STM32F4_RCC_APB1_SPI2 14
+#define STM32F4_RCC_APB1_SPI3 15
+#define STM32F4_RCC_APB1_UART2 17
+#define STM32F4_RCC_APB1_UART3 18
+#define STM32F4_RCC_APB1_UART4 19
+#define STM32F4_RCC_APB1_UART5 20
+#define STM32F4_RCC_APB1_I2C1 21
+#define STM32F4_RCC_APB1_I2C2 22
+#define STM32F4_RCC_APB1_I2C3 23
+#define STM32F4_RCC_APB1_CAN1 25
+#define STM32F4_RCC_APB1_CAN2 26
+#define STM32F4_RCC_APB1_PWR 28
+#define STM32F4_RCC_APB1_DAC 29
+#define STM32F4_RCC_APB1_UART7 30
+#define STM32F4_RCC_APB1_UART8 31
+
+#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F4_RCC_APB2_TIM1 0
+#define STM32F4_RCC_APB2_TIM8 1
+#define STM32F4_RCC_APB2_USART1 4
+#define STM32F4_RCC_APB2_USART6 5
+#define STM32F4_RCC_APB2_ADC1 8
+#define STM32F4_RCC_APB2_ADC2 9
+#define STM32F4_RCC_APB2_ADC3 10
+#define STM32F4_RCC_APB2_SDIO 11
+#define STM32F4_RCC_APB2_SPI1 12
+#define STM32F4_RCC_APB2_SPI4 13
+#define STM32F4_RCC_APB2_SYSCFG 14
+#define STM32F4_RCC_APB2_TIM9 16
+#define STM32F4_RCC_APB2_TIM10 17
+#define STM32F4_RCC_APB2_TIM11 18
+#define STM32F4_RCC_APB2_SPI5 20
+#define STM32F4_RCC_APB2_SPI6 21
+#define STM32F4_RCC_APB2_SAI1 22
+#define STM32F4_RCC_APB2_LTDC 26
+#define STM32F4_RCC_APB2_DSI 27
+
+#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */
--- /dev/null
+#ifndef _DT_BINDINGS_STM32_PINFUNC_H
+#define _DT_BINDINGS_STM32_PINFUNC_H
+
+/* define PIN modes */
+#define GPIO 0x0
+#define AF0 0x1
+#define AF1 0x2
+#define AF2 0x3
+#define AF3 0x4
+#define AF4 0x5
+#define AF5 0x6
+#define AF6 0x7
+#define AF7 0x8
+#define AF8 0x9
+#define AF9 0xa
+#define AF10 0xb
+#define AF11 0xc
+#define AF12 0xd
+#define AF13 0xe
+#define AF14 0xf
+#define AF15 0x10
+#define ANALOG 0x11
+
+/* define Pins number*/
+#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
+
+#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
+
+#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
+
#define STM32F746_PA15_FUNC_EVENTOUT 0xf10
#define STM32F746_PA15_FUNC_ANALOG 0xf11
-
#define STM32F746_PB0_FUNC_GPIO 0x1000
#define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002
#define STM32F746_PB0_FUNC_TIM3_CH3 0x1003
#define STM32F746_PB3_FUNC_TIM2_CH2 0x1302
#define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306
#define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
+
+#define STM32F769_PB3_FUNC_SDMMC2_D2 0x130b
+
#define STM32F746_PB3_FUNC_EVENTOUT 0x1310
#define STM32F746_PB3_FUNC_ANALOG 0x1311
#define STM32F746_PB4_FUNC_SPI1_MISO 0x1406
#define STM32F746_PB4_FUNC_SPI3_MISO 0x1407
#define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408
+
+#define STM32F769_PB4_FUNC_SDMMC2_D3 0x140b
+
#define STM32F746_PB4_FUNC_EVENTOUT 0x1410
#define STM32F746_PB4_FUNC_ANALOG 0x1411
#define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606
#define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607
#define STM32F746_PD6_FUNC_USART2_RX 0x3608
+
+#define STM32F769_PD6_FUNC_SDMMC2_CLK 0x360c
+
#define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d
#define STM32F746_PD6_FUNC_DCMI_D10 0x360e
#define STM32F746_PD6_FUNC_LCD_B2 0x360f
#define STM32F746_PD7_FUNC_GPIO 0x3700
#define STM32F746_PD7_FUNC_USART2_CK 0x3708
#define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709
+
+#define STM32F769_PD7_FUNC_SDMMC2_CMD 0x370c
+
#define STM32F746_PD7_FUNC_FMC_NE1 0x370d
#define STM32F746_PD7_FUNC_EVENTOUT 0x3710
#define STM32F746_PD7_FUNC_ANALOG 0x3711
#define STM32F746_PG9_FUNC_USART6_RX 0x6909
#define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a
#define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b
+
+#define STM32F769_PG9_FUNC_SDMMC2_D0 0x690c
+
#define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d
#define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e
#define STM32F746_PG9_FUNC_EVENTOUT 0x6910
#define STM32F746_PG10_FUNC_GPIO 0x6a00
#define STM32F746_PG10_FUNC_LCD_G3 0x6a0a
#define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b
+
+#define STM32F769_PG10_FUNC_SDMMC2_D1 0x6a0c
+
#define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d
#define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e
#define STM32F746_PG10_FUNC_LCD_B2 0x6a0f
efi_status_t (EFIAPI *reinstall_protocol_interface)(
void *handle, const efi_guid_t *protocol,
void *old_interface, void *new_interface);
- efi_status_t (EFIAPI *uninstall_protocol_interface)(void *handle,
- const efi_guid_t *protocol, void *protocol_interface);
- efi_status_t (EFIAPI *handle_protocol)(efi_handle_t,
- const efi_guid_t *protocol,
- void **protocol_interface);
+ efi_status_t (EFIAPI *uninstall_protocol_interface)(
+ efi_handle_t handle, const efi_guid_t *protocol,
+ void *protocol_interface);
+ efi_status_t (EFIAPI *handle_protocol)(
+ efi_handle_t handle, const efi_guid_t *protocol,
+ void **protocol_interface);
void *reserved;
efi_status_t (EFIAPI *register_protocol_notify)(
const efi_guid_t *protocol, struct efi_event *event,
efi_status_t (EFIAPI *exit)(efi_handle_t handle,
efi_status_t exit_status,
unsigned long exitdata_size, s16 *exitdata);
- efi_status_t (EFIAPI *unload_image)(void *image_handle);
+ efi_status_t (EFIAPI *unload_image)(efi_handle_t image_handle);
efi_status_t (EFIAPI *exit_boot_services)(efi_handle_t, unsigned long);
efi_status_t (EFIAPI *get_next_monotonic_count)(u64 *count);
efi_handle_t *driver_image_handle,
struct efi_device_path *remaining_device_path,
bool recursive);
- efi_status_t (EFIAPI *disconnect_controller)(void *controller_handle,
- void *driver_image_handle, void *child_handle);
+ efi_status_t (EFIAPI *disconnect_controller)(
+ efi_handle_t controller_handle,
+ efi_handle_t driver_image_handle,
+ efi_handle_t child_handle);
#define EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL 0x00000001
#define EFI_OPEN_PROTOCOL_GET_PROTOCOL 0x00000002
#define EFI_OPEN_PROTOCOL_TEST_PROTOCOL 0x00000004
const efi_guid_t *protocol, void **interface,
efi_handle_t agent_handle,
efi_handle_t controller_handle, u32 attributes);
- efi_status_t (EFIAPI *close_protocol)(void *handle,
- const efi_guid_t *protocol, void *agent_handle,
- void *controller_handle);
+ efi_status_t (EFIAPI *close_protocol)(
+ efi_handle_t handle, const efi_guid_t *protocol,
+ efi_handle_t agent_handle,
+ efi_handle_t controller_handle);
efi_status_t(EFIAPI *open_protocol_information)(efi_handle_t handle,
const efi_guid_t *protocol,
struct efi_open_protocol_info_entry **entry_buffer,
struct efi_table_hdr hdr;
unsigned long fw_vendor; /* physical addr of wchar_t vendor string */
u32 fw_revision;
- unsigned long con_in_handle;
+ efi_handle_t con_in_handle;
struct efi_simple_input_interface *con_in;
- unsigned long con_out_handle;
+ efi_handle_t con_out_handle;
struct efi_simple_text_output_protocol *con_out;
- unsigned long stderr_handle;
+ efi_handle_t stderr_handle;
struct efi_simple_text_output_protocol *std_err;
struct efi_runtime_services *runtime;
struct efi_boot_services *boottime;
} __packed;
#define DEVICE_PATH_TYPE_MESSAGING_DEVICE 0x03
+# define DEVICE_PATH_SUB_TYPE_MSG_ATAPI 0x01
+# define DEVICE_PATH_SUB_TYPE_MSG_SCSI 0x02
# define DEVICE_PATH_SUB_TYPE_MSG_USB 0x05
# define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b
# define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f
# define DEVICE_PATH_SUB_TYPE_MSG_SD 0x1a
# define DEVICE_PATH_SUB_TYPE_MSG_MMC 0x1d
+struct efi_device_path_atapi {
+ struct efi_device_path dp;
+ u8 primary_secondary;
+ u8 slave_master;
+ u16 logical_unit_number;
+} __packed;
+
+struct efi_device_path_scsi {
+ struct efi_device_path dp;
+ u16 target_id;
+ u16 logical_unit_number;
+} __packed;
+
struct efi_device_path_usb {
struct efi_device_path dp;
u8 parent_port_number;
u32 io_align;
u8 pad2[4];
u64 last_block;
+ /* Added in revision 2 of the protocol */
+ u64 lowest_aligned_lba;
+ u32 logical_blocks_per_physical_block;
+ /* Added in revision 3 of the protocol */
+ u32 optimal_transfer_length_granualarity;
};
+#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
+#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x0002001f
+
struct efi_block_io {
u64 revision;
struct efi_block_io_media *media;
efi_status_t (EFIAPI *reset)(struct efi_block_io *this,
char extended_verification);
efi_status_t (EFIAPI *read_blocks)(struct efi_block_io *this,
- u32 media_id, u64 lba, unsigned long buffer_size,
+ u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer);
efi_status_t (EFIAPI *write_blocks)(struct efi_block_io *this,
- u32 media_id, u64 lba, unsigned long buffer_size,
+ u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer);
efi_status_t (EFIAPI *flush_blocks)(struct efi_block_io *this);
};
s16 file_name[0];
};
+#define EFI_DRIVER_BINDING_PROTOCOL_GUID \
+ EFI_GUID(0x18a031ab, 0xb443, 0x4d1a,\
+ 0xa5, 0xc0, 0x0c, 0x09, 0x26, 0x1e, 0x9f, 0x71)
+struct efi_driver_binding_protocol {
+ efi_status_t (EFIAPI * supported)(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path);
+ efi_status_t (EFIAPI * start)(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path);
+ efi_status_t (EFIAPI * stop)(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ efi_uintn_t number_of_children,
+ efi_handle_t *child_handle_buffer);
+ u32 version;
+ efi_handle_t image_handle;
+ efi_handle_t driver_binding_handle;
+};
+
#endif
--- /dev/null
+/*
+ * EFI application loader
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EFI_DRIVER_H
+#define _EFI_DRIVER_H 1
+
+#include <common.h>
+#include <dm.h>
+#include <efi_loader.h>
+
+struct efi_driver_ops {
+ const efi_guid_t *protocol;
+ const efi_guid_t *child_protocol;
+ int (*bind)(efi_handle_t handle, void *interface);
+};
+
+/*
+ * This structure adds internal fields to the driver binding protocol.
+ */
+struct efi_driver_binding_extended_protocol {
+ struct efi_driver_binding_protocol bp;
+ const struct efi_driver_ops *ops;
+};
+
+#endif /* _EFI_DRIVER_H */
} while(0)
/*
- * Write GUID
+ * Write an indented message with EFI prefix
*/
-#define EFI_PRINT_GUID(txt, guid) ({ \
- debug("%sEFI: %s %pUl\n", __efi_nesting(), txt, guid); \
+#define EFI_PRINT(format, ...) ({ \
+ debug("%sEFI: " format, __efi_nesting(), \
+ ##__VA_ARGS__); \
})
extern struct efi_runtime_services efi_runtime_services;
uint16_t *efi_dp_str(struct efi_device_path *dp);
+/* GUID of the EFI_BLOCK_IO_PROTOCOL */
+extern const efi_guid_t efi_block_io_guid;
extern const efi_guid_t efi_global_variable_guid;
extern const efi_guid_t efi_guid_console_control;
extern const efi_guid_t efi_guid_device_path;
+/* GUID of the EFI_DRIVER_BINDING_PROTOCOL */
+extern const efi_guid_t efi_guid_driver_binding_protocol;
extern const efi_guid_t efi_guid_loaded_image;
extern const efi_guid_t efi_guid_device_path_to_text_protocol;
extern const efi_guid_t efi_simple_file_system_protocol_guid;
extern unsigned int __efi_runtime_start, __efi_runtime_stop;
extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
+/*
+ * When a protocol is opened a open protocol info entry is created.
+ * These are maintained in a list.
+ */
+struct efi_open_protocol_info_item {
+ /* Link to the list of open protocol info entries of a protocol */
+ struct list_head link;
+ struct efi_open_protocol_info_entry info;
+};
+
/*
* When the UEFI payload wants to open a protocol on an object to get its
* interface (usually a struct with callback functions), this struct maps the
- * protocol GUID to the respective protocol interface */
+ * protocol GUID to the respective protocol interface
+ */
struct efi_handler {
/* Link to the list of protocols of a handle */
struct list_head link;
const efi_guid_t *guid;
void *protocol_interface;
+ /* Link to the list of open protocol info items */
+ struct list_head open_infos;
};
/*
int efi_console_register(void);
/* Called by bootefi to make all disk storage accessible as EFI objects */
int efi_disk_register(void);
+/* Create handles and protocols for the partitions of a block device */
+int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
+ const char *if_typename, int diskid,
+ const char *pdevname);
/* Called by bootefi to make GOP (graphical) interface available */
int efi_gop_register(void);
/* Called by bootefi to make the network interface available */
/* Add a new object to the object list. */
void efi_add_handle(struct efi_object *obj);
/* Create handle */
-efi_status_t efi_create_handle(void **handle);
+efi_status_t efi_create_handle(efi_handle_t *handle);
/* Delete handle */
void efi_delete_handle(struct efi_object *obj);
/* Call this to validate a handle and find the EFI object for it */
-struct efi_object *efi_search_obj(const void *handle);
+struct efi_object *efi_search_obj(const efi_handle_t handle);
/* Find a protocol on a handle */
-efi_status_t efi_search_protocol(const void *handle,
+efi_status_t efi_search_protocol(const efi_handle_t handle,
const efi_guid_t *protocol_guid,
struct efi_handler **handler);
/* Install new protocol on a handle */
-efi_status_t efi_add_protocol(const void *handle, const efi_guid_t *protocol,
+efi_status_t efi_add_protocol(const efi_handle_t handle,
+ const efi_guid_t *protocol,
void *protocol_interface);
/* Delete protocol from a handle */
-efi_status_t efi_remove_protocol(const void *handle, const efi_guid_t *protocol,
+efi_status_t efi_remove_protocol(const efi_handle_t handle,
+ const efi_guid_t *protocol,
void *protocol_interface);
/* Delete all protocols from a handle */
-efi_status_t efi_remove_all_protocols(const void *handle);
+efi_status_t efi_remove_all_protocols(const efi_handle_t handle);
/* Call this to create an event */
efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl,
void (EFIAPI *notify_function) (
efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
uint64_t trigger_time);
/* Call this to signal an event */
-void efi_signal_event(struct efi_event *event);
+void efi_signal_event(struct efi_event *event, bool check_tpl);
/* open file system: */
struct efi_simple_file_system_protocol *efi_simple_file_system(
/* Adds a range into the EFI memory map */
uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
bool overlap_only_ram);
+/* Called by board init to initialize the EFI drivers */
+int efi_driver_init(void);
/* Called by board init to initialize the EFI memory map */
int efi_memory_init(void);
/* Adds new or overrides configuration table entry to the system table */
struct efi_device_path *efi_dp_from_dev(struct udevice *dev);
struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part);
+/* Create a device node for a block device partition. */
+struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part);
struct efi_device_path *efi_dp_from_file(struct blk_desc *desc, int part,
const char *path);
struct efi_device_path *efi_dp_from_eth(void);
struct efi_device_path *efi_dp_from_mem(uint32_t mem_type,
uint64_t start_address,
uint64_t end_address);
-void efi_dp_split_file_path(struct efi_device_path *full_path,
- struct efi_device_path **device_path,
- struct efi_device_path **file_path);
+/* Determine the last device path node that is not the end node. */
+const struct efi_device_path *efi_dp_last_node(
+ const struct efi_device_path *dp);
+efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path,
+ struct efi_device_path **device_path,
+ struct efi_device_path **file_path);
#define EFI_DP_TYPE(_dp, _type, _subtype) \
(((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
#define EFI_ST_SUCCESS 0
#define EFI_ST_FAILURE 1
+/*
+ * Prints a message.
+ */
+#define efi_st_printf(...) \
+ (efi_st_printc(-1, __VA_ARGS__))
+
/*
* Prints an error message.
*
* @... format string followed by fields to print
*/
#define efi_st_error(...) \
- (efi_st_printf("%s(%u):\nERROR: ", __FILE__, __LINE__), \
- efi_st_printf(__VA_ARGS__)) \
+ (efi_st_printc(EFI_LIGHTRED, "%s(%u):\nERROR: ", __FILE__, __LINE__), \
+ efi_st_printc(EFI_LIGHTRED, __VA_ARGS__))
/*
* Prints a TODO message.
* @... format string followed by fields to print
*/
#define efi_st_todo(...) \
- (efi_st_printf("%s(%u):\nTODO: ", __FILE__, __LINE__), \
- efi_st_printf(__VA_ARGS__)) \
+ (efi_st_printc(EFI_YELLOW, "%s(%u):\nTODO: ", __FILE__, __LINE__), \
+ efi_st_printc(EFI_YELLOW, __VA_ARGS__)) \
/*
* A test may be setup and executed at boottime,
void efi_st_exit_boot_services(void);
/*
- * Print a pointer to an u16 string
+ * Print a colored message
*
- * @pointer: pointer
- * @buf: pointer to buffer address
- * on return position of terminating zero word
+ * @color color, see constants in efi_api.h, use -1 for no color
+ * @fmt printf format
+ * @... arguments to be printed
+ * on return position of terminating zero word
*/
-void efi_st_printf(const char *fmt, ...)
- __attribute__ ((format (__printf__, 1, 2)));
+void efi_st_printc(int color, const char *fmt, ...)
+ __attribute__ ((format (__printf__, 2, 3)));
/*
* Compare memory.
#define R_AARCH64_NONE 0 /* No relocation. */
#define R_AARCH64_RELATIVE 1027 /* Adjust by program base. */
+/* RISC-V relocations */
+#define R_RISCV_32 1
+#define R_RISCV_64 2
+#define R_RISCV_RELATIVE 3
+
#ifndef __ASSEMBLER__
int valid_elf_image(unsigned long addr);
#endif
"setenv fdtfile dra72-evm.dtb; fi;" \
"if test $board_name = dra71x; then " \
"setenv fdtfile dra71-evm.dtb; fi;" \
- "if test $board_name = dra76x; then " \
+ "if test $board_name = dra76x_acd; then " \
"setenv fdtfile dra76-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \
"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
"setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \
"if test $board_name = am572x_idk; then " \
"setenv fdtfile am572x-idk.dtb; fi;" \
+ "if test $board_name = am574x_idk; then " \
+ "setenv fdtfile am574x-idk.dtb; fi;" \
"if test $board_name = am57xx_evm; then " \
"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
"if test $board_name = am57xx_evm_reva3; then " \
#include <asm/byteorder.h>
#include <fs.h>
-#define CONFIG_SUPPORT_VFAT
/* Maximum Long File Name length supported here is 128 UTF-16 code units */
#define VFAT_MAXLEN_BYTES 256 /* Maximum LFN buffer in bytes */
#define VFAT_MAXSEQ 9 /* Up to 9 of 13 2-byte UTF-16 entries */
/**
* Board-specific FDT initialization. Returns the address to a device tree blob.
- * Called when CONFIG_OF_BOARD is defined.
+ * Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined
+ * and the board implements it.
*/
void *board_fdt_blob_setup(void);
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_QBMAN_H__
+#define __FSL_QBMAN_H__
+void fdt_fixup_qportals(void *blob);
+void fdt_fixup_bportals(void *blob);
+void inhibit_portals(void __iomem *addr, int max_portals,
+ int arch_max_portals, int portal_cinh_size);
+void setup_qbman_portals(void);
+
+struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ u8 res0[0x200];
+#else
+ struct {
+ u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
+ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
+ u32 res;
+ u32 qcsp_dd_cfg; /* 0xc - SW Portal Dynamic Debug cfg */
+ } qcsp[32];
+#endif
+ /* Not actually reserved, but irrelevant to u-boot */
+ u8 res[0xbf8 - 0x200];
+ u32 ip_rev_1;
+ u32 ip_rev_2;
+ u32 fqd_bare; /* FQD Extended Base Addr Register */
+ u32 fqd_bar; /* FQD Base Addr Register */
+ u8 res1[0x8];
+ u32 fqd_ar; /* FQD Attributes Register */
+ u8 res2[0xc];
+ u32 pfdr_bare; /* PFDR Extended Base Addr Register */
+ u32 pfdr_bar; /* PFDR Base Addr Register */
+ u8 res3[0x8];
+ u32 pfdr_ar; /* PFDR Attributes Register */
+ u8 res4[0x4c];
+ u32 qcsp_bare; /* QCSP Extended Base Addr Register */
+ u32 qcsp_bar; /* QCSP Base Addr Register */
+ u8 res5[0x78];
+ u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
+ u32 srcidr; /* Source ID Register */
+ u32 liodnr; /* LIODN Register */
+ u8 res6[4];
+ u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
+ u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
+ u8 res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ struct {
+ u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
+ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
+ u32 res;
+ u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
+ } qcsp[50];
+#endif
+};
+
+struct ccsr_bman {
+ /* Not actually reserved, but irrelevant to u-boot */
+ u8 res[0xbf8];
+ u32 ip_rev_1;
+ u32 ip_rev_2;
+ u32 fbpr_bare; /* FBPR Extended Base Addr Register */
+ u32 fbpr_bar; /* FBPR Base Addr Register */
+ u8 res1[0x8];
+ u32 fbpr_ar; /* FBPR Attributes Register */
+ u8 res2[0xf0];
+ u32 srcidr; /* Source ID Register */
+ u32 liodnr; /* LIODN Register */
+ u8 res7[0x2f4];
+};
+
+#endif /* __FSL_QBMAN_H__ */
IH_ARCH_ARC, /* Synopsys DesignWare ARC */
IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */
IH_ARCH_XTENSA, /* Xtensa */
+ IH_ARCH_RISCV, /* RISC-V */
IH_ARCH_COUNT,
};
* boot_get_loadable() will take the given FIT configuration, and look
* for a field named "loadables". Loadables, is a list of elements in
* the FIT given as strings. exe:
- * loadables = "linux_kernel@1", "fdt@2";
+ * loadables = "linux_kernel", "fdt-2";
* this function will attempt to parse each string, and load the
* corresponding element from the FIT into memory. Once placed,
* no aditional actions are taken.
* @param images Boot images structure
* @param addr Address of FIT in memory
* @param fit_unamep On entry this is the requested image name
- * (e.g. "kernel@1") or NULL to use the default. On exit
+ * (e.g. "kernel") or NULL to use the default. On exit
* points to the selected image name
* @param fit_uname_configp On entry this is the requested configuration
- * name (e.g. "conf@1") or NULL to use the default. On
+ * name (e.g. "conf-1") or NULL to use the default. On
* exit points to the selected configuration name.
* @param arch Expected architecture (IH_ARCH_...)
* @param datap Returns address of loaded image
* @param images Boot images structure
* @param addr Address of FIT in memory
* @param fit_unamep On entry this is the requested image name
- * (e.g. "kernel@1") or NULL to use the default. On exit
+ * (e.g. "kernel") or NULL to use the default. On exit
* points to the selected image name
* @param fit_uname_configp On entry this is the requested configuration
- * name (e.g. "conf@1") or NULL to use the default. On
+ * name (e.g. "conf-1") or NULL to use the default. On
* exit points to the selected configuration name.
* @param arch Expected architecture (IH_ARCH_...)
* @param image_type Required image type (IH_TYPE_...). If this is
/**
* fit_get_node_from_config() - Look up an image a FIT by type
*
- * This looks in the selected conf@ node (images->fit_uname_cfg) for a
+ * This looks in the selected conf- node (images->fit_uname_cfg) for a
* particular image type (e.g. "kernel") and then finds the image that is
* referred to.
*
* For example, for something like:
*
* images {
- * kernel@1 {
+ * kernel {
* ...
* };
* };
* configurations {
- * conf@1 {
- * kernel = "kernel@1";
+ * conf-1 {
+ * kernel = "kernel";
* };
* };
*
* the function will return the node offset of the kernel@1 node, assuming
- * that conf@1 is the chosen configuration.
+ * that conf-1 is the chosen configuration.
*
* @param images Boot images structure
* @param prop_name Property name to look up (FIT_..._PROP)
* @noffset: Offset of conf@xxx node to check
* @prop_name: Property to read from the conf node
*
- * The conf@ nodes contain references to other nodes, using properties
- * like 'kernel = "kernel@1"'. Given such a property name (e.g. "kernel"),
+ * The conf- nodes contain references to other nodes, using properties
+ * like 'kernel = "kernel"'. Given such a property name (e.g. "kernel"),
* return the offset of the node referred to (e.g. offset of node
- * "/images/kernel@1".
+ * "/images/kernel".
*/
int fit_conf_get_prop_node(const void *fit, int noffset,
const char *prop_name);
#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
+#define ALIGN_DOWN(x, a) ALIGN((x) - ((a) - 1), (a))
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
#include <linux/compiler.h>
#include <part.h>
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+#define MMC_SUPPORTS_TUNING
+#endif
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+#define MMC_SUPPORTS_TUNING
+#endif
+
/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
#define SD_VERSION_SD (1U << 31)
#define MMC_VERSION_MMC (1U << 30)
#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
-#define MMC_MODE_HS (1 << 0)
-#define MMC_MODE_HS_52MHz (1 << 1)
-#define MMC_MODE_4BIT (1 << 2)
-#define MMC_MODE_8BIT (1 << 3)
-#define MMC_MODE_SPI (1 << 4)
-#define MMC_MODE_DDR_52MHz (1 << 5)
+#define MMC_CAP(mode) (1 << mode)
+#define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
+#define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
+#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
+#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
+
+#define MMC_MODE_8BIT BIT(30)
+#define MMC_MODE_4BIT BIT(29)
+#define MMC_MODE_1BIT BIT(28)
+#define MMC_MODE_SPI BIT(27)
+
#define SD_DATA_4BIT 0x00040000
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+#define MMC_CMD_SEND_TUNING_BLOCK 19
+#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
#define MMC_CMD_SET_BLOCK_COUNT 23
#define MMC_CMD_WRITE_SINGLE_BLOCK 24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
#define SD_CMD_APP_SEND_OP_COND 41
#define SD_CMD_APP_SEND_SCR 51
+static inline bool mmc_is_tuning_cmd(uint cmdidx)
+{
+ if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
+ (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
+ return true;
+ return false;
+}
+
/* SCR definitions in different words */
#define SD_HIGHSPEED_BUSY 0x00020000
#define SD_HIGHSPEED_SUPPORTED 0x00020000
+#define UHS_SDR12_BUS_SPEED 0
+#define HIGH_SPEED_BUS_SPEED 1
+#define UHS_SDR25_BUS_SPEED 1
+#define UHS_SDR50_BUS_SPEED 2
+#define UHS_SDR104_BUS_SPEED 3
+#define UHS_DDR50_BUS_SPEED 4
+
+#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
+#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
+#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
+#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
+#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
+
#define OCR_BUSY 0x80000000
#define OCR_HCS 0x40000000
+#define OCR_S18R 0x1000000
#define OCR_VOLTAGE_MASK 0x007FFF80
#define OCR_ACCESS_MODE 0x60000000
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
| EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
+ /* SDR mode @1.8V I/O */
+#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
+ /* SDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
+ EXT_CSD_CARD_TYPE_HS200_1_2V)
+
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
+#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
+
+#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
+#define EXT_CSD_TIMING_HS 1 /* HS */
+#define EXT_CSD_TIMING_HS200 2 /* HS200 */
#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
#define ENHNCD_SUPPORT (0x2)
#define PART_ENH_ATTRIB (0x1f)
+#define MMC_QUIRK_RETRY_SEND_CID BIT(0)
+#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
+
+enum mmc_voltage {
+ MMC_SIGNAL_VOLTAGE_000 = 0,
+ MMC_SIGNAL_VOLTAGE_120 = 1,
+ MMC_SIGNAL_VOLTAGE_180 = 2,
+ MMC_SIGNAL_VOLTAGE_330 = 4,
+};
+
+#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
+ MMC_SIGNAL_VOLTAGE_180 |\
+ MMC_SIGNAL_VOLTAGE_330)
+
/* Maximum block size for MMC */
#define MMC_MAX_BLOCK_LEN 512
*/
int (*set_ios)(struct udevice *dev);
+ /**
+ * send_init_stream() - send the initialization stream: 74 clock cycles
+ * This is used after power up before sending the first command
+ *
+ * @dev: Device to update
+ */
+ void (*send_init_stream)(struct udevice *dev);
+
/**
* get_cd() - See whether a card is present
*
* @return 0 if write-enabled, 1 if write-protected, -ve on error
*/
int (*get_wp)(struct udevice *dev);
+
+#ifdef MMC_SUPPORTS_TUNING
+ /**
+ * execute_tuning() - Start the tuning process
+ *
+ * @dev: Device to start the tuning
+ * @opcode: Command opcode to send
+ * @return 0 if OK, -ve on error
+ */
+ int (*execute_tuning)(struct udevice *dev, uint opcode);
+#endif
+
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ /**
+ * wait_dat0() - wait until dat0 is in the target state
+ * (CLK must be running during the wait)
+ *
+ * @dev: Device to check
+ * @state: target state
+ * @timeout: timeout in us
+ * @return 0 if dat0 is in the target state, -ve on error
+ */
+ int (*wait_dat0)(struct udevice *dev, int state, int timeout);
+#endif
};
#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data);
int dm_mmc_set_ios(struct udevice *dev);
+void dm_mmc_send_init_stream(struct udevice *dev);
int dm_mmc_get_cd(struct udevice *dev);
int dm_mmc_get_wp(struct udevice *dev);
+int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
/* Transition functions for compatibility */
int mmc_set_ios(struct mmc *mmc);
+void mmc_send_init_stream(struct mmc *mmc);
int mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
+int mmc_execute_tuning(struct mmc *mmc, uint opcode);
+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
#else
struct mmc_ops {
unsigned int erase_offset; /* In milliseconds */
};
+enum bus_mode {
+ MMC_LEGACY,
+ SD_LEGACY,
+ MMC_HS,
+ SD_HS,
+ MMC_HS_52,
+ MMC_DDR_52,
+ UHS_SDR12,
+ UHS_SDR25,
+ UHS_SDR50,
+ UHS_DDR50,
+ UHS_SDR104,
+ MMC_HS_200,
+ MMC_MODES_END
+};
+
+const char *mmc_mode_name(enum bus_mode mode);
+void mmc_dump_capabilities(const char *text, uint caps);
+
+static inline bool mmc_is_mode_ddr(enum bus_mode mode)
+{
+ if (mode == MMC_DDR_52)
+ return true;
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ else if (mode == UHS_DDR50)
+ return true;
+#endif
+ else
+ return false;
+}
+
+#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
+ MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
+ MMC_CAP(UHS_DDR50))
+
+static inline bool supports_uhs(uint caps)
+{
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ return (caps & UHS_CAPS) ? true : false;
+#else
+ return false;
+#endif
+}
+
/*
* With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
* with mmc_get_mmc_dev().
void *priv;
uint has_init;
int high_capacity;
+ bool clk_disable; /* true if the clock can be turned off */
uint bus_width;
uint clock;
+ enum mmc_voltage signal_voltage;
uint card_caps;
+ uint host_caps;
uint ocr;
uint dsr;
uint dsr_imp;
u8 wr_rel_set;
u8 part_config;
uint tran_speed;
+ uint legacy_speed; /* speed for the legacy mode provided by the card */
uint read_bl_len;
+#if CONFIG_IS_ENABLED(MMC_WRITE)
uint write_bl_len;
uint erase_grp_size; /* in 512-byte sectors */
+#endif
+#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
uint hc_wp_grp_size; /* in 512-byte sectors */
+#endif
+#if CONFIG_IS_ENABLED(MMC_WRITE)
struct sd_ssr ssr; /* SD status register */
+#endif
u64 capacity;
u64 capacity_user;
u64 capacity_boot;
u64 capacity_rpmb;
u64 capacity_gp[4];
+#ifndef CONFIG_SPL_BUILD
u64 enh_user_start;
u64 enh_user_size;
+#endif
#if !CONFIG_IS_ENABLED(BLK)
struct blk_desc block_dev;
#endif
int ddr_mode;
#if CONFIG_IS_ENABLED(DM_MMC)
struct udevice *dev; /* Device for this MMC controller */
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
+ struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
#endif
+#endif
+ u8 *ext_csd;
+ u32 cardtype; /* cardtype read from the MMC */
+ enum mmc_voltage current_voltage;
+ enum bus_mode selected_mode; /* mode currently used */
+ enum bus_mode best_mode; /* best mode is the supported mode with the
+ * highest bandwidth. It may not always be the
+ * operating mode due to limitations when
+ * accessing the boot partitions
+ */
+ u32 quirks;
};
struct mmc_hwpart_conf {
int mmc_unbind(struct udevice *dev);
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
+int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
+
+/**
+ * mmc_of_parse() - Parse the device tree to get the capabilities of the host
+ *
+ * @dev: MMC device
+ * @cfg: MMC configuration
+ * @return 0 if OK, -ve on error
+ */
+int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
+
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
-void mmc_set_clock(struct mmc *mmc, uint clock);
+
+/**
+ * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
+ *
+ * @voltage: The mmc_voltage to convert
+ * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
+ */
+int mmc_voltage_to_mv(enum mmc_voltage voltage);
+
+/**
+ * mmc_set_clock() - change the bus clock
+ * @mmc: MMC struct
+ * @clock: bus frequency in Hz
+ * @disable: flag indicating if the clock must on or off
+ * @return 0 if OK, -ve on error
+ */
+int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
+
struct mmc *find_mmc_device(int dev_num);
int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
ulong or;
} pcmcia_win_t;
-/*
- * Definitions for PCMCIA control registers to operate in IDE mode
- *
- * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
- * to be done later (depending on CPU clock)
- */
-
-/* Window 0:
- * Base: 0xFE100000 CS1
- * Port Size: 2 Bytes
- * Port Size: 16 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
-#define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
- | PCMCIA_PPS_16 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 1:
- * Base: 0xFE100080 CS1
- * Port Size: 8 Bytes
- * Port Size: 8 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
-#define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
- | PCMCIA_PPS_8 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 2:
- * Base: 0xFE100100 CS2
- * Port Size: 8 Bytes
- * Port Size: 8 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
-#define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
- | PCMCIA_PPS_8 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 3:
- * not used
- */
-#define CONFIG_SYS_PCMCIA_PBR3 0
-#define CONFIG_SYS_PCMCIA_POR3 0
-
-/* Window 4:
- * Base: 0xFE100C00 CS1
- * Port Size: 2 Bytes
- * Port Size: 16 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
-#define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
- | PCMCIA_PPS_16 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 5:
- * Base: 0xFE100C80 CS1
- * Port Size: 8 Bytes
- * Port Size: 8 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
-#define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
- | PCMCIA_PPS_8 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 6:
- * Base: 0xFE100D00 CS2
- * Port Size: 8 Bytes
- * Port Size: 8 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
-#define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
- | PCMCIA_PPS_8 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 7:
- * not used
- */
-#define CONFIG_SYS_PCMCIA_PBR7 0
-#define CONFIG_SYS_PCMCIA_POR7 0
-
/**********************************************************************/
/*
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);
+int phy_b53_init(void);
int phy_mv88e61xx_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
#define S2MPS11_LDO26_ENABLE 0xec
+#define S2MPS11_LDO_NUM 26
+#define S2MPS11_BUCK_NUM 10
+
+/* Driver name */
+#define S2MPS11_BUCK_DRIVER "s2mps11_buck"
+#define S2MPS11_OF_BUCK_PREFIX "BUCK"
+#define S2MPS11_LDO_DRIVER "s2mps11_ldo"
+#define S2MPS11_OF_LDO_PREFIX "LDO"
+
+/* BUCK */
+#define S2MPS11_BUCK_VOLT_MASK 0xff
+#define S2MPS11_BUCK9_VOLT_MASK 0x1f
+
+#define S2MPS11_BUCK_LSTEP 6250
+#define S2MPS11_BUCK_HSTEP 12500
+#define S2MPS11_BUCK9_STEP 25000
+
+#define S2MPS11_BUCK_UV_MIN 600000
+#define S2MPS11_BUCK_UV_HMIN 750000
+#define S2MPS11_BUCK9_UV_MIN 1400000
+
+#define S2MPS11_BUCK_VOLT_MAX_HEX 0xA0
+#define S2MPS11_BUCK5_VOLT_MAX_HEX 0xDF
+#define S2MPS11_BUCK7_8_10_VOLT_MAX_HEX 0xDC
+#define S2MPS11_BUCK9_VOLT_MAX_HEX 0x5F
+
+#define S2MPS11_BUCK_MODE_SHIFT 6
+#define S2MPS11_BUCK_MODE_MASK (0x3)
+#define S2MPS11_BUCK_MODE_OFF (0x0 << 6)
+#define S2MPS11_BUCK_MODE_STANDBY (0x1 << 6)
+#define S2MPS11_BUCK_MODE_ON (0x3 << 6)
+
+/* LDO */
+#define S2MPS11_LDO_VOLT_MASK 0x3F
+#define S2MPS11_LDO_VOLT_MAX_HEX 0x3F
+
+#define S2MPS11_LDO_STEP 25000
+#define S2MPS11_LDO_UV_MIN 800000
+
+#define S2MPS11_LDO_MODE_MASK 0x3
+#define S2MPS11_LDO_MODE_SHIFT 6
+
+#define S2MPS11_LDO_MODE_OFF (0x0 << 6)
+#define S2MPS11_LDO_MODE_STANDBY (0x1 << 6)
+#define S2MPS11_LDO_MODE_STANDBY_LPM (0x2 << 6)
+#define S2MPS11_LDO_MODE_ON (0x3 << 6)
+
+enum {
+ OP_OFF = 0,
+ OP_LPM,
+ OP_STANDBY,
+ OP_STANDBY_LPM,
+ OP_ON,
+};
+
#endif
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_EFI) += efi/
+obj-$(CONFIG_EFI_LOADER) += efi_driver/
obj-$(CONFIG_EFI_LOADER) += efi_loader/
obj-$(CONFIG_EFI_LOADER) += efi_selftest/
obj-$(CONFIG_LZMA) += lzma/
--- /dev/null
+#
+# (C) Copyright 2017 Heinrich Schuchardt
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# This file only gets included with CONFIG_EFI_LOADER set, so all
+# object inclusion implicitly depends on it
+
+obj-y += efi_uclass.o
+ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy)
+obj-y += efi_block_device.o
+endif
--- /dev/null
+/*
+ * EFI block driver
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The EFI uclass creates a handle for this driver and installs the
+ * driver binding protocol on it.
+ *
+ * The EFI block driver binds to controllers implementing the block io
+ * protocol.
+ *
+ * When the bind function of the EFI block driver is called it creates a
+ * new U-Boot block device. It installs child handles for all partitions and
+ * installs the simple file protocol on these.
+ *
+ * The read and write functions of the EFI block driver delegate calls to the
+ * controller that it is bound to.
+ *
+ * A usage example is as following:
+ *
+ * U-Boot loads the iPXE snp.efi executable. iPXE connects an iSCSI drive and
+ * exposes a handle with the block IO protocol. It calls ConnectController.
+ *
+ * Now the EFI block driver installs the partitions with the simple file
+ * protocol.
+ *
+ * iPXE uses the simple file protocol to load Grub or the Linux Kernel.
+ */
+
+#include <efi_driver.h>
+#include <dm/device-internal.h>
+#include <dm/root.h>
+
+/*
+ * EFI attributes of the udevice handled by this driver.
+ *
+ * handle handle of the controller on which this driver is installed
+ * io block io protocol proxied by this driver
+ */
+struct efi_blk_priv {
+ efi_handle_t handle;
+ struct efi_block_io *io;
+};
+
+/*
+ * Read from block device
+ *
+ * @dev device
+ * @blknr first block to be read
+ * @blkcnt number of blocks to read
+ * @buffer output buffer
+ * @return number of blocks transferred
+ */
+static ulong efi_bl_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+{
+ struct efi_blk_priv *priv = dev->priv;
+ struct efi_block_io *io = priv->io;
+ efi_status_t ret;
+
+ EFI_PRINT("%s: read '%s', from block " LBAFU ", " LBAFU " blocks\n",
+ __func__, dev->name, blknr, blkcnt);
+ ret = EFI_CALL(io->read_blocks(
+ io, io->media->media_id, (u64)blknr,
+ (efi_uintn_t)blkcnt *
+ (efi_uintn_t)io->media->block_size, buffer));
+ EFI_PRINT("%s: r = %u\n", __func__,
+ (unsigned int)(ret & ~EFI_ERROR_MASK));
+ if (ret != EFI_SUCCESS)
+ return 0;
+ return blkcnt;
+}
+
+/*
+ * Write to block device
+ *
+ * @dev device
+ * @blknr first block to be write
+ * @blkcnt number of blocks to write
+ * @buffer input buffer
+ * @return number of blocks transferred
+ */
+static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+{
+ struct efi_blk_priv *priv = dev->priv;
+ struct efi_block_io *io = priv->io;
+ efi_status_t ret;
+
+ EFI_PRINT("%s: write '%s', from block " LBAFU ", " LBAFU " blocks\n",
+ __func__, dev->name, blknr, blkcnt);
+ ret = EFI_CALL(io->write_blocks(
+ io, io->media->media_id, (u64)blknr,
+ (efi_uintn_t)blkcnt *
+ (efi_uintn_t)io->media->block_size,
+ (void *)buffer));
+ EFI_PRINT("%s: r = %u\n", __func__,
+ (unsigned int)(ret & ~EFI_ERROR_MASK));
+ if (ret != EFI_SUCCESS)
+ return 0;
+ return blkcnt;
+}
+
+/*
+ * Create partions for the block device.
+ *
+ * @handle EFI handle of the block device
+ * @dev udevice of the block device
+ */
+static int efi_bl_bind_partitions(efi_handle_t handle, struct udevice *dev)
+{
+ struct blk_desc *desc;
+ const char *if_typename;
+
+ desc = dev_get_uclass_platdata(dev);
+ if_typename = blk_get_if_type_name(desc->if_type);
+
+ return efi_disk_create_partitions(handle, desc, if_typename,
+ desc->devnum, dev->name);
+}
+
+/*
+ * Create a block device for a handle
+ *
+ * @handle handle
+ * @interface block io protocol
+ * @return 0 = success
+ */
+static int efi_bl_bind(efi_handle_t handle, void *interface)
+{
+ struct udevice *bdev, *parent = dm_root();
+ int ret, devnum;
+ char *name;
+ struct efi_object *obj = efi_search_obj(handle);
+ struct efi_block_io *io = interface;
+ int disks;
+ struct efi_blk_priv *priv;
+
+ EFI_PRINT("%s: handle %p, interface %p\n", __func__, handle, io);
+
+ if (!obj)
+ return -ENOENT;
+
+ devnum = blk_find_max_devnum(IF_TYPE_EFI);
+ if (devnum == -ENODEV)
+ devnum = 0;
+ else if (devnum < 0)
+ return devnum;
+
+ name = calloc(1, 18); /* strlen("efiblk#2147483648") + 1 */
+ if (!name)
+ return -ENOMEM;
+ sprintf(name, "efiblk#%d", devnum);
+
+ /* Create driver model udevice for the EFI block io device */
+ ret = blk_create_device(parent, "efi_blk", name, IF_TYPE_EFI, devnum,
+ io->media->block_size,
+ (lbaint_t)io->media->last_block, &bdev);
+ if (ret)
+ return ret;
+ if (!bdev)
+ return -ENOENT;
+ /* Allocate priv */
+ ret = device_probe(bdev);
+ if (ret)
+ return ret;
+ EFI_PRINT("%s: block device '%s' created\n", __func__, bdev->name);
+
+ priv = bdev->priv;
+ priv->handle = handle;
+ priv->io = interface;
+
+ ret = blk_prepare_device(bdev);
+
+ /* Create handles for the partions of the block device */
+ disks = efi_bl_bind_partitions(handle, bdev);
+ EFI_PRINT("Found %d partitions\n", disks);
+
+ return 0;
+}
+
+/* Block device driver operators */
+static const struct blk_ops efi_blk_ops = {
+ .read = efi_bl_read,
+ .write = efi_bl_write,
+};
+
+/* Identify as block device driver */
+U_BOOT_DRIVER(efi_blk) = {
+ .name = "efi_blk",
+ .id = UCLASS_BLK,
+ .ops = &efi_blk_ops,
+ .priv_auto_alloc_size = sizeof(struct efi_blk_priv),
+};
+
+/* EFI driver operators */
+static const struct efi_driver_ops driver_ops = {
+ .protocol = &efi_block_io_guid,
+ .child_protocol = &efi_block_io_guid,
+ .bind = efi_bl_bind,
+};
+
+/* Identify as EFI driver */
+U_BOOT_DRIVER(efi_block) = {
+ .name = "EFI block driver",
+ .id = UCLASS_EFI,
+ .ops = &driver_ops,
+};
--- /dev/null
+/*
+ * Uclass for EFI drivers
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * For each EFI driver the uclass
+ * - creates a handle
+ * - installs the driver binding protocol
+ *
+ * The uclass provides the bind, start, and stop entry points for the driver
+ * binding protocol.
+ *
+ * In bind() and stop() it checks if the controller implements the protocol
+ * supported by the EFI driver. In the start() function it calls the bind()
+ * function of the EFI driver. In the stop() function it destroys the child
+ * controllers.
+ */
+
+#include <efi_driver.h>
+
+/*
+ * Check node type. We do not support partitions as controller handles.
+ *
+ * @handle handle to be checked
+ * @return status code
+ */
+static efi_status_t check_node_type(efi_handle_t handle)
+{
+ efi_status_t r, ret = EFI_SUCCESS;
+ const struct efi_device_path *dp;
+
+ /* Open the device path protocol */
+ r = EFI_CALL(systab.boottime->open_protocol(
+ handle, &efi_guid_device_path, (void **)&dp,
+ NULL, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (r == EFI_SUCCESS && dp) {
+ /* Get the last node */
+ const struct efi_device_path *node = efi_dp_last_node(dp);
+ /* We do not support partitions as controller */
+ if (!node || node->type == DEVICE_PATH_TYPE_MEDIA_DEVICE)
+ ret = EFI_UNSUPPORTED;
+ }
+ return ret;
+}
+
+/*
+ * Check if the driver supports the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @remaining_device_path path specifying the child controller
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_uc_supported(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path)
+{
+ efi_status_t r, ret;
+ void *interface;
+ struct efi_driver_binding_extended_protocol *bp =
+ (struct efi_driver_binding_extended_protocol *)this;
+
+ EFI_ENTRY("%p, %p, %ls", this, controller_handle,
+ efi_dp_str(remaining_device_path));
+
+ ret = EFI_CALL(systab.boottime->open_protocol(
+ controller_handle, bp->ops->protocol,
+ &interface, this->driver_binding_handle,
+ controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER));
+ switch (ret) {
+ case EFI_ACCESS_DENIED:
+ case EFI_ALREADY_STARTED:
+ goto out;
+ case EFI_SUCCESS:
+ break;
+ default:
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+
+ ret = check_node_type(controller_handle);
+
+ r = EFI_CALL(systab.boottime->close_protocol(
+ controller_handle, bp->ops->protocol,
+ this->driver_binding_handle,
+ controller_handle));
+ if (r != EFI_SUCCESS)
+ ret = EFI_UNSUPPORTED;
+out:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * Create child controllers and attach driver.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @remaining_device_path path specifying the child controller
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_uc_start(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path)
+{
+ efi_status_t r, ret;
+ void *interface = NULL;
+ struct efi_driver_binding_extended_protocol *bp =
+ (struct efi_driver_binding_extended_protocol *)this;
+
+ EFI_ENTRY("%p, %pUl, %ls", this, controller_handle,
+ efi_dp_str(remaining_device_path));
+
+ /* Attach driver to controller */
+ ret = EFI_CALL(systab.boottime->open_protocol(
+ controller_handle, bp->ops->protocol,
+ &interface, this->driver_binding_handle,
+ controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER));
+ switch (ret) {
+ case EFI_ACCESS_DENIED:
+ case EFI_ALREADY_STARTED:
+ goto out;
+ case EFI_SUCCESS:
+ break;
+ default:
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+ ret = check_node_type(controller_handle);
+ if (ret != EFI_SUCCESS) {
+ r = EFI_CALL(systab.boottime->close_protocol(
+ controller_handle, bp->ops->protocol,
+ this->driver_binding_handle,
+ controller_handle));
+ if (r != EFI_SUCCESS)
+ EFI_PRINT("Failure to close handle\n");
+ goto out;
+ }
+
+ /* TODO: driver specific stuff */
+ bp->ops->bind(controller_handle, interface);
+
+out:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * Remove a single child controller from the parent controller.
+ *
+ * @controller_handle parent controller
+ * @child_handle child controller
+ * @return status code
+ */
+static efi_status_t disconnect_child(efi_handle_t controller_handle,
+ efi_handle_t child_handle)
+{
+ efi_status_t ret;
+ efi_guid_t *guid_controller = NULL;
+ efi_guid_t *guid_child_controller = NULL;
+
+ ret = EFI_CALL(systab.boottime->close_protocol(
+ controller_handle, guid_controller,
+ child_handle, child_handle));
+ if (ret != EFI_SUCCESS) {
+ EFI_PRINT("Cannot close protocol\n");
+ return ret;
+ }
+ ret = EFI_CALL(systab.boottime->uninstall_protocol_interface(
+ child_handle, guid_child_controller, NULL));
+ if (ret != EFI_SUCCESS) {
+ EFI_PRINT("Cannot uninstall protocol interface\n");
+ return ret;
+ }
+ return ret;
+}
+
+/*
+ * Remove child controllers and disconnect the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @number_of_children number of child controllers to remove
+ * @child_handle_buffer handles of the child controllers to remove
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_uc_stop(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ size_t number_of_children,
+ efi_handle_t *child_handle_buffer)
+{
+ efi_status_t ret;
+ efi_uintn_t count;
+ struct efi_open_protocol_info_entry *entry_buffer;
+ efi_guid_t *guid_controller = NULL;
+
+ EFI_ENTRY("%p, %pUl, %zu, %p", this, controller_handle,
+ number_of_children, child_handle_buffer);
+
+ /* Destroy provided child controllers */
+ if (number_of_children) {
+ efi_uintn_t i;
+
+ for (i = 0; i < number_of_children; ++i) {
+ ret = disconnect_child(controller_handle,
+ child_handle_buffer[i]);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+ return EFI_SUCCESS;
+ }
+
+ /* Destroy all children */
+ ret = EFI_CALL(systab.boottime->open_protocol_information(
+ controller_handle, guid_controller,
+ &entry_buffer, &count));
+ if (ret != EFI_SUCCESS)
+ goto out;
+ while (count) {
+ if (entry_buffer[--count].attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
+ ret = disconnect_child(
+ controller_handle,
+ entry_buffer[count].agent_handle);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
+ }
+ ret = EFI_CALL(systab.boottime->free_pool(entry_buffer));
+ if (ret != EFI_SUCCESS)
+ printf("%s(%u) %s: ERROR: Cannot free pool\n",
+ __FILE__, __LINE__, __func__);
+
+ /* Detach driver from controller */
+ ret = EFI_CALL(systab.boottime->close_protocol(
+ controller_handle, guid_controller,
+ this->driver_binding_handle, controller_handle));
+out:
+ return EFI_EXIT(ret);
+}
+
+static efi_status_t efi_add_driver(struct driver *drv)
+{
+ efi_status_t ret;
+ const struct efi_driver_ops *ops = drv->ops;
+ struct efi_driver_binding_extended_protocol *bp;
+
+ debug("EFI: Adding driver '%s'\n", drv->name);
+ if (!ops->protocol) {
+ printf("EFI: ERROR: protocol GUID missing for driver '%s'\n",
+ drv->name);
+ return EFI_INVALID_PARAMETER;
+ }
+ bp = calloc(1, sizeof(struct efi_driver_binding_extended_protocol));
+ if (!bp)
+ return EFI_OUT_OF_RESOURCES;
+
+ bp->bp.supported = efi_uc_supported;
+ bp->bp.start = efi_uc_start;
+ bp->bp.stop = efi_uc_stop;
+ bp->bp.version = 0xffffffff;
+ bp->ops = drv->ops;
+
+ ret = efi_create_handle(&bp->bp.driver_binding_handle);
+ if (ret != EFI_SUCCESS) {
+ free(bp);
+ goto out;
+ }
+ bp->bp.image_handle = bp->bp.driver_binding_handle;
+ ret = efi_add_protocol(bp->bp.driver_binding_handle,
+ &efi_guid_driver_binding_protocol, bp);
+ if (ret != EFI_SUCCESS) {
+ efi_delete_handle(bp->bp.driver_binding_handle);
+ free(bp);
+ goto out;
+ }
+out:
+ return ret;
+}
+
+/*
+ * Initialize the EFI drivers.
+ * Called by board_init_r().
+ *
+ * @return 0 = success, any other value will stop further execution
+ */
+int efi_driver_init(void)
+{
+ struct driver *drv;
+ int ret = 0;
+
+ /* Save 'gd' pointer */
+ efi_save_gd();
+
+ debug("EFI: Initializing EFI driver framework\n");
+ for (drv = ll_entry_start(struct driver, driver);
+ drv < ll_entry_end(struct driver, driver); ++drv) {
+ if (drv->id == UCLASS_EFI) {
+ ret = efi_add_driver(drv);
+ if (ret) {
+ printf("EFI: ERROR: failed to add driver %s\n",
+ drv->name);
+ break;
+ }
+ }
+ }
+ return ret;
+}
+
+static int efi_uc_init(struct uclass *class)
+{
+ printf("EFI: Initializing UCLASS_EFI\n");
+ return 0;
+}
+
+static int efi_uc_destroy(struct uclass *class)
+{
+ printf("Destroying UCLASS_EFI\n");
+ return 0;
+}
+
+UCLASS_DRIVER(efi) = {
+ .name = "efi",
+ .id = UCLASS_EFI,
+ .init = efi_uc_init,
+ .destroy = efi_uc_destroy,
+};
static int entry_count;
static int nesting_level;
+/* GUID of the EFI_DRIVER_BINDING_PROTOCOL */
+const efi_guid_t efi_guid_driver_binding_protocol =
+ EFI_DRIVER_BINDING_PROTOCOL_GUID;
+
+static efi_status_t EFIAPI efi_disconnect_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t driver_image_handle,
+ efi_handle_t child_handle);
/* Called on every callback entry */
int __efi_entry_check(void)
* For the SignalEvent service see efi_signal_event_ext.
*
* @event event to signal
+ * @check_tpl check the TPL level
*/
-void efi_signal_event(struct efi_event *event)
+void efi_signal_event(struct efi_event *event, bool check_tpl)
{
if (event->notify_function) {
event->is_queued = true;
/* Check TPL */
- if (efi_tpl >= event->notify_tpl)
+ if (check_tpl && efi_tpl >= event->notify_tpl)
return;
EFI_CALL_VOID(event->notify_function(event,
event->notify_context));
* @handle new handle
* @return status code
*/
-efi_status_t efi_create_handle(void **handle)
+efi_status_t efi_create_handle(efi_handle_t *handle)
{
struct efi_object *obj;
efi_status_t r;
* @handler reference to the protocol
* @return status code
*/
-efi_status_t efi_search_protocol(const void *handle,
+efi_status_t efi_search_protocol(const efi_handle_t handle,
const efi_guid_t *protocol_guid,
struct efi_handler **handler)
{
* @protocol_interface interface of the protocol implementation
* @return status code
*/
-efi_status_t efi_remove_protocol(const void *handle, const efi_guid_t *protocol,
+efi_status_t efi_remove_protocol(const efi_handle_t handle,
+ const efi_guid_t *protocol,
void *protocol_interface)
{
struct efi_handler *handler;
* @handle handle from which the protocols shall be deleted
* @return status code
*/
-efi_status_t efi_remove_all_protocols(const void *handle)
+efi_status_t efi_remove_all_protocols(const efi_handle_t handle)
{
struct efi_object *efiobj;
- struct list_head *lhandle;
- struct list_head *pos;
+ struct efi_handler *protocol;
+ struct efi_handler *pos;
efiobj = efi_search_obj(handle);
if (!efiobj)
return EFI_INVALID_PARAMETER;
- list_for_each_safe(lhandle, pos, &efiobj->protocols) {
- struct efi_handler *protocol;
+ list_for_each_entry_safe(protocol, pos, &efiobj->protocols, link) {
efi_status_t ret;
- protocol = list_entry(lhandle, struct efi_handler, link);
-
ret = efi_remove_protocol(handle, protocol->guid,
protocol->protocol_interface);
if (ret != EFI_SUCCESS)
if (!efi_events[i].type)
continue;
if (efi_events[i].is_queued)
- efi_signal_event(&efi_events[i]);
+ efi_signal_event(&efi_events[i], true);
if (!(efi_events[i].type & EVT_TIMER) ||
now < efi_events[i].trigger_next)
continue;
continue;
}
efi_events[i].is_signaled = true;
- efi_signal_event(&efi_events[i]);
+ efi_signal_event(&efi_events[i], true);
}
WATCHDOG_RESET();
}
if (!event[i]->type || event[i]->type & EVT_NOTIFY_SIGNAL)
return EFI_EXIT(EFI_INVALID_PARAMETER);
if (!event[i]->is_signaled)
- efi_signal_event(event[i]);
+ efi_signal_event(event[i], true);
}
/* Wait for signal */
break;
event->is_signaled = true;
if (event->type & EVT_NOTIFY_SIGNAL)
- efi_signal_event(event);
+ efi_signal_event(event, true);
break;
}
return EFI_EXIT(EFI_SUCCESS);
if (!event->type || event->type & EVT_NOTIFY_SIGNAL)
break;
if (!event->is_signaled)
- efi_signal_event(event);
+ efi_signal_event(event, true);
if (event->is_signaled)
return EFI_EXIT(EFI_SUCCESS);
return EFI_EXIT(EFI_NOT_READY);
* @handle handle to find
* @return EFI object
*/
-struct efi_object *efi_search_obj(const void *handle)
+struct efi_object *efi_search_obj(const efi_handle_t handle)
{
struct efi_object *efiobj;
return NULL;
}
+/*
+ * Create open protocol info entry and add it to a protocol.
+ *
+ * @handler handler of a protocol
+ * @return open protocol info entry
+ */
+static struct efi_open_protocol_info_entry *efi_create_open_info(
+ struct efi_handler *handler)
+{
+ struct efi_open_protocol_info_item *item;
+
+ item = calloc(1, sizeof(struct efi_open_protocol_info_item));
+ if (!item)
+ return NULL;
+ /* Append the item to the open protocol info list. */
+ list_add_tail(&item->link, &handler->open_infos);
+
+ return &item->info;
+}
+
+/*
+ * Remove an open protocol info entry from a protocol.
+ *
+ * @handler handler of a protocol
+ * @return status code
+ */
+static efi_status_t efi_delete_open_info(
+ struct efi_open_protocol_info_item *item)
+{
+ list_del(&item->link);
+ free(item);
+ return EFI_SUCCESS;
+}
+
/*
* Install new protocol on a handle.
*
* @protocol_interface interface of the protocol implementation
* @return status code
*/
-efi_status_t efi_add_protocol(const void *handle, const efi_guid_t *protocol,
+efi_status_t efi_add_protocol(const efi_handle_t handle,
+ const efi_guid_t *protocol,
void *protocol_interface)
{
struct efi_object *efiobj;
return EFI_OUT_OF_RESOURCES;
handler->guid = protocol;
handler->protocol_interface = protocol_interface;
+ INIT_LIST_HEAD(&handler->open_infos);
list_add_tail(&handler->link, &efiobj->protocols);
+ if (!guidcmp(&efi_guid_device_path, protocol))
+ EFI_PRINT("installed device path '%pD'\n", protocol_interface);
return EFI_SUCCESS;
}
* @new_interface interface to be installed
* @return status code
*/
-static efi_status_t EFIAPI efi_reinstall_protocol_interface(void *handle,
- const efi_guid_t *protocol, void *old_interface,
- void *new_interface)
+static efi_status_t EFIAPI efi_reinstall_protocol_interface(
+ efi_handle_t handle, const efi_guid_t *protocol,
+ void *old_interface, void *new_interface)
{
EFI_ENTRY("%p, %pUl, %p, %p", handle, protocol, old_interface,
new_interface);
return EFI_EXIT(EFI_ACCESS_DENIED);
}
+/*
+ * Get all drivers associated to a controller.
+ * The allocated buffer has to be freed with free().
+ *
+ * @efiobj handle of the controller
+ * @protocol protocol guid (optional)
+ * @number_of_drivers number of child controllers
+ * @driver_handle_buffer handles of the the drivers
+ * @return status code
+ */
+static efi_status_t efi_get_drivers(struct efi_object *efiobj,
+ const efi_guid_t *protocol,
+ efi_uintn_t *number_of_drivers,
+ efi_handle_t **driver_handle_buffer)
+{
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ efi_uintn_t count = 0, i;
+ bool duplicate;
+
+ /* Count all driver associations */
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ if (protocol && guidcmp(handler->guid, protocol))
+ continue;
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_DRIVER)
+ ++count;
+ }
+ }
+ /*
+ * Create buffer. In case of duplicate driver assignments the buffer
+ * will be too large. But that does not harm.
+ */
+ *number_of_drivers = 0;
+ *driver_handle_buffer = calloc(count, sizeof(efi_handle_t));
+ if (!*driver_handle_buffer)
+ return EFI_OUT_OF_RESOURCES;
+ /* Collect unique driver handles */
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ if (protocol && guidcmp(handler->guid, protocol))
+ continue;
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_DRIVER) {
+ /* Check this is a new driver */
+ duplicate = false;
+ for (i = 0; i < *number_of_drivers; ++i) {
+ if ((*driver_handle_buffer)[i] ==
+ item->info.agent_handle)
+ duplicate = true;
+ }
+ /* Copy handle to buffer */
+ if (!duplicate) {
+ i = (*number_of_drivers)++;
+ (*driver_handle_buffer)[i] =
+ item->info.agent_handle;
+ }
+ }
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/*
+ * Disconnect all drivers from a controller.
+ *
+ * This function implements the DisconnectController service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @efiobj handle of the controller
+ * @protocol protocol guid (optional)
+ * @child_handle handle of the child to destroy
+ * @return status code
+ */
+static efi_status_t efi_disconnect_all_drivers(
+ struct efi_object *efiobj,
+ const efi_guid_t *protocol,
+ efi_handle_t child_handle)
+{
+ efi_uintn_t number_of_drivers;
+ efi_handle_t *driver_handle_buffer;
+ efi_status_t r, ret;
+
+ ret = efi_get_drivers(efiobj, protocol, &number_of_drivers,
+ &driver_handle_buffer);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = EFI_NOT_FOUND;
+ while (number_of_drivers) {
+ r = EFI_CALL(efi_disconnect_controller(
+ efiobj->handle,
+ driver_handle_buffer[--number_of_drivers],
+ child_handle));
+ if (r == EFI_SUCCESS)
+ ret = r;
+ }
+ free(driver_handle_buffer);
+ return ret;
+}
+
/*
* Uninstall protocol interface.
*
* @return status code
*/
static efi_status_t EFIAPI efi_uninstall_protocol_interface(
- void *handle, const efi_guid_t *protocol,
+ efi_handle_t handle, const efi_guid_t *protocol,
void *protocol_interface)
{
+ struct efi_object *efiobj;
struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ struct efi_open_protocol_info_item *pos;
efi_status_t r;
EFI_ENTRY("%p, %pUl, %p", handle, protocol, protocol_interface);
- if (!handle || !protocol) {
+ /* Check handle */
+ efiobj = efi_search_obj(handle);
+ if (!efiobj) {
r = EFI_INVALID_PARAMETER;
goto out;
}
-
/* Find the protocol on the handle */
r = efi_search_protocol(handle, protocol, &handler);
if (r != EFI_SUCCESS)
goto out;
- if (handler->protocol_interface) {
- /* TODO disconnect controllers */
+ /* Disconnect controllers */
+ efi_disconnect_all_drivers(efiobj, protocol, NULL);
+ if (!list_empty(&handler->open_infos)) {
r = EFI_ACCESS_DENIED;
- } else {
- r = efi_remove_protocol(handle, protocol, protocol_interface);
+ goto out;
+ }
+ /* Close protocol */
+ list_for_each_entry_safe(item, pos, &handler->open_infos, link) {
+ if (item->info.attributes ==
+ EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL ||
+ item->info.attributes == EFI_OPEN_PROTOCOL_GET_PROTOCOL ||
+ item->info.attributes == EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
+ list_del(&item->link);
}
+ if (!list_empty(&handler->open_infos)) {
+ r = EFI_ACCESS_DENIED;
+ goto out;
+ }
+ r = efi_remove_protocol(handle, protocol, protocol_interface);
out:
return EFI_EXIT(r);
}
struct efi_object *obj;
efi_status_t ret;
- EFI_ENTRY("%d, %p, %p, %p, %ld, %p", boot_policy, parent_image,
+ EFI_ENTRY("%d, %p, %pD, %p, %ld, %p", boot_policy, parent_image,
file_path, source_buffer, source_size, image_handle);
info = calloc(1, sizeof(*info));
unsigned long *exit_data_size,
s16 **exit_data)
{
- ulong (*entry)(void *image_handle, struct efi_system_table *st);
+ asmlinkage ulong (*entry)(efi_handle_t image_handle,
+ struct efi_system_table *st);
struct efi_loaded_image *info = image_handle;
+ efi_status_t ret;
EFI_ENTRY("%p, %p, %p", image_handle, exit_data_size, exit_data);
entry = info->reserved;
/* call the image! */
if (setjmp(&info->exit_jmp)) {
- /* We returned from the child image */
+ /*
+ * We called the entry point of the child image with EFI_CALL
+ * in the lines below. The child image called the Exit() boot
+ * service efi_exit() which executed the long jump that brought
+ * us to the current line. This implies that the second half
+ * of the EFI_CALL macro has not been executed.
+ */
+#ifdef CONFIG_ARM
+ /*
+ * efi_exit() called efi_restore_gd(). We have to undo this
+ * otherwise __efi_entry_check() will put the wrong value into
+ * app_gd.
+ */
+ gd = app_gd;
+#endif
+ /*
+ * To get ready to call EFI_EXIT below we have to execute the
+ * missed out steps of EFI_CALL.
+ */
+ assert(__efi_entry_check());
+ debug("%sEFI: %lu returned by started image\n",
+ __efi_nesting_dec(),
+ (unsigned long)((uintptr_t)info->exit_status &
+ ~EFI_ERROR_MASK));
return EFI_EXIT(info->exit_status);
}
- __efi_nesting_dec();
- __efi_exit_check();
- entry(image_handle, &systab);
- __efi_entry_check();
- __efi_nesting_inc();
+ ret = EFI_CALL(entry(image_handle, &systab));
/* Should usually never get here */
- return EFI_EXIT(EFI_SUCCESS);
+ return EFI_EXIT(ret);
}
/*
exit_data_size, exit_data);
/* Make sure entry/exit counts for EFI world cross-overs match */
- __efi_exit_check();
+ EFI_EXIT(exit_status);
/*
* But longjmp out with the U-Boot gd, not the application's, as
* @image_handle handle of the image to be unloaded
* @return status code
*/
-static efi_status_t EFIAPI efi_unload_image(void *image_handle)
+static efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle)
{
struct efi_object *efiobj;
}
/*
- * Stop boot services.
+ * Stop all boot services.
*
* This function implements the ExitBootServices service.
* See the Unified Extensible Firmware Interface (UEFI) specification
* for details.
*
+ * All timer events are disabled.
+ * For exit boot services events the notification function is called.
+ * The boot services are disabled in the system table.
+ *
* @image_handle handle of the loaded image
* @map_key key of the memory map
* @return status code
*/
-static efi_status_t EFIAPI efi_exit_boot_services(void *image_handle,
+static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle,
unsigned long map_key)
{
int i;
EFI_ENTRY("%p, %ld", image_handle, map_key);
+ /* Make sure that notification functions are not called anymore */
+ efi_tpl = TPL_HIGH_LEVEL;
+
+ /* Check if ExitBootServices has already been called */
+ if (!systab.boottime)
+ return EFI_EXIT(EFI_SUCCESS);
+
/* Notify that ExitBootServices is invoked. */
for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
if (efi_events[i].type != EVT_SIGNAL_EXIT_BOOT_SERVICES)
continue;
- efi_signal_event(&efi_events[i]);
+ efi_events[i].is_signaled = true;
+ efi_signal_event(&efi_events[i], false);
}
- /* Make sure that notification functions are not called anymore */
- efi_tpl = TPL_HIGH_LEVEL;
- /* XXX Should persist EFI variables here */
+ /* TODO Should persist EFI variables here */
board_quiesce_devices();
/* This stops all lingering devices */
bootm_disable_interrupts();
+ /* Disable boottime services */
+ systab.con_in_handle = NULL;
+ systab.con_in = NULL;
+ systab.con_out_handle = NULL;
+ systab.con_out = NULL;
+ systab.stderr_handle = NULL;
+ systab.std_err = NULL;
+ systab.boottime = NULL;
+
+ /* Recalculate CRC32 */
+ systab.hdr.crc32 = 0;
+ systab.hdr.crc32 = crc32(0, (const unsigned char *)&systab,
+ sizeof(struct efi_system_table));
+
/* Give the payload some time to boot */
efi_set_watchdog(0);
WATCHDOG_RESET();
return EFI_EXIT(efi_set_watchdog(timeout));
}
-/*
- * Connect a controller to a driver.
- *
- * This function implements the ConnectController service.
- * See the Unified Extensible Firmware Interface (UEFI) specification
- * for details.
- *
- * @controller_handle handle of the controller
- * @driver_image_handle handle of the driver
- * @remain_device_path device path of a child controller
- * @recursive true to connect all child controllers
- * @return status code
- */
-static efi_status_t EFIAPI efi_connect_controller(
- efi_handle_t controller_handle,
- efi_handle_t *driver_image_handle,
- struct efi_device_path *remain_device_path,
- bool recursive)
-{
- EFI_ENTRY("%p, %p, %p, %d", controller_handle, driver_image_handle,
- remain_device_path, recursive);
- return EFI_EXIT(EFI_NOT_FOUND);
-}
-
-/*
- * Disconnect a controller from a driver.
- *
- * This function implements the DisconnectController service.
- * See the Unified Extensible Firmware Interface (UEFI) specification
- * for details.
- *
- * @controller_handle handle of the controller
- * @driver_image_handle handle of the driver
- * @child_handle handle of the child to destroy
- * @return status code
- */
-static efi_status_t EFIAPI efi_disconnect_controller(void *controller_handle,
- void *driver_image_handle,
- void *child_handle)
-{
- EFI_ENTRY("%p, %p, %p", controller_handle, driver_image_handle,
- child_handle);
- return EFI_EXIT(EFI_INVALID_PARAMETER);
-}
-
/*
* Close a protocol.
*
* @controller_handle handle of the controller
* @return status code
*/
-static efi_status_t EFIAPI efi_close_protocol(void *handle,
+static efi_status_t EFIAPI efi_close_protocol(efi_handle_t handle,
const efi_guid_t *protocol,
- void *agent_handle,
- void *controller_handle)
+ efi_handle_t agent_handle,
+ efi_handle_t controller_handle)
{
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ struct efi_open_protocol_info_item *pos;
+ efi_status_t r;
+
EFI_ENTRY("%p, %pUl, %p, %p", handle, protocol, agent_handle,
controller_handle);
- return EFI_EXIT(EFI_NOT_FOUND);
+
+ if (!agent_handle) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ r = efi_search_protocol(handle, protocol, &handler);
+ if (r != EFI_SUCCESS)
+ goto out;
+
+ r = EFI_NOT_FOUND;
+ list_for_each_entry_safe(item, pos, &handler->open_infos, link) {
+ if (item->info.agent_handle == agent_handle &&
+ item->info.controller_handle == controller_handle) {
+ efi_delete_open_info(item);
+ r = EFI_SUCCESS;
+ break;
+ }
+ }
+out:
+ return EFI_EXIT(r);
}
/*
struct efi_open_protocol_info_entry **entry_buffer,
efi_uintn_t *entry_count)
{
+ unsigned long buffer_size;
+ unsigned long count;
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ efi_status_t r;
+
EFI_ENTRY("%p, %pUl, %p, %p", handle, protocol, entry_buffer,
entry_count);
- return EFI_EXIT(EFI_NOT_FOUND);
+
+ /* Check parameters */
+ if (!entry_buffer) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ r = efi_search_protocol(handle, protocol, &handler);
+ if (r != EFI_SUCCESS)
+ goto out;
+
+ /* Count entries */
+ count = 0;
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.open_count)
+ ++count;
+ }
+ *entry_count = count;
+ *entry_buffer = NULL;
+ if (!count) {
+ r = EFI_SUCCESS;
+ goto out;
+ }
+
+ /* Copy entries */
+ buffer_size = count * sizeof(struct efi_open_protocol_info_entry);
+ r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, buffer_size,
+ (void **)entry_buffer);
+ if (r != EFI_SUCCESS)
+ goto out;
+ list_for_each_entry_reverse(item, &handler->open_infos, link) {
+ if (item->info.open_count)
+ (*entry_buffer)[--count] = item->info;
+ }
+out:
+ return EFI_EXIT(r);
}
/*
* @protocol_buffer_count number of entries in the buffer
* @return status code
*/
-static efi_status_t EFIAPI efi_protocols_per_handle(void *handle,
- efi_guid_t ***protocol_buffer,
+static efi_status_t EFIAPI efi_protocols_per_handle(
+ efi_handle_t handle, efi_guid_t ***protocol_buffer,
efi_uintn_t *protocol_buffer_count)
{
unsigned long buffer_size;
r = efi_locate_handle(search_type, protocol, search_key, &buffer_size,
*buffer);
if (r == EFI_SUCCESS)
- *no_handles = buffer_size / sizeof(void *);
+ *no_handles = buffer_size / sizeof(efi_handle_t);
out:
return EFI_EXIT(r);
}
EFI_EXIT(EFI_SUCCESS);
}
+/*
+ * Open protocol interface on a handle.
+ *
+ * @handler handler of a protocol
+ * @protocol_interface interface implementing the protocol
+ * @agent_handle handle of the driver
+ * @controller_handle handle of the controller
+ * @attributes attributes indicating how to open the protocol
+ * @return status code
+ */
+static efi_status_t efi_protocol_open(
+ struct efi_handler *handler,
+ void **protocol_interface, void *agent_handle,
+ void *controller_handle, uint32_t attributes)
+{
+ struct efi_open_protocol_info_item *item;
+ struct efi_open_protocol_info_entry *match = NULL;
+ bool opened_by_driver = false;
+ bool opened_exclusive = false;
+
+ /* If there is no agent, only return the interface */
+ if (!agent_handle)
+ goto out;
+
+ /* For TEST_PROTOCOL ignore interface attribute */
+ if (attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
+ *protocol_interface = NULL;
+
+ /*
+ * Check if the protocol is already opened by a driver with the same
+ * attributes or opened exclusively
+ */
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.agent_handle == agent_handle) {
+ if ((attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) &&
+ (item->info.attributes == attributes))
+ return EFI_ALREADY_STARTED;
+ }
+ if (item->info.attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE)
+ opened_exclusive = true;
+ }
+
+ /* Only one controller can open the protocol exclusively */
+ if (opened_exclusive && attributes &
+ (EFI_OPEN_PROTOCOL_EXCLUSIVE | EFI_OPEN_PROTOCOL_BY_DRIVER))
+ return EFI_ACCESS_DENIED;
+
+ /* Prepare exclusive opening */
+ if (attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE) {
+ /* Try to disconnect controllers */
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes ==
+ EFI_OPEN_PROTOCOL_BY_DRIVER)
+ EFI_CALL(efi_disconnect_controller(
+ item->info.controller_handle,
+ item->info.agent_handle,
+ NULL));
+ }
+ opened_by_driver = false;
+ /* Check if all controllers are disconnected */
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes & EFI_OPEN_PROTOCOL_BY_DRIVER)
+ opened_by_driver = true;
+ }
+ /* Only one controller can be conncected */
+ if (opened_by_driver)
+ return EFI_ACCESS_DENIED;
+ }
+
+ /* Find existing entry */
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.agent_handle == agent_handle &&
+ item->info.controller_handle == controller_handle)
+ match = &item->info;
+ }
+ /* None found, create one */
+ if (!match) {
+ match = efi_create_open_info(handler);
+ if (!match)
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ match->agent_handle = agent_handle;
+ match->controller_handle = controller_handle;
+ match->attributes = attributes;
+ match->open_count++;
+
+out:
+ /* For TEST_PROTOCOL ignore interface attribute. */
+ if (attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
+ *protocol_interface = handler->protocol_interface;
+
+ return EFI_SUCCESS;
+}
+
/*
* Open protocol interface on a handle.
*
case EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER:
if (controller_handle == handle)
goto out;
+ /* fall-through */
case EFI_OPEN_PROTOCOL_BY_DRIVER:
case EFI_OPEN_PROTOCOL_BY_DRIVER | EFI_OPEN_PROTOCOL_EXCLUSIVE:
- if (controller_handle == NULL)
+ /* Check that the controller handle is valid */
+ if (!efi_search_obj(controller_handle))
goto out;
+ /* fall-through */
case EFI_OPEN_PROTOCOL_EXCLUSIVE:
- if (agent_handle == NULL)
+ /* Check that the agent handle is valid */
+ if (!efi_search_obj(agent_handle))
goto out;
break;
default:
if (r != EFI_SUCCESS)
goto out;
- if (attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
- *protocol_interface = handler->protocol_interface;
+ r = efi_protocol_open(handler, protocol_interface, agent_handle,
+ controller_handle, attributes);
out:
return EFI_EXIT(r);
}
* @protocol_interface interface implementing the protocol
* @return status code
*/
-static efi_status_t EFIAPI efi_handle_protocol(void *handle,
+static efi_status_t EFIAPI efi_handle_protocol(efi_handle_t handle,
const efi_guid_t *protocol,
void **protocol_interface)
{
NULL, EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL);
}
+static efi_status_t efi_bind_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t driver_image_handle,
+ struct efi_device_path *remain_device_path)
+{
+ struct efi_driver_binding_protocol *binding_protocol;
+ efi_status_t r;
+
+ r = EFI_CALL(efi_open_protocol(driver_image_handle,
+ &efi_guid_driver_binding_protocol,
+ (void **)&binding_protocol,
+ driver_image_handle, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (r != EFI_SUCCESS)
+ return r;
+ r = EFI_CALL(binding_protocol->supported(binding_protocol,
+ controller_handle,
+ remain_device_path));
+ if (r == EFI_SUCCESS)
+ r = EFI_CALL(binding_protocol->start(binding_protocol,
+ controller_handle,
+ remain_device_path));
+ EFI_CALL(efi_close_protocol(driver_image_handle,
+ &efi_guid_driver_binding_protocol,
+ driver_image_handle, NULL));
+ return r;
+}
+
+static efi_status_t efi_connect_single_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t *driver_image_handle,
+ struct efi_device_path *remain_device_path)
+{
+ efi_handle_t *buffer;
+ size_t count;
+ size_t i;
+ efi_status_t r;
+ size_t connected = 0;
+
+ /* Get buffer with all handles with driver binding protocol */
+ r = EFI_CALL(efi_locate_handle_buffer(BY_PROTOCOL,
+ &efi_guid_driver_binding_protocol,
+ NULL, &count, &buffer));
+ if (r != EFI_SUCCESS)
+ return r;
+
+ /* Context Override */
+ if (driver_image_handle) {
+ for (; *driver_image_handle; ++driver_image_handle) {
+ for (i = 0; i < count; ++i) {
+ if (buffer[i] == *driver_image_handle) {
+ buffer[i] = NULL;
+ r = efi_bind_controller(
+ controller_handle,
+ *driver_image_handle,
+ remain_device_path);
+ /*
+ * For drivers that do not support the
+ * controller or are already connected
+ * we receive an error code here.
+ */
+ if (r == EFI_SUCCESS)
+ ++connected;
+ }
+ }
+ }
+ }
+
+ /*
+ * TODO: Some overrides are not yet implemented:
+ * - Platform Driver Override
+ * - Driver Family Override Search
+ * - Bus Specific Driver Override
+ */
+
+ /* Driver Binding Search */
+ for (i = 0; i < count; ++i) {
+ if (buffer[i]) {
+ r = efi_bind_controller(controller_handle,
+ buffer[i],
+ remain_device_path);
+ if (r == EFI_SUCCESS)
+ ++connected;
+ }
+ }
+
+ efi_free_pool(buffer);
+ if (!connected)
+ return EFI_NOT_FOUND;
+ return EFI_SUCCESS;
+}
+
+/*
+ * Connect a controller to a driver.
+ *
+ * This function implements the ConnectController service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * First all driver binding protocol handles are tried for binding drivers.
+ * Afterwards all handles that have openened a protocol of the controller
+ * with EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER are connected to drivers.
+ *
+ * @controller_handle handle of the controller
+ * @driver_image_handle handle of the driver
+ * @remain_device_path device path of a child controller
+ * @recursive true to connect all child controllers
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_connect_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t *driver_image_handle,
+ struct efi_device_path *remain_device_path,
+ bool recursive)
+{
+ efi_status_t r;
+ efi_status_t ret = EFI_NOT_FOUND;
+ struct efi_object *efiobj;
+
+ EFI_ENTRY("%p, %p, %p, %d", controller_handle, driver_image_handle,
+ remain_device_path, recursive);
+
+ efiobj = efi_search_obj(controller_handle);
+ if (!efiobj) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ r = efi_connect_single_controller(controller_handle,
+ driver_image_handle,
+ remain_device_path);
+ if (r == EFI_SUCCESS)
+ ret = EFI_SUCCESS;
+ if (recursive) {
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
+ r = EFI_CALL(efi_connect_controller(
+ item->info.controller_handle,
+ driver_image_handle,
+ remain_device_path,
+ recursive));
+ if (r == EFI_SUCCESS)
+ ret = EFI_SUCCESS;
+ }
+ }
+ }
+ }
+ /* Check for child controller specified by end node */
+ if (ret != EFI_SUCCESS && remain_device_path &&
+ remain_device_path->type == DEVICE_PATH_TYPE_END)
+ ret = EFI_SUCCESS;
+out:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * Get all child controllers associated to a driver.
+ * The allocated buffer has to be freed with free().
+ *
+ * @efiobj handle of the controller
+ * @driver_handle handle of the driver
+ * @number_of_children number of child controllers
+ * @child_handle_buffer handles of the the child controllers
+ */
+static efi_status_t efi_get_child_controllers(
+ struct efi_object *efiobj,
+ efi_handle_t driver_handle,
+ efi_uintn_t *number_of_children,
+ efi_handle_t **child_handle_buffer)
+{
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ efi_uintn_t count = 0, i;
+ bool duplicate;
+
+ /* Count all child controller associations */
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.agent_handle == driver_handle &&
+ item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)
+ ++count;
+ }
+ }
+ /*
+ * Create buffer. In case of duplicate child controller assignments
+ * the buffer will be too large. But that does not harm.
+ */
+ *number_of_children = 0;
+ *child_handle_buffer = calloc(count, sizeof(efi_handle_t));
+ if (!*child_handle_buffer)
+ return EFI_OUT_OF_RESOURCES;
+ /* Copy unique child handles */
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.agent_handle == driver_handle &&
+ item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
+ /* Check this is a new child controller */
+ duplicate = false;
+ for (i = 0; i < *number_of_children; ++i) {
+ if ((*child_handle_buffer)[i] ==
+ item->info.controller_handle)
+ duplicate = true;
+ }
+ /* Copy handle to buffer */
+ if (!duplicate) {
+ i = (*number_of_children)++;
+ (*child_handle_buffer)[i] =
+ item->info.controller_handle;
+ }
+ }
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/*
+ * Disconnect a controller from a driver.
+ *
+ * This function implements the DisconnectController service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @controller_handle handle of the controller
+ * @driver_image_handle handle of the driver
+ * @child_handle handle of the child to destroy
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_disconnect_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t driver_image_handle,
+ efi_handle_t child_handle)
+{
+ struct efi_driver_binding_protocol *binding_protocol;
+ efi_handle_t *child_handle_buffer = NULL;
+ size_t number_of_children = 0;
+ efi_status_t r;
+ size_t stop_count = 0;
+ struct efi_object *efiobj;
+
+ EFI_ENTRY("%p, %p, %p", controller_handle, driver_image_handle,
+ child_handle);
+
+ efiobj = efi_search_obj(controller_handle);
+ if (!efiobj) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ if (child_handle && !efi_search_obj(child_handle)) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ /* If no driver handle is supplied, disconnect all drivers */
+ if (!driver_image_handle) {
+ r = efi_disconnect_all_drivers(efiobj, NULL, child_handle);
+ goto out;
+ }
+
+ /* Create list of child handles */
+ if (child_handle) {
+ number_of_children = 1;
+ child_handle_buffer = &child_handle;
+ } else {
+ efi_get_child_controllers(efiobj,
+ driver_image_handle,
+ &number_of_children,
+ &child_handle_buffer);
+ }
+
+ /* Get the driver binding protocol */
+ r = EFI_CALL(efi_open_protocol(driver_image_handle,
+ &efi_guid_driver_binding_protocol,
+ (void **)&binding_protocol,
+ driver_image_handle, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (r != EFI_SUCCESS)
+ goto out;
+ /* Remove the children */
+ if (number_of_children) {
+ r = EFI_CALL(binding_protocol->stop(binding_protocol,
+ controller_handle,
+ number_of_children,
+ child_handle_buffer));
+ if (r == EFI_SUCCESS)
+ ++stop_count;
+ }
+ /* Remove the driver */
+ if (!child_handle)
+ r = EFI_CALL(binding_protocol->stop(binding_protocol,
+ controller_handle,
+ 0, NULL));
+ if (r == EFI_SUCCESS)
+ ++stop_count;
+ EFI_CALL(efi_close_protocol(driver_image_handle,
+ &efi_guid_driver_binding_protocol,
+ driver_image_handle, NULL));
+
+ if (stop_count)
+ r = EFI_SUCCESS;
+ else
+ r = EFI_NOT_FOUND;
+out:
+ if (!child_handle)
+ free(child_handle_buffer);
+ return EFI_EXIT(r);
+}
+
static const struct efi_boot_services efi_boot_services = {
.hdr = {
.headersize = sizeof(struct efi_table_hdr),
};
-static uint16_t __efi_runtime_data firmware_vendor[] =
- { 'D','a','s',' ','U','-','b','o','o','t',0 };
+static uint16_t __efi_runtime_data firmware_vendor[] = L"Das U-Boot";
struct efi_system_table __efi_runtime_data systab = {
.hdr = {
{
}
+/*
+ * Notification function of the console timer event.
+ *
+ * event: console timer event
+ * context: not used
+ */
static void EFIAPI efi_console_timer_notify(struct efi_event *event,
void *context)
{
EFI_ENTRY("%p, %p", event, context);
+
+ /* Check if input is available */
if (tstc()) {
+ /* Queue the wait for key event */
efi_con_in.wait_for_key->is_signaled = true;
- efi_signal_event(efi_con_in.wait_for_key);
- }
+ efi_signal_event(efi_con_in.wait_for_key, true);
+ }
EFI_EXIT(EFI_SUCCESS);
}
-
/* This gets called from do_bootefi_exec(). */
int efi_console_register(void)
{
struct efi_object *efi_console_input_obj;
/* Create handles */
- r = efi_create_handle((void **)&efi_console_control_obj);
+ r = efi_create_handle((efi_handle_t *)&efi_console_control_obj);
if (r != EFI_SUCCESS)
goto out_of_memory;
r = efi_add_protocol(efi_console_control_obj->handle,
&efi_guid_console_control, &efi_console_control);
if (r != EFI_SUCCESS)
goto out_of_memory;
- r = efi_create_handle((void **)&efi_console_output_obj);
+ r = efi_create_handle((efi_handle_t *)&efi_console_output_obj);
if (r != EFI_SUCCESS)
goto out_of_memory;
r = efi_add_protocol(efi_console_output_obj->handle,
&efi_guid_text_output_protocol, &efi_con_out);
if (r != EFI_SUCCESS)
goto out_of_memory;
- r = efi_create_handle((void **)&efi_console_input_obj);
+ r = efi_create_handle((efi_handle_t *)&efi_console_input_obj);
if (r != EFI_SUCCESS)
goto out_of_memory;
r = efi_add_protocol(efi_console_input_obj->handle,
* SPDX-License-Identifier: GPL-2.0+
*/
+#define LOG_CATEGORY LOGL_ERR
+
#include <common.h>
#include <blk.h>
#include <dm.h>
{
void *buf;
- if (efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, sz, &buf) != EFI_SUCCESS)
+ if (efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, sz, &buf) !=
+ EFI_SUCCESS) {
+ debug("EFI: ERROR: out of memory in %s\n", __func__);
return NULL;
+ }
return buf;
}
}
}
-
/*
* See UEFI spec (section 3.1.2, about short-form device-paths..
* tl;dr: we can have a device-path that starts with a USB WWID
return NULL;
}
-
/*
* Find an efiobj from device-path, if 'rem' is not NULL, returns the
* remaining part of the device path after the matched object.
return efiobj;
}
+/*
+ * Determine the last device path node that is not the end node.
+ *
+ * @dp device path
+ * @return last node before the end node if it exists
+ * otherwise NULL
+ */
+const struct efi_device_path *efi_dp_last_node(const struct efi_device_path *dp)
+{
+ struct efi_device_path *ret;
+
+ if (!dp || dp->type == DEVICE_PATH_TYPE_END)
+ return NULL;
+ while (dp) {
+ ret = (struct efi_device_path *)dp;
+ dp = efi_dp_next(dp);
+ }
+ return ret;
+}
+
/* return size not including End node: */
unsigned efi_dp_size(const struct efi_device_path *dp)
{
return NULL;
ndp = dp_alloc(sz);
+ if (!ndp)
+ return NULL;
memcpy(ndp, dp, sz);
return ndp;
unsigned sz1 = efi_dp_size(dp1);
unsigned sz2 = efi_dp_size(dp2);
void *p = dp_alloc(sz1 + sz2 + sizeof(END));
+ if (!p)
+ return NULL;
memcpy(p, dp1, sz1);
memcpy(p + sz1, dp2, sz2);
memcpy(p + sz1 + sz2, &END, sizeof(END));
} else if (!dp) {
unsigned sz = node->length;
void *p = dp_alloc(sz + sizeof(END));
+ if (!p)
+ return NULL;
memcpy(p, node, sz);
memcpy(p + sz, &END, sizeof(END));
ret = p;
/* both dp and node are non-null */
unsigned sz = efi_dp_size(dp);
void *p = dp_alloc(sz + node->length + sizeof(END));
+ if (!p)
+ return NULL;
memcpy(p, dp, sz);
memcpy(p + sz, node, node->length);
memcpy(p + sz + node->length, &END, sizeof(END));
case UCLASS_SIMPLE_BUS:
/* stop traversing parents at this point: */
return sizeof(ROOT);
+ case UCLASS_ETH:
+ return dp_size(dev->parent) +
+ sizeof(struct efi_device_path_mac_addr);
+#ifdef CONFIG_BLK
+ case UCLASS_BLK:
+ switch (dev->parent->uclass->uc_drv->id) {
+#ifdef CONFIG_IDE
+ case UCLASS_IDE:
+ return dp_size(dev->parent) +
+ sizeof(struct efi_device_path_atapi);
+#endif
+#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+ case UCLASS_SCSI:
+ return dp_size(dev->parent) +
+ sizeof(struct efi_device_path_scsi);
+#endif
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+ case UCLASS_MMC:
+ return dp_size(dev->parent) +
+ sizeof(struct efi_device_path_sd_mmc_path);
+#endif
+ default:
+ return dp_size(dev->parent);
+ }
+#endif
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
case UCLASS_MMC:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_sd_mmc_path);
+#endif
case UCLASS_MASS_STORAGE:
case UCLASS_USB_HUB:
return dp_size(dev->parent) +
}
}
+/*
+ * Recursively build a device path.
+ *
+ * @buf pointer to the end of the device path
+ * @dev device
+ * @return pointer to the end of the device path
+ */
static void *dp_fill(void *buf, struct udevice *dev)
{
if (!dev || !dev->driver)
*vdp = ROOT;
return &vdp[1];
}
+#ifdef CONFIG_DM_ETH
+ case UCLASS_ETH: {
+ struct efi_device_path_mac_addr *dp =
+ dp_fill(buf, dev->parent);
+ struct eth_pdata *pdata = dev->platdata;
+
+ dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR;
+ dp->dp.length = sizeof(*dp);
+ memset(&dp->mac, 0, sizeof(dp->mac));
+ /* We only support IPv4 */
+ memcpy(&dp->mac, &pdata->enetaddr, ARP_HLEN);
+ /* Ethernet */
+ dp->if_type = 1;
+ return &dp[1];
+ }
+#endif
+#ifdef CONFIG_BLK
+ case UCLASS_BLK:
+ switch (dev->parent->uclass->uc_drv->id) {
+#ifdef CONFIG_IDE
+ case UCLASS_IDE: {
+ struct efi_device_path_atapi *dp =
+ dp_fill(buf, dev->parent);
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_ATAPI;
+ dp->dp.length = sizeof(*dp);
+ dp->logical_unit_number = desc->devnum;
+ dp->primary_secondary = IDE_BUS(desc->devnum);
+ dp->slave_master = desc->devnum %
+ (CONFIG_SYS_IDE_MAXDEVICE /
+ CONFIG_SYS_IDE_MAXBUS);
+ return &dp[1];
+ }
+#endif
+#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+ case UCLASS_SCSI: {
+ struct efi_device_path_scsi *dp =
+ dp_fill(buf, dev->parent);
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_SCSI;
+ dp->dp.length = sizeof(*dp);
+ dp->logical_unit_number = desc->lun;
+ dp->target_id = desc->target;
+ return &dp[1];
+ }
+#endif
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+ case UCLASS_MMC: {
+ struct efi_device_path_sd_mmc_path *sddp =
+ dp_fill(buf, dev->parent);
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ sddp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ sddp->dp.sub_type = is_sd(desc) ?
+ DEVICE_PATH_SUB_TYPE_MSG_SD :
+ DEVICE_PATH_SUB_TYPE_MSG_MMC;
+ sddp->dp.length = sizeof(*sddp);
+ sddp->slot_number = dev->seq;
+ return &sddp[1];
+ }
+#endif
+ default:
+ debug("%s(%u) %s: unhandled parent class: %s (%u)\n",
+ __FILE__, __LINE__, __func__,
+ dev->name, dev->parent->uclass->uc_drv->id);
+ return dp_fill(buf, dev->parent);
+ }
+#endif
#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
case UCLASS_MMC: {
struct efi_device_path_sd_mmc_path *sddp =
return &udp[1];
}
default:
- debug("unhandled device class: %s (%u)\n",
+ debug("%s(%u) %s: unhandled device class: %s (%u)\n",
+ __FILE__, __LINE__, __func__,
dev->name, dev->driver->id);
return dp_fill(buf, dev->parent);
}
void *buf, *start;
start = buf = dp_alloc(dp_size(dev) + sizeof(END));
+ if (!buf)
+ return NULL;
buf = dp_fill(buf, dev);
*((struct efi_device_path *)buf) = END;
unsigned dpsize;
#ifdef CONFIG_BLK
- dpsize = dp_size(desc->bdev->parent);
+ {
+ struct udevice *dev;
+ int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+
+ if (ret)
+ dev = desc->bdev->parent;
+ dpsize = dp_size(dev);
+ }
#else
dpsize = sizeof(ROOT) + sizeof(struct efi_device_path_usb);
#endif
}
/*
- * Create a device path for a block device or one of its partitions.
+ * Create a device node for a block device partition.
*
* @buf buffer to which the device path is wirtten
* @desc block device descriptor
* @part partition number, 0 identifies a block device
*/
-static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
+static void *dp_part_node(void *buf, struct blk_desc *desc, int part)
{
disk_partition_t info;
-#ifdef CONFIG_BLK
- buf = dp_fill(buf, desc->bdev->parent);
-#else
- /*
- * We *could* make a more accurate path, by looking at if_type
- * and handling all the different cases like we do for non-
- * legacy (ie CONFIG_BLK=y) case. But most important thing
- * is just to have a unique device-path for if_type+devnum.
- * So map things to a fictitious USB device.
- */
- struct efi_device_path_usb *udp;
-
- memcpy(buf, &ROOT, sizeof(ROOT));
- buf += sizeof(ROOT);
-
- udp = buf;
- udp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
- udp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_USB;
- udp->dp.length = sizeof(*udp);
- udp->parent_port_number = desc->if_type;
- udp->usb_interface = desc->devnum;
- buf = &udp[1];
-#endif
-
- if (part == 0) /* the actual disk, not a partition */
- return buf;
-
part_get_info(desc, part, &info);
if (desc->part_type == PART_TYPE_ISO) {
return buf;
}
+/*
+ * Create a device path for a block device or one of its partitions.
+ *
+ * @buf buffer to which the device path is wirtten
+ * @desc block device descriptor
+ * @part partition number, 0 identifies a block device
+ */
+static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
+{
+#ifdef CONFIG_BLK
+ {
+ struct udevice *dev;
+ int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+
+ if (ret)
+ dev = desc->bdev->parent;
+ buf = dp_fill(buf, dev);
+ }
+#else
+ /*
+ * We *could* make a more accurate path, by looking at if_type
+ * and handling all the different cases like we do for non-
+ * legacy (ie CONFIG_BLK=y) case. But most important thing
+ * is just to have a unique device-path for if_type+devnum.
+ * So map things to a fictitious USB device.
+ */
+ struct efi_device_path_usb *udp;
+
+ memcpy(buf, &ROOT, sizeof(ROOT));
+ buf += sizeof(ROOT);
+
+ udp = buf;
+ udp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ udp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_USB;
+ udp->dp.length = sizeof(*udp);
+ udp->parent_port_number = desc->if_type;
+ udp->usb_interface = desc->devnum;
+ buf = &udp[1];
+#endif
+
+ if (part == 0) /* the actual disk, not a partition */
+ return buf;
+
+ return dp_part_node(buf, desc, part);
+}
/* Construct a device-path from a partition on a blk device: */
struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part)
void *buf, *start;
start = buf = dp_alloc(dp_part_size(desc, part) + sizeof(END));
+ if (!buf)
+ return NULL;
buf = dp_part_fill(buf, desc, part);
return start;
}
+/*
+ * Create a device node for a block device partition.
+ *
+ * @buf buffer to which the device path is wirtten
+ * @desc block device descriptor
+ * @part partition number, 0 identifies a block device
+ */
+struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part)
+{
+ efi_uintn_t dpsize;
+ void *buf;
+
+ if (desc->part_type == PART_TYPE_ISO)
+ dpsize = sizeof(struct efi_device_path_cdrom_path);
+ else
+ dpsize = sizeof(struct efi_device_path_hard_drive_path);
+ buf = dp_alloc(dpsize);
+
+ dp_part_node(buf, desc, part);
+
+ return buf;
+}
+
/* convert path to an UEFI style path (ie. DOS style backslashes and utf16) */
static void path_to_uefi(u16 *uefi, const char *path)
{
dpsize += fpsize;
start = buf = dp_alloc(dpsize + sizeof(END));
+ if (!buf)
+ return NULL;
if (desc)
buf = dp_part_fill(buf, desc, part);
dpsize += sizeof(*ndp);
start = buf = dp_alloc(dpsize + sizeof(END));
+ if (!buf)
+ return NULL;
#ifdef CONFIG_DM_ETH
buf = dp_fill(buf, eth_get_dev());
void *buf, *start;
start = buf = dp_alloc(sizeof(*mdp) + sizeof(END));
+ if (!buf)
+ return NULL;
mdp = buf;
mdp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
* Helper to split a full device path (containing both device and file
* parts) into it's constituent parts.
*/
-void efi_dp_split_file_path(struct efi_device_path *full_path,
- struct efi_device_path **device_path,
- struct efi_device_path **file_path)
+efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path,
+ struct efi_device_path **device_path,
+ struct efi_device_path **file_path)
{
struct efi_device_path *p, *dp, *fp;
+ *device_path = NULL;
+ *file_path = NULL;
dp = efi_dp_dup(full_path);
+ if (!dp)
+ return EFI_OUT_OF_RESOURCES;
p = dp;
- while (!EFI_DP_TYPE(p, MEDIA_DEVICE, FILE_PATH))
+ while (!EFI_DP_TYPE(p, MEDIA_DEVICE, FILE_PATH)) {
p = efi_dp_next(p);
+ if (!p)
+ return EFI_OUT_OF_RESOURCES;
+ }
fp = efi_dp_dup(p);
-
+ if (!fp)
+ return EFI_OUT_OF_RESOURCES;
p->type = DEVICE_PATH_TYPE_END;
p->sub_type = DEVICE_PATH_SUB_TYPE_END;
p->length = sizeof(*p);
*device_path = dp;
*file_path = fp;
+ return EFI_SUCCESS;
}
static char *dp_msging(char *s, struct efi_device_path *dp)
{
switch (dp->sub_type) {
+ case DEVICE_PATH_SUB_TYPE_MSG_ATAPI: {
+ struct efi_device_path_atapi *ide =
+ (struct efi_device_path_atapi *)dp;
+ s += sprintf(s, "Ata(%d,%d,%d)", ide->primary_secondary,
+ ide->slave_master, ide->logical_unit_number);
+ break;
+ }
+ case DEVICE_PATH_SUB_TYPE_MSG_SCSI: {
+ struct efi_device_path_scsi *ide =
+ (struct efi_device_path_scsi *)dp;
+ s += sprintf(s, "Scsi(%u,%u)", ide->target_id,
+ ide->logical_unit_number);
+ break;
+ }
case DEVICE_PATH_SUB_TYPE_MSG_USB: {
struct efi_device_path_usb *udp =
(struct efi_device_path_usb *)dp;
case DEVICE_PATH_TYPE_MEDIA_DEVICE:
str = dp_media(str, dp);
break;
+ case DEVICE_PATH_TYPE_END:
+ break;
default:
str = dp_unknown(str, dp);
}
#include <part.h>
#include <malloc.h>
-static const efi_guid_t efi_block_io_guid = BLOCK_IO_GUID;
+const efi_guid_t efi_block_io_guid = BLOCK_IO_GUID;
struct efi_disk_obj {
/* Generic EFI object parent class data */
}
static efi_status_t EFIAPI efi_disk_read_blocks(struct efi_block_io *this,
- u32 media_id, u64 lba, unsigned long buffer_size,
+ u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer)
{
void *real_buffer = buffer;
real_buffer = efi_bounce_buffer;
#endif
- EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+ EFI_ENTRY("%p, %x, %" PRIx64 ", %zx, %p", this, media_id, lba,
buffer_size, buffer);
r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
}
static efi_status_t EFIAPI efi_disk_write_blocks(struct efi_block_io *this,
- u32 media_id, u64 lba, unsigned long buffer_size,
+ u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer)
{
void *real_buffer = buffer;
real_buffer = efi_bounce_buffer;
#endif
- EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+ EFI_ENTRY("%p, %x, %" PRIx64 ", %zx, %p", this, media_id, lba,
buffer_size, buffer);
/* Populate bounce buffer if necessary */
};
/*
- * Find filesystem from a device-path. The passed in path 'p' probably
- * contains one or more /File(name) nodes, so the comparison stops at
- * the first /File() node, and returns the pointer to that via 'rp'.
- * This is mostly intended to be a helper to map a device-path to an
- * efi_file_handle object.
+ * Get the simple file system protocol for a file device path.
+ *
+ * The full path provided is split into device part and into a file
+ * part. The device part is used to find the handle on which the
+ * simple file system protocol is installed.
+ *
+ * @full_path device path including device and file
+ * @return simple file system protocol
*/
struct efi_simple_file_system_protocol *
-efi_fs_from_path(struct efi_device_path *fp)
+efi_fs_from_path(struct efi_device_path *full_path)
{
struct efi_object *efiobj;
- struct efi_disk_obj *diskobj;
+ struct efi_handler *handler;
+ struct efi_device_path *device_path;
+ struct efi_device_path *file_path;
+ efi_status_t ret;
- efiobj = efi_dp_find_obj(fp, NULL);
+ /* Split the path into a device part and a file part */
+ ret = efi_dp_split_file_path(full_path, &device_path, &file_path);
+ if (ret != EFI_SUCCESS)
+ return NULL;
+ efi_free_pool(file_path);
+
+ /* Get the EFI object for the partition */
+ efiobj = efi_dp_find_obj(device_path, NULL);
+ efi_free_pool(device_path);
if (!efiobj)
return NULL;
- diskobj = container_of(efiobj, struct efi_disk_obj, parent);
+ /* Find the simple file system protocol */
+ ret = efi_search_protocol(efiobj, &efi_simple_file_system_protocol_guid,
+ &handler);
+ if (ret != EFI_SUCCESS)
+ return NULL;
- return diskobj->volume;
+ /* Return the simple file system protocol for the partition */
+ return handler->protocol_interface;
}
/*
- * Create a device for a disk
+ * Create a handle for a partition or disk
*
- * @name not used
+ * @parent parent handle
+ * @dp_parent parent device path
* @if_typename interface name for block device
* @desc internal block device
* @dev_index device index for block device
* @offset offset into disk for simple partitions
+ * @return disk object
*/
-static void efi_disk_add_dev(const char *name,
- const char *if_typename,
- struct blk_desc *desc,
- int dev_index,
- lbaint_t offset,
- unsigned int part)
+static struct efi_disk_obj *efi_disk_add_dev(
+ efi_handle_t parent,
+ struct efi_device_path *dp_parent,
+ const char *if_typename,
+ struct blk_desc *desc,
+ int dev_index,
+ lbaint_t offset,
+ unsigned int part)
{
struct efi_disk_obj *diskobj;
efi_status_t ret;
/* Don't add empty devices */
if (!desc->lba)
- return;
+ return NULL;
diskobj = calloc(1, sizeof(*diskobj));
if (!diskobj)
efi_add_handle(&diskobj->parent);
/* Fill in object data */
- diskobj->dp = efi_dp_from_part(desc, part);
+ if (part) {
+ struct efi_device_path *node = efi_dp_part_node(desc, part);
+
+ diskobj->dp = efi_dp_append_node(dp_parent, node);
+ efi_free_pool(node);
+ } else {
+ diskobj->dp = efi_dp_from_part(desc, part);
+ }
diskobj->part = part;
ret = efi_add_protocol(diskobj->parent.handle, &efi_block_io_guid,
&diskobj->ops);
diskobj->dp);
ret = efi_add_protocol(diskobj->parent.handle,
&efi_simple_file_system_protocol_guid,
- &diskobj->volume);
+ diskobj->volume);
if (ret != EFI_SUCCESS)
goto out_of_memory;
}
if (part != 0)
diskobj->media.logical_partition = 1;
diskobj->ops.media = &diskobj->media;
- return;
+ return diskobj;
out_of_memory:
printf("ERROR: Out of memory\n");
+ return NULL;
}
-static int efi_disk_create_partitions(struct blk_desc *desc,
- const char *if_typename,
- int diskid,
- const char *pdevname)
+/*
+ * Create handles and protocols for the partitions of a block device
+ *
+ * @parent handle of the parent disk
+ * @blk_desc block device
+ * @if_typename interface type
+ * @diskid device number
+ * @pdevname device name
+ * @return number of partitions created
+ */
+int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
+ const char *if_typename, int diskid,
+ const char *pdevname)
{
int disks = 0;
char devname[32] = { 0 }; /* dp->str is u16[32] long */
disk_partition_t info;
int part;
+ struct efi_device_path *dp = NULL;
+ efi_status_t ret;
+ struct efi_handler *handler;
+
+ /* Get the device path of the parent */
+ ret = efi_search_protocol(parent, &efi_guid_device_path, &handler);
+ if (ret == EFI_SUCCESS)
+ dp = handler->protocol_interface;
/* Add devices for each partition */
for (part = 1; part <= MAX_SEARCH_PARTITIONS; part++) {
continue;
snprintf(devname, sizeof(devname), "%s:%d", pdevname,
part);
- efi_disk_add_dev(devname, if_typename, desc, diskid,
+ efi_disk_add_dev(parent, dp, if_typename, desc, diskid,
info.start, part);
disks++;
}
*/
int efi_disk_register(void)
{
+ struct efi_disk_obj *disk;
int disks = 0;
#ifdef CONFIG_BLK
struct udevice *dev;
dev;
uclass_next_device_check(&dev)) {
struct blk_desc *desc = dev_get_uclass_platdata(dev);
- const char *if_typename = dev->driver->name;
+ const char *if_typename = blk_get_if_type_name(desc->if_type);
printf("Scanning disk %s...\n", dev->name);
/* Add block device for the full device */
- efi_disk_add_dev(dev->name, if_typename, desc,
- desc->devnum, 0, 0);
-
+ disk = efi_disk_add_dev(NULL, NULL, if_typename,
+ desc, desc->devnum, 0, 0);
+ if (!disk)
+ return -ENOMEM;
disks++;
/* Partitions show up as block devices in EFI */
- disks += efi_disk_create_partitions(desc, if_typename,
- desc->devnum, dev->name);
+ disks += efi_disk_create_partitions(
+ disk->parent.handle, desc, if_typename,
+ desc->devnum, dev->name);
}
#else
int i, if_type;
if_typename, i);
/* Add block device for the full device */
- efi_disk_add_dev(devname, if_typename, desc, i, 0, 0);
+ disk = efi_disk_add_dev(NULL, NULL, if_typename, desc,
+ i, 0, 0);
+ if (!disk)
+ return -ENOMEM;
disks++;
/* Partitions show up as block devices in EFI */
- disks += efi_disk_create_partitions(desc, if_typename,
- i, devname);
+ disks += efi_disk_create_partitions(
+ disk->parent.handle, desc,
+ if_typename, i, devname);
}
}
#endif
/* If the system doesn't support icache_all flush, cross our fingers */
}
+/*
+ * Determine the memory types to be used for code and data.
+ *
+ * @loaded_image_info image descriptor
+ * @image_type field Subsystem of the optional header for
+ * Windows specific field
+ */
+static void efi_set_code_and_data_type(
+ struct efi_loaded_image *loaded_image_info,
+ uint16_t image_type)
+{
+ switch (image_type) {
+ case IMAGE_SUBSYSTEM_EFI_APPLICATION:
+ loaded_image_info->image_code_type = EFI_LOADER_CODE;
+ loaded_image_info->image_data_type = EFI_LOADER_DATA;
+ break;
+ case IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER:
+ loaded_image_info->image_code_type = EFI_BOOT_SERVICES_CODE;
+ loaded_image_info->image_data_type = EFI_BOOT_SERVICES_DATA;
+ break;
+ case IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER:
+ case IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER:
+ loaded_image_info->image_code_type = EFI_RUNTIME_SERVICES_CODE;
+ loaded_image_info->image_data_type = EFI_RUNTIME_SERVICES_DATA;
+ break;
+ default:
+ printf("%s: invalid image type: %u\n", __func__, image_type);
+ /* Let's assume it is an application */
+ loaded_image_info->image_code_type = EFI_LOADER_CODE;
+ loaded_image_info->image_data_type = EFI_LOADER_DATA;
+ break;
+ }
+}
+
/*
* This function loads all sections from a PE binary into a newly reserved
* piece of memory. On successful load it then returns the entry point for
unsigned long virt_size = 0;
bool can_run_nt64 = true;
bool can_run_nt32 = true;
- uint16_t image_type;
#if defined(CONFIG_ARM64)
can_run_nt32 = false;
IMAGE_NT_HEADERS64 *nt64 = (void *)nt;
IMAGE_OPTIONAL_HEADER64 *opt = &nt64->OptionalHeader;
image_size = opt->SizeOfImage;
- efi_reloc = efi_alloc(virt_size, EFI_LOADER_DATA);
+ efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
+ efi_reloc = efi_alloc(virt_size,
+ loaded_image_info->image_code_type);
if (!efi_reloc) {
- printf("%s: Could not allocate %ld bytes\n",
- __func__, virt_size);
+ printf("%s: Could not allocate %lu bytes\n",
+ __func__, virt_size);
return NULL;
}
entry = efi_reloc + opt->AddressOfEntryPoint;
rel_size = opt->DataDirectory[rel_idx].Size;
rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
- image_type = opt->Subsystem;
} else if (can_run_nt32 &&
(nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC)) {
IMAGE_OPTIONAL_HEADER32 *opt = &nt->OptionalHeader;
image_size = opt->SizeOfImage;
- efi_reloc = efi_alloc(virt_size, EFI_LOADER_DATA);
+ efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
+ efi_reloc = efi_alloc(virt_size,
+ loaded_image_info->image_code_type);
if (!efi_reloc) {
- printf("%s: Could not allocate %ld bytes\n",
- __func__, virt_size);
+ printf("%s: Could not allocate %lu bytes\n",
+ __func__, virt_size);
return NULL;
}
entry = efi_reloc + opt->AddressOfEntryPoint;
rel_size = opt->DataDirectory[rel_idx].Size;
rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
- image_type = opt->Subsystem;
} else {
printf("%s: Invalid optional header magic %x\n", __func__,
nt->OptionalHeader.Magic);
return NULL;
}
- switch (image_type) {
- case IMAGE_SUBSYSTEM_EFI_APPLICATION:
- loaded_image_info->image_code_type = EFI_LOADER_CODE;
- loaded_image_info->image_data_type = EFI_LOADER_DATA;
- break;
- case IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER:
- loaded_image_info->image_code_type = EFI_BOOT_SERVICES_CODE;
- loaded_image_info->image_data_type = EFI_BOOT_SERVICES_DATA;
- break;
- case IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER:
- case IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER:
- loaded_image_info->image_code_type = EFI_RUNTIME_SERVICES_CODE;
- loaded_image_info->image_data_type = EFI_RUNTIME_SERVICES_DATA;
- break;
- default:
- printf("%s: invalid image type: %u\n", __func__, image_type);
- break;
- }
-
/* Load sections into RAM */
for (i = num_sections - 1; i >= 0; i--) {
IMAGE_SECTION_HEADER *sec = §ions[i];
return 0;
}
+/*
+ * Allocate memory pages.
+ *
+ * @type type of allocation to be performed
+ * @memory_type usage type of the allocated memory
+ * @pages number of pages to be allocated
+ * @memory allocated memory
+ * @return status code
+ */
efi_status_t efi_allocate_pages(int type, int memory_type,
efi_uintn_t pages, uint64_t *memory)
{
return NULL;
}
+/*
+ * Free memory pages.
+ *
+ * @memory start of the memory area to be freed
+ * @pages number of pages to be freed
+ * @return status code
+ */
efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
{
uint64_t r = 0;
return EFI_NOT_FOUND;
}
-efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size,
- void **buffer)
+/*
+ * Allocate memory from pool.
+ *
+ * @pool_type type of the pool from which memory is to be allocated
+ * @size number of bytes to be allocated
+ * @buffer allocated memory
+ * @return status code
+ */
+efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer)
{
efi_status_t r;
efi_physical_addr_t t;
return r;
}
+/*
+ * Free memory from pool.
+ *
+ * @buffer start of memory to be freed
+ * @return status code
+ */
efi_status_t efi_free_pool(void *buffer)
{
efi_status_t r;
return r;
}
+/*
+ * Get map describing memory usage.
+ *
+ * @memory_map_size on entry the size, in bytes, of the memory map buffer,
+ * on exit the size of the copied memory map
+ * @memory_map buffer to which the memory map is written
+ * @map_key key for the memory map
+ * @descriptor_size size of an individual memory descriptor
+ * @descriptor_version version number of the memory descriptor structure
+ * @return status code
+ */
efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size,
struct efi_mem_desc *memory_map,
efi_uintn_t *map_key,
#include <efi_api.h>
static const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID;
+static const efi_guid_t fdt_guid = EFI_FDT_GUID;
+static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID;
+
+static int hw_memcmp(const void *buf1, const void *buf2, size_t length)
+{
+ const u8 *pos1 = buf1;
+ const u8 *pos2 = buf2;
+
+ for (; length; --length) {
+ if (*pos1 != *pos2)
+ return *pos1 - *pos2;
+ ++pos1;
+ ++pos2;
+ }
+ return 0;
+}
/*
* Entry point of the EFI application.
struct efi_boot_services *boottime = systable->boottime;
struct efi_loaded_image *loaded_image;
efi_status_t ret;
+ efi_uintn_t i;
con_out->output_string(con_out, L"Hello, world!\n");
L"Cannot open loaded image protocol\n");
goto out;
}
+ /* Find configuration tables */
+ for (i = 0; i < systable->nr_tables; ++i) {
+ if (!hw_memcmp(&systable->tables[i].guid, &fdt_guid,
+ sizeof(efi_guid_t)))
+ con_out->output_string(con_out, L"Have device tree\n");
+ if (!hw_memcmp(&systable->tables[i].guid, &smbios_guid,
+ sizeof(efi_guid_t)))
+ con_out->output_string(con_out, L"Have SMBIOS table\n");
+ }
/* Output the load options */
con_out->output_string(con_out, L"Load options: ");
if (loaded_image->load_options_size && loaded_image->load_options)
--- /dev/null
+efi_miniapp_file_image.h
+*.efi
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
+CFLAGS_efi_selftest_miniapp.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_REMOVE_efi_selftest_miniapp.o := $(CFLAGS_NON_EFI) -Os
+
obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += \
efi_selftest.o \
+efi_selftest_controllers.o \
efi_selftest_console.o \
efi_selftest_devicepath.o \
efi_selftest_events.o \
efi_selftest_tpl.o \
efi_selftest_util.o \
efi_selftest_watchdog.o
+
+ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy)
+obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += efi_selftest_block_device.o
+endif
+
+# TODO: As of v2018.01 the relocation code for the EFI application cannot
+# be built on x86_64.
+ifeq ($(CONFIG_X86_64),)
+
+ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST),)
+
+obj-y += \
+efi_selftest_startimage_exit.o \
+efi_selftest_startimage_return.o
+
+targets += \
+efi_miniapp_file_image_exit.h \
+efi_miniapp_file_image_return.h \
+efi_selftest_miniapp_exit.efi \
+efi_selftest_miniapp_return.efi
+
+$(obj)/efi_miniapp_file_image_exit.h: $(obj)/efi_selftest_miniapp_exit.efi
+ $(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_exit.efi > \
+ $(obj)/efi_miniapp_file_image_exit.h
+
+$(obj)/efi_miniapp_file_image_return.h: $(obj)/efi_selftest_miniapp_return.efi
+ $(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_return.efi > \
+ $(obj)/efi_miniapp_file_image_return.h
+
+$(obj)/efi_selftest_startimage_exit.o: $(obj)/efi_miniapp_file_image_exit.h
+
+$(obj)/efi_selftest_startimage_return.o: $(obj)/efi_miniapp_file_image_return.h
+
+endif
+
+endif
efi_st_error("ExitBootServices did not return EFI_SUCCESS\n");
return;
}
- efi_st_printf("\nBoot services terminated\n");
+ efi_st_printc(EFI_WHITE, "\nBoot services terminated\n");
}
/*
if (!test->setup)
return EFI_ST_SUCCESS;
- efi_st_printf("\nSetting up '%s'\n", test->name);
+ efi_st_printc(EFI_LIGHTBLUE, "\nSetting up '%s'\n", test->name);
ret = test->setup(handle, systable);
if (ret != EFI_ST_SUCCESS) {
efi_st_error("Setting up '%s' failed\n", test->name);
++*failures;
} else {
- efi_st_printf("Setting up '%s' succeeded\n", test->name);
+ efi_st_printc(EFI_LIGHTGREEN,
+ "Setting up '%s' succeeded\n", test->name);
}
return ret;
}
if (!test->execute)
return EFI_ST_SUCCESS;
- efi_st_printf("\nExecuting '%s'\n", test->name);
+ efi_st_printc(EFI_LIGHTBLUE, "\nExecuting '%s'\n", test->name);
ret = test->execute();
if (ret != EFI_ST_SUCCESS) {
efi_st_error("Executing '%s' failed\n", test->name);
++*failures;
} else {
- efi_st_printf("Executing '%s' succeeded\n", test->name);
+ efi_st_printc(EFI_LIGHTGREEN,
+ "Executing '%s' succeeded\n", test->name);
}
return ret;
}
if (!test->teardown)
return EFI_ST_SUCCESS;
- efi_st_printf("\nTearing down '%s'\n", test->name);
+ efi_st_printc(EFI_LIGHTBLUE, "\nTearing down '%s'\n", test->name);
ret = test->teardown();
if (ret != EFI_ST_SUCCESS) {
efi_st_error("Tearing down '%s' failed\n", test->name);
++*failures;
} else {
- efi_st_printf("Tearing down '%s' succeeded\n", test->name);
+ efi_st_printc(EFI_LIGHTGREEN,
+ "Tearing down '%s' succeeded\n", test->name);
}
return ret;
}
}
}
- efi_st_printf("\nTesting EFI API implementation\n");
+ efi_st_printc(EFI_WHITE, "\nTesting EFI API implementation\n");
if (testname)
- efi_st_printf("\nSelected test: '%ps'\n", testname);
+ efi_st_printc(EFI_WHITE, "\nSelected test: '%ps'\n", testname);
else
- efi_st_printf("\nNumber of tests to execute: %u\n",
+ efi_st_printc(EFI_WHITE, "\nNumber of tests to execute: %u\n",
ll_entry_count(struct efi_unit_test,
efi_unit_test));
&failures);
/* Give feedback */
- efi_st_printf("\nSummary: %u failures\n\n", failures);
+ efi_st_printc(EFI_WHITE, "\nSummary: %u failures\n\n", failures);
/* Reset system */
efi_st_printf("Preparing for reset. Press any key.\n");
--- /dev/null
+/*
+ * efi_selftest_block
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This test checks the driver for block IO devices.
+ * A disk image is created in memory.
+ * A handle is created for the new block IO device.
+ * The block I/O protocol is installed on the handle.
+ * ConnectController is used to setup partitions and to install the simple
+ * file protocol.
+ * A known file is read from the file system and verified.
+ */
+
+#include <efi_selftest.h>
+#include "efi_selftest_disk_image.h"
+
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+/* Binary logarithm of the block size */
+#define LB_BLOCK_SIZE 9
+
+static struct efi_boot_services *boottime;
+
+static const efi_guid_t block_io_protocol_guid = BLOCK_IO_GUID;
+static const efi_guid_t guid_device_path = DEVICE_PATH_GUID;
+static const efi_guid_t guid_simple_file_system_protocol =
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
+static efi_guid_t guid_vendor =
+ EFI_GUID(0xdbca4c98, 0x6cb0, 0x694d,
+ 0x08, 0x72, 0x81, 0x9c, 0x65, 0x0c, 0xb7, 0xb8);
+
+static struct efi_device_path *dp;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed disk image */
+struct compressed_disk_image {
+ size_t length;
+ struct line lines[];
+};
+
+static const struct compressed_disk_image img = EFI_ST_DISK_IMG;
+
+/* Decompressed disk image */
+static u8 *image;
+
+/*
+ * Reset service of the block IO protocol.
+ *
+ * @this block IO protocol
+ * @return status code
+ */
+static efi_status_t EFIAPI reset(
+ struct efi_block_io *this,
+ char extended_verification)
+{
+ return EFI_SUCCESS;
+}
+
+/*
+ * Read service of the block IO protocol.
+ *
+ * @this block IO protocol
+ * @media_id media id
+ * @lba start of the read in logical blocks
+ * @buffer_size number of bytes to read
+ * @buffer target buffer
+ * @return status code
+ */
+static efi_status_t EFIAPI read_blocks(
+ struct efi_block_io *this, u32 media_id, u64 lba,
+ efi_uintn_t buffer_size, void *buffer)
+{
+ u8 *start;
+
+ if ((lba << LB_BLOCK_SIZE) + buffer_size > img.length)
+ return EFI_INVALID_PARAMETER;
+ start = image + (lba << LB_BLOCK_SIZE);
+
+ boottime->copy_mem(buffer, start, buffer_size);
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Write service of the block IO protocol.
+ *
+ * @this block IO protocol
+ * @media_id media id
+ * @lba start of the write in logical blocks
+ * @buffer_size number of bytes to read
+ * @buffer source buffer
+ * @return status code
+ */
+static efi_status_t EFIAPI write_blocks(
+ struct efi_block_io *this, u32 media_id, u64 lba,
+ efi_uintn_t buffer_size, void *buffer)
+{
+ u8 *start;
+
+ if ((lba << LB_BLOCK_SIZE) + buffer_size > img.length)
+ return EFI_INVALID_PARAMETER;
+ start = image + (lba << LB_BLOCK_SIZE);
+
+ boottime->copy_mem(start, buffer, buffer_size);
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Flush service of the block IO protocol.
+ *
+ * @this block IO protocol
+ * @return status code
+ */
+static efi_status_t EFIAPI flush_blocks(struct efi_block_io *this)
+{
+ return EFI_SUCCESS;
+}
+
+/*
+ * Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
+ */
+static efi_status_t decompress(u8 **image)
+{
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ return ret;
+}
+
+static struct efi_block_io_media media;
+
+static struct efi_block_io block_io = {
+ .media = &media,
+ .reset = reset,
+ .read_blocks = read_blocks,
+ .write_blocks = write_blocks,
+ .flush_blocks = flush_blocks,
+};
+
+/* Handle for the block IO device */
+static efi_handle_t disk_handle;
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+ struct efi_device_path_vendor vendor_node;
+ struct efi_device_path end_node;
+
+ boottime = systable->boottime;
+
+ decompress(&image);
+
+ block_io.media->block_size = 1 << LB_BLOCK_SIZE;
+ block_io.media->last_block = img.length >> LB_BLOCK_SIZE;
+
+ ret = boottime->install_protocol_interface(
+ &disk_handle, &block_io_protocol_guid,
+ EFI_NATIVE_INTERFACE, &block_io);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to install block I/O protocol\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ sizeof(struct efi_device_path_vendor) +
+ sizeof(struct efi_device_path),
+ (void **)&dp);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return EFI_ST_FAILURE;
+ }
+ vendor_node.dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
+ vendor_node.dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
+ vendor_node.dp.length = sizeof(struct efi_device_path_vendor);
+
+ boottime->copy_mem(&vendor_node.guid, &guid_vendor,
+ sizeof(efi_guid_t));
+ boottime->copy_mem(dp, &vendor_node,
+ sizeof(struct efi_device_path_vendor));
+ end_node.type = DEVICE_PATH_TYPE_END;
+ end_node.sub_type = DEVICE_PATH_SUB_TYPE_END;
+ end_node.length = sizeof(struct efi_device_path);
+
+ boottime->copy_mem((char *)dp + sizeof(struct efi_device_path_vendor),
+ &end_node, sizeof(struct efi_device_path));
+ ret = boottime->install_protocol_interface(&disk_handle,
+ &guid_device_path,
+ EFI_NATIVE_INTERFACE,
+ dp);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t r = EFI_ST_SUCCESS;
+
+ if (disk_handle) {
+ r = boottime->uninstall_protocol_interface(disk_handle,
+ &guid_device_path,
+ dp);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Uninstall device path failed\n");
+ return EFI_ST_FAILURE;
+ }
+ r = boottime->uninstall_protocol_interface(
+ disk_handle, &block_io_protocol_guid,
+ &block_io);
+ if (r != EFI_SUCCESS) {
+ efi_st_todo(
+ "Failed to uninstall block I/O protocol\n");
+ return EFI_ST_SUCCESS;
+ }
+ }
+
+ if (image) {
+ r = efi_free_pool(image);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free image\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return r;
+}
+
+/*
+ * Get length of device path without end tag.
+ *
+ * @dp device path
+ * @return length of device path in bytes
+ */
+static efi_uintn_t dp_size(struct efi_device_path *dp)
+{
+ struct efi_device_path *pos = dp;
+
+ while (pos->type != DEVICE_PATH_TYPE_END)
+ pos = (struct efi_device_path *)((char *)pos + pos->length);
+ return (char *)pos - (char *)dp;
+}
+
+/*
+ * Execute unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_uintn_t no_handles, i, len;
+ efi_handle_t *handles;
+ efi_handle_t handle_partition = NULL;
+ struct efi_device_path *dp_partition;
+ struct efi_simple_file_system_protocol *file_system;
+ struct efi_file_handle *root, *file;
+ u64 buf_size;
+ char buf[16] __aligned(ARCH_DMA_MINALIGN);
+
+ ret = boottime->connect_controller(disk_handle, NULL, NULL, 1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to connect controller\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->locate_handle_buffer(
+ BY_PROTOCOL, &guid_device_path, NULL,
+ &no_handles, &handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to locate handles\n");
+ return EFI_ST_FAILURE;
+ }
+ len = dp_size(dp);
+ for (i = 0; i < no_handles; ++i) {
+ ret = boottime->open_protocol(handles[i], &guid_device_path,
+ (void **)&dp_partition,
+ NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open device path protocol\n");
+ return EFI_ST_FAILURE;
+ }
+ if (len >= dp_size(dp_partition))
+ continue;
+ if (efi_st_memcmp(dp, dp_partition, len))
+ continue;
+ handle_partition = handles[i];
+ break;
+ }
+ ret = boottime->free_pool(handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to free pool memory\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!handle_partition) {
+ efi_st_error("Partition handle not found\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->open_protocol(handle_partition,
+ &guid_simple_file_system_protocol,
+ (void **)&file_system, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open simple file system protocol\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = file_system->open_volume(file_system, &root);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open volume\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = root->open(root, &file, (s16 *)L"hello.txt", EFI_FILE_MODE_READ,
+ 0);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open file\n");
+ return EFI_ST_FAILURE;
+ }
+ buf_size = sizeof(buf) - 1;
+ ret = file->read(file, &buf_size, buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to read file\n");
+ return EFI_ST_FAILURE;
+ }
+ if (efi_st_memcmp(buf, "Hello world!", 12)) {
+ efi_st_error("Unexpected file content\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = file->close(file);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close file\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = root->close(root);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close volume\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(blkdev) = {
+ .name = "block device",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
}
/*
- * Print a formatted string to the EFI console
+ * Print a colored formatted string to the EFI console
*
- * @fmt: format string
- * @...: optional arguments
+ * @color color, see constants in efi_api.h, use -1 for no color
+ * @fmt format string
+ * @... optional arguments
*/
-void efi_st_printf(const char *fmt, ...)
+void efi_st_printc(int color, const char *fmt, ...)
{
va_list args;
u16 buf[160];
const char *c;
u16 *pos = buf;
const char *s;
- const u16 *u;
+ u16 *u;
va_start(args, fmt);
+ if (color >= 0)
+ con_out->set_attribute(con_out, (unsigned long)color);
c = fmt;
for (; *c; ++c) {
switch (*c) {
/* u16 string */
case 's':
u = va_arg(args, u16*);
- /* Ensure string fits into buffer */
- for (; *u && pos < buf + 120; ++u)
- *pos++ = *u;
+ if (pos > buf) {
+ *pos = 0;
+ con_out->output_string(con_out,
+ buf);
+ }
+ con_out->output_string(con_out, u);
+ pos = buf;
break;
default:
--c;
va_end(args);
*pos = 0;
con_out->output_string(con_out, buf);
+ if (color >= 0)
+ con_out->set_attribute(con_out, EFI_LIGHTGRAY);
}
/*
--- /dev/null
+/*
+ * efi_selftest_controllers
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This unit test checks the following protocol services:
+ * ConnectController, DisconnectController,
+ * InstallProtocol, UninstallProtocol,
+ * OpenProtocol, CloseProtcol, OpenProtocolInformation
+ */
+
+#include <efi_selftest.h>
+
+#define NUMBER_OF_CHILD_CONTROLLERS 4
+
+static struct efi_boot_services *boottime;
+const efi_guid_t guid_driver_binding_protocol =
+ EFI_DRIVER_BINDING_PROTOCOL_GUID;
+static efi_guid_t guid_controller =
+ EFI_GUID(0xe6ab1d96, 0x6bff, 0xdb42,
+ 0xaa, 0x05, 0xc8, 0x1f, 0x7f, 0x45, 0x26, 0x34);
+static efi_guid_t guid_child_controller =
+ EFI_GUID(0x1d41f6f5, 0x2c41, 0xddfb,
+ 0xe2, 0x9b, 0xb8, 0x0e, 0x2e, 0xe8, 0x3a, 0x85);
+static efi_handle_t handle_controller;
+static efi_handle_t handle_child_controller[NUMBER_OF_CHILD_CONTROLLERS];
+static efi_handle_t handle_driver;
+
+/*
+ * Count child controllers
+ *
+ * @handle handle on which child controllers are installed
+ * @protocol protocol for which the child controlles where installed
+ * @count number of child controllers
+ * @return status code
+ */
+static efi_status_t count_child_controllers(efi_handle_t handle,
+ efi_guid_t *protocol,
+ efi_uintn_t *count)
+{
+ efi_status_t ret;
+ efi_uintn_t entry_count;
+ struct efi_open_protocol_info_entry *entry_buffer;
+
+ *count = 0;
+ ret = boottime->open_protocol_information(handle, protocol,
+ &entry_buffer, &entry_count);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ if (!entry_count)
+ return EFI_SUCCESS;
+ while (entry_count) {
+ if (entry_buffer[--entry_count].attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)
+ ++*count;
+ }
+ ret = boottime->free_pool(entry_buffer);
+ if (ret != EFI_SUCCESS)
+ efi_st_error("Cannot free buffer\n");
+ return ret;
+}
+
+/*
+ * Check if the driver supports the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @remaining_device_path path specifying the child controller
+ * @return status code
+ */
+static efi_status_t EFIAPI supported(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path)
+{
+ efi_status_t ret;
+ void *interface;
+
+ ret = boottime->open_protocol(
+ controller_handle, &guid_controller,
+ &interface, handle_driver,
+ controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER);
+ switch (ret) {
+ case EFI_ACCESS_DENIED:
+ case EFI_ALREADY_STARTED:
+ return ret;
+ case EFI_SUCCESS:
+ break;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+ ret = boottime->close_protocol(
+ controller_handle, &guid_controller,
+ handle_driver, controller_handle);
+ if (ret != EFI_SUCCESS)
+ ret = EFI_UNSUPPORTED;
+ return ret;
+}
+
+/*
+ * Create child controllers and attach driver.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @remaining_device_path path specifying the child controller
+ * @return status code
+ */
+static efi_status_t EFIAPI start(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path)
+{
+ size_t i;
+ efi_status_t ret;
+ void *interface;
+
+ /* Attach driver to controller */
+ ret = boottime->open_protocol(
+ controller_handle, &guid_controller,
+ &interface, handle_driver,
+ controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER);
+ switch (ret) {
+ case EFI_ACCESS_DENIED:
+ case EFI_ALREADY_STARTED:
+ return ret;
+ case EFI_SUCCESS:
+ break;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ /* Create child controllers */
+ for (i = 0; i < NUMBER_OF_CHILD_CONTROLLERS; ++i) {
+ ret = boottime->install_protocol_interface(
+ &handle_child_controller[i], &guid_child_controller,
+ EFI_NATIVE_INTERFACE, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->open_protocol(
+ controller_handle, &guid_controller,
+ &interface, handle_child_controller[i],
+ handle_child_controller[i],
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocol failed\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return ret;
+}
+
+/*
+ * Remove a single child controller from the parent controller.
+ *
+ * @controller_handle parent controller
+ * @child_handle child controller
+ * @return status code
+ */
+static efi_status_t disconnect_child(efi_handle_t controller_handle,
+ efi_handle_t child_handle)
+{
+ efi_status_t ret;
+
+ ret = boottime->close_protocol(
+ controller_handle, &guid_controller,
+ child_handle, child_handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot close protocol\n");
+ return ret;
+ }
+ ret = boottime->uninstall_protocol_interface(
+ child_handle, &guid_child_controller, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot uninstall protocol interface\n");
+ return ret;
+ }
+ return ret;
+}
+
+/*
+ * Remove child controllers and disconnect the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @number_of_children number of child controllers to remove
+ * @child_handle_buffer handles of the child controllers to remove
+ * @return status code
+ */
+static efi_status_t EFIAPI stop(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ size_t number_of_children,
+ efi_handle_t *child_handle_buffer)
+{
+ efi_status_t ret;
+ efi_uintn_t count;
+ struct efi_open_protocol_info_entry *entry_buffer;
+
+ /* Destroy provided child controllers */
+ if (number_of_children) {
+ efi_uintn_t i;
+
+ for (i = 0; i < number_of_children; ++i) {
+ ret = disconnect_child(controller_handle,
+ child_handle_buffer[i]);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+ return EFI_SUCCESS;
+ }
+
+ /* Destroy all children */
+ ret = boottime->open_protocol_information(
+ controller_handle, &guid_controller,
+ &entry_buffer, &count);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocolInformation failed\n");
+ return ret;
+ }
+ while (count) {
+ if (entry_buffer[--count].attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
+ ret = disconnect_child(
+ controller_handle,
+ entry_buffer[count].agent_handle);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+ }
+ ret = boottime->free_pool(entry_buffer);
+ if (ret != EFI_SUCCESS)
+ efi_st_error("Cannot free buffer\n");
+
+ /* Detach driver from controller */
+ ret = boottime->close_protocol(
+ controller_handle, &guid_controller,
+ handle_driver, controller_handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot close protocol\n");
+ return ret;
+ }
+ return EFI_SUCCESS;
+}
+
+/* Driver binding protocol interface */
+static struct efi_driver_binding_protocol binding_interface = {
+ supported,
+ start,
+ stop,
+ 0xffffffff,
+ NULL,
+ NULL,
+ };
+
+/*
+ * Setup unit test.
+ *
+ * @handle handle of the loaded image
+ * @systable system table
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+
+ boottime = systable->boottime;
+
+ /* Create controller handle */
+ ret = boottime->install_protocol_interface(
+ &handle_controller, &guid_controller,
+ EFI_NATIVE_INTERFACE, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Create driver handle */
+ ret = boottime->install_protocol_interface(
+ &handle_driver, &guid_driver_binding_protocol,
+ EFI_NATIVE_INTERFACE, &binding_interface);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * The number of child controllers is checked after each of the following
+ * actions:
+ *
+ * Connect a controller to a driver.
+ * Disconnect and destroy a child controller.
+ * Disconnect and destroy the remaining child controllers.
+ *
+ * Connect a controller to a driver.
+ * Uninstall the driver protocol from the controller.
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_uintn_t count;
+
+ /* Connect controller to driver */
+ ret = boottime->connect_controller(handle_controller, NULL, NULL, 1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to connect controller\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret != EFI_SUCCESS || count != NUMBER_OF_CHILD_CONTROLLERS) {
+ efi_st_error("Number of children %u != %u\n",
+ (unsigned int)count, NUMBER_OF_CHILD_CONTROLLERS);
+ }
+ /* Destroy second child controller */
+ ret = boottime->disconnect_controller(handle_controller,
+ handle_driver,
+ handle_child_controller[1]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to disconnect child controller\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret != EFI_SUCCESS || count != NUMBER_OF_CHILD_CONTROLLERS - 1) {
+ efi_st_error("Destroying single child controller failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Destroy remaining child controllers and disconnect controller */
+ ret = boottime->disconnect_controller(handle_controller, NULL, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to disconnect controller\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret != EFI_SUCCESS || count) {
+ efi_st_error("Destroying child controllers failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Connect controller to driver */
+ ret = boottime->connect_controller(handle_controller, NULL, NULL, 1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to connect controller\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret != EFI_SUCCESS || count != NUMBER_OF_CHILD_CONTROLLERS) {
+ efi_st_error("Number of children %u != %u\n",
+ (unsigned int)count, NUMBER_OF_CHILD_CONTROLLERS);
+ }
+ /* Uninstall controller protocol */
+ ret = boottime->uninstall_protocol_interface(handle_controller,
+ &guid_controller, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to uninstall protocols\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret == EFI_SUCCESS)
+ efi_st_error("Uninstall failed\n");
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(controllers) = {
+ .name = "controllers",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
{
efi_status_t ret;
- ret = boottime->uninstall_protocol_interface(&handle1,
+ ret = boottime->uninstall_protocol_interface(handle1,
&guid_device_path,
dp1);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
- ret = boottime->uninstall_protocol_interface(&handle1,
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_protocol_interface(handle1,
&guid_protocol,
&interface);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
- ret = boottime->uninstall_protocol_interface(&handle2,
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_protocol_interface(handle2,
&guid_device_path,
dp2);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
- ret = boottime->uninstall_protocol_interface(&handle2,
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_protocol_interface(handle2,
&guid_protocol,
&interface);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
- ret = boottime->uninstall_protocol_interface(&handle3,
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_protocol_interface(handle3,
&guid_device_path,
dp3);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
if (dp1) {
ret = boottime->free_pool(dp1);
if (ret != EFI_SUCCESS) {
efi_st_error("FreePool failed\n");
return EFI_ST_FAILURE;
}
- ret = boottime->close_protocol(handles[i], &guid_device_path,
- NULL, NULL);
- if (ret != EFI_SUCCESS)
- efi_st_todo("Cannot close device path protocol.\n");
+ /*
+ * CloseProtocol cannot be called without agent handle.
+ * There is no need to close the device path protocol.
+ */
}
ret = boottime->free_pool(handles);
if (ret != EFI_SUCCESS) {
efi_st_error("FreePool failed\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("\n");
/* Test ConvertDevicePathToText */
string = device_path_to_text->convert_device_path_to_text(
efi_st_error("ConvertDevicePathToText failed\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("dp2: %ps\n", string);
if (efi_st_strcmp_16_8(
string,
"/VenHw(dbca4c98-6cb0-694d-0872-819c650cbbb1)/VenHw(dbca4c98-6cb0-694d-0872-819c650cbba2)")
) {
+ efi_st_printf("dp2: %ps\n", string);
efi_st_error("Incorrect text from ConvertDevicePathToText\n");
return EFI_ST_FAILURE;
}
-
ret = boottime->free_pool(string);
if (ret != EFI_SUCCESS) {
efi_st_error("FreePool failed\n");
efi_st_error("ConvertDeviceNodeToText failed\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("dp_node: %ps\n", string);
- ret = boottime->free_pool(string);
- if (ret != EFI_SUCCESS) {
- efi_st_error("FreePool failed\n");
- return EFI_ST_FAILURE;
- }
if (efi_st_strcmp_16_8(string, "u-boot")) {
+ efi_st_printf("dp_node: %ps\n", string);
efi_st_error(
"Incorrect conversion by ConvertDeviceNodeToText\n");
return EFI_ST_FAILURE;
}
+ ret = boottime->free_pool(string);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
/* Test LocateDevicePath */
remaining_dp = (struct efi_device_path *)dp3;
efi_st_error("ConvertDevicePathToText failed\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("remaining device path: %ps\n", string);
if (efi_st_strcmp_16_8(string,
"/VenHw(dbca4c98-6cb0-694d-0872-819c650cbbc3)")
) {
+ efi_st_printf("remaining device path: %ps\n", string);
efi_st_error("LocateDevicePath: wrong remaining device path\n");
return EFI_ST_FAILURE;
}
+ ret = boottime->free_pool(string);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
return EFI_ST_SUCCESS;
}
--- /dev/null
+/*
+ * Non-zero 8 byte strings of a disk image
+ *
+ * Generated with tools/file2include
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define EFI_ST_DISK_IMG { 0x00010000, { \
+ {0x000001b8, "\x94\x37\x69\xfc\x00\x00\x00\x00"}, /* .7i..... */ \
+ {0x000001c0, "\x02\x00\x83\x02\x02\x00\x01\x00"}, /* ........ */ \
+ {0x000001c8, "\x00\x00\x7f\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000001f8, "\x00\x00\x00\x00\x00\x00\x55\xaa"}, /* ......U. */ \
+ {0x00000200, "\xeb\x3c\x90\x6d\x6b\x66\x73\x2e"}, /* .<.mkfs. */ \
+ {0x00000208, "\x66\x61\x74\x00\x02\x04\x01\x00"}, /* fat..... */ \
+ {0x00000210, "\x02\x00\x02\x7f\x00\xf8\x01\x00"}, /* ........ */ \
+ {0x00000218, "\x20\x00\x40\x00\x00\x00\x00\x00"}, /* .@..... */ \
+ {0x00000220, "\x00\x00\x00\x00\x80\x00\x29\x86"}, /* ......). */ \
+ {0x00000228, "\xe8\x82\x80\x4e\x4f\x20\x4e\x41"}, /* ...NO NA */ \
+ {0x00000230, "\x4d\x45\x20\x20\x20\x20\x46\x41"}, /* ME FA */ \
+ {0x00000238, "\x54\x31\x32\x20\x20\x20\x0e\x1f"}, /* T12 .. */ \
+ {0x00000240, "\xbe\x5b\x7c\xac\x22\xc0\x74\x0b"}, /* .[|.".t. */ \
+ {0x00000248, "\x56\xb4\x0e\xbb\x07\x00\xcd\x10"}, /* V....... */ \
+ {0x00000250, "\x5e\xeb\xf0\x32\xe4\xcd\x16\xcd"}, /* ^..2.... */ \
+ {0x00000258, "\x19\xeb\xfe\x54\x68\x69\x73\x20"}, /* ...This */ \
+ {0x00000260, "\x69\x73\x20\x6e\x6f\x74\x20\x61"}, /* is not a */ \
+ {0x00000268, "\x20\x62\x6f\x6f\x74\x61\x62\x6c"}, /* bootabl */ \
+ {0x00000270, "\x65\x20\x64\x69\x73\x6b\x2e\x20"}, /* e disk. */ \
+ {0x00000278, "\x20\x50\x6c\x65\x61\x73\x65\x20"}, /* Please */ \
+ {0x00000280, "\x69\x6e\x73\x65\x72\x74\x20\x61"}, /* insert a */ \
+ {0x00000288, "\x20\x62\x6f\x6f\x74\x61\x62\x6c"}, /* bootabl */ \
+ {0x00000290, "\x65\x20\x66\x6c\x6f\x70\x70\x79"}, /* e floppy */ \
+ {0x00000298, "\x20\x61\x6e\x64\x0d\x0a\x70\x72"}, /* and..pr */ \
+ {0x000002a0, "\x65\x73\x73\x20\x61\x6e\x79\x20"}, /* ess any */ \
+ {0x000002a8, "\x6b\x65\x79\x20\x74\x6f\x20\x74"}, /* key to t */ \
+ {0x000002b0, "\x72\x79\x20\x61\x67\x61\x69\x6e"}, /* ry again */ \
+ {0x000002b8, "\x20\x2e\x2e\x2e\x20\x0d\x0a\x00"}, /* ... ... */ \
+ {0x000003f8, "\x00\x00\x00\x00\x00\x00\x55\xaa"}, /* ......U. */ \
+ {0x00000400, "\xf8\xff\xff\x00\x00\x00\x00\xf0"}, /* ........ */ \
+ {0x00000408, "\xff\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000600, "\xf8\xff\xff\x00\x00\x00\x00\xf0"}, /* ........ */ \
+ {0x00000608, "\xff\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000800, "\xe5\x70\x00\x00\x00\xff\xff\xff"}, /* .p...... */ \
+ {0x00000808, "\xff\xff\xff\x0f\x00\x0e\xff\xff"}, /* ........ */ \
+ {0x00000810, "\xff\xff\xff\xff\xff\xff\xff\xff"}, /* ........ */ \
+ {0x00000818, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \
+ {0x00000820, "\xe5\x2e\x00\x68\x00\x65\x00\x6c"}, /* ...h.e.l */ \
+ {0x00000828, "\x00\x6c\x00\x0f\x00\x0e\x6f\x00"}, /* .l....o. */ \
+ {0x00000830, "\x2e\x00\x74\x00\x78\x00\x74\x00"}, /* ..t.x.t. */ \
+ {0x00000838, "\x2e\x00\x00\x00\x73\x00\x77\x00"}, /* ....s.w. */ \
+ {0x00000840, "\xe5\x45\x4c\x4c\x4f\x54\x7e\x31"}, /* .ELLOT~1 */ \
+ {0x00000848, "\x53\x57\x50\x20\x00\x64\xd0\x8a"}, /* SWP .d.. */ \
+ {0x00000850, "\x92\x4b\x92\x4b\x00\x00\xd0\x8a"}, /* .K.K.... */ \
+ {0x00000858, "\x92\x4b\x00\x00\x00\x00\x00\x00"}, /* .K...... */ \
+ {0x00000860, "\x41\x68\x00\x65\x00\x6c\x00\x6c"}, /* Ah.e.l.l */ \
+ {0x00000868, "\x00\x6f\x00\x0f\x00\xf1\x2e\x00"}, /* .o...... */ \
+ {0x00000870, "\x74\x00\x78\x00\x74\x00\x00\x00"}, /* t.x.t... */ \
+ {0x00000878, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \
+ {0x00000880, "\x48\x45\x4c\x4c\x4f\x20\x20\x20"}, /* HELLO */ \
+ {0x00000888, "\x54\x58\x54\x20\x00\x64\xd4\x8a"}, /* TXT .d.. */ \
+ {0x00000890, "\x92\x4b\x92\x4b\x00\x00\xd4\x8a"}, /* .K.K.... */ \
+ {0x00000898, "\x92\x4b\x05\x00\x0d\x00\x00\x00"}, /* .K...... */ \
+ {0x000008a0, "\xe5\x45\x4c\x4c\x4f\x54\x7e\x31"}, /* .ELLOT~1 */ \
+ {0x000008a8, "\x53\x57\x58\x20\x00\x64\xd0\x8a"}, /* SWX .d.. */ \
+ {0x000008b0, "\x92\x4b\x92\x4b\x00\x00\xd0\x8a"}, /* .K.K.... */ \
+ {0x000008b8, "\x92\x4b\x00\x00\x00\x00\x00\x00"}, /* .K...... */ \
+ {0x00006000, "\x48\x65\x6c\x6c\x6f\x20\x77\x6f"}, /* Hello wo */ \
+ {0x00006008, "\x72\x6c\x64\x21\x0a\x00\x00\x00"}, /* rld!.... */ \
+ {0, NULL} } }
efi_st_error("WaitForEvent returned wrong index\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count periodic: %u\n", timer_ticks);
if (timer_ticks < 8 || timer_ticks > 12) {
+ efi_st_printf("Notification count periodic: %u\n", timer_ticks);
efi_st_error("Incorrect timing of events\n");
return EFI_ST_FAILURE;
}
efi_st_error("Could not wait for event\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count single shot: %u\n", timer_ticks);
if (timer_ticks != 1) {
+ efi_st_printf("Notification count single shot: %u\n",
+ timer_ticks);
efi_st_error("Single shot timer failed\n");
return EFI_ST_FAILURE;
}
efi_st_error("Could not wait for event\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count stopped timer: %u\n", timer_ticks);
if (timer_ticks != 1) {
+ efi_st_printf("Notification count stopped timer: %u\n",
+ timer_ticks);
efi_st_error("Stopped timer fired\n");
return EFI_ST_FAILURE;
}
&guid3, &interface3,
NULL);
if (ret == EFI_SUCCESS) {
- efi_st_todo("UninstallMultipleProtocolInterfaces did not catch error\n");
+ efi_st_error("UninstallMultipleProtocolInterfaces did not catch error\n");
return EFI_ST_FAILURE;
}
&guid2, &interface2,
NULL);
if (ret != EFI_SUCCESS) {
- efi_st_todo("UninstallMultipleProtocolInterfaces failed\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallMultipleProtocolInterfaces failed\n");
+ return EFI_ST_FAILURE;
}
/*
* Check that the protocols are really uninstalled.
return EFI_ST_FAILURE;
}
if (count != 1) {
- efi_st_todo("UninstallMultipleProtocolInterfaces failed to uninstall protocols\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallMultipleProtocolInterfaces failed to uninstall protocols\n");
+ return EFI_ST_FAILURE;
}
ret = find_in_buffer(handle1, count, buffer);
if (ret != EFI_SUCCESS) {
ret = boottime->uninstall_protocol_interface(handle1, &guid1,
&interface1);
if (ret != EFI_SUCCESS) {
- efi_st_todo("UninstallProtocolInterface failed\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
}
ret = boottime->handle_protocol(handle1, &guid1, (void **)&interface);
if (ret == EFI_SUCCESS) {
- efi_st_todo("UninstallProtocolInterface failed\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
}
ret = boottime->uninstall_protocol_interface(handle1, &guid3,
&interface1);
if (ret != EFI_SUCCESS) {
- efi_st_todo("UninstallProtocolInterface failed\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
}
return EFI_ST_SUCCESS;
--- /dev/null
+/*
+ * efi_selftest_miniapp_exit
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This EFI application is run by the StartImage selftest.
+ * It uses the Exit boot service to return.
+ */
+
+#include <common.h>
+#include <efi_api.h>
+
+/*
+ * Entry point of the EFI application.
+ *
+ * @handle handle of the loaded image
+ * @systable system table
+ * @return status code
+ */
+efi_status_t EFIAPI efi_main(efi_handle_t handle,
+ struct efi_system_table *systable)
+{
+ struct efi_simple_text_output_protocol *con_out = systable->con_out;
+
+ con_out->output_string(con_out, L"EFI application calling Exit\n");
+
+ /* The return value is checked by the calling test */
+ systable->boottime->exit(handle, EFI_UNSUPPORTED, 0, NULL);
+
+ /*
+ * This statement should not be reached.
+ * To enable testing use a different return value.
+ */
+ return EFI_SUCCESS;
+}
--- /dev/null
+/*
+ * efi_selftest_miniapp_return
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This EFI application is run by the StartImage selftest.
+ * It returns directly without calling the Exit boot service.
+ */
+
+#include <common.h>
+#include <efi_api.h>
+
+/*
+ * Entry point of the EFI application.
+ *
+ * @handle handle of the loaded image
+ * @systable system table
+ * @return status code
+ */
+efi_status_t EFIAPI efi_main(efi_handle_t handle,
+ struct efi_system_table *systable)
+{
+ struct efi_simple_text_output_protocol *con_out = systable->con_out;
+
+ con_out->output_string(con_out,
+ L"EFI application returning w/o calling Exit\n");
+
+ /* The return value is checked by the calling test */
+ return EFI_INCOMPATIBLE_VERSION;
+}
--- /dev/null
+/*
+ * efi_selftest_start_image
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This test checks the StartImage boot service.
+ * The efi_selftest_miniapp_exit.efi application is loaded into memory
+ * and started.
+ */
+
+#include <efi_selftest.h>
+/* Include containing the miniapp.efi application */
+#include "efi_miniapp_file_image_exit.h"
+
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+/* Binary logarithm of the block size */
+#define LB_BLOCK_SIZE 9
+
+static efi_handle_t image_handle;
+static struct efi_boot_services *boottime;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed file image */
+struct compressed_file_image {
+ size_t length;
+ struct line lines[];
+};
+
+static struct compressed_file_image img = EFI_ST_DISK_IMG;
+
+/* Decompressed file image */
+static u8 *image;
+
+/*
+ * Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
+ */
+static efi_status_t decompress(u8 **image)
+{
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ return ret;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ image_handle = handle;
+ boottime = systable->boottime;
+
+ /* Load the application image into memory */
+ decompress(&image);
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t r = EFI_ST_SUCCESS;
+
+ if (image) {
+ r = efi_free_pool(image);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free image\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return r;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Load and start the application image.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+
+ ret = boottime->load_image(false, image_handle, NULL, image,
+ img.length, &handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to load image\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->start_image(handle, NULL, NULL);
+ if (ret != EFI_UNSUPPORTED) {
+ efi_st_error("Wrong return value from application\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(startimage_exit) = {
+ .name = "start image exit",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
--- /dev/null
+/*
+ * efi_selftest_start_image
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This test checks the StartImage boot service.
+ * The efi_selftest_miniapp_return.efi application is loaded into memory
+ * and started.
+ */
+
+#include <efi_selftest.h>
+/* Include containing the miniapp.efi application */
+#include "efi_miniapp_file_image_return.h"
+
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+/* Binary logarithm of the block size */
+#define LB_BLOCK_SIZE 9
+
+static efi_handle_t image_handle;
+static struct efi_boot_services *boottime;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed file image */
+struct compressed_file_image {
+ size_t length;
+ struct line lines[];
+};
+
+static struct compressed_file_image img = EFI_ST_DISK_IMG;
+
+/* Decompressed file image */
+static u8 *image;
+
+/*
+ * Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
+ */
+static efi_status_t decompress(u8 **image)
+{
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ return ret;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ image_handle = handle;
+ boottime = systable->boottime;
+
+ /* Load the application image into memory */
+ decompress(&image);
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t r = EFI_ST_SUCCESS;
+
+ if (image) {
+ r = efi_free_pool(image);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free image\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return r;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Load and start the application image.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+
+ ret = boottime->load_image(false, image_handle, NULL, image,
+ img.length, &handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to load image\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->start_image(handle, NULL, NULL);
+ if (ret != EFI_INCOMPATIBLE_VERSION) {
+ efi_st_error("Wrong return value from application\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(startimage) = {
+ .name = "start image return",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
efi_st_error("WaitForEvent returned wrong index\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count with TPL level TPL_APPLICATION: %u\n",
- notification_count);
if (notification_count < 8 || notification_count > 12) {
+ efi_st_printf(
+ "Notification count with TPL level TPL_APPLICATION: %u\n",
+ notification_count);
efi_st_error("Incorrect timing of events\n");
return EFI_ST_FAILURE;
}
efi_st_error("Could not check event\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count with TPL level TPL_CALLBACK: %u\n",
- notification_count);
if (notification_count != 0) {
+ efi_st_printf(
+ "Notification count with TPL level TPL_CALLBACK: %u\n",
+ notification_count);
efi_st_error("Suppressed timer fired\n");
return EFI_ST_FAILURE;
}
efi_st_error("Could not wait for event\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count with TPL level TPL_APPLICATION: %u\n",
- notification_count);
if (notification_count < 1) {
+ efi_st_printf(
+ "Notification count with TPL level TPL_APPLICATION: %u\n",
+ notification_count);
efi_st_error("Queued timer event did not fire\n");
return EFI_ST_FAILURE;
}
}
fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
- const char *prop_name, int index, int na, int ns,
- fdt_size_t *sizep, bool translate)
+ const char *prop_name, int index, int na,
+ int ns, fdt_size_t *sizep,
+ bool translate)
{
const fdt32_t *prop, *prop_end;
const fdt32_t *prop_addr, *prop_size, *prop_after_size;
}
fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent,
- int node, const char *prop_name, int index, fdt_size_t *sizep,
- bool translate)
+ int node, const char *prop_name,
+ int index, fdt_size_t *sizep,
+ bool translate)
{
int na, ns;
}
fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node,
- const char *prop_name, int index, fdt_size_t *sizep,
- bool translate)
+ const char *prop_name, int index,
+ fdt_size_t *sizep,
+ bool translate)
{
int parent;
}
fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
- const char *prop_name, fdt_size_t *sizep)
+ const char *prop_name, fdt_size_t *sizep)
{
int ns = sizep ? (sizeof(fdt_size_t) / sizeof(fdt32_t)) : 0;
ns, sizep, false);
}
-fdt_addr_t fdtdec_get_addr(const void *blob, int node,
- const char *prop_name)
+fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name)
{
return fdtdec_get_addr_size(blob, node, prop_name, NULL);
}
#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
- const char *prop_name, struct fdt_pci_addr *addr)
+ const char *prop_name, struct fdt_pci_addr *addr)
{
const u32 *cell;
int len;
addr->phys_mid = fdt32_to_cpu(cell[1]);
addr->phys_lo = fdt32_to_cpu(cell[1]);
break;
- } else {
- cell += (FDT_PCI_ADDR_CELLS +
- FDT_PCI_SIZE_CELLS);
}
+
+ cell += (FDT_PCI_ADDR_CELLS +
+ FDT_PCI_SIZE_CELLS);
}
if (i == num) {
}
return 0;
- } else {
- ret = -EINVAL;
}
+ ret = -EINVAL;
+
fail:
debug("(not found)\n");
return ret;
end = list + len;
while (list < end) {
- char *s;
-
len = strlen(list);
if (len >= strlen("pciVVVV,DDDD")) {
- s = strstr(list, "pci");
+ char *s = strstr(list, "pci");
/*
* check if the string is something like pciVVVV,DDDD.RR
/* extract the bar number from fdt_pci_addr */
barnum = addr->phys_hi & 0xff;
- if ((barnum < PCI_BASE_ADDRESS_0) || (barnum > PCI_CARDBUS_CIS))
+ if (barnum < PCI_BASE_ADDRESS_0 || barnum > PCI_CARDBUS_CIS)
return -EINVAL;
barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
#endif
uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
- uint64_t default_val)
+ uint64_t default_val)
{
const uint64_t *cell64;
int length;
*/
cell = fdt_getprop(blob, node, "status", NULL);
if (cell)
- return 0 == strcmp(cell, "okay");
+ return strcmp(cell, "okay") == 0;
return 1;
}
/* Search our drivers */
for (id = COMPAT_UNKNOWN; id < COMPAT_COUNT; id++)
- if (0 == fdt_node_check_compatible(blob, node,
- compat_names[id]))
+ if (fdt_node_check_compatible(blob, node,
+ compat_names[id]) == 0)
return id;
return COMPAT_UNKNOWN;
}
-int fdtdec_next_compatible(const void *blob, int node,
- enum fdt_compat_id id)
+int fdtdec_next_compatible(const void *blob, int node, enum fdt_compat_id id)
{
return fdt_node_offset_by_compatible(blob, node, compat_names[id]);
}
int fdtdec_next_compatible_subnode(const void *blob, int node,
- enum fdt_compat_id id, int *depthp)
+ enum fdt_compat_id id, int *depthp)
{
do {
node = fdt_next_node(blob, node, depthp);
return -FDT_ERR_NOTFOUND;
}
-int fdtdec_next_alias(const void *blob, const char *name,
- enum fdt_compat_id id, int *upto)
+int fdtdec_next_alias(const void *blob, const char *name, enum fdt_compat_id id,
+ int *upto)
{
#define MAX_STR_LEN 20
char str[MAX_STR_LEN + 20];
}
int fdtdec_find_aliases_for_id(const void *blob, const char *name,
- enum fdt_compat_id id, int *node_list, int maxcount)
+ enum fdt_compat_id id, int *node_list,
+ int maxcount)
{
memset(node_list, '\0', sizeof(*node_list) * maxcount);
/* TODO: Can we tighten this code up a little? */
int fdtdec_add_aliases_for_id(const void *blob, const char *name,
- enum fdt_compat_id id, int *node_list, int maxcount)
+ enum fdt_compat_id id, int *node_list,
+ int maxcount)
{
int name_len = strlen(name);
int nodes[maxcount];
}
if (node >= 0)
debug("%s: warning: maxcount exceeded with alias '%s'\n",
- __func__, name);
+ __func__, name);
/* Now find all the aliases */
for (offset = fdt_first_property_offset(blob, alias_node);
number = simple_strtoul(path + name_len, NULL, 10);
if (number < 0 || number >= maxcount) {
debug("%s: warning: alias '%s' is out of range\n",
- __func__, path);
+ __func__, path);
continue;
}
if (!node_list[i]) {
for (; j < maxcount; j++)
if (nodes[j] &&
- fdtdec_get_is_enabled(blob, nodes[j]))
+ fdtdec_get_is_enabled(blob, nodes[j]))
break;
/* Have we run out of nodes to add? */
* @return pointer to cell, which is only valid if err == 0
*/
static const void *get_prop_check_min_len(const void *blob, int node,
- const char *prop_name, int min_len, int *err)
+ const char *prop_name, int min_len,
+ int *err)
{
const void *cell;
int len;
}
int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
- u32 *array, int count)
+ u32 *array, int count)
{
const u32 *cell;
- int i, err = 0;
+ int err = 0;
debug("%s: %s\n", __func__, prop_name);
cell = get_prop_check_min_len(blob, node, prop_name,
sizeof(u32) * count, &err);
if (!err) {
+ int i;
+
for (i = 0; i < count; i++)
array[i] = fdt32_to_cpu(cell[i]);
}
}
int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
- u8 *array, int count)
+ u8 *array, int count)
{
const u8 *cell;
int err;
}
const u8 *fdtdec_locate_byte_array(const void *blob, int node,
- const char *prop_name, int count)
+ const char *prop_name, int count)
{
const u8 *cell;
int err;
}
int fdtdec_get_config_int(const void *blob, const char *prop_name,
- int default_val)
+ int default_val)
{
int config_node;
while (ptr + na + ns <= end) {
if (i == index) {
- res->start = res->end = fdtdec_get_number(ptr, na);
+ res->start = fdtdec_get_number(ptr, na);
+ res->end = res->start;
res->end += fdtdec_get_number(&ptr[na], ns) - 1;
return 0;
}
# endif
#endif
+#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
+/*
+ * For CONFIG_OF_SEPARATE, the board may optionally implement this to
+ * provide and/or fixup the fdt.
+ */
+__weak void *board_fdt_blob_setup(void)
+{
+ void *fdt_blob = NULL;
+#ifdef CONFIG_SPL_BUILD
+ /* FDT is at end of BSS unless it is in a different memory region */
+ if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
+ fdt_blob = (ulong *)&_image_binary_end;
+ else
+ fdt_blob = (ulong *)&__bss_end;
+#else
+ /* FDT is at end of image */
+ fdt_blob = (ulong *)&_end;
+#endif
+ return fdt_blob;
+}
+#endif
+
int fdtdec_setup(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
# else
gd->fdt_blob = __dtb_dt_begin;
# endif
-# elif defined CONFIG_OF_SEPARATE
-# ifdef CONFIG_SPL_BUILD
- /* FDT is at end of BSS unless it is in a different memory region */
- if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
- gd->fdt_blob = (ulong *)&_image_binary_end;
- else
- gd->fdt_blob = (ulong *)&__bss_end;
-# else
- /* FDT is at end of image */
- gd->fdt_blob = (ulong *)&_end;
-# endif
-# elif defined(CONFIG_OF_BOARD)
+# elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
/* Allow the board to override the fdt address. */
gd->fdt_blob = board_fdt_blob_setup();
# elif defined(CONFIG_OF_HOSTFILE)
* from hush: simple_itoa() was lifted from boa-0.93.15
*/
-#include <stdarg.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/ctype.h>
-
#include <common.h>
#include <charset.h>
+#include <efi_loader.h>
+#include <div64.h>
#include <uuid.h>
+#include <stdarg.h>
+#include <linux/ctype.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/string.h>
-#include <div64.h>
#define noinline __attribute__((noinline))
/* we use this so that we can do without the ctype library */
return buf;
}
+#if defined(CONFIG_EFI_LOADER) && \
+ !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+static char *device_path_string(char *buf, char *end, void *dp, int field_width,
+ int precision, int flags)
+{
+ u16 *str;
+
+ if (!dp)
+ return "<NULL>";
+
+ str = efi_dp_str((struct efi_device_path *)dp);
+ if (!str)
+ return ERR_PTR(-ENOMEM);
+
+ buf = string16(buf, end, str, field_width, precision, flags);
+ efi_free_pool(str);
+ return buf;
+}
+#endif
+
#ifdef CONFIG_CMD_NET
static const char hex_asc[] = "0123456789abcdef";
#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
#endif
switch (*fmt) {
+#if defined(CONFIG_EFI_LOADER) && \
+ !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+ case 'D':
+ return device_path_string(buf, end, ptr, field_width,
+ precision, flags);
+#endif
#ifdef CONFIG_CMD_NET
case 'a':
flags |= SPECIAL | ZEROPAD;
str = pointer(fmt + 1, str, end,
va_arg(args, void *),
field_width, precision, flags);
+ if (IS_ERR(str))
+ return PTR_ERR(str);
/* Skip all alphanumeric pointer suffixes */
while (isalnum(fmt[1]))
fmt++;
i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
va_end(args);
+ /* Handle error */
+ if (i <= 0)
+ return i;
/* Print the string */
puts(printbuffer);
return i;
*/
i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
+ /* Handle error */
+ if (i <= 0)
+ return i;
/* Print the string */
puts(printbuffer);
return i;
#include <net.h>
#include <net/tftp.h>
#include "bootp.h"
-#include "nfs.h"
#ifdef CONFIG_LED_STATUS
#include <status_led.h>
#endif
if (time_taken >= time_taken_max) {
#ifdef CONFIG_BOOTP_MAY_FAIL
- puts("\nRetry time exceeded\n");
- net_set_state(NETLOOP_FAIL);
-#else
- puts("\nRetry time exceeded; starting again\n");
- net_start_again();
+ char *ethrotate;
+
+ ethrotate = env_get("ethrotate");
+ if ((ethrotate && strcmp(ethrotate, "no") == 0) ||
+ net_restart_wrap) {
+ puts("\nRetry time exceeded\n");
+ net_set_state(NETLOOP_FAIL);
+ } else
#endif
+ {
+ puts("\nRetry time exceeded; starting again\n");
+ net_start_again();
+ }
} else {
bootp_timeout *= 2;
if (bootp_timeout > 2000)
CONFIG_ADDR_AUTO_INCR_BIT
CONFIG_ADDR_MAP
CONFIG_ADNPESC1
-CONFIG_ADP_AG101P
CONFIG_AEABI
CONFIG_AEMIF_CNTRL_BASE
CONFIG_ALTERA_SPI_IDLE_VAL
CONFIG_AM335X_USB1
CONFIG_AM335X_USB1_MODE
CONFIG_AM437X_USB2PHY2_HOST
-CONFIG_AMCORE
CONFIG_ANDES_PCU
CONFIG_ANDES_PCU_BASE
-CONFIG_AP325RXA
CONFIG_APBH_DMA
CONFIG_APBH_DMA_BURST
CONFIG_APBH_DMA_BURST8
CONFIG_APER_1_BASE
CONFIG_APER_SIZE
CONFIG_APUS_FAST_EXCEPT
-CONFIG_AP_SH4A_4A
CONFIG_ARCH_ADPAG101P
CONFIG_ARCH_CPU_INIT
CONFIG_ARCH_HAS_ILOG2_U32
CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
CONFIG_ARM_THUMB
CONFIG_ARP_TIMEOUT
-CONFIG_ASTRO5373L
CONFIG_ASTRO_COFDMDUOS2
CONFIG_ASTRO_TWIN7S2
CONFIG_ASTRO_V512
CONFIG_CPU_SH7763
CONFIG_CPU_SH7780
CONFIG_CPU_SH7785
-CONFIG_CPU_SH_TYPE_R
CONFIG_CPU_TYPE_R
CONFIG_CPU_VR41XX
CONFIG_CQSPI_DECODER
CONFIG_CTL_JTAG
CONFIG_CTL_TBE
CONFIG_CUSTOMER_BOARD_SUPPORT
-CONFIG_CYRUS
CONFIG_D2NET_V2
CONFIG_DA850_AM18X_EVM
CONFIG_DA850_EVM_MAX_CPU_CLK
-CONFIG_DA850_LOWLEVEL
CONFIG_DA8XX_GPIO
-CONFIG_DAVINCI_SPI
CONFIG_DBAU1000
CONFIG_DBAU1X00
CONFIG_DBGU
CONFIG_ECC_SRAM_ADDR_MASK
CONFIG_ECC_SRAM_ADDR_SHIFT
CONFIG_ECC_SRAM_REQ_BIT
-CONFIG_ECOVEC
CONFIG_ECOVEC_ROMIMAGE_ADDR
CONFIG_EDB9301
CONFIG_EDB9302
CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1
CONFIG_ESDHC_HC_BLK_ADDR
CONFIG_ESPRESSO7420
-CONFIG_ESPT
CONFIG_ET1100_BASE
CONFIG_ETH1ADDR
CONFIG_ETH2ADDR
CONFIG_ETHPRIME
CONFIG_ETH_BUFSIZE
CONFIG_ETH_RXSIZE
-CONFIG_EXT4_WRITE
CONFIG_EXTRA_BOOTARGS
CONFIG_EXTRA_CLOCK
CONFIG_EXTRA_ENV
CONFIG_FSMC_NAND_BASE
CONFIG_FSMTDBLK
CONFIG_FSNOTIFY
-CONFIG_FS_EXT4
CONFIG_FS_POSIX_ACL
CONFIG_FTAHBC020S
CONFIG_FTAHBC020S_BASE
CONFIG_IDE_PREINIT
CONFIG_IDE_RESET
CONFIG_IDE_SWAP_IO
-CONFIG_IDS8313
CONFIG_IDT8T49N222A
CONFIG_ID_EEPROM
CONFIG_IMA
CONFIG_LYNXKDI
CONFIG_M41T94_SPI_CS
CONFIG_M520x
-CONFIG_M52277EVB
-CONFIG_M5253DEMO
-CONFIG_M5253EVBE
-CONFIG_M5275EVB
CONFIG_M5301x
-CONFIG_M54418TWR
CONFIG_M54451EVB
CONFIG_M54455EVB
CONFIG_MACB0_PHY
CONFIG_MACB2_PHY
CONFIG_MACB3_PHY
CONFIG_MACB_SEARCH_PHY
-CONFIG_MACH_ASPENITE
-CONFIG_MACH_DAVINCI_CALIMAIN
-CONFIG_MACH_DAVINCI_DA850_EVM
-CONFIG_MACH_DOCKSTAR
-CONFIG_MACH_EDMINIV2
-CONFIG_MACH_GOFLEXHOME
-CONFIG_MACH_GONI
-CONFIG_MACH_GURUPLUG
-CONFIG_MACH_KM_KIRKWOOD
CONFIG_MACH_OMAPL138_LCDK
-CONFIG_MACH_OPENRD_BASE
-CONFIG_MACH_SHEEVAPLUG
CONFIG_MACH_SPECIFIC
CONFIG_MACH_TYPE
CONFIG_MACH_TYPE_COMPAT_REV
CONFIG_MENUPROMPT
CONFIG_MENU_SHOW
CONFIG_MFG_ENV_SETTINGS
-CONFIG_MIGO_R
CONFIG_MII
CONFIG_MIIM_ADDRESS
CONFIG_MII_DEFAULT_TSEC
CONFIG_MONITOR_IS_IN_RAM
CONFIG_MP
CONFIG_MPC8308
-CONFIG_MPC8308RDB
-CONFIG_MPC8308_P1M
CONFIG_MPC8309
CONFIG_MPC830x
CONFIG_MPC8313
CONFIG_MPC832XEMDS
CONFIG_MPC832x
CONFIG_MPC8349
-CONFIG_MPC8349EMDS
CONFIG_MPC8349ITX
-CONFIG_MPC8349ITXGP
CONFIG_MPC834x
CONFIG_MPC8360
CONFIG_MPC837XEMDS
CONFIG_MPC8XXX_SPI
CONFIG_MPC8xxx_DISABLE_BPTR
CONFIG_MPLL_FREQ
-CONFIG_MPR2
CONFIG_MP_CLK_FREQ
-CONFIG_MS7720SE
-CONFIG_MS7722SE
-CONFIG_MS7750SE
CONFIG_MSHC_FREQ
CONFIG_MTD_CONCAT
CONFIG_MTD_DEVICE
CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
CONFIG_OMAP_USB2PHY2_HOST
CONFIG_OMAP_USB3PHY1_HOST
-CONFIG_OMAP_USB_PHY
CONFIG_ORIGEN
CONFIG_OS1_ENV_ADDR
CONFIG_OS2_ENV_ADDR
CONFIG_QSPI_QUAD_SUPPORT
CONFIG_QSPI_SEL_GPIO
CONFIG_QUOTA
-CONFIG_R0P7734
-CONFIG_R2DPLUS
CONFIG_R7780MP
CONFIG_R8A66597_BASE_ADDR
CONFIG_R8A66597_ENDIAN
CONFIG_ROCKCHIP_CHIP_TAG
CONFIG_ROCKCHIP_MAX_INIT_SIZE
CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
-CONFIG_ROCKCHIP_USB2_PHY
CONFIG_ROM_STUBS
CONFIG_ROOTFS_OFFSET
CONFIG_ROOTPATH
-CONFIG_RSK7203
-CONFIG_RSK7264
-CONFIG_RSK7269
CONFIG_RTC_DS1337
CONFIG_RTC_DS1337_NOOSC
CONFIG_RTC_DS1338
CONFIG_SATA1
CONFIG_SATA2
CONFIG_SATA_ULI5288
-CONFIG_SBC8349
-CONFIG_SBC8548
-CONFIG_SBC8641D
CONFIG_SCF0403_LCD
CONFIG_SCIF
CONFIG_SCIF_A
CONFIG_SH4_PCI
CONFIG_SH73A0
CONFIG_SH7751_PCI
-CONFIG_SH7752EVB
-CONFIG_SH7753EVB
-CONFIG_SH7757LCR
CONFIG_SH7757LCR_DDR_ECC
-CONFIG_SH7763RDP
CONFIG_SH7780_PCI
CONFIG_SH7780_PCI_BAR
CONFIG_SH7780_PCI_LAR
CONFIG_SH7780_PCI_LSR
-CONFIG_SH7785LCR
CONFIG_SHARP_LM8V31
CONFIG_SHARP_LQ035Q7DH06
CONFIG_SHEEVA_88SV131
CONFIG_SHOW_BOOT_PROGRESS
CONFIG_SH_CMT_CLK_FREQ
CONFIG_SH_DSP
-CONFIG_SH_ETHER
CONFIG_SH_ETHER_ALIGNE_SIZE
CONFIG_SH_ETHER_BASE_ADDR
CONFIG_SH_ETHER_CACHE_INVALIDATE
CONFIG_SOC_AU1500
CONFIG_SOC_AU1550
CONFIG_SOC_AU1X00
-CONFIG_SOC_DA850
-CONFIG_SOC_DA8XX
CONFIG_SOC_DM355
CONFIG_SOC_DM365
CONFIG_SOC_DM644X
CONFIG_STM32_HSE_HZ
CONFIG_STM32_HZ
CONFIG_STM32_SERIAL
-CONFIG_STMARK2
CONFIG_STRIDER
CONFIG_STRIDER_CON
CONFIG_STRIDER_CON_DP
CONFIG_SUPPORT_EMMC_BOOT
CONFIG_SUPPORT_EMMC_RPMB
CONFIG_SUPPORT_RAW_INITRD
-CONFIG_SUPPORT_VFAT
CONFIG_SUVD3
CONFIG_SXNI855T
CONFIG_SYSFLAGS_ADDR
CONFIG_SYS_PCMCIA_IO_BASE
CONFIG_SYS_PCMCIA_MEM_ADDR
CONFIG_SYS_PCMCIA_MEM_SIZE
-CONFIG_SYS_PCMCIA_PBR0
-CONFIG_SYS_PCMCIA_PBR1
-CONFIG_SYS_PCMCIA_PBR2
-CONFIG_SYS_PCMCIA_PBR3
-CONFIG_SYS_PCMCIA_PBR4
-CONFIG_SYS_PCMCIA_PBR5
-CONFIG_SYS_PCMCIA_PBR6
-CONFIG_SYS_PCMCIA_PBR7
-CONFIG_SYS_PCMCIA_POR0
-CONFIG_SYS_PCMCIA_POR1
-CONFIG_SYS_PCMCIA_POR2
-CONFIG_SYS_PCMCIA_POR3
-CONFIG_SYS_PCMCIA_POR4
-CONFIG_SYS_PCMCIA_POR5
-CONFIG_SYS_PCMCIA_POR6
-CONFIG_SYS_PCMCIA_POR7
CONFIG_SYS_PDCNT
CONFIG_SYS_PEHLPAR
CONFIG_SYS_PEPAR
CONFIG_TPL_PAD_TO
CONFIG_TPM_TIS_BASE_ADDRESS
CONFIG_TPS6586X_POWER
-CONFIG_TQM834X
CONFIG_TRACE
CONFIG_TRACE_BUFFER_SIZE
CONFIG_TRACE_EARLY
CONFIG_TWL4030_INPUT
CONFIG_TWL4030_KEYPAD
CONFIG_TWL4030_LED
-CONFIG_TWL4030_USB
CONFIG_TWL6030_INPUT
CONFIG_TWL6030_POWER
CONFIG_TWR
CONFIG_USBID_ADDR
CONFIG_USBNET_DEV_ADDR
CONFIG_USBTTY
-CONFIG_USB_AM35X
CONFIG_USB_ATMEL
CONFIG_USB_ATMEL_CLK_SEL_PLLB
CONFIG_USB_ATMEL_CLK_SEL_UPLL
CONFIG_USB_INVENTRA_DMA
CONFIG_USB_ISP1301_I2C_ADDR
CONFIG_USB_MAX_CONTROLLER_COUNT
-CONFIG_USB_MUSB_AM35X
CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-CONFIG_USB_MUSB_DSPS
-CONFIG_USB_MUSB_HCD
-CONFIG_USB_MUSB_OMAP2PLUS
-CONFIG_USB_MUSB_PIO_ONLY
CONFIG_USB_MUSB_TIMEOUT
CONFIG_USB_MUSB_TUSB6010
-CONFIG_USB_MUSB_UDC
CONFIG_USB_OHCI
CONFIG_USB_OHCI_EP93XX
CONFIG_USB_OHCI_LPC32XX
CONFIG_USB_OHCI_NEW
CONFIG_USB_OHCI_SUNXI
-CONFIG_USB_OMAP3
CONFIG_USB_OTG
CONFIG_USB_OTG_BLACKLIST_HUB
CONFIG_USB_PHY_CFG_BASE
CONFIG_VAL
CONFIG_VAR_SIZE_SPL
CONFIG_VCT_NOR
-CONFIG_VE8313
CONFIG_VERY_BIG_RAM
CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
CONFIG_XILINX_LL_TEMAC_CLK
CONFIG_XILINX_SPI_IDLE_VAL
CONFIG_XILINX_TB_WATCHDOG
-CONFIG_XPEDITE5140
-CONFIG_XPEDITE5200
-CONFIG_XPEDITE550X
CONFIG_XR16L2751
CONFIG_XSENGINE
CONFIG_XTFPGA
/* Test that we can probe for children */
static int dm_test_bus_children(struct unit_test_state *uts)
{
- int num_devices = 6;
+ int num_devices = 7;
struct udevice *bus;
struct uclass *uc;
/* Test that FDT-based binding works correctly */
static int dm_test_fdt(struct unit_test_state *uts)
{
- const int num_devices = 6;
+ const int num_devices = 7;
struct udevice *dev;
struct uclass *uc;
int ret;
#define DEBUG
#include <common.h>
+#if defined(CONFIG_EFI_LOADER) && \
+ !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+#include <efi_api.h>
+#endif
#include <display_options.h>
#include <version.h>
#define FAKE_BUILD_TAG "jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \
"and a lot more text to come"
+/* Test efi_loader specific printing */
+static void efi_ut_print(void)
+{
+#if defined(CONFIG_EFI_LOADER) && \
+ !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+ char str[10];
+ u8 buf[sizeof(struct efi_device_path_sd_mmc_path) +
+ sizeof(struct efi_device_path)];
+ u8 *pos = buf;
+ struct efi_device_path *dp_end;
+ struct efi_device_path_sd_mmc_path *dp_sd =
+ (struct efi_device_path_sd_mmc_path *)pos;
+
+ /* Create a device path for an SD card */
+ dp_sd->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ dp_sd->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_SD;
+ dp_sd->dp.length = sizeof(struct efi_device_path_sd_mmc_path);
+ dp_sd->slot_number = 3;
+ pos += sizeof(struct efi_device_path_sd_mmc_path);
+ /* Append end node */
+ dp_end = (struct efi_device_path *)pos;
+ dp_end->type = DEVICE_PATH_TYPE_END;
+ dp_end->sub_type = DEVICE_PATH_SUB_TYPE_END;
+ dp_end->length = sizeof(struct efi_device_path);
+
+ snprintf(str, sizeof(str), "_%pD_", buf);
+ assert(!strcmp("_/SD(3)_", str));
+#endif
+}
+
static int do_ut_print(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
assert(!strncmp(FAKE_BUILD_TAG, s + 9 + len, 12));
assert(!strcmp("\n\n", s + big_str_len - 3));
+ /* Test efi_loader specific printing */
+ efi_ut_print();
+
printf("%s: Everything went swimmingly\n", __func__);
return 0;
}
# Run tests for the flat DT version of sandbox
./test/py/test.py --bd sandbox_flattree --build
+DTC_DIR=build-sandbox_spl/scripts/dtc
+
+PYTHONPATH=${DTC_DIR}/pylibfdt DTC=${DTC_DIR}/dtc run_test \
+ ./tools/binman/binman -t
+run_test ./tools/patman/patman --test
+run_test ./tools/buildman/buildman -t
+PYTHONPATH=${DTC_DIR}/pylibfdt DTC=${DTC_DIR}/dtc run_test ./tools/dtoc/dtoc -t
+
+# This needs you to set up Python test coverage tools.
+# To enable Python test coverage on Debian-type distributions (e.g. Ubuntu):
+# $ sudo apt-get install python-pip python-pytest
+# $ sudo pip install coverage
+PYTHONPATH=${DTC_DIR}/pylibfdt DTC=${DTC_DIR}/dtc run_test \
+ ./tools/binman/binman -T
+
if [ $result == 0 ]; then
echo "Tests passed!"
else
/easylogo/easylogo
/envcrc
/fdtgrep
+/file2include
/fit_check_sign
/fit_info
/gdb/gdbcont
hostprogs-y += dumpimage mkimage
hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign
+hostprogs-$(CONFIG_CMD_BOOTEFI_SELFTEST) += file2include
+
FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o
# The following files are synced with upstream DTC.
mkimage-objs := $(dumpimage-mkimage-objs) mkimage.o
fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o
fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
+file2include-objs := file2include.o
ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot
hostprogs-y += proftool
hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
+hostprogs-$(CONFIG_RISCV) += prelink-riscv
hostprogs-y += fdtgrep
fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o
Most of the time such essoteric behaviour is not needed, but it can be
essential for complex images.
+If you need to specify a particular device-tree compiler to use, you can define
+the DTC environment variable. This can be useful when the system dtc is too
+old.
+
History / Credits
-----------------
"""Test that the full help is displayed with -H"""
result = self._RunBinman('-H')
help_file = os.path.join(self._binman_dir, 'README')
- self.assertEqual(len(result.stdout), os.path.getsize(help_file))
+ # Remove possible extraneous strings
+ extra = '::::::::::::::\n' + help_file + '\n::::::::::::::\n'
+ gothelp = result.stdout.replace(extra, '')
+ self.assertEqual(len(gothelp), os.path.getsize(help_file))
self.assertEqual(0, len(result.stderr))
self.assertEqual(0, result.return_code)
command.test_result = None
result = self._RunBuildman('-H')
help_file = os.path.join(self._buildman_dir, 'README')
- self.assertEqual(len(result.stdout), os.path.getsize(help_file))
+ # Remove possible extraneous strings
+ extra = '::::::::::::::\n' + help_file + '\n::::::::::::::\n'
+ gothelp = result.stdout.replace(extra, '')
+ self.assertEqual(len(gothelp), os.path.getsize(help_file))
self.assertEqual(0, len(result.stderr))
self.assertEqual(0, result.return_code)
'-W', 'no-unit_address_vs_reg']
args.extend(search_list)
args.append(dts_input)
- command.Run('dtc', *args)
+ dtc = os.environ.get('DTC') or 'dtc'
+ command.Run(dtc, *args)
return dtb_output
def GetInt(node, propname, default=None):
--- /dev/null
+/*
+ * Convert a file image to a C define
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * For testing EFI disk management we need an in memory image of
+ * a disk.
+ *
+ * The tool file2include converts a file to a C include. The file
+ * is separated into strings of 8 bytes. Only the non-zero strings
+ * are written to the include. The output format has been designed
+ * to maintain readability.
+ *
+ * As the disk image needed for testing contains mostly zeroes a high
+ * compression ratio can be attained.
+ */
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <malloc.h>
+
+/* Size of the blocks written to the compressed file */
+#define BLOCK_SIZE 8
+
+int main(int argc, char *argv[])
+{
+ FILE *file;
+ int ret;
+ unsigned char *buf;
+ size_t count, i, j;
+
+ /* Provide usage help */
+ if (argc != 2) {
+ printf("Usage:\n%s FILENAME\n", argv[0]);
+ return EXIT_FAILURE;
+ }
+ /* Open file */
+ file = fopen(argv[1], "r");
+ if (!file) {
+ perror("fopen");
+ return EXIT_FAILURE;
+ }
+ /* Get file length */
+ ret = fseek(file, 0, SEEK_END);
+ if (ret < 0) {
+ perror("fseek");
+ return EXIT_FAILURE;
+ }
+ count = ftell(file);
+ if (!count) {
+ fprintf(stderr, "File %s has length 0\n", argv[1]);
+ return EXIT_FAILURE;
+ }
+ rewind(file);
+ /* Read file */
+ buf = malloc(count);
+ if (!buf) {
+ perror("calloc");
+ return EXIT_FAILURE;
+ }
+ count = fread(buf, 1, count, file);
+
+ /* Generate output */
+ printf("/*\n");
+ printf(" * Non-zero %u byte strings of a disk image\n", BLOCK_SIZE);
+ printf(" *\n");
+ printf(" * Generated with tools/file2include\n");
+ printf(" *\n");
+ printf(" * SPDX-License-Identifier: GPL-2.0+\n");
+ printf(" */\n\n");
+ printf("#define EFI_ST_DISK_IMG { 0x%08zx, { \\\n", count);
+
+ for (i = 0; i < count; i += BLOCK_SIZE) {
+ int c = 0;
+
+ for (j = i; j < i + BLOCK_SIZE && j < count; ++j) {
+ if (buf[j])
+ c = 1;
+ }
+ if (!c)
+ continue;
+ printf("\t{0x%08zx, \"", i);
+ for (j = i; j < i + BLOCK_SIZE && j < count; ++j)
+ printf("\\x%02x", buf[j]);
+ printf("\"}, /* ");
+ for (j = i; j < i + BLOCK_SIZE && j < count; ++j) {
+ if (buf[j] >= 0x20 && buf[j] <= 0x7e)
+ printf("%c", buf[j]);
+ else
+ printf(".");
+ }
+ printf(" */ \\\n");
+ }
+ printf("\t{0, NULL} } }\n");
+
+ /* Release resources */
+ free(buf);
+ ret = fclose(file);
+ if (ret) {
+ perror("fclose");
+ return EXIT_FAILURE;
+ }
+ return EXIT_SUCCESS;
+}
* fit_write_images() - Write out a list of images to the FIT
*
* We always include the main image (params->datafile). If there are device
- * tree files, we include an fdt@ node for each of those too.
+ * tree files, we include an fdt- node for each of those too.
*/
static int fit_write_images(struct image_tool_params *params, char *fdt)
{
/* First the main image */
typename = genimg_get_type_short_name(params->fit_image_type);
- snprintf(str, sizeof(str), "%s@1", typename);
+ snprintf(str, sizeof(str), "%s-1", typename);
fdt_begin_node(fdt, str);
fdt_property_string(fdt, "description", params->imagename);
fdt_property_string(fdt, "type", typename);
for (cont = params->content_head; cont; cont = cont->next) {
if (cont->type != IH_TYPE_FLATDT)
continue;
- snprintf(str, sizeof(str), "%s@%d", FIT_FDT_PROP, ++upto);
+ snprintf(str, sizeof(str), "%s-%d", FIT_FDT_PROP, ++upto);
fdt_begin_node(fdt, str);
get_basename(str, sizeof(str), cont->fname);
/* And a ramdisk file if available */
if (params->fit_ramdisk) {
- fdt_begin_node(fdt, FIT_RAMDISK_PROP "@1");
+ fdt_begin_node(fdt, FIT_RAMDISK_PROP "-1");
fdt_property_string(fdt, "type", FIT_RAMDISK_PROP);
fdt_property_string(fdt, "os", genimg_get_os_short_name(params->os));
int upto;
fdt_begin_node(fdt, "configurations");
- fdt_property_string(fdt, "default", "conf@1");
+ fdt_property_string(fdt, "default", "conf-1");
upto = 0;
for (cont = params->content_head; cont; cont = cont->next) {
if (cont->type != IH_TYPE_FLATDT)
continue;
typename = genimg_get_type_short_name(cont->type);
- snprintf(str, sizeof(str), "conf@%d", ++upto);
+ snprintf(str, sizeof(str), "conf-%d", ++upto);
fdt_begin_node(fdt, str);
get_basename(str, sizeof(str), cont->fname);
fdt_property_string(fdt, "description", str);
typename = genimg_get_type_short_name(params->fit_image_type);
- snprintf(str, sizeof(str), "%s@1", typename);
+ snprintf(str, sizeof(str), "%s-1", typename);
fdt_property_string(fdt, typename, str);
if (params->fit_ramdisk)
fdt_property_string(fdt, FIT_RAMDISK_PROP,
- FIT_RAMDISK_PROP "@1");
+ FIT_RAMDISK_PROP "-1");
- snprintf(str, sizeof(str), FIT_FDT_PROP "@%d", upto);
+ snprintf(str, sizeof(str), FIT_FDT_PROP "-%d", upto);
fdt_property_string(fdt, FIT_FDT_PROP, str);
fdt_end_node(fdt);
}
if (!upto) {
- fdt_begin_node(fdt, "conf@1");
+ fdt_begin_node(fdt, "conf-1");
typename = genimg_get_type_short_name(params->fit_image_type);
- snprintf(str, sizeof(str), "%s@1", typename);
+ snprintf(str, sizeof(str), "%s-1", typename);
fdt_property_string(fdt, typename, str);
if (params->fit_ramdisk)
fdt_property_string(fdt, FIT_RAMDISK_PROP,
- FIT_RAMDISK_PROP "@1");
+ FIT_RAMDISK_PROP "-1");
fdt_end_node(fdt);
}
*
* Input component image node structure:
*
- * o image@1 (at image_noffset)
+ * o image-1 (at image_noffset)
* | - data = [binary data]
- * o hash@1
+ * o hash-1
* |- algo = "sha1"
*
* Output component image node structure:
*
- * o image@1 (at image_noffset)
+ * o image-1 (at image_noffset)
* | - data = [binary data]
- * o hash@1
+ * o hash-1
* |- algo = "sha1"
* |- value = sha1(data)
*
/*
* Check subnode name, must be equal to "hash" or "signature".
* Multiple hash nodes require unique unit node
- * names, e.g. hash@1, hash@2, signature@1, etc.
+ * names, e.g. hash-1, hash-2, signature-1, etc.
*/
node_name = fit_get_name(fit, noffset, NULL);
if (!strncmp(node_name, FIT_HASH_NODENAME,
--- /dev/null
+#!/bin/bash
+#
+######################################################
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0
+# https://spdx.org/licenses
+#
+# Author: Konstantin Porotchkin kostap@marvell.com
+#
+# Version 0.3
+#
+# UART recovery downloader for Armada SoCs
+#
+######################################################
+
+port=$1
+file=$2
+speed=$3
+
+pattern_repeat=1500
+default_baudrate=115200
+tmpfile=/tmp/xmodem.pattern
+tools=( dd stty sx minicom )
+
+case "$3" in
+ 2)
+ fast_baudrate=230400
+ prefix="\xF2"
+ ;;
+ 4)
+ fast_baudrate=460800
+ prefix="\xF4"
+ ;;
+ 8)
+ fast_baudrate=921600
+ prefix="\xF8"
+ ;;
+ *)
+ fast_baudrate=$default_baudrate
+ prefix="\xBB"
+esac
+
+if [[ -z "$port" || -z "$file" ]]
+then
+ echo -e "\nMarvell recovery image downloader for Armada SoC family."
+ echo -e "Command syntax:"
+ echo -e "\t$(basename $0) <port> <file> [2|4|8]"
+ echo -e "\tport - serial port the target board connected to"
+ echo -e "\tfile - recovery boot image for target download"
+ echo -e "\t2|4|8 - times to increase the default serial port speed by"
+ echo -e "For example - load the image over ttyUSB0 @ 460800 baud:"
+ echo -e "$(basename $0) /dev/ttyUSB0 /tmp/flash-image.bin 4\n"
+ echo -e "=====WARNING====="
+ echo -e "- The speed-up option is not awailable in SoC families prior to A8K+"
+ echo -e "- This utility is not compatible with Armada 37xx SoC family\n"
+fi
+
+# Sanity checks
+if [ -c "$port" ]
+then
+ echo -e "Using device connected on serial port \"$port\""
+else
+ echo "Wrong serial port name!"
+ exit 1
+fi
+
+if [ -f "$file" ]
+then
+ echo -e "Loading flash image file \"$file\""
+else
+ echo "File $file does not exist!"
+ exit 1
+fi
+
+# Verify required tools installation
+for tool in ${tools[@]}
+do
+ toolname=`which $tool`
+ if [ -z "$toolname" ]
+ then
+ echo -e "Missing installation of \"$tool\" --> Exiting"
+ exit 1
+ fi
+done
+
+
+echo -e "Recovery will run at $fast_baudrate baud"
+echo -e "========================================"
+
+if [ -f "$tmpfile" ]
+then
+ rm -f $tmpfile
+fi
+
+# Send the escape sequence to target board using default debug port speed
+stty -F $port raw ignbrk time 5 $default_baudrate
+counter=0
+while [ $counter -lt $pattern_repeat ]; do
+ echo -n -e "$prefix\x11\x22\x33\x44\x55\x66\x77" >> $tmpfile
+ let counter=counter+1
+done
+
+echo -en "Press the \"Reset\" button on the target board and "
+echo -en "the \"Enter\" key on the host keyboard simultaneously"
+read
+dd if=$tmpfile of=$port &>/dev/null
+
+# Speed up the binary image transfer
+stty -F $port raw ignbrk time 5 $fast_baudrate
+sx -vv $file > $port < $port
+#sx-at91 $port $file
+
+# return the port to the default speed
+stty -F $port raw ignbrk time 5 $default_baudrate
+
+# Optional - fire up Minicom
+minicom -D $port
+
toc++;
memset(toc, 0xff, sizeof(*toc));
- gph_set_header(gph, sbuf->st_size - OMAP_CH_HDR_SIZE + GPIMAGE_HDR_SIZE,
+ gph_set_header(gph, sbuf->st_size - OMAP_CH_HDR_SIZE,
params->addr, 0);
if (strncmp(params->imagename, "byteswap", 8) == 0) {
return []
stdout = command.Output(get_maintainer, '--norolestats', fname)
- return stdout.splitlines()
+ lines = stdout.splitlines()
+ return [ x.replace('"', '') for x in lines ]
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology
+ * Chih-Mao Chen <cmchen@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Statically process runtime relocations on RISC-V ELF images
+ * so that it can be directly executed when loaded at LMA
+ * without fixup. Both RV32 and RV64 are supported.
+ */
+
+#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
+#error "Only little-endian host is supported"
+#endif
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <elf.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#ifndef EM_RISCV
+#define EM_RISCV 243
+#endif
+
+#ifndef R_RISCV_32
+#define R_RISCV_32 1
+#endif
+
+#ifndef R_RISCV_64
+#define R_RISCV_64 2
+#endif
+
+#ifndef R_RISCV_RELATIVE
+#define R_RISCV_RELATIVE 3
+#endif
+
+const char *argv0;
+
+#define die(fmt, ...) \
+ do { \
+ fprintf(stderr, "%s: " fmt "\n", argv0, ## __VA_ARGS__); \
+ exit(EXIT_FAILURE); \
+ } while (0)
+
+#define PRELINK_INC_BITS 32
+#include "prelink-riscv.inc"
+#undef PRELINK_INC_BITS
+
+#define PRELINK_INC_BITS 64
+#include "prelink-riscv.inc"
+#undef PRELINK_INC_BITS
+
+int main(int argc, const char *const *argv)
+{
+ argv0 = argv[0];
+
+ if (argc < 2) {
+ fprintf(stderr, "Usage: %s <u-boot>\n", argv0);
+ exit(EXIT_FAILURE);
+ }
+
+ int fd = open(argv[1], O_RDWR, 0);
+
+ if (fd < 0)
+ die("Cannot open %s: %s", argv[1], strerror(errno));
+
+ struct stat st;
+
+ if (fstat(fd, &st) < 0)
+ die("Cannot stat %s: %s", argv[1], strerror(errno));
+
+ void *data =
+ mmap(0, st.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+
+ if (data == MAP_FAILED)
+ die("Cannot mmap %s: %s", argv[1], strerror(errno));
+
+ close(fd);
+
+ unsigned char *e_ident = (unsigned char *)data;
+
+ if (memcmp(e_ident, ELFMAG, SELFMAG) != 0)
+ die("Invalid ELF file %s", argv[1]);
+
+ bool is64 = e_ident[EI_CLASS] == ELFCLASS64;
+
+ if (is64)
+ prelink64(data);
+ else
+ prelink32(data);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2017 Andes Technology
+ * Chih-Mao Chen <cmchen@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Statically process runtime relocations on RISC-V ELF images
+ * so that it can be directly executed when loaded at LMA
+ * without fixup. Both RV32 and RV64 are supported.
+ */
+
+#define CONCAT_IMPL(x, y) x##y
+#define CONCAT(x, y) CONCAT_IMPL(x, y)
+#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
+
+#define prelink_nn CONCAT(prelink, PRELINK_INC_BITS)
+#define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t)
+#define get_offset_nn CONCAT(get_offset_, PRELINK_INC_BITS)
+#define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
+#define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
+#define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
+#define Elf_Sym CONCAT3(Elf, PRELINK_INC_BITS, _Sym)
+#define Elf_Dyn CONCAT3(Elf, PRELINK_INC_BITS, _Dyn)
+#define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
+#define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
+#define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
+
+static void* get_offset_nn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
+{
+ Elf_Phdr *p;
+
+ for (p = phdrs; p < phdrs + phnum; ++p)
+ if (p->p_vaddr <= addr && p->p_vaddr + p->p_memsz > addr)
+ return data + p->p_offset + (addr - p->p_vaddr);
+
+ return NULL;
+}
+
+static void prelink_nn(void *data)
+{
+ Elf_Ehdr *ehdr = data;
+ Elf_Phdr *p;
+ Elf_Dyn *dyn;
+ Elf_Rela *r;
+
+ if (ehdr->e_machine != EM_RISCV)
+ die("Machine type is not RISC-V");
+
+ Elf_Phdr *phdrs = data + ehdr->e_phoff;
+
+ Elf_Dyn *dyns = NULL;
+ for (p = phdrs; p < phdrs + ehdr->e_phnum; ++p) {
+ if (p->p_type == PT_DYNAMIC) {
+ dyns = data + p->p_offset;
+ break;
+ }
+ }
+
+ if (dyns == NULL)
+ die("No dynamic section found");
+
+ Elf_Rela *rela_dyn = NULL;
+ size_t rela_count = 0;
+ Elf_Sym *dynsym = NULL;
+ for (dyn = dyns;; ++dyn) {
+ if (dyn->d_tag == DT_NULL)
+ break;
+ else if (dyn->d_tag == DT_RELA)
+ rela_dyn = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr);
+ else if (dyn->d_tag == DT_RELASZ)
+ rela_count = dyn->d_un.d_val / sizeof(Elf_Rela);
+ else if (dyn->d_tag == DT_SYMTAB)
+ dynsym = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr);
+
+ }
+
+ if (rela_dyn == NULL)
+ die("No .rela.dyn found");
+
+ if (dynsym == NULL)
+ die("No .dynsym found");
+
+ for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
+ void* buf = get_offset_nn(data, phdrs, ehdr->e_phnum, r->r_offset);
+
+ if (buf == NULL)
+ continue;
+
+ if (ELF_R_TYPE(r->r_info) == R_RISCV_RELATIVE)
+ *((uintnn_t*) buf) = r->r_addend;
+ else if (ELF_R_TYPE(r->r_info) == R_RISCV_32)
+ *((uint32_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value;
+ else if (ELF_R_TYPE(r->r_info) == R_RISCV_64)
+ *((uint64_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value;
+ }
+}
+
+#undef prelink_nn
+#undef uintnn_t
+#undef get_offset_nn
+#undef Elf_Ehdr
+#undef Elf_Phdr
+#undef Elf_Rela
+#undef Elf_Sym
+#undef Elf_Dyn
+#undef Elf_Addr
+#undef ELF_R_TYPE
+#undef ELF_R_SYM
+
+#undef CONCAT_IMPL
+#undef CONCAT
+#undef CONCAT3
projects / u-boot / commitdiff