]> git.sur5r.net Git - u-boot/commitdiff
Eliminated arch-specific mmc header requirement
authorAndy Fleming <afleming@freescale.com>
Thu, 30 Oct 2008 21:31:39 +0000 (16:31 -0500)
committerAndy Fleming <afleming@freescale.com>
Tue, 17 Feb 2009 00:07:41 +0000 (18:07 -0600)
The current MMC infrastructure relies on the existence of an
arch-specific header file.  This isn't necessary, and a couple
drivers were forced to implement dummy files to meet this requirement.
Instead, we move the stuff in those header files into a more appropriate
place, and eliminate the stubs and the #include of asm/arch/mmc.h

Signed-off-by: Andy Fleming <afleming@freescale.com>
cpu/pxa/mmc.c
cpu/pxa/mmc.h [new file with mode: 0644]
include/asm-arm/arch-lpc2292/mmc.h [deleted file]
include/asm-arm/arch-pxa/mmc.h [deleted file]
include/asm-avr32/arch-at32ap700x/mmc.h [deleted file]
include/mmc.h

index 7199e8952b676f7c44c0d2ab5da2d9fef420c2ac..8f5277e10d9824dec8681d150c796f5ba7a3cf86 100644 (file)
@@ -28,6 +28,8 @@
 #include <asm/arch/hardware.h>
 #include <part.h>
 
+#include "mmc.h"
+
 #ifdef CONFIG_MMC
 
 extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no);
diff --git a/cpu/pxa/mmc.h b/cpu/pxa/mmc.h
new file mode 100644 (file)
index 0000000..85e144b
--- /dev/null
@@ -0,0 +1,189 @@
+/*
+ *  linux/drivers/mmc/mmc_pxa.h
+ *
+ *  Author: Vladimir Shebordaev, Igor Oblakov
+ *  Copyright:  MontaVista Software Inc.
+ *
+ *  $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __MMC_PXA_P_H__
+#define __MMC_PXA_P_H__
+
+/* PXA-250 MMC controller registers */
+
+/* MMC_STRPCL */
+#define MMC_STRPCL_STOP_CLK            (0x0001UL)
+#define MMC_STRPCL_START_CLK           (0x0002UL)
+
+/* MMC_STAT */
+#define MMC_STAT_END_CMD_RES           (0x0001UL << 13)
+#define MMC_STAT_PRG_DONE              (0x0001UL << 12)
+#define MMC_STAT_DATA_TRAN_DONE                (0x0001UL << 11)
+#define MMC_STAT_CLK_EN                        (0x0001UL << 8)
+#define MMC_STAT_RECV_FIFO_FULL                (0x0001UL << 7)
+#define MMC_STAT_XMIT_FIFO_EMPTY       (0x0001UL << 6)
+#define MMC_STAT_RES_CRC_ERROR         (0x0001UL << 5)
+#define MMC_STAT_SPI_READ_ERROR_TOKEN   (0x0001UL << 4)
+#define MMC_STAT_CRC_READ_ERROR                (0x0001UL << 3)
+#define MMC_STAT_CRC_WRITE_ERROR       (0x0001UL << 2)
+#define MMC_STAT_TIME_OUT_RESPONSE     (0x0001UL << 1)
+#define MMC_STAT_READ_TIME_OUT         (0x0001UL)
+
+#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
+       |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
+       |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
+
+/* MMC_CLKRT */
+#define MMC_CLKRT_20MHZ                        (0x0000UL)
+#define MMC_CLKRT_10MHZ                        (0x0001UL)
+#define MMC_CLKRT_5MHZ                 (0x0002UL)
+#define MMC_CLKRT_2_5MHZ               (0x0003UL)
+#define MMC_CLKRT_1_25MHZ              (0x0004UL)
+#define MMC_CLKRT_0_625MHZ             (0x0005UL)
+#define MMC_CLKRT_0_3125MHZ            (0x0006UL)
+
+/* MMC_SPI */
+#define MMC_SPI_DISABLE                        (0x00UL)
+#define MMC_SPI_EN                     (0x01UL)
+#define MMC_SPI_CS_EN                  (0x01UL << 2)
+#define MMC_SPI_CS_ADDRESS             (0x01UL << 3)
+#define MMC_SPI_CRC_ON                 (0x01UL << 1)
+
+/* MMC_CMDAT */
+#define MMC_CMDAT_SD_4DAT              (0x0001UL << 8)
+#define MMC_CMDAT_MMC_DMA_EN           (0x0001UL << 7)
+#define MMC_CMDAT_INIT                 (0x0001UL << 6)
+#define MMC_CMDAT_BUSY                 (0x0001UL << 5)
+#define MMC_CMDAT_BCR                  (0x0003UL << 5)
+#define MMC_CMDAT_STREAM               (0x0001UL << 4)
+#define MMC_CMDAT_BLOCK                        (0x0000UL << 4)
+#define MMC_CMDAT_WRITE                        (0x0001UL << 3)
+#define MMC_CMDAT_READ                 (0x0000UL << 3)
+#define MMC_CMDAT_DATA_EN              (0x0001UL << 2)
+#define MMC_CMDAT_R0                   (0)
+#define MMC_CMDAT_R1                   (0x0001UL)
+#define MMC_CMDAT_R2                   (0x0002UL)
+#define MMC_CMDAT_R3                   (0x0003UL)
+
+/* MMC_RESTO */
+#define MMC_RES_TO_MAX                 (0x007fUL) /* [6:0] */
+
+/* MMC_RDTO */
+#define MMC_READ_TO_MAX                        (0x0ffffUL) /* [15:0] */
+
+/* MMC_BLKLEN */
+#define MMC_BLK_LEN_MAX                        (0x03ffUL) /* [9:0] */
+
+/* MMC_PRTBUF */
+#define MMC_PRTBUF_BUF_PART_FULL       (0x01UL)
+#define MMC_PRTBUF_BUF_FULL            (0x00UL    )
+
+/* MMC_I_MASK */
+#define MMC_I_MASK_TXFIFO_WR_REQ       (0x01UL << 6)
+#define MMC_I_MASK_RXFIFO_RD_REQ       (0x01UL << 5)
+#define MMC_I_MASK_CLK_IS_OFF          (0x01UL << 4)
+#define MMC_I_MASK_STOP_CMD            (0x01UL << 3)
+#define MMC_I_MASK_END_CMD_RES         (0x01UL << 2)
+#define MMC_I_MASK_PRG_DONE            (0x01UL << 1)
+#define MMC_I_MASK_DATA_TRAN_DONE       (0x01UL)
+#define MMC_I_MASK_ALL                 (0x07fUL)
+
+
+/* MMC_I_REG */
+#define MMC_I_REG_TXFIFO_WR_REQ                (0x01UL << 6)
+#define MMC_I_REG_RXFIFO_RD_REQ                (0x01UL << 5)
+#define MMC_I_REG_CLK_IS_OFF           (0x01UL << 4)
+#define MMC_I_REG_STOP_CMD             (0x01UL << 3)
+#define MMC_I_REG_END_CMD_RES          (0x01UL << 2)
+#define MMC_I_REG_PRG_DONE             (0x01UL << 1)
+#define MMC_I_REG_DATA_TRAN_DONE       (0x01UL)
+#define MMC_I_REG_ALL                  (0x007fUL)
+
+/* MMC_CMD */
+#define MMC_CMD_INDEX_MAX              (0x006fUL)  /* [5:0] */
+#define CMD(x)  (x)
+
+#define MMC_DEFAULT_RCA                        1
+
+#define MMC_BLOCK_SIZE                 512
+#define MMC_MAX_BLOCK_SIZE             512
+
+#define MMC_R1_IDLE_STATE              0x01
+#define MMC_R1_ERASE_STATE             0x02
+#define MMC_R1_ILLEGAL_CMD             0x04
+#define MMC_R1_COM_CRC_ERR             0x08
+#define MMC_R1_ERASE_SEQ_ERR           0x01
+#define MMC_R1_ADDR_ERR                        0x02
+#define MMC_R1_PARAM_ERR               0x04
+
+#define MMC_R1B_WP_ERASE_SKIP          0x0002
+#define MMC_R1B_ERR                    0x0004
+#define MMC_R1B_CC_ERR                 0x0008
+#define MMC_R1B_CARD_ECC_ERR           0x0010
+#define MMC_R1B_WP_VIOLATION           0x0020
+#define MMC_R1B_ERASE_PARAM            0x0040
+#define MMC_R1B_OOR                    0x0080
+#define MMC_R1B_IDLE_STATE             0x0100
+#define MMC_R1B_ERASE_RESET            0x0200
+#define MMC_R1B_ILLEGAL_CMD            0x0400
+#define MMC_R1B_COM_CRC_ERR            0x0800
+#define MMC_R1B_ERASE_SEQ_ERR          0x1000
+#define MMC_R1B_ADDR_ERR               0x2000
+#define MMC_R1B_PARAM_ERR              0x4000
+
+typedef struct mmc_cid
+{
+/* FIXME: BYTE_ORDER */
+   uchar year:4,
+   month:4;
+   uchar sn[3];
+   uchar fwrev:4,
+   hwrev:4;
+   uchar name[6];
+   uchar id[3];
+} mmc_cid_t;
+
+typedef struct mmc_csd
+{
+       uint8_t         csd_structure:2,
+                       spec_ver:4,
+                       rsvd1:2;
+       uint8_t         taac;
+       uint8_t         nsac;
+       uint8_t         tran_speed;
+       uint16_t        ccc:12,
+                       read_bl_len:4;
+       uint64_t        read_bl_partial:1,
+                       write_blk_misalign:1,
+                       read_blk_misalign:1,
+                       dsr_imp:1,
+                       rsvd2:2,
+                       c_size:12,
+                       vdd_r_curr_min:3,
+                       vdd_r_curr_max:3,
+                       vdd_w_curr_min:3,
+                       vdd_w_curr_max:3,
+                       c_size_mult:3,
+                       erase_blk_en:1,
+                       sector_size:7,
+                       wp_grp_size:7,
+                       wp_grp_enable:1,
+                       default_ecc:2,
+                       r2w_factor:3,
+                       write_bl_len:4,
+                       write_bl_partial:1,
+                       rsvd3:4,
+                       content_prot_app:1;
+       uint8_t         file_format_grp:1,
+                       copy:1,
+                       perm_write_protect:1,
+                       tmp_write_protect:1,
+                       file_format:2,
+                       ecc:2;
+} mmc_csd_t;
+
+#endif /* __MMC_PXA_P_H__ */
diff --git a/include/asm-arm/arch-lpc2292/mmc.h b/include/asm-arm/arch-lpc2292/mmc.h
deleted file mode 100644 (file)
index e664a5f..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * A dummy header file for use with the LPC2292 port to keep the
- * compiler happy.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _MMC_ARM_TDM_H_
-#define _MMC_ARM_TDM_H_
-#endif /* _MMC_ARM_TDM_H_ */
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
deleted file mode 100644 (file)
index 85e144b..0000000
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- *  linux/drivers/mmc/mmc_pxa.h
- *
- *  Author: Vladimir Shebordaev, Igor Oblakov
- *  Copyright:  MontaVista Software Inc.
- *
- *  $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#ifndef __MMC_PXA_P_H__
-#define __MMC_PXA_P_H__
-
-/* PXA-250 MMC controller registers */
-
-/* MMC_STRPCL */
-#define MMC_STRPCL_STOP_CLK            (0x0001UL)
-#define MMC_STRPCL_START_CLK           (0x0002UL)
-
-/* MMC_STAT */
-#define MMC_STAT_END_CMD_RES           (0x0001UL << 13)
-#define MMC_STAT_PRG_DONE              (0x0001UL << 12)
-#define MMC_STAT_DATA_TRAN_DONE                (0x0001UL << 11)
-#define MMC_STAT_CLK_EN                        (0x0001UL << 8)
-#define MMC_STAT_RECV_FIFO_FULL                (0x0001UL << 7)
-#define MMC_STAT_XMIT_FIFO_EMPTY       (0x0001UL << 6)
-#define MMC_STAT_RES_CRC_ERROR         (0x0001UL << 5)
-#define MMC_STAT_SPI_READ_ERROR_TOKEN   (0x0001UL << 4)
-#define MMC_STAT_CRC_READ_ERROR                (0x0001UL << 3)
-#define MMC_STAT_CRC_WRITE_ERROR       (0x0001UL << 2)
-#define MMC_STAT_TIME_OUT_RESPONSE     (0x0001UL << 1)
-#define MMC_STAT_READ_TIME_OUT         (0x0001UL)
-
-#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
-       |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
-       |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
-
-/* MMC_CLKRT */
-#define MMC_CLKRT_20MHZ                        (0x0000UL)
-#define MMC_CLKRT_10MHZ                        (0x0001UL)
-#define MMC_CLKRT_5MHZ                 (0x0002UL)
-#define MMC_CLKRT_2_5MHZ               (0x0003UL)
-#define MMC_CLKRT_1_25MHZ              (0x0004UL)
-#define MMC_CLKRT_0_625MHZ             (0x0005UL)
-#define MMC_CLKRT_0_3125MHZ            (0x0006UL)
-
-/* MMC_SPI */
-#define MMC_SPI_DISABLE                        (0x00UL)
-#define MMC_SPI_EN                     (0x01UL)
-#define MMC_SPI_CS_EN                  (0x01UL << 2)
-#define MMC_SPI_CS_ADDRESS             (0x01UL << 3)
-#define MMC_SPI_CRC_ON                 (0x01UL << 1)
-
-/* MMC_CMDAT */
-#define MMC_CMDAT_SD_4DAT              (0x0001UL << 8)
-#define MMC_CMDAT_MMC_DMA_EN           (0x0001UL << 7)
-#define MMC_CMDAT_INIT                 (0x0001UL << 6)
-#define MMC_CMDAT_BUSY                 (0x0001UL << 5)
-#define MMC_CMDAT_BCR                  (0x0003UL << 5)
-#define MMC_CMDAT_STREAM               (0x0001UL << 4)
-#define MMC_CMDAT_BLOCK                        (0x0000UL << 4)
-#define MMC_CMDAT_WRITE                        (0x0001UL << 3)
-#define MMC_CMDAT_READ                 (0x0000UL << 3)
-#define MMC_CMDAT_DATA_EN              (0x0001UL << 2)
-#define MMC_CMDAT_R0                   (0)
-#define MMC_CMDAT_R1                   (0x0001UL)
-#define MMC_CMDAT_R2                   (0x0002UL)
-#define MMC_CMDAT_R3                   (0x0003UL)
-
-/* MMC_RESTO */
-#define MMC_RES_TO_MAX                 (0x007fUL) /* [6:0] */
-
-/* MMC_RDTO */
-#define MMC_READ_TO_MAX                        (0x0ffffUL) /* [15:0] */
-
-/* MMC_BLKLEN */
-#define MMC_BLK_LEN_MAX                        (0x03ffUL) /* [9:0] */
-
-/* MMC_PRTBUF */
-#define MMC_PRTBUF_BUF_PART_FULL       (0x01UL)
-#define MMC_PRTBUF_BUF_FULL            (0x00UL    )
-
-/* MMC_I_MASK */
-#define MMC_I_MASK_TXFIFO_WR_REQ       (0x01UL << 6)
-#define MMC_I_MASK_RXFIFO_RD_REQ       (0x01UL << 5)
-#define MMC_I_MASK_CLK_IS_OFF          (0x01UL << 4)
-#define MMC_I_MASK_STOP_CMD            (0x01UL << 3)
-#define MMC_I_MASK_END_CMD_RES         (0x01UL << 2)
-#define MMC_I_MASK_PRG_DONE            (0x01UL << 1)
-#define MMC_I_MASK_DATA_TRAN_DONE       (0x01UL)
-#define MMC_I_MASK_ALL                 (0x07fUL)
-
-
-/* MMC_I_REG */
-#define MMC_I_REG_TXFIFO_WR_REQ                (0x01UL << 6)
-#define MMC_I_REG_RXFIFO_RD_REQ                (0x01UL << 5)
-#define MMC_I_REG_CLK_IS_OFF           (0x01UL << 4)
-#define MMC_I_REG_STOP_CMD             (0x01UL << 3)
-#define MMC_I_REG_END_CMD_RES          (0x01UL << 2)
-#define MMC_I_REG_PRG_DONE             (0x01UL << 1)
-#define MMC_I_REG_DATA_TRAN_DONE       (0x01UL)
-#define MMC_I_REG_ALL                  (0x007fUL)
-
-/* MMC_CMD */
-#define MMC_CMD_INDEX_MAX              (0x006fUL)  /* [5:0] */
-#define CMD(x)  (x)
-
-#define MMC_DEFAULT_RCA                        1
-
-#define MMC_BLOCK_SIZE                 512
-#define MMC_MAX_BLOCK_SIZE             512
-
-#define MMC_R1_IDLE_STATE              0x01
-#define MMC_R1_ERASE_STATE             0x02
-#define MMC_R1_ILLEGAL_CMD             0x04
-#define MMC_R1_COM_CRC_ERR             0x08
-#define MMC_R1_ERASE_SEQ_ERR           0x01
-#define MMC_R1_ADDR_ERR                        0x02
-#define MMC_R1_PARAM_ERR               0x04
-
-#define MMC_R1B_WP_ERASE_SKIP          0x0002
-#define MMC_R1B_ERR                    0x0004
-#define MMC_R1B_CC_ERR                 0x0008
-#define MMC_R1B_CARD_ECC_ERR           0x0010
-#define MMC_R1B_WP_VIOLATION           0x0020
-#define MMC_R1B_ERASE_PARAM            0x0040
-#define MMC_R1B_OOR                    0x0080
-#define MMC_R1B_IDLE_STATE             0x0100
-#define MMC_R1B_ERASE_RESET            0x0200
-#define MMC_R1B_ILLEGAL_CMD            0x0400
-#define MMC_R1B_COM_CRC_ERR            0x0800
-#define MMC_R1B_ERASE_SEQ_ERR          0x1000
-#define MMC_R1B_ADDR_ERR               0x2000
-#define MMC_R1B_PARAM_ERR              0x4000
-
-typedef struct mmc_cid
-{
-/* FIXME: BYTE_ORDER */
-   uchar year:4,
-   month:4;
-   uchar sn[3];
-   uchar fwrev:4,
-   hwrev:4;
-   uchar name[6];
-   uchar id[3];
-} mmc_cid_t;
-
-typedef struct mmc_csd
-{
-       uint8_t         csd_structure:2,
-                       spec_ver:4,
-                       rsvd1:2;
-       uint8_t         taac;
-       uint8_t         nsac;
-       uint8_t         tran_speed;
-       uint16_t        ccc:12,
-                       read_bl_len:4;
-       uint64_t        read_bl_partial:1,
-                       write_blk_misalign:1,
-                       read_blk_misalign:1,
-                       dsr_imp:1,
-                       rsvd2:2,
-                       c_size:12,
-                       vdd_r_curr_min:3,
-                       vdd_r_curr_max:3,
-                       vdd_w_curr_min:3,
-                       vdd_w_curr_max:3,
-                       c_size_mult:3,
-                       erase_blk_en:1,
-                       sector_size:7,
-                       wp_grp_size:7,
-                       wp_grp_enable:1,
-                       default_ecc:2,
-                       r2w_factor:3,
-                       write_bl_len:4,
-                       write_bl_partial:1,
-                       rsvd3:4,
-                       content_prot_app:1;
-       uint8_t         file_format_grp:1,
-                       copy:1,
-                       perm_write_protect:1,
-                       tmp_write_protect:1,
-                       file_format:2,
-                       ecc:2;
-} mmc_csd_t;
-
-#endif /* __MMC_PXA_P_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h
deleted file mode 100644 (file)
index 9caba91..0000000
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_AVR32_MMC_H
-#define __ASM_AVR32_MMC_H
-
-struct mmc_cid {
-       unsigned long psn;
-       unsigned short oid;
-       unsigned char mid;
-       unsigned char prv;
-       unsigned char mdt;
-       char pnm[7];
-};
-
-struct mmc_csd
-{
-       u8      csd_structure:2,
-               spec_vers:4,
-               rsvd1:2;
-       u8      taac;
-       u8      nsac;
-       u8      tran_speed;
-       u16     ccc:12,
-               read_bl_len:4;
-       u64     read_bl_partial:1,
-               write_blk_misalign:1,
-               read_blk_misalign:1,
-               dsr_imp:1,
-               rsvd2:2,
-               c_size:12,
-               vdd_r_curr_min:3,
-               vdd_r_curr_max:3,
-               vdd_w_curr_min:3,
-               vdd_w_curr_max:3,
-               c_size_mult:3,
-               sector_size:5,
-               erase_grp_size:5,
-               wp_grp_size:5,
-               wp_grp_enable:1,
-               default_ecc:2,
-               r2w_factor:3,
-               write_bl_len:4,
-               write_bl_partial:1,
-               rsvd3:5;
-       u8      file_format_grp:1,
-               copy:1,
-               perm_write_protect:1,
-               tmp_write_protect:1,
-               file_format:2,
-               ecc:2;
-       u8      crc:7;
-       u8      one:1;
-};
-
-#define R1_ILLEGAL_COMMAND             (1 << 22)
-#define R1_APP_CMD                     (1 << 5)
-
-#endif /* __ASM_AVR32_MMC_H */
index 47cc053ffc9c9f4b262753ce0044ddde99ed4a67..e41033f291d9cf626b6219c02ebffd845ce97852 100644 (file)
@@ -23,7 +23,6 @@
 
 #ifndef _MMC_H_
 #define _MMC_H_
-#include <asm/arch/mmc.h>
 
 /* MMC command numbers */
 #define MMC_CMD_GO_IDLE_STATE          0
 #define SD_CMD_APP_SET_BUS_WIDTH       6
 #define SD_CMD_APP_SEND_OP_COND                41
 
+#define R1_ILLEGAL_COMMAND             (1 << 22)
+#define R1_APP_CMD                     (1 << 5)
+
 int mmc_legacy_init(int verbose);
 int mmc_read(ulong src, uchar *dst, int size);
 int mmc_write(uchar *src, ulong dst, int size);
 
+struct mmc_cid {
+       unsigned long psn;
+       unsigned short oid;
+       unsigned char mid;
+       unsigned char prv;
+       unsigned char mdt;
+       char pnm[7];
+};
+
+struct mmc_csd
+{
+       u8      csd_structure:2,
+               spec_vers:4,
+               rsvd1:2;
+       u8      taac;
+       u8      nsac;
+       u8      tran_speed;
+       u16     ccc:12,
+               read_bl_len:4;
+       u64     read_bl_partial:1,
+               write_blk_misalign:1,
+               read_blk_misalign:1,
+               dsr_imp:1,
+               rsvd2:2,
+               c_size:12,
+               vdd_r_curr_min:3,
+               vdd_r_curr_max:3,
+               vdd_w_curr_min:3,
+               vdd_w_curr_max:3,
+               c_size_mult:3,
+               sector_size:5,
+               erase_grp_size:5,
+               wp_grp_size:5,
+               wp_grp_enable:1,
+               default_ecc:2,
+               r2w_factor:3,
+               write_bl_len:4,
+               write_bl_partial:1,
+               rsvd3:5;
+       u8      file_format_grp:1,
+               copy:1,
+               perm_write_protect:1,
+               tmp_write_protect:1,
+               file_format:2,
+               ecc:2;
+       u8      crc:7;
+       u8      one:1;
+};
+
 #endif /* _MMC_H_ */