static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
exynos_dp_set_training_pattern(regs, DP_NONE);
struct exynos_dp *regs, unsigned char enable)
{
unsigned char data;
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
&data);
static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
unsigned char enhance_mode)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
if (ret != EXYNOS_DP_SUCCESS) {
static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
unsigned char lane_num, unsigned char *sw, unsigned char *em)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
unsigned char buf;
unsigned int dpcd_addr;
unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
struct exynos_dp_priv *priv)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
unsigned char lane_stat;
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
unsigned int i;
static unsigned int exynos_dp_process_equalizer_training(
struct exynos_dp *regs, struct exynos_dp_priv *priv)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
unsigned char lane_stat, adj_req_sw, adj_req_em, i;
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
unsigned char interlane_aligned = 0;