]> git.sur5r.net Git - u-boot/commitdiff
dm: x86: Add a driver for Intel PCH7
authorSimon Glass <sjg@chromium.org>
Tue, 19 Jan 2016 03:19:18 +0000 (20:19 -0700)
committerBin Meng <bmeng.cn@gmail.com>
Sun, 24 Jan 2016 04:07:17 +0000 (12:07 +0800)
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
drivers/pch/Makefile
drivers/pch/pch7.c [new file with mode: 0644]
include/pch.h

index d69a99c22685c0cd93ee89c7a5b8704f33348666..33aa727017188d9cd47a8dd3a7df04a6efc454a0 100644 (file)
@@ -3,3 +3,4 @@
 #
 
 obj-y += pch-uclass.o
+obj-y += pch7.o
diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c
new file mode 100644 (file)
index 0000000..ef72422
--- /dev/null
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+
+#define BIOS_CTRL      0xd8
+
+static int pch7_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+       u32 rcba;
+
+       dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+       /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+       rcba = rcba & 0xffffc000;
+       *sbasep = rcba + 0x3020;
+
+       return 0;
+}
+
+static enum pch_version pch7_get_version(struct udevice *dev)
+{
+       return PCHV_7;
+}
+
+static int pch7_set_spi_protect(struct udevice *dev, bool protect)
+{
+       uint8_t bios_cntl;
+
+       /* Adjust the BIOS write protect to dis/allow write commands */
+       dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
+       if (protect)
+               bios_cntl &= ~BIOS_CTRL_BIOSWE;
+       else
+               bios_cntl |= BIOS_CTRL_BIOSWE;
+       dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+       return 0;
+}
+
+static const struct pch_ops pch7_ops = {
+       .get_sbase      = pch7_get_sbase,
+       .get_version    = pch7_get_version,
+       .set_spi_protect = pch7_set_spi_protect,
+};
+
+static const struct udevice_id pch7_ids[] = {
+       { .compatible = "intel,pch7" },
+       { }
+};
+
+U_BOOT_DRIVER(pch7_drv) = {
+       .name           = "intel-pch7",
+       .id             = UCLASS_PCH,
+       .of_match       = pch7_ids,
+       .ops            = &pch7_ops,
+};
index ff2686504593895ecc73726e7baabaffc975d0a2..79f49bd5f673a3c6a454358d5d0a7b799d8b9ffd 100644 (file)
@@ -14,6 +14,10 @@ enum pch_version {
        PCHV_9,
 };
 
+#define PCH_RCBA               0xf0
+
+#define BIOS_CTRL_BIOSWE       BIT(0)
+
 /* Operations for the Platform Controller Hub */
 struct pch_ops {
        /**