ARM: keystone2: add MSMC cache coherency support for K2E SOC

This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index f4c293aa892e2bc352412aff03350235a5dbb4ff..a8f8aee8ab45d4df9c5d76132120d5af8d7663d6 100644 (file)
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <ns16550.h>
 #include <asm/io.h>
+#include <asm/arch/msmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 
@@ -24,11 +25,12 @@ int arch_cpu_init(void)
        chip_configuration_unlock();
        icache_enable();
 
-#ifdef CONFIG_SOC_K2HK
-       share_all_segments(8);
-       share_all_segments(9);
-       share_all_segments(10); /* QM PDSP */
-       share_all_segments(11); /* PCIE */
+       msmc_share_all_segments(8);  /* TETRIS */
+       msmc_share_all_segments(9);  /* NETCP */
+       msmc_share_all_segments(10); /* QM PDSP */
+       msmc_share_all_segments(11); /* PCIE 0 */
+#ifdef CONFIG_SOC_K2E
+       msmc_share_all_segments(13); /* PCIE 1 */
 #endif
 
        /*

diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index af858fa7580a611370c72e2c75198da43f0782e5..7d8e5978dfad307a5bbe97afa7a8aae59265b56b 100644 (file)
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/msmc.h>
 
 struct mpax {
        u32     mpaxl;
@@ -56,7 +56,7 @@ struct msms_regs {
 };
 
 
-void share_all_segments(int priv_id)
+void msmc_share_all_segments(int priv_id)
 {
        struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
        int j;

diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 9c86b695b45b6236ab66890e48bde4d9c52b653f..bcfb5517ea21b2358e16c8fb5ae2b552abc93254 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -180,7 +180,6 @@ static inline int cpu_revision(void)
        return rev;
 }
 
-void share_all_segments(int priv_id);
 int cpu_to_bus(u32 *ptr, u32 length);
 void sdelay(unsigned long);
 

diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h
new file mode 100644 (file)
index 0000000..c320db5
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/msmc.h
@@ -0,0 +1,17 @@
+/*
+ * MSMC controller
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _MSMC_H_
+#define _MSMC_H_
+
+#include <asm/arch/hardware.h>
+
+void msmc_share_all_segments(int priv_id);
+
+#endif