arm1136/arm1176: Merge cache handling code

As both cores are similar merge the cache handling code for both CPUs
to arm11 directory.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Add hunk to arch/arm/cpu/arm1136/Makefile]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/arm11/Makefile b/arch/arm/cpu/arm11/Makefile
new file mode 100644 (file)
index 0000000..2379b0f
--- /dev/null
+++ b/arch/arm/cpu/arm11/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  = cpu.o

diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
new file mode 100644 (file)
index 0000000..5d4b3c2
--- /dev/null
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+       /*
+        * this function is called just before we call linux
+        * it prepares the processor for linux
+        *
+        * we turn off caches etc ...
+        */
+
+       disable_interrupts ();
+
+       /* turn off I/D-cache */
+       icache_disable();
+       dcache_disable();
+       /* flush I/D-cache */
+       cache_flush();
+
+       return 0;
+}
+
+static void cache_flush(void)
+{
+       unsigned long i = 0;
+       /* clean entire data cache */
+       asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+       /* invalidate both caches and flush btb */
+       asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+       /* mem barrier to sync things */
+       asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE      32
+#endif
+
+void invalidate_dcache_all(void)
+{
+       asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+       asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+       asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+       int ok = 1;
+
+       if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+               ok = 0;
+
+       if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+               ok = 0;
+
+       if (!ok)
+               debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+                       start, stop);
+
+       return ok;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+       if (!check_cache_range(start, stop))
+               return;
+
+       while (start < stop) {
+               asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+               start += CONFIG_SYS_CACHELINE_SIZE;
+       }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+       if (!check_cache_range(start, stop))
+               return;
+
+       while (start < stop) {
+               asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+               start += CONFIG_SYS_CACHELINE_SIZE;
+       }
+
+       asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+       flush_dcache_range(start, start + size);
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+       icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       dcache_enable();
+#endif
+}
+#endif

diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 56a9390b0111856fcb335f858ec5bef5a75b2277..dbdafeb47f61ba59516f0178a903b50021ded413 100644 (file)
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -6,7 +6,7 @@
 #
 
 extra-y        = start.o
-obj-y  = cpu.o
 
+obj-y += ../arm11/
 obj-$(CONFIG_MX31) += mx31/
 obj-$(CONFIG_MX35) += mx35/

diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
deleted file mode 100644 (file)
index 5d4b3c2..0000000
--- a/arch/arm/cpu/arm1136/cpu.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-       /*
-        * this function is called just before we call linux
-        * it prepares the processor for linux
-        *
-        * we turn off caches etc ...
-        */
-
-       disable_interrupts ();
-
-       /* turn off I/D-cache */
-       icache_disable();
-       dcache_disable();
-       /* flush I/D-cache */
-       cache_flush();
-
-       return 0;
-}
-
-static void cache_flush(void)
-{
-       unsigned long i = 0;
-       /* clean entire data cache */
-       asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
-       /* invalidate both caches and flush btb */
-       asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
-       /* mem barrier to sync things */
-       asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE      32
-#endif
-
-void invalidate_dcache_all(void)
-{
-       asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
-}
-
-void flush_dcache_all(void)
-{
-       asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
-       asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-}
-
-static int check_cache_range(unsigned long start, unsigned long stop)
-{
-       int ok = 1;
-
-       if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
-               ok = 0;
-
-       if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
-               ok = 0;
-
-       if (!ok)
-               debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
-                       start, stop);
-
-       return ok;
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-       if (!check_cache_range(start, stop))
-               return;
-
-       while (start < stop) {
-               asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
-               start += CONFIG_SYS_CACHELINE_SIZE;
-       }
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-       if (!check_cache_range(start, stop))
-               return;
-
-       while (start < stop) {
-               asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
-               start += CONFIG_SYS_CACHELINE_SIZE;
-       }
-
-       asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
-}
-
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
-void invalidate_dcache_all(void)
-{
-}
-
-void flush_dcache_all(void)
-{
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
-
-#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
-       icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-       dcache_enable();
-#endif
-}
-#endif

diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
index deec4274477551b17b13b8e1b601892246d2641c..cd6dc9c1304d8afd12f2750835a73734d7a38123 100644 (file)
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
@@ -8,5 +8,7 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+obj- += dummy.o
 extra-y        = start.o
-obj-y  = cpu.o
+
+obj-y += ../arm11/

diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
deleted file mode 100644 (file)
index 2d81651..0000000
--- a/arch/arm/cpu/arm1176/cpu.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush (void);
-
-int cleanup_before_linux (void)
-{
-       /*
-        * this function is called just before we call linux
-        * it prepares the processor for linux
-        *
-        * we turn off caches etc ...
-        */
-
-       disable_interrupts ();
-
-       /* turn off I/D-cache */
-       icache_disable();
-       dcache_disable();
-       /* flush I/D-cache */
-       cache_flush();
-
-       return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-       /* invalidate both caches and flush btb */
-       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
-       /* mem barrier to sync things */
-       asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
-}