]> git.sur5r.net Git - u-boot/commitdiff
board: ti: am571x: Add 666MHz support for AM571x IDK
authorSteve Kipisz <s-kipisz2@ti.com>
Tue, 22 Aug 2017 08:22:58 +0000 (13:52 +0530)
committerTom Rini <trini@konsulko.com>
Mon, 11 Sep 2017 20:22:31 +0000 (16:22 -0400)
AM571x supports DDR running at 666MHz. Right now it is
clocked at 532MHz which is lower than what is supported.
In order to have maximum performance on AM571-IDK,
switch DDR to 666MHz.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/include/asm/omap_common.h
board/ti/am57xx/board.c

index d7e453e579082aaecc4cf14268519d39cfd96fdc..8b296c96852754acbafdf33352ce33664feac975 100644 (file)
@@ -596,6 +596,7 @@ extern struct prcm_regs const omap4_prcm;
 extern struct prcm_regs const dra7xx_prcm;
 extern struct dplls const **dplls_data;
 extern struct dplls dra7xx_dplls;
+extern struct dplls dra72x_dplls;
 extern struct vcores_data const **omap_vcores;
 extern const u32 sys_clk_array[8];
 extern struct omap_sys_ctrl_regs const **ctrl;
index 7e7056cf71c5012150a1328a0cd8defee3fd6871..3d15cb1dbfb1aa4f2bee06766221e422f1b3eb7a 100644 (file)
@@ -223,11 +223,39 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
        0x0
 };
 
+static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
+       .sdram_config_init              = 0x61863332,
+       .sdram_config                   = 0x61863332,
+       .sdram_config2                  = 0x08000000,
+       .ref_ctrl                       = 0x0000514d,
+       .ref_ctrl_final                 = 0x0000144a,
+       .sdram_tim1                     = 0xd333887c,
+       .sdram_tim2                     = 0x40b37fe3,
+       .sdram_tim3                     = 0x409f8ada,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x5007190b,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
+       .emif_ddr_phy_ctlr_1            = 0x0e24400f,
+       .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x00000305
+};
+
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 {
        switch (emif_nr) {
        case 1:
-               *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
+               if (board_is_am571x_idk())
+                       *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+               else
+                       *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
                break;
        case 2:
                *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
@@ -513,7 +541,10 @@ void vcores_init(void)
 void hw_data_init(void)
 {
        *prcm = &dra7xx_prcm;
-       *dplls_data = &dra7xx_dplls;
+       if (is_dra72x())
+               *dplls_data = &dra72x_dplls;
+       else
+               *dplls_data = &dra7xx_dplls;
        *ctrl = &dra7xx_ctrl;
 }